1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <drm/drmP.h> 25 #include <drm/drm_cache.h> 26 #include "amdgpu.h" 27 #include "gmc_v8_0.h" 28 #include "amdgpu_ucode.h" 29 #include "amdgpu_amdkfd.h" 30 31 #include "gmc/gmc_8_1_d.h" 32 #include "gmc/gmc_8_1_sh_mask.h" 33 34 #include "bif/bif_5_0_d.h" 35 #include "bif/bif_5_0_sh_mask.h" 36 37 #include "oss/oss_3_0_d.h" 38 #include "oss/oss_3_0_sh_mask.h" 39 40 #include "dce/dce_10_0_d.h" 41 #include "dce/dce_10_0_sh_mask.h" 42 43 #include "vid.h" 44 #include "vi.h" 45 46 #include "amdgpu_atombios.h" 47 48 #include "ivsrcid/ivsrcid_vislands30.h" 49 50 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 51 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 52 static int gmc_v8_0_wait_for_idle(void *handle); 53 54 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 55 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 56 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 57 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 58 59 static const u32 golden_settings_tonga_a11[] = 60 { 61 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 62 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 63 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 64 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 65 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 66 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 67 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 68 }; 69 70 static const u32 tonga_mgcg_cgcg_init[] = 71 { 72 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 73 }; 74 75 static const u32 golden_settings_fiji_a10[] = 76 { 77 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 78 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 79 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 80 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 81 }; 82 83 static const u32 fiji_mgcg_cgcg_init[] = 84 { 85 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 86 }; 87 88 static const u32 golden_settings_polaris11_a11[] = 89 { 90 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 91 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 92 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 93 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 94 }; 95 96 static const u32 golden_settings_polaris10_a11[] = 97 { 98 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 99 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 100 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 101 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 102 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 103 }; 104 105 static const u32 cz_mgcg_cgcg_init[] = 106 { 107 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 108 }; 109 110 static const u32 stoney_mgcg_cgcg_init[] = 111 { 112 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 113 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 114 }; 115 116 static const u32 golden_settings_stoney_common[] = 117 { 118 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 119 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 120 }; 121 122 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 123 { 124 switch (adev->asic_type) { 125 case CHIP_FIJI: 126 amdgpu_device_program_register_sequence(adev, 127 fiji_mgcg_cgcg_init, 128 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 129 amdgpu_device_program_register_sequence(adev, 130 golden_settings_fiji_a10, 131 ARRAY_SIZE(golden_settings_fiji_a10)); 132 break; 133 case CHIP_TONGA: 134 amdgpu_device_program_register_sequence(adev, 135 tonga_mgcg_cgcg_init, 136 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 137 amdgpu_device_program_register_sequence(adev, 138 golden_settings_tonga_a11, 139 ARRAY_SIZE(golden_settings_tonga_a11)); 140 break; 141 case CHIP_POLARIS11: 142 case CHIP_POLARIS12: 143 case CHIP_VEGAM: 144 amdgpu_device_program_register_sequence(adev, 145 golden_settings_polaris11_a11, 146 ARRAY_SIZE(golden_settings_polaris11_a11)); 147 break; 148 case CHIP_POLARIS10: 149 amdgpu_device_program_register_sequence(adev, 150 golden_settings_polaris10_a11, 151 ARRAY_SIZE(golden_settings_polaris10_a11)); 152 break; 153 case CHIP_CARRIZO: 154 amdgpu_device_program_register_sequence(adev, 155 cz_mgcg_cgcg_init, 156 ARRAY_SIZE(cz_mgcg_cgcg_init)); 157 break; 158 case CHIP_STONEY: 159 amdgpu_device_program_register_sequence(adev, 160 stoney_mgcg_cgcg_init, 161 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 162 amdgpu_device_program_register_sequence(adev, 163 golden_settings_stoney_common, 164 ARRAY_SIZE(golden_settings_stoney_common)); 165 break; 166 default: 167 break; 168 } 169 } 170 171 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 172 { 173 u32 blackout; 174 175 gmc_v8_0_wait_for_idle(adev); 176 177 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 178 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 179 /* Block CPU access */ 180 WREG32(mmBIF_FB_EN, 0); 181 /* blackout the MC */ 182 blackout = REG_SET_FIELD(blackout, 183 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 184 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 185 } 186 /* wait for the MC to settle */ 187 udelay(100); 188 } 189 190 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 191 { 192 u32 tmp; 193 194 /* unblackout the MC */ 195 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 196 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 197 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 198 /* allow CPU access */ 199 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 200 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 201 WREG32(mmBIF_FB_EN, tmp); 202 } 203 204 /** 205 * gmc_v8_0_init_microcode - load ucode images from disk 206 * 207 * @adev: amdgpu_device pointer 208 * 209 * Use the firmware interface to load the ucode images into 210 * the driver (not loaded into hw). 211 * Returns 0 on success, error on failure. 212 */ 213 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 214 { 215 const char *chip_name; 216 char fw_name[30]; 217 int err; 218 219 DRM_DEBUG("\n"); 220 221 switch (adev->asic_type) { 222 case CHIP_TONGA: 223 chip_name = "tonga"; 224 break; 225 case CHIP_POLARIS11: 226 chip_name = "polaris11"; 227 break; 228 case CHIP_POLARIS10: 229 chip_name = "polaris10"; 230 break; 231 case CHIP_POLARIS12: 232 chip_name = "polaris12"; 233 break; 234 case CHIP_FIJI: 235 case CHIP_CARRIZO: 236 case CHIP_STONEY: 237 case CHIP_VEGAM: 238 return 0; 239 default: BUG(); 240 } 241 242 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 243 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 244 if (err) 245 goto out; 246 err = amdgpu_ucode_validate(adev->gmc.fw); 247 248 out: 249 if (err) { 250 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 251 release_firmware(adev->gmc.fw); 252 adev->gmc.fw = NULL; 253 } 254 return err; 255 } 256 257 /** 258 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 259 * 260 * @adev: amdgpu_device pointer 261 * 262 * Load the GDDR MC ucode into the hw (CIK). 263 * Returns 0 on success, error on failure. 264 */ 265 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 266 { 267 const struct mc_firmware_header_v1_0 *hdr; 268 const __le32 *fw_data = NULL; 269 const __le32 *io_mc_regs = NULL; 270 u32 running; 271 int i, ucode_size, regs_size; 272 273 /* Skip MC ucode loading on SR-IOV capable boards. 274 * vbios does this for us in asic_init in that case. 275 * Skip MC ucode loading on VF, because hypervisor will do that 276 * for this adaptor. 277 */ 278 if (amdgpu_sriov_bios(adev)) 279 return 0; 280 281 if (!adev->gmc.fw) 282 return -EINVAL; 283 284 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 285 amdgpu_ucode_print_mc_hdr(&hdr->header); 286 287 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 288 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 289 io_mc_regs = (const __le32 *) 290 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 291 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 292 fw_data = (const __le32 *) 293 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 294 295 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 296 297 if (running == 0) { 298 /* reset the engine and set to writable */ 299 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 300 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 301 302 /* load mc io regs */ 303 for (i = 0; i < regs_size; i++) { 304 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 305 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 306 } 307 /* load the MC ucode */ 308 for (i = 0; i < ucode_size; i++) 309 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 310 311 /* put the engine back into the active state */ 312 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 315 316 /* wait for training to complete */ 317 for (i = 0; i < adev->usec_timeout; i++) { 318 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 319 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 320 break; 321 udelay(1); 322 } 323 for (i = 0; i < adev->usec_timeout; i++) { 324 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 325 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 326 break; 327 udelay(1); 328 } 329 } 330 331 return 0; 332 } 333 334 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 335 { 336 const struct mc_firmware_header_v1_0 *hdr; 337 const __le32 *fw_data = NULL; 338 const __le32 *io_mc_regs = NULL; 339 u32 data, vbios_version; 340 int i, ucode_size, regs_size; 341 342 /* Skip MC ucode loading on SR-IOV capable boards. 343 * vbios does this for us in asic_init in that case. 344 * Skip MC ucode loading on VF, because hypervisor will do that 345 * for this adaptor. 346 */ 347 if (amdgpu_sriov_bios(adev)) 348 return 0; 349 350 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); 351 data = RREG32(mmMC_SEQ_IO_DEBUG_DATA); 352 vbios_version = data & 0xf; 353 354 if (vbios_version == 0) 355 return 0; 356 357 if (!adev->gmc.fw) 358 return -EINVAL; 359 360 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 361 amdgpu_ucode_print_mc_hdr(&hdr->header); 362 363 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 364 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 365 io_mc_regs = (const __le32 *) 366 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 367 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 368 fw_data = (const __le32 *) 369 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 370 371 data = RREG32(mmMC_SEQ_MISC0); 372 data &= ~(0x40); 373 WREG32(mmMC_SEQ_MISC0, data); 374 375 /* load mc io regs */ 376 for (i = 0; i < regs_size; i++) { 377 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 378 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 379 } 380 381 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 382 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 383 384 /* load the MC ucode */ 385 for (i = 0; i < ucode_size; i++) 386 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 387 388 /* put the engine back into the active state */ 389 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 390 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 391 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 392 393 /* wait for training to complete */ 394 for (i = 0; i < adev->usec_timeout; i++) { 395 data = RREG32(mmMC_SEQ_MISC0); 396 if (data & 0x80) 397 break; 398 udelay(1); 399 } 400 401 return 0; 402 } 403 404 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 405 struct amdgpu_gmc *mc) 406 { 407 u64 base = 0; 408 409 if (!amdgpu_sriov_vf(adev)) 410 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 411 base <<= 24; 412 413 amdgpu_device_vram_location(adev, &adev->gmc, base); 414 amdgpu_device_gart_location(adev, mc); 415 } 416 417 /** 418 * gmc_v8_0_mc_program - program the GPU memory controller 419 * 420 * @adev: amdgpu_device pointer 421 * 422 * Set the location of vram, gart, and AGP in the GPU's 423 * physical address space (CIK). 424 */ 425 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 426 { 427 u32 tmp; 428 int i, j; 429 430 /* Initialize HDP */ 431 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 432 WREG32((0xb05 + j), 0x00000000); 433 WREG32((0xb06 + j), 0x00000000); 434 WREG32((0xb07 + j), 0x00000000); 435 WREG32((0xb08 + j), 0x00000000); 436 WREG32((0xb09 + j), 0x00000000); 437 } 438 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 439 440 if (gmc_v8_0_wait_for_idle((void *)adev)) { 441 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 442 } 443 if (adev->mode_info.num_crtc) { 444 /* Lockout access through VGA aperture*/ 445 tmp = RREG32(mmVGA_HDP_CONTROL); 446 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 447 WREG32(mmVGA_HDP_CONTROL, tmp); 448 449 /* disable VGA render */ 450 tmp = RREG32(mmVGA_RENDER_CONTROL); 451 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 452 WREG32(mmVGA_RENDER_CONTROL, tmp); 453 } 454 /* Update configuration */ 455 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 456 adev->gmc.vram_start >> 12); 457 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 458 adev->gmc.vram_end >> 12); 459 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 460 adev->vram_scratch.gpu_addr >> 12); 461 462 if (amdgpu_sriov_vf(adev)) { 463 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 464 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 465 WREG32(mmMC_VM_FB_LOCATION, tmp); 466 /* XXX double check these! */ 467 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 468 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 469 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 470 } 471 472 WREG32(mmMC_VM_AGP_BASE, 0); 473 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 474 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 475 if (gmc_v8_0_wait_for_idle((void *)adev)) { 476 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 477 } 478 479 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 480 481 tmp = RREG32(mmHDP_MISC_CNTL); 482 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 483 WREG32(mmHDP_MISC_CNTL, tmp); 484 485 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 486 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 487 } 488 489 /** 490 * gmc_v8_0_mc_init - initialize the memory controller driver params 491 * 492 * @adev: amdgpu_device pointer 493 * 494 * Look up the amount of vram, vram width, and decide how to place 495 * vram and gart within the GPU's physical address space (CIK). 496 * Returns 0 for success. 497 */ 498 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 499 { 500 int r; 501 502 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 503 if (!adev->gmc.vram_width) { 504 u32 tmp; 505 int chansize, numchan; 506 507 /* Get VRAM informations */ 508 tmp = RREG32(mmMC_ARB_RAMCFG); 509 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 510 chansize = 64; 511 } else { 512 chansize = 32; 513 } 514 tmp = RREG32(mmMC_SHARED_CHMAP); 515 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 516 case 0: 517 default: 518 numchan = 1; 519 break; 520 case 1: 521 numchan = 2; 522 break; 523 case 2: 524 numchan = 4; 525 break; 526 case 3: 527 numchan = 8; 528 break; 529 case 4: 530 numchan = 3; 531 break; 532 case 5: 533 numchan = 6; 534 break; 535 case 6: 536 numchan = 10; 537 break; 538 case 7: 539 numchan = 12; 540 break; 541 case 8: 542 numchan = 16; 543 break; 544 } 545 adev->gmc.vram_width = numchan * chansize; 546 } 547 /* size in MB on si */ 548 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 549 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 550 551 if (!(adev->flags & AMD_IS_APU)) { 552 r = amdgpu_device_resize_fb_bar(adev); 553 if (r) 554 return r; 555 } 556 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 557 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 558 559 #ifdef CONFIG_X86_64 560 if (adev->flags & AMD_IS_APU) { 561 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 562 adev->gmc.aper_size = adev->gmc.real_vram_size; 563 } 564 #endif 565 566 /* In case the PCI BAR is larger than the actual amount of vram */ 567 adev->gmc.visible_vram_size = adev->gmc.aper_size; 568 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 569 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 570 571 /* set the gart size */ 572 if (amdgpu_gart_size == -1) { 573 switch (adev->asic_type) { 574 case CHIP_POLARIS10: /* all engines support GPUVM */ 575 case CHIP_POLARIS11: /* all engines support GPUVM */ 576 case CHIP_POLARIS12: /* all engines support GPUVM */ 577 case CHIP_VEGAM: /* all engines support GPUVM */ 578 default: 579 adev->gmc.gart_size = 256ULL << 20; 580 break; 581 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 582 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 583 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 584 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 585 adev->gmc.gart_size = 1024ULL << 20; 586 break; 587 } 588 } else { 589 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 590 } 591 592 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 593 594 return 0; 595 } 596 597 /* 598 * GART 599 * VMID 0 is the physical GPU addresses as used by the kernel. 600 * VMIDs 1-15 are used for userspace clients and are handled 601 * by the amdgpu vm/hsa code. 602 */ 603 604 /** 605 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 606 * 607 * @adev: amdgpu_device pointer 608 * @vmid: vm instance to flush 609 * 610 * Flush the TLB for the requested page table (CIK). 611 */ 612 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, 613 uint32_t vmid) 614 { 615 /* bits 0-15 are the VM contexts0-15 */ 616 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 617 } 618 619 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 620 unsigned vmid, uint64_t pd_addr) 621 { 622 uint32_t reg; 623 624 if (vmid < 8) 625 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 626 else 627 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 628 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 629 630 /* bits 0-15 are the VM contexts0-15 */ 631 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 632 633 return pd_addr; 634 } 635 636 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 637 unsigned pasid) 638 { 639 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 640 } 641 642 /** 643 * gmc_v8_0_set_pte_pde - update the page tables using MMIO 644 * 645 * @adev: amdgpu_device pointer 646 * @cpu_pt_addr: cpu address of the page table 647 * @gpu_page_idx: entry in the page table to update 648 * @addr: dst addr to write into pte/pde 649 * @flags: access flags 650 * 651 * Update the page tables using the CPU. 652 */ 653 static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 654 uint32_t gpu_page_idx, uint64_t addr, 655 uint64_t flags) 656 { 657 void __iomem *ptr = (void *)cpu_pt_addr; 658 uint64_t value; 659 660 /* 661 * PTE format on VI: 662 * 63:40 reserved 663 * 39:12 4k physical page base address 664 * 11:7 fragment 665 * 6 write 666 * 5 read 667 * 4 exe 668 * 3 reserved 669 * 2 snooped 670 * 1 system 671 * 0 valid 672 * 673 * PDE format on VI: 674 * 63:59 block fragment size 675 * 58:40 reserved 676 * 39:1 physical base address of PTE 677 * bits 5:1 must be 0. 678 * 0 valid 679 */ 680 value = addr & 0x000000FFFFFFF000ULL; 681 value |= flags; 682 writeq(value, ptr + (gpu_page_idx * 8)); 683 684 return 0; 685 } 686 687 static uint64_t gmc_v8_0_get_vm_pte_flags(struct amdgpu_device *adev, 688 uint32_t flags) 689 { 690 uint64_t pte_flag = 0; 691 692 if (flags & AMDGPU_VM_PAGE_EXECUTABLE) 693 pte_flag |= AMDGPU_PTE_EXECUTABLE; 694 if (flags & AMDGPU_VM_PAGE_READABLE) 695 pte_flag |= AMDGPU_PTE_READABLE; 696 if (flags & AMDGPU_VM_PAGE_WRITEABLE) 697 pte_flag |= AMDGPU_PTE_WRITEABLE; 698 if (flags & AMDGPU_VM_PAGE_PRT) 699 pte_flag |= AMDGPU_PTE_PRT; 700 701 return pte_flag; 702 } 703 704 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 705 uint64_t *addr, uint64_t *flags) 706 { 707 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 708 } 709 710 /** 711 * gmc_v8_0_set_fault_enable_default - update VM fault handling 712 * 713 * @adev: amdgpu_device pointer 714 * @value: true redirects VM faults to the default page 715 */ 716 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 717 bool value) 718 { 719 u32 tmp; 720 721 tmp = RREG32(mmVM_CONTEXT1_CNTL); 722 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 723 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 724 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 725 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 726 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 727 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 728 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 729 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 730 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 731 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 732 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 733 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 734 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 735 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 736 WREG32(mmVM_CONTEXT1_CNTL, tmp); 737 } 738 739 /** 740 * gmc_v8_0_set_prt - set PRT VM fault 741 * 742 * @adev: amdgpu_device pointer 743 * @enable: enable/disable VM fault handling for PRT 744 */ 745 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 746 { 747 u32 tmp; 748 749 if (enable && !adev->gmc.prt_warning) { 750 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 751 adev->gmc.prt_warning = true; 752 } 753 754 tmp = RREG32(mmVM_PRT_CNTL); 755 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 756 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 757 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 758 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 759 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 760 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 761 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 762 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 763 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 764 L2_CACHE_STORE_INVALID_ENTRIES, enable); 765 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 766 L1_TLB_STORE_INVALID_ENTRIES, enable); 767 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 768 MASK_PDE0_FAULT, enable); 769 WREG32(mmVM_PRT_CNTL, tmp); 770 771 if (enable) { 772 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 773 uint32_t high = adev->vm_manager.max_pfn - 774 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 775 776 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 777 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 778 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 779 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 780 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 781 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 782 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 783 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 784 } else { 785 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 786 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 787 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 788 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 789 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 790 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 791 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 792 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 793 } 794 } 795 796 /** 797 * gmc_v8_0_gart_enable - gart enable 798 * 799 * @adev: amdgpu_device pointer 800 * 801 * This sets up the TLBs, programs the page tables for VMID0, 802 * sets up the hw for VMIDs 1-15 which are allocated on 803 * demand, and sets up the global locations for the LDS, GDS, 804 * and GPUVM for FSA64 clients (CIK). 805 * Returns 0 for success, errors for failure. 806 */ 807 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 808 { 809 int r, i; 810 u32 tmp, field; 811 812 if (adev->gart.robj == NULL) { 813 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 814 return -EINVAL; 815 } 816 r = amdgpu_gart_table_vram_pin(adev); 817 if (r) 818 return r; 819 /* Setup TLB control */ 820 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 821 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 822 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 823 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 824 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 825 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 826 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 827 /* Setup L2 cache */ 828 tmp = RREG32(mmVM_L2_CNTL); 829 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 830 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 831 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 832 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 833 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 834 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 835 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 836 WREG32(mmVM_L2_CNTL, tmp); 837 tmp = RREG32(mmVM_L2_CNTL2); 838 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 839 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 840 WREG32(mmVM_L2_CNTL2, tmp); 841 842 field = adev->vm_manager.fragment_size; 843 tmp = RREG32(mmVM_L2_CNTL3); 844 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 845 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 846 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 847 WREG32(mmVM_L2_CNTL3, tmp); 848 /* XXX: set to enable PTE/PDE in system memory */ 849 tmp = RREG32(mmVM_L2_CNTL4); 850 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 859 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 862 WREG32(mmVM_L2_CNTL4, tmp); 863 /* setup context0 */ 864 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 865 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 866 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 867 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 868 (u32)(adev->dummy_page_addr >> 12)); 869 WREG32(mmVM_CONTEXT0_CNTL2, 0); 870 tmp = RREG32(mmVM_CONTEXT0_CNTL); 871 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 872 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 873 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 874 WREG32(mmVM_CONTEXT0_CNTL, tmp); 875 876 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 877 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 878 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 879 880 /* empty context1-15 */ 881 /* FIXME start with 4G, once using 2 level pt switch to full 882 * vm size space 883 */ 884 /* set vm size, must be a multiple of 4 */ 885 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 886 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 887 for (i = 1; i < 16; i++) { 888 if (i < 8) 889 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 890 adev->gart.table_addr >> 12); 891 else 892 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 893 adev->gart.table_addr >> 12); 894 } 895 896 /* enable context1-15 */ 897 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 898 (u32)(adev->dummy_page_addr >> 12)); 899 WREG32(mmVM_CONTEXT1_CNTL2, 4); 900 tmp = RREG32(mmVM_CONTEXT1_CNTL); 901 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 902 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 903 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 904 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 905 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 906 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 907 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 908 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 909 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 910 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 911 adev->vm_manager.block_size - 9); 912 WREG32(mmVM_CONTEXT1_CNTL, tmp); 913 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 914 gmc_v8_0_set_fault_enable_default(adev, false); 915 else 916 gmc_v8_0_set_fault_enable_default(adev, true); 917 918 gmc_v8_0_flush_gpu_tlb(adev, 0); 919 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 920 (unsigned)(adev->gmc.gart_size >> 20), 921 (unsigned long long)adev->gart.table_addr); 922 adev->gart.ready = true; 923 return 0; 924 } 925 926 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 927 { 928 int r; 929 930 if (adev->gart.robj) { 931 WARN(1, "R600 PCIE GART already initialized\n"); 932 return 0; 933 } 934 /* Initialize common gart structure */ 935 r = amdgpu_gart_init(adev); 936 if (r) 937 return r; 938 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 939 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 940 return amdgpu_gart_table_vram_alloc(adev); 941 } 942 943 /** 944 * gmc_v8_0_gart_disable - gart disable 945 * 946 * @adev: amdgpu_device pointer 947 * 948 * This disables all VM page table (CIK). 949 */ 950 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 951 { 952 u32 tmp; 953 954 /* Disable all tables */ 955 WREG32(mmVM_CONTEXT0_CNTL, 0); 956 WREG32(mmVM_CONTEXT1_CNTL, 0); 957 /* Setup TLB control */ 958 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 959 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 960 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 961 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 962 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 963 /* Setup L2 cache */ 964 tmp = RREG32(mmVM_L2_CNTL); 965 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 966 WREG32(mmVM_L2_CNTL, tmp); 967 WREG32(mmVM_L2_CNTL2, 0); 968 amdgpu_gart_table_vram_unpin(adev); 969 } 970 971 /** 972 * gmc_v8_0_vm_decode_fault - print human readable fault info 973 * 974 * @adev: amdgpu_device pointer 975 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 976 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 977 * 978 * Print human readable fault information (CIK). 979 */ 980 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 981 u32 addr, u32 mc_client, unsigned pasid) 982 { 983 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 984 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 985 PROTECTIONS); 986 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 987 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 988 u32 mc_id; 989 990 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 991 MEMORY_CLIENT_ID); 992 993 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 994 protections, vmid, pasid, addr, 995 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 996 MEMORY_CLIENT_RW) ? 997 "write" : "read", block, mc_client, mc_id); 998 } 999 1000 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1001 { 1002 switch (mc_seq_vram_type) { 1003 case MC_SEQ_MISC0__MT__GDDR1: 1004 return AMDGPU_VRAM_TYPE_GDDR1; 1005 case MC_SEQ_MISC0__MT__DDR2: 1006 return AMDGPU_VRAM_TYPE_DDR2; 1007 case MC_SEQ_MISC0__MT__GDDR3: 1008 return AMDGPU_VRAM_TYPE_GDDR3; 1009 case MC_SEQ_MISC0__MT__GDDR4: 1010 return AMDGPU_VRAM_TYPE_GDDR4; 1011 case MC_SEQ_MISC0__MT__GDDR5: 1012 return AMDGPU_VRAM_TYPE_GDDR5; 1013 case MC_SEQ_MISC0__MT__HBM: 1014 return AMDGPU_VRAM_TYPE_HBM; 1015 case MC_SEQ_MISC0__MT__DDR3: 1016 return AMDGPU_VRAM_TYPE_DDR3; 1017 default: 1018 return AMDGPU_VRAM_TYPE_UNKNOWN; 1019 } 1020 } 1021 1022 static int gmc_v8_0_early_init(void *handle) 1023 { 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1025 1026 gmc_v8_0_set_gmc_funcs(adev); 1027 gmc_v8_0_set_irq_funcs(adev); 1028 1029 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1030 adev->gmc.shared_aperture_end = 1031 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1032 adev->gmc.private_aperture_start = 1033 adev->gmc.shared_aperture_end + 1; 1034 adev->gmc.private_aperture_end = 1035 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1036 1037 return 0; 1038 } 1039 1040 static int gmc_v8_0_late_init(void *handle) 1041 { 1042 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1043 1044 amdgpu_bo_late_init(adev); 1045 1046 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1047 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1048 else 1049 return 0; 1050 } 1051 1052 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1053 { 1054 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1055 unsigned size; 1056 1057 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1058 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */ 1059 } else { 1060 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1061 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1062 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1063 4); 1064 } 1065 /* return 0 if the pre-OS buffer uses up most of vram */ 1066 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) 1067 return 0; 1068 return size; 1069 } 1070 1071 #define mmMC_SEQ_MISC0_FIJI 0xA71 1072 1073 static int gmc_v8_0_sw_init(void *handle) 1074 { 1075 int r; 1076 int dma_bits; 1077 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1078 1079 if (adev->flags & AMD_IS_APU) { 1080 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1081 } else { 1082 u32 tmp; 1083 1084 if ((adev->asic_type == CHIP_FIJI) || 1085 (adev->asic_type == CHIP_VEGAM)) 1086 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1087 else 1088 tmp = RREG32(mmMC_SEQ_MISC0); 1089 tmp &= MC_SEQ_MISC0__MT__MASK; 1090 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1091 } 1092 1093 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1094 if (r) 1095 return r; 1096 1097 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1098 if (r) 1099 return r; 1100 1101 /* Adjust VM size here. 1102 * Currently set to 4GB ((1 << 20) 4k pages). 1103 * Max GPUVM size for cayman and SI is 40 bits. 1104 */ 1105 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1106 1107 /* Set the internal MC address mask 1108 * This is the max address of the GPU's 1109 * internal address space. 1110 */ 1111 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1112 1113 /* set DMA mask + need_dma32 flags. 1114 * PCIE - can handle 40-bits. 1115 * IGP - can handle 40-bits 1116 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1117 */ 1118 adev->need_dma32 = false; 1119 dma_bits = adev->need_dma32 ? 32 : 40; 1120 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1121 if (r) { 1122 adev->need_dma32 = true; 1123 dma_bits = 32; 1124 pr_warn("amdgpu: No suitable DMA available\n"); 1125 } 1126 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 1127 if (r) { 1128 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 1129 pr_warn("amdgpu: No coherent DMA available\n"); 1130 } 1131 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits); 1132 1133 r = gmc_v8_0_init_microcode(adev); 1134 if (r) { 1135 DRM_ERROR("Failed to load mc firmware!\n"); 1136 return r; 1137 } 1138 1139 r = gmc_v8_0_mc_init(adev); 1140 if (r) 1141 return r; 1142 1143 adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev); 1144 1145 /* Memory manager */ 1146 r = amdgpu_bo_init(adev); 1147 if (r) 1148 return r; 1149 1150 r = gmc_v8_0_gart_init(adev); 1151 if (r) 1152 return r; 1153 1154 /* 1155 * number of VMs 1156 * VMID 0 is reserved for System 1157 * amdgpu graphics/compute will use VMIDs 1-7 1158 * amdkfd will use VMIDs 8-15 1159 */ 1160 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; 1161 amdgpu_vm_manager_init(adev); 1162 1163 /* base offset of vram pages */ 1164 if (adev->flags & AMD_IS_APU) { 1165 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1166 1167 tmp <<= 22; 1168 adev->vm_manager.vram_base_offset = tmp; 1169 } else { 1170 adev->vm_manager.vram_base_offset = 0; 1171 } 1172 1173 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1174 GFP_KERNEL); 1175 if (!adev->gmc.vm_fault_info) 1176 return -ENOMEM; 1177 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1178 1179 return 0; 1180 } 1181 1182 static int gmc_v8_0_sw_fini(void *handle) 1183 { 1184 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1185 1186 amdgpu_gem_force_release(adev); 1187 amdgpu_vm_manager_fini(adev); 1188 kfree(adev->gmc.vm_fault_info); 1189 amdgpu_gart_table_vram_free(adev); 1190 amdgpu_bo_fini(adev); 1191 amdgpu_gart_fini(adev); 1192 release_firmware(adev->gmc.fw); 1193 adev->gmc.fw = NULL; 1194 1195 return 0; 1196 } 1197 1198 static int gmc_v8_0_hw_init(void *handle) 1199 { 1200 int r; 1201 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1202 1203 gmc_v8_0_init_golden_registers(adev); 1204 1205 gmc_v8_0_mc_program(adev); 1206 1207 if (adev->asic_type == CHIP_TONGA) { 1208 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1209 if (r) { 1210 DRM_ERROR("Failed to load MC firmware!\n"); 1211 return r; 1212 } 1213 } else if (adev->asic_type == CHIP_POLARIS11 || 1214 adev->asic_type == CHIP_POLARIS10 || 1215 adev->asic_type == CHIP_POLARIS12) { 1216 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1217 if (r) { 1218 DRM_ERROR("Failed to load MC firmware!\n"); 1219 return r; 1220 } 1221 } 1222 1223 r = gmc_v8_0_gart_enable(adev); 1224 if (r) 1225 return r; 1226 1227 return r; 1228 } 1229 1230 static int gmc_v8_0_hw_fini(void *handle) 1231 { 1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1233 1234 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1235 gmc_v8_0_gart_disable(adev); 1236 1237 return 0; 1238 } 1239 1240 static int gmc_v8_0_suspend(void *handle) 1241 { 1242 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1243 1244 gmc_v8_0_hw_fini(adev); 1245 1246 return 0; 1247 } 1248 1249 static int gmc_v8_0_resume(void *handle) 1250 { 1251 int r; 1252 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1253 1254 r = gmc_v8_0_hw_init(adev); 1255 if (r) 1256 return r; 1257 1258 amdgpu_vmid_reset_all(adev); 1259 1260 return 0; 1261 } 1262 1263 static bool gmc_v8_0_is_idle(void *handle) 1264 { 1265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1266 u32 tmp = RREG32(mmSRBM_STATUS); 1267 1268 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1269 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1270 return false; 1271 1272 return true; 1273 } 1274 1275 static int gmc_v8_0_wait_for_idle(void *handle) 1276 { 1277 unsigned i; 1278 u32 tmp; 1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1280 1281 for (i = 0; i < adev->usec_timeout; i++) { 1282 /* read MC_STATUS */ 1283 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1284 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1285 SRBM_STATUS__MCC_BUSY_MASK | 1286 SRBM_STATUS__MCD_BUSY_MASK | 1287 SRBM_STATUS__VMC_BUSY_MASK | 1288 SRBM_STATUS__VMC1_BUSY_MASK); 1289 if (!tmp) 1290 return 0; 1291 udelay(1); 1292 } 1293 return -ETIMEDOUT; 1294 1295 } 1296 1297 static bool gmc_v8_0_check_soft_reset(void *handle) 1298 { 1299 u32 srbm_soft_reset = 0; 1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1301 u32 tmp = RREG32(mmSRBM_STATUS); 1302 1303 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1304 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1305 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1306 1307 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1308 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1309 if (!(adev->flags & AMD_IS_APU)) 1310 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1311 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1312 } 1313 if (srbm_soft_reset) { 1314 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1315 return true; 1316 } else { 1317 adev->gmc.srbm_soft_reset = 0; 1318 return false; 1319 } 1320 } 1321 1322 static int gmc_v8_0_pre_soft_reset(void *handle) 1323 { 1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1325 1326 if (!adev->gmc.srbm_soft_reset) 1327 return 0; 1328 1329 gmc_v8_0_mc_stop(adev); 1330 if (gmc_v8_0_wait_for_idle(adev)) { 1331 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1332 } 1333 1334 return 0; 1335 } 1336 1337 static int gmc_v8_0_soft_reset(void *handle) 1338 { 1339 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1340 u32 srbm_soft_reset; 1341 1342 if (!adev->gmc.srbm_soft_reset) 1343 return 0; 1344 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1345 1346 if (srbm_soft_reset) { 1347 u32 tmp; 1348 1349 tmp = RREG32(mmSRBM_SOFT_RESET); 1350 tmp |= srbm_soft_reset; 1351 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1352 WREG32(mmSRBM_SOFT_RESET, tmp); 1353 tmp = RREG32(mmSRBM_SOFT_RESET); 1354 1355 udelay(50); 1356 1357 tmp &= ~srbm_soft_reset; 1358 WREG32(mmSRBM_SOFT_RESET, tmp); 1359 tmp = RREG32(mmSRBM_SOFT_RESET); 1360 1361 /* Wait a little for things to settle down */ 1362 udelay(50); 1363 } 1364 1365 return 0; 1366 } 1367 1368 static int gmc_v8_0_post_soft_reset(void *handle) 1369 { 1370 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1371 1372 if (!adev->gmc.srbm_soft_reset) 1373 return 0; 1374 1375 gmc_v8_0_mc_resume(adev); 1376 return 0; 1377 } 1378 1379 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1380 struct amdgpu_irq_src *src, 1381 unsigned type, 1382 enum amdgpu_interrupt_state state) 1383 { 1384 u32 tmp; 1385 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1386 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1387 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1388 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1389 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1390 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1391 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1392 1393 switch (state) { 1394 case AMDGPU_IRQ_STATE_DISABLE: 1395 /* system context */ 1396 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1397 tmp &= ~bits; 1398 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1399 /* VMs */ 1400 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1401 tmp &= ~bits; 1402 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1403 break; 1404 case AMDGPU_IRQ_STATE_ENABLE: 1405 /* system context */ 1406 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1407 tmp |= bits; 1408 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1409 /* VMs */ 1410 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1411 tmp |= bits; 1412 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1413 break; 1414 default: 1415 break; 1416 } 1417 1418 return 0; 1419 } 1420 1421 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1422 struct amdgpu_irq_src *source, 1423 struct amdgpu_iv_entry *entry) 1424 { 1425 u32 addr, status, mc_client, vmid; 1426 1427 if (amdgpu_sriov_vf(adev)) { 1428 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1429 entry->src_id, entry->src_data[0]); 1430 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1431 return 0; 1432 } 1433 1434 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1435 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1436 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1437 /* reset addr and status */ 1438 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1439 1440 if (!addr && !status) 1441 return 0; 1442 1443 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1444 gmc_v8_0_set_fault_enable_default(adev, false); 1445 1446 if (printk_ratelimit()) { 1447 struct amdgpu_task_info task_info = { 0 }; 1448 1449 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1450 1451 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n", 1452 entry->src_id, entry->src_data[0], task_info.process_name, 1453 task_info.tgid, task_info.task_name, task_info.pid); 1454 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1455 addr); 1456 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1457 status); 1458 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1459 entry->pasid); 1460 } 1461 1462 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1463 VMID); 1464 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1465 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1466 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1467 u32 protections = REG_GET_FIELD(status, 1468 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1469 PROTECTIONS); 1470 1471 info->vmid = vmid; 1472 info->mc_id = REG_GET_FIELD(status, 1473 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1474 MEMORY_CLIENT_ID); 1475 info->status = status; 1476 info->page_addr = addr; 1477 info->prot_valid = protections & 0x7 ? true : false; 1478 info->prot_read = protections & 0x8 ? true : false; 1479 info->prot_write = protections & 0x10 ? true : false; 1480 info->prot_exec = protections & 0x20 ? true : false; 1481 mb(); 1482 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1483 } 1484 1485 return 0; 1486 } 1487 1488 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1489 bool enable) 1490 { 1491 uint32_t data; 1492 1493 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1494 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1495 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1496 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1497 1498 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1499 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1500 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1501 1502 data = RREG32(mmMC_HUB_MISC_VM_CG); 1503 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1504 WREG32(mmMC_HUB_MISC_VM_CG, data); 1505 1506 data = RREG32(mmMC_XPB_CLK_GAT); 1507 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1508 WREG32(mmMC_XPB_CLK_GAT, data); 1509 1510 data = RREG32(mmATC_MISC_CG); 1511 data |= ATC_MISC_CG__ENABLE_MASK; 1512 WREG32(mmATC_MISC_CG, data); 1513 1514 data = RREG32(mmMC_CITF_MISC_WR_CG); 1515 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1516 WREG32(mmMC_CITF_MISC_WR_CG, data); 1517 1518 data = RREG32(mmMC_CITF_MISC_RD_CG); 1519 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1520 WREG32(mmMC_CITF_MISC_RD_CG, data); 1521 1522 data = RREG32(mmMC_CITF_MISC_VM_CG); 1523 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1524 WREG32(mmMC_CITF_MISC_VM_CG, data); 1525 1526 data = RREG32(mmVM_L2_CG); 1527 data |= VM_L2_CG__ENABLE_MASK; 1528 WREG32(mmVM_L2_CG, data); 1529 } else { 1530 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1531 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1532 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1533 1534 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1535 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1536 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1537 1538 data = RREG32(mmMC_HUB_MISC_VM_CG); 1539 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1540 WREG32(mmMC_HUB_MISC_VM_CG, data); 1541 1542 data = RREG32(mmMC_XPB_CLK_GAT); 1543 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1544 WREG32(mmMC_XPB_CLK_GAT, data); 1545 1546 data = RREG32(mmATC_MISC_CG); 1547 data &= ~ATC_MISC_CG__ENABLE_MASK; 1548 WREG32(mmATC_MISC_CG, data); 1549 1550 data = RREG32(mmMC_CITF_MISC_WR_CG); 1551 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1552 WREG32(mmMC_CITF_MISC_WR_CG, data); 1553 1554 data = RREG32(mmMC_CITF_MISC_RD_CG); 1555 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1556 WREG32(mmMC_CITF_MISC_RD_CG, data); 1557 1558 data = RREG32(mmMC_CITF_MISC_VM_CG); 1559 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1560 WREG32(mmMC_CITF_MISC_VM_CG, data); 1561 1562 data = RREG32(mmVM_L2_CG); 1563 data &= ~VM_L2_CG__ENABLE_MASK; 1564 WREG32(mmVM_L2_CG, data); 1565 } 1566 } 1567 1568 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1569 bool enable) 1570 { 1571 uint32_t data; 1572 1573 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1574 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1575 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1576 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1577 1578 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1579 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1580 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1581 1582 data = RREG32(mmMC_HUB_MISC_VM_CG); 1583 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1584 WREG32(mmMC_HUB_MISC_VM_CG, data); 1585 1586 data = RREG32(mmMC_XPB_CLK_GAT); 1587 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1588 WREG32(mmMC_XPB_CLK_GAT, data); 1589 1590 data = RREG32(mmATC_MISC_CG); 1591 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1592 WREG32(mmATC_MISC_CG, data); 1593 1594 data = RREG32(mmMC_CITF_MISC_WR_CG); 1595 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1596 WREG32(mmMC_CITF_MISC_WR_CG, data); 1597 1598 data = RREG32(mmMC_CITF_MISC_RD_CG); 1599 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1600 WREG32(mmMC_CITF_MISC_RD_CG, data); 1601 1602 data = RREG32(mmMC_CITF_MISC_VM_CG); 1603 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1604 WREG32(mmMC_CITF_MISC_VM_CG, data); 1605 1606 data = RREG32(mmVM_L2_CG); 1607 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1608 WREG32(mmVM_L2_CG, data); 1609 } else { 1610 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1611 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1612 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1613 1614 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1615 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1616 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1617 1618 data = RREG32(mmMC_HUB_MISC_VM_CG); 1619 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1620 WREG32(mmMC_HUB_MISC_VM_CG, data); 1621 1622 data = RREG32(mmMC_XPB_CLK_GAT); 1623 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1624 WREG32(mmMC_XPB_CLK_GAT, data); 1625 1626 data = RREG32(mmATC_MISC_CG); 1627 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1628 WREG32(mmATC_MISC_CG, data); 1629 1630 data = RREG32(mmMC_CITF_MISC_WR_CG); 1631 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1632 WREG32(mmMC_CITF_MISC_WR_CG, data); 1633 1634 data = RREG32(mmMC_CITF_MISC_RD_CG); 1635 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1636 WREG32(mmMC_CITF_MISC_RD_CG, data); 1637 1638 data = RREG32(mmMC_CITF_MISC_VM_CG); 1639 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1640 WREG32(mmMC_CITF_MISC_VM_CG, data); 1641 1642 data = RREG32(mmVM_L2_CG); 1643 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1644 WREG32(mmVM_L2_CG, data); 1645 } 1646 } 1647 1648 static int gmc_v8_0_set_clockgating_state(void *handle, 1649 enum amd_clockgating_state state) 1650 { 1651 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1652 1653 if (amdgpu_sriov_vf(adev)) 1654 return 0; 1655 1656 switch (adev->asic_type) { 1657 case CHIP_FIJI: 1658 fiji_update_mc_medium_grain_clock_gating(adev, 1659 state == AMD_CG_STATE_GATE); 1660 fiji_update_mc_light_sleep(adev, 1661 state == AMD_CG_STATE_GATE); 1662 break; 1663 default: 1664 break; 1665 } 1666 return 0; 1667 } 1668 1669 static int gmc_v8_0_set_powergating_state(void *handle, 1670 enum amd_powergating_state state) 1671 { 1672 return 0; 1673 } 1674 1675 static void gmc_v8_0_get_clockgating_state(void *handle, u32 *flags) 1676 { 1677 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1678 int data; 1679 1680 if (amdgpu_sriov_vf(adev)) 1681 *flags = 0; 1682 1683 /* AMD_CG_SUPPORT_MC_MGCG */ 1684 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1685 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1686 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1687 1688 /* AMD_CG_SUPPORT_MC_LS */ 1689 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1690 *flags |= AMD_CG_SUPPORT_MC_LS; 1691 } 1692 1693 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1694 .name = "gmc_v8_0", 1695 .early_init = gmc_v8_0_early_init, 1696 .late_init = gmc_v8_0_late_init, 1697 .sw_init = gmc_v8_0_sw_init, 1698 .sw_fini = gmc_v8_0_sw_fini, 1699 .hw_init = gmc_v8_0_hw_init, 1700 .hw_fini = gmc_v8_0_hw_fini, 1701 .suspend = gmc_v8_0_suspend, 1702 .resume = gmc_v8_0_resume, 1703 .is_idle = gmc_v8_0_is_idle, 1704 .wait_for_idle = gmc_v8_0_wait_for_idle, 1705 .check_soft_reset = gmc_v8_0_check_soft_reset, 1706 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1707 .soft_reset = gmc_v8_0_soft_reset, 1708 .post_soft_reset = gmc_v8_0_post_soft_reset, 1709 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1710 .set_powergating_state = gmc_v8_0_set_powergating_state, 1711 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1712 }; 1713 1714 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1715 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1716 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1717 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1718 .set_pte_pde = gmc_v8_0_set_pte_pde, 1719 .set_prt = gmc_v8_0_set_prt, 1720 .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags, 1721 .get_vm_pde = gmc_v8_0_get_vm_pde 1722 }; 1723 1724 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1725 .set = gmc_v8_0_vm_fault_interrupt_state, 1726 .process = gmc_v8_0_process_interrupt, 1727 }; 1728 1729 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1730 { 1731 if (adev->gmc.gmc_funcs == NULL) 1732 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1733 } 1734 1735 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1736 { 1737 adev->gmc.vm_fault.num_types = 1; 1738 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1739 } 1740 1741 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1742 { 1743 .type = AMD_IP_BLOCK_TYPE_GMC, 1744 .major = 8, 1745 .minor = 0, 1746 .rev = 0, 1747 .funcs = &gmc_v8_0_ip_funcs, 1748 }; 1749 1750 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1751 { 1752 .type = AMD_IP_BLOCK_TYPE_GMC, 1753 .major = 8, 1754 .minor = 1, 1755 .rev = 0, 1756 .funcs = &gmc_v8_0_ip_funcs, 1757 }; 1758 1759 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1760 { 1761 .type = AMD_IP_BLOCK_TYPE_GMC, 1762 .major = 8, 1763 .minor = 5, 1764 .rev = 0, 1765 .funcs = &gmc_v8_0_ip_funcs, 1766 }; 1767