1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "gmc_v8_0.h" 27 #include "amdgpu_ucode.h" 28 29 #include "gmc/gmc_8_1_d.h" 30 #include "gmc/gmc_8_1_sh_mask.h" 31 32 #include "bif/bif_5_0_d.h" 33 #include "bif/bif_5_0_sh_mask.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "vid.h" 39 #include "vi.h" 40 41 42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); 43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 44 45 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 46 47 static const u32 golden_settings_tonga_a11[] = 48 { 49 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 50 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 51 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 52 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 53 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 54 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 55 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 56 }; 57 58 static const u32 tonga_mgcg_cgcg_init[] = 59 { 60 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 61 }; 62 63 static const u32 golden_settings_fiji_a10[] = 64 { 65 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 66 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 67 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 68 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 69 }; 70 71 static const u32 fiji_mgcg_cgcg_init[] = 72 { 73 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 74 }; 75 76 static const u32 cz_mgcg_cgcg_init[] = 77 { 78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 79 }; 80 81 static const u32 stoney_mgcg_cgcg_init[] = 82 { 83 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 84 }; 85 86 87 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 88 { 89 switch (adev->asic_type) { 90 case CHIP_FIJI: 91 amdgpu_program_register_sequence(adev, 92 fiji_mgcg_cgcg_init, 93 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 94 amdgpu_program_register_sequence(adev, 95 golden_settings_fiji_a10, 96 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 97 break; 98 case CHIP_TONGA: 99 amdgpu_program_register_sequence(adev, 100 tonga_mgcg_cgcg_init, 101 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 102 amdgpu_program_register_sequence(adev, 103 golden_settings_tonga_a11, 104 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 105 break; 106 case CHIP_CARRIZO: 107 amdgpu_program_register_sequence(adev, 108 cz_mgcg_cgcg_init, 109 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 110 break; 111 case CHIP_STONEY: 112 amdgpu_program_register_sequence(adev, 113 stoney_mgcg_cgcg_init, 114 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 115 break; 116 default: 117 break; 118 } 119 } 120 121 /** 122 * gmc8_mc_wait_for_idle - wait for MC idle callback. 123 * 124 * @adev: amdgpu_device pointer 125 * 126 * Wait for the MC (memory controller) to be idle. 127 * (evergreen+). 128 * Returns 0 if the MC is idle, -1 if not. 129 */ 130 int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev) 131 { 132 unsigned i; 133 u32 tmp; 134 135 for (i = 0; i < adev->usec_timeout; i++) { 136 /* read MC_STATUS */ 137 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK | 138 SRBM_STATUS__MCB_BUSY_MASK | 139 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 140 SRBM_STATUS__MCC_BUSY_MASK | 141 SRBM_STATUS__MCD_BUSY_MASK | 142 SRBM_STATUS__VMC1_BUSY_MASK); 143 if (!tmp) 144 return 0; 145 udelay(1); 146 } 147 return -1; 148 } 149 150 void gmc_v8_0_mc_stop(struct amdgpu_device *adev, 151 struct amdgpu_mode_mc_save *save) 152 { 153 u32 blackout; 154 155 if (adev->mode_info.num_crtc) 156 amdgpu_display_stop_mc_access(adev, save); 157 158 amdgpu_asic_wait_for_mc_idle(adev); 159 160 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 161 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 162 /* Block CPU access */ 163 WREG32(mmBIF_FB_EN, 0); 164 /* blackout the MC */ 165 blackout = REG_SET_FIELD(blackout, 166 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 167 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 168 } 169 /* wait for the MC to settle */ 170 udelay(100); 171 } 172 173 void gmc_v8_0_mc_resume(struct amdgpu_device *adev, 174 struct amdgpu_mode_mc_save *save) 175 { 176 u32 tmp; 177 178 /* unblackout the MC */ 179 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 180 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 181 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 182 /* allow CPU access */ 183 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 184 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 185 WREG32(mmBIF_FB_EN, tmp); 186 187 if (adev->mode_info.num_crtc) 188 amdgpu_display_resume_mc_access(adev, save); 189 } 190 191 /** 192 * gmc_v8_0_init_microcode - load ucode images from disk 193 * 194 * @adev: amdgpu_device pointer 195 * 196 * Use the firmware interface to load the ucode images into 197 * the driver (not loaded into hw). 198 * Returns 0 on success, error on failure. 199 */ 200 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 201 { 202 const char *chip_name; 203 char fw_name[30]; 204 int err; 205 206 DRM_DEBUG("\n"); 207 208 switch (adev->asic_type) { 209 case CHIP_TONGA: 210 chip_name = "tonga"; 211 break; 212 case CHIP_FIJI: 213 case CHIP_CARRIZO: 214 case CHIP_STONEY: 215 return 0; 216 default: BUG(); 217 } 218 219 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 220 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 221 if (err) 222 goto out; 223 err = amdgpu_ucode_validate(adev->mc.fw); 224 225 out: 226 if (err) { 227 printk(KERN_ERR 228 "mc: Failed to load firmware \"%s\"\n", 229 fw_name); 230 release_firmware(adev->mc.fw); 231 adev->mc.fw = NULL; 232 } 233 return err; 234 } 235 236 /** 237 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw 238 * 239 * @adev: amdgpu_device pointer 240 * 241 * Load the GDDR MC ucode into the hw (CIK). 242 * Returns 0 on success, error on failure. 243 */ 244 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev) 245 { 246 const struct mc_firmware_header_v1_0 *hdr; 247 const __le32 *fw_data = NULL; 248 const __le32 *io_mc_regs = NULL; 249 u32 running, blackout = 0; 250 int i, ucode_size, regs_size; 251 252 if (!adev->mc.fw) 253 return -EINVAL; 254 255 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 256 amdgpu_ucode_print_mc_hdr(&hdr->header); 257 258 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 259 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 260 io_mc_regs = (const __le32 *) 261 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 262 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 263 fw_data = (const __le32 *) 264 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 265 266 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 267 268 if (running == 0) { 269 if (running) { 270 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 271 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 272 } 273 274 /* reset the engine and set to writable */ 275 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 276 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 277 278 /* load mc io regs */ 279 for (i = 0; i < regs_size; i++) { 280 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 281 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 282 } 283 /* load the MC ucode */ 284 for (i = 0; i < ucode_size; i++) 285 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 286 287 /* put the engine back into the active state */ 288 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 289 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 290 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 291 292 /* wait for training to complete */ 293 for (i = 0; i < adev->usec_timeout; i++) { 294 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 295 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 296 break; 297 udelay(1); 298 } 299 for (i = 0; i < adev->usec_timeout; i++) { 300 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 301 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 302 break; 303 udelay(1); 304 } 305 306 if (running) 307 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 308 } 309 310 return 0; 311 } 312 313 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 314 struct amdgpu_mc *mc) 315 { 316 if (mc->mc_vram_size > 0xFFC0000000ULL) { 317 /* leave room for at least 1024M GTT */ 318 dev_warn(adev->dev, "limiting VRAM\n"); 319 mc->real_vram_size = 0xFFC0000000ULL; 320 mc->mc_vram_size = 0xFFC0000000ULL; 321 } 322 amdgpu_vram_location(adev, &adev->mc, 0); 323 adev->mc.gtt_base_align = 0; 324 amdgpu_gtt_location(adev, mc); 325 } 326 327 /** 328 * gmc_v8_0_mc_program - program the GPU memory controller 329 * 330 * @adev: amdgpu_device pointer 331 * 332 * Set the location of vram, gart, and AGP in the GPU's 333 * physical address space (CIK). 334 */ 335 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 336 { 337 struct amdgpu_mode_mc_save save; 338 u32 tmp; 339 int i, j; 340 341 /* Initialize HDP */ 342 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 343 WREG32((0xb05 + j), 0x00000000); 344 WREG32((0xb06 + j), 0x00000000); 345 WREG32((0xb07 + j), 0x00000000); 346 WREG32((0xb08 + j), 0x00000000); 347 WREG32((0xb09 + j), 0x00000000); 348 } 349 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 350 351 if (adev->mode_info.num_crtc) 352 amdgpu_display_set_vga_render_state(adev, false); 353 354 gmc_v8_0_mc_stop(adev, &save); 355 if (amdgpu_asic_wait_for_mc_idle(adev)) { 356 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 357 } 358 /* Update configuration */ 359 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 360 adev->mc.vram_start >> 12); 361 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 362 adev->mc.vram_end >> 12); 363 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 364 adev->vram_scratch.gpu_addr >> 12); 365 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 366 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 367 WREG32(mmMC_VM_FB_LOCATION, tmp); 368 /* XXX double check these! */ 369 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 370 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 371 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 372 WREG32(mmMC_VM_AGP_BASE, 0); 373 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 374 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 375 if (amdgpu_asic_wait_for_mc_idle(adev)) { 376 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 377 } 378 gmc_v8_0_mc_resume(adev, &save); 379 380 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 381 382 tmp = RREG32(mmHDP_MISC_CNTL); 383 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); 384 WREG32(mmHDP_MISC_CNTL, tmp); 385 386 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 387 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 388 } 389 390 /** 391 * gmc_v8_0_mc_init - initialize the memory controller driver params 392 * 393 * @adev: amdgpu_device pointer 394 * 395 * Look up the amount of vram, vram width, and decide how to place 396 * vram and gart within the GPU's physical address space (CIK). 397 * Returns 0 for success. 398 */ 399 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 400 { 401 u32 tmp; 402 int chansize, numchan; 403 404 /* Get VRAM informations */ 405 tmp = RREG32(mmMC_ARB_RAMCFG); 406 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 407 chansize = 64; 408 } else { 409 chansize = 32; 410 } 411 tmp = RREG32(mmMC_SHARED_CHMAP); 412 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 413 case 0: 414 default: 415 numchan = 1; 416 break; 417 case 1: 418 numchan = 2; 419 break; 420 case 2: 421 numchan = 4; 422 break; 423 case 3: 424 numchan = 8; 425 break; 426 case 4: 427 numchan = 3; 428 break; 429 case 5: 430 numchan = 6; 431 break; 432 case 6: 433 numchan = 10; 434 break; 435 case 7: 436 numchan = 12; 437 break; 438 case 8: 439 numchan = 16; 440 break; 441 } 442 adev->mc.vram_width = numchan * chansize; 443 /* Could aper size report 0 ? */ 444 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 445 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 446 /* size in MB on si */ 447 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 448 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 449 adev->mc.visible_vram_size = adev->mc.aper_size; 450 451 /* In case the PCI BAR is larger than the actual amount of vram */ 452 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 453 adev->mc.visible_vram_size = adev->mc.real_vram_size; 454 455 /* unless the user had overridden it, set the gart 456 * size equal to the 1024 or vram, whichever is larger. 457 */ 458 if (amdgpu_gart_size == -1) 459 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 460 else 461 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 462 463 gmc_v8_0_vram_gtt_location(adev, &adev->mc); 464 465 return 0; 466 } 467 468 /* 469 * GART 470 * VMID 0 is the physical GPU addresses as used by the kernel. 471 * VMIDs 1-15 are used for userspace clients and are handled 472 * by the amdgpu vm/hsa code. 473 */ 474 475 /** 476 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback 477 * 478 * @adev: amdgpu_device pointer 479 * @vmid: vm instance to flush 480 * 481 * Flush the TLB for the requested page table (CIK). 482 */ 483 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 484 uint32_t vmid) 485 { 486 /* flush hdp cache */ 487 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 488 489 /* bits 0-15 are the VM contexts0-15 */ 490 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 491 } 492 493 /** 494 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO 495 * 496 * @adev: amdgpu_device pointer 497 * @cpu_pt_addr: cpu address of the page table 498 * @gpu_page_idx: entry in the page table to update 499 * @addr: dst addr to write into pte/pde 500 * @flags: access flags 501 * 502 * Update the page tables using the CPU. 503 */ 504 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, 505 void *cpu_pt_addr, 506 uint32_t gpu_page_idx, 507 uint64_t addr, 508 uint32_t flags) 509 { 510 void __iomem *ptr = (void *)cpu_pt_addr; 511 uint64_t value; 512 513 /* 514 * PTE format on VI: 515 * 63:40 reserved 516 * 39:12 4k physical page base address 517 * 11:7 fragment 518 * 6 write 519 * 5 read 520 * 4 exe 521 * 3 reserved 522 * 2 snooped 523 * 1 system 524 * 0 valid 525 * 526 * PDE format on VI: 527 * 63:59 block fragment size 528 * 58:40 reserved 529 * 39:1 physical base address of PTE 530 * bits 5:1 must be 0. 531 * 0 valid 532 */ 533 value = addr & 0x000000FFFFFFF000ULL; 534 value |= flags; 535 writeq(value, ptr + (gpu_page_idx * 8)); 536 537 return 0; 538 } 539 540 /** 541 * gmc_v8_0_set_fault_enable_default - update VM fault handling 542 * 543 * @adev: amdgpu_device pointer 544 * @value: true redirects VM faults to the default page 545 */ 546 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 547 bool value) 548 { 549 u32 tmp; 550 551 tmp = RREG32(mmVM_CONTEXT1_CNTL); 552 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 553 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 554 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 555 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 556 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 557 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 558 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 559 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 560 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 561 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 562 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 563 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 564 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 565 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 566 WREG32(mmVM_CONTEXT1_CNTL, tmp); 567 } 568 569 /** 570 * gmc_v8_0_gart_enable - gart enable 571 * 572 * @adev: amdgpu_device pointer 573 * 574 * This sets up the TLBs, programs the page tables for VMID0, 575 * sets up the hw for VMIDs 1-15 which are allocated on 576 * demand, and sets up the global locations for the LDS, GDS, 577 * and GPUVM for FSA64 clients (CIK). 578 * Returns 0 for success, errors for failure. 579 */ 580 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 581 { 582 int r, i; 583 u32 tmp; 584 585 if (adev->gart.robj == NULL) { 586 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 587 return -EINVAL; 588 } 589 r = amdgpu_gart_table_vram_pin(adev); 590 if (r) 591 return r; 592 /* Setup TLB control */ 593 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 594 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 595 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 596 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 597 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 598 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 599 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 600 /* Setup L2 cache */ 601 tmp = RREG32(mmVM_L2_CNTL); 602 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 603 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 604 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 605 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 606 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 607 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 608 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 609 WREG32(mmVM_L2_CNTL, tmp); 610 tmp = RREG32(mmVM_L2_CNTL2); 611 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 612 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 613 WREG32(mmVM_L2_CNTL2, tmp); 614 tmp = RREG32(mmVM_L2_CNTL3); 615 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 616 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); 617 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); 618 WREG32(mmVM_L2_CNTL3, tmp); 619 /* XXX: set to enable PTE/PDE in system memory */ 620 tmp = RREG32(mmVM_L2_CNTL4); 621 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 622 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 623 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 626 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 627 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 633 WREG32(mmVM_L2_CNTL4, tmp); 634 /* setup context0 */ 635 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 636 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 637 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 638 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 639 (u32)(adev->dummy_page.addr >> 12)); 640 WREG32(mmVM_CONTEXT0_CNTL2, 0); 641 tmp = RREG32(mmVM_CONTEXT0_CNTL); 642 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 643 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 644 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 645 WREG32(mmVM_CONTEXT0_CNTL, tmp); 646 647 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 648 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 649 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 650 651 /* empty context1-15 */ 652 /* FIXME start with 4G, once using 2 level pt switch to full 653 * vm size space 654 */ 655 /* set vm size, must be a multiple of 4 */ 656 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 657 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 658 for (i = 1; i < 16; i++) { 659 if (i < 8) 660 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 661 adev->gart.table_addr >> 12); 662 else 663 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 664 adev->gart.table_addr >> 12); 665 } 666 667 /* enable context1-15 */ 668 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 669 (u32)(adev->dummy_page.addr >> 12)); 670 WREG32(mmVM_CONTEXT1_CNTL2, 4); 671 tmp = RREG32(mmVM_CONTEXT1_CNTL); 672 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 673 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 674 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 675 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 676 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 677 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 678 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 679 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 680 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 681 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 682 amdgpu_vm_block_size - 9); 683 WREG32(mmVM_CONTEXT1_CNTL, tmp); 684 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 685 gmc_v8_0_set_fault_enable_default(adev, false); 686 else 687 gmc_v8_0_set_fault_enable_default(adev, true); 688 689 gmc_v8_0_gart_flush_gpu_tlb(adev, 0); 690 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 691 (unsigned)(adev->mc.gtt_size >> 20), 692 (unsigned long long)adev->gart.table_addr); 693 adev->gart.ready = true; 694 return 0; 695 } 696 697 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 698 { 699 int r; 700 701 if (adev->gart.robj) { 702 WARN(1, "R600 PCIE GART already initialized\n"); 703 return 0; 704 } 705 /* Initialize common gart structure */ 706 r = amdgpu_gart_init(adev); 707 if (r) 708 return r; 709 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 710 return amdgpu_gart_table_vram_alloc(adev); 711 } 712 713 /** 714 * gmc_v8_0_gart_disable - gart disable 715 * 716 * @adev: amdgpu_device pointer 717 * 718 * This disables all VM page table (CIK). 719 */ 720 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 721 { 722 u32 tmp; 723 724 /* Disable all tables */ 725 WREG32(mmVM_CONTEXT0_CNTL, 0); 726 WREG32(mmVM_CONTEXT1_CNTL, 0); 727 /* Setup TLB control */ 728 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 729 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 730 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 731 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 732 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 733 /* Setup L2 cache */ 734 tmp = RREG32(mmVM_L2_CNTL); 735 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 736 WREG32(mmVM_L2_CNTL, tmp); 737 WREG32(mmVM_L2_CNTL2, 0); 738 amdgpu_gart_table_vram_unpin(adev); 739 } 740 741 /** 742 * gmc_v8_0_gart_fini - vm fini callback 743 * 744 * @adev: amdgpu_device pointer 745 * 746 * Tears down the driver GART/VM setup (CIK). 747 */ 748 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) 749 { 750 amdgpu_gart_table_vram_free(adev); 751 amdgpu_gart_fini(adev); 752 } 753 754 /* 755 * vm 756 * VMID 0 is the physical GPU addresses as used by the kernel. 757 * VMIDs 1-15 are used for userspace clients and are handled 758 * by the amdgpu vm/hsa code. 759 */ 760 /** 761 * gmc_v8_0_vm_init - cik vm init callback 762 * 763 * @adev: amdgpu_device pointer 764 * 765 * Inits cik specific vm parameters (number of VMs, base of vram for 766 * VMIDs 1-15) (CIK). 767 * Returns 0 for success. 768 */ 769 static int gmc_v8_0_vm_init(struct amdgpu_device *adev) 770 { 771 /* 772 * number of VMs 773 * VMID 0 is reserved for System 774 * amdgpu graphics/compute will use VMIDs 1-7 775 * amdkfd will use VMIDs 8-15 776 */ 777 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 778 amdgpu_vm_manager_init(adev); 779 780 /* base offset of vram pages */ 781 if (adev->flags & AMD_IS_APU) { 782 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 783 tmp <<= 22; 784 adev->vm_manager.vram_base_offset = tmp; 785 } else 786 adev->vm_manager.vram_base_offset = 0; 787 788 return 0; 789 } 790 791 /** 792 * gmc_v8_0_vm_fini - cik vm fini callback 793 * 794 * @adev: amdgpu_device pointer 795 * 796 * Tear down any asic specific VM setup (CIK). 797 */ 798 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev) 799 { 800 } 801 802 /** 803 * gmc_v8_0_vm_decode_fault - print human readable fault info 804 * 805 * @adev: amdgpu_device pointer 806 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 807 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 808 * 809 * Print human readable fault information (CIK). 810 */ 811 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, 812 u32 status, u32 addr, u32 mc_client) 813 { 814 u32 mc_id; 815 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 816 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 817 PROTECTIONS); 818 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 819 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 820 821 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 822 MEMORY_CLIENT_ID); 823 824 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 825 protections, vmid, addr, 826 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 827 MEMORY_CLIENT_RW) ? 828 "write" : "read", block, mc_client, mc_id); 829 } 830 831 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 832 { 833 switch (mc_seq_vram_type) { 834 case MC_SEQ_MISC0__MT__GDDR1: 835 return AMDGPU_VRAM_TYPE_GDDR1; 836 case MC_SEQ_MISC0__MT__DDR2: 837 return AMDGPU_VRAM_TYPE_DDR2; 838 case MC_SEQ_MISC0__MT__GDDR3: 839 return AMDGPU_VRAM_TYPE_GDDR3; 840 case MC_SEQ_MISC0__MT__GDDR4: 841 return AMDGPU_VRAM_TYPE_GDDR4; 842 case MC_SEQ_MISC0__MT__GDDR5: 843 return AMDGPU_VRAM_TYPE_GDDR5; 844 case MC_SEQ_MISC0__MT__HBM: 845 return AMDGPU_VRAM_TYPE_HBM; 846 case MC_SEQ_MISC0__MT__DDR3: 847 return AMDGPU_VRAM_TYPE_DDR3; 848 default: 849 return AMDGPU_VRAM_TYPE_UNKNOWN; 850 } 851 } 852 853 static int gmc_v8_0_early_init(void *handle) 854 { 855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 856 857 gmc_v8_0_set_gart_funcs(adev); 858 gmc_v8_0_set_irq_funcs(adev); 859 860 if (adev->flags & AMD_IS_APU) { 861 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 862 } else { 863 u32 tmp = RREG32(mmMC_SEQ_MISC0); 864 tmp &= MC_SEQ_MISC0__MT__MASK; 865 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); 866 } 867 868 return 0; 869 } 870 871 static int gmc_v8_0_late_init(void *handle) 872 { 873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 874 875 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 876 } 877 878 static int gmc_v8_0_sw_init(void *handle) 879 { 880 int r; 881 int dma_bits; 882 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 883 884 r = amdgpu_gem_init(adev); 885 if (r) 886 return r; 887 888 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); 889 if (r) 890 return r; 891 892 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); 893 if (r) 894 return r; 895 896 /* Adjust VM size here. 897 * Currently set to 4GB ((1 << 20) 4k pages). 898 * Max GPUVM size for cayman and SI is 40 bits. 899 */ 900 adev->vm_manager.max_pfn = amdgpu_vm_size << 18; 901 902 /* Set the internal MC address mask 903 * This is the max address of the GPU's 904 * internal address space. 905 */ 906 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 907 908 /* set DMA mask + need_dma32 flags. 909 * PCIE - can handle 40-bits. 910 * IGP - can handle 40-bits 911 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 912 */ 913 adev->need_dma32 = false; 914 dma_bits = adev->need_dma32 ? 32 : 40; 915 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 916 if (r) { 917 adev->need_dma32 = true; 918 dma_bits = 32; 919 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 920 } 921 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 922 if (r) { 923 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 924 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 925 } 926 927 r = gmc_v8_0_init_microcode(adev); 928 if (r) { 929 DRM_ERROR("Failed to load mc firmware!\n"); 930 return r; 931 } 932 933 r = gmc_v8_0_mc_init(adev); 934 if (r) 935 return r; 936 937 /* Memory manager */ 938 r = amdgpu_bo_init(adev); 939 if (r) 940 return r; 941 942 r = gmc_v8_0_gart_init(adev); 943 if (r) 944 return r; 945 946 if (!adev->vm_manager.enabled) { 947 r = gmc_v8_0_vm_init(adev); 948 if (r) { 949 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 950 return r; 951 } 952 adev->vm_manager.enabled = true; 953 } 954 955 return r; 956 } 957 958 static int gmc_v8_0_sw_fini(void *handle) 959 { 960 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 961 962 if (adev->vm_manager.enabled) { 963 amdgpu_vm_manager_fini(adev); 964 gmc_v8_0_vm_fini(adev); 965 adev->vm_manager.enabled = false; 966 } 967 gmc_v8_0_gart_fini(adev); 968 amdgpu_gem_fini(adev); 969 amdgpu_bo_fini(adev); 970 971 return 0; 972 } 973 974 static int gmc_v8_0_hw_init(void *handle) 975 { 976 int r; 977 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 978 979 gmc_v8_0_init_golden_registers(adev); 980 981 gmc_v8_0_mc_program(adev); 982 983 if (adev->asic_type == CHIP_TONGA) { 984 r = gmc_v8_0_mc_load_microcode(adev); 985 if (r) { 986 DRM_ERROR("Failed to load MC firmware!\n"); 987 return r; 988 } 989 } 990 991 r = gmc_v8_0_gart_enable(adev); 992 if (r) 993 return r; 994 995 return r; 996 } 997 998 static int gmc_v8_0_hw_fini(void *handle) 999 { 1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1001 1002 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1003 gmc_v8_0_gart_disable(adev); 1004 1005 return 0; 1006 } 1007 1008 static int gmc_v8_0_suspend(void *handle) 1009 { 1010 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1011 1012 if (adev->vm_manager.enabled) { 1013 gmc_v8_0_vm_fini(adev); 1014 adev->vm_manager.enabled = false; 1015 } 1016 gmc_v8_0_hw_fini(adev); 1017 1018 return 0; 1019 } 1020 1021 static int gmc_v8_0_resume(void *handle) 1022 { 1023 int r; 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1025 1026 r = gmc_v8_0_hw_init(adev); 1027 if (r) 1028 return r; 1029 1030 if (!adev->vm_manager.enabled) { 1031 r = gmc_v8_0_vm_init(adev); 1032 if (r) { 1033 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 1034 return r; 1035 } 1036 adev->vm_manager.enabled = true; 1037 } 1038 1039 return r; 1040 } 1041 1042 static bool gmc_v8_0_is_idle(void *handle) 1043 { 1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1045 u32 tmp = RREG32(mmSRBM_STATUS); 1046 1047 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1048 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1049 return false; 1050 1051 return true; 1052 } 1053 1054 static int gmc_v8_0_wait_for_idle(void *handle) 1055 { 1056 unsigned i; 1057 u32 tmp; 1058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1059 1060 for (i = 0; i < adev->usec_timeout; i++) { 1061 /* read MC_STATUS */ 1062 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1063 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1064 SRBM_STATUS__MCC_BUSY_MASK | 1065 SRBM_STATUS__MCD_BUSY_MASK | 1066 SRBM_STATUS__VMC_BUSY_MASK | 1067 SRBM_STATUS__VMC1_BUSY_MASK); 1068 if (!tmp) 1069 return 0; 1070 udelay(1); 1071 } 1072 return -ETIMEDOUT; 1073 1074 } 1075 1076 static void gmc_v8_0_print_status(void *handle) 1077 { 1078 int i, j; 1079 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1080 1081 dev_info(adev->dev, "GMC 8.x registers\n"); 1082 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 1083 RREG32(mmSRBM_STATUS)); 1084 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1085 RREG32(mmSRBM_STATUS2)); 1086 1087 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1088 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); 1089 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1090 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); 1091 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n", 1092 RREG32(mmMC_VM_MX_L1_TLB_CNTL)); 1093 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n", 1094 RREG32(mmVM_L2_CNTL)); 1095 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n", 1096 RREG32(mmVM_L2_CNTL2)); 1097 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n", 1098 RREG32(mmVM_L2_CNTL3)); 1099 dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n", 1100 RREG32(mmVM_L2_CNTL4)); 1101 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n", 1102 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)); 1103 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n", 1104 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)); 1105 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", 1106 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)); 1107 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n", 1108 RREG32(mmVM_CONTEXT0_CNTL2)); 1109 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n", 1110 RREG32(mmVM_CONTEXT0_CNTL)); 1111 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n", 1112 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)); 1113 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n", 1114 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)); 1115 dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n", 1116 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)); 1117 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n", 1118 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)); 1119 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n", 1120 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)); 1121 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n", 1122 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)); 1123 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n", 1124 RREG32(mmVM_CONTEXT1_CNTL2)); 1125 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n", 1126 RREG32(mmVM_CONTEXT1_CNTL)); 1127 for (i = 0; i < 16; i++) { 1128 if (i < 8) 1129 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", 1130 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i)); 1131 else 1132 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n", 1133 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8)); 1134 } 1135 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n", 1136 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)); 1137 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n", 1138 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)); 1139 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n", 1140 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)); 1141 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n", 1142 RREG32(mmMC_VM_FB_LOCATION)); 1143 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n", 1144 RREG32(mmMC_VM_AGP_BASE)); 1145 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n", 1146 RREG32(mmMC_VM_AGP_TOP)); 1147 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n", 1148 RREG32(mmMC_VM_AGP_BOT)); 1149 1150 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n", 1151 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL)); 1152 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n", 1153 RREG32(mmHDP_NONSURFACE_BASE)); 1154 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n", 1155 RREG32(mmHDP_NONSURFACE_INFO)); 1156 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n", 1157 RREG32(mmHDP_NONSURFACE_SIZE)); 1158 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n", 1159 RREG32(mmHDP_MISC_CNTL)); 1160 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n", 1161 RREG32(mmHDP_HOST_PATH_CNTL)); 1162 1163 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 1164 dev_info(adev->dev, " %d:\n", i); 1165 dev_info(adev->dev, " 0x%04X=0x%08X\n", 1166 0xb05 + j, RREG32(0xb05 + j)); 1167 dev_info(adev->dev, " 0x%04X=0x%08X\n", 1168 0xb06 + j, RREG32(0xb06 + j)); 1169 dev_info(adev->dev, " 0x%04X=0x%08X\n", 1170 0xb07 + j, RREG32(0xb07 + j)); 1171 dev_info(adev->dev, " 0x%04X=0x%08X\n", 1172 0xb08 + j, RREG32(0xb08 + j)); 1173 dev_info(adev->dev, " 0x%04X=0x%08X\n", 1174 0xb09 + j, RREG32(0xb09 + j)); 1175 } 1176 1177 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n", 1178 RREG32(mmBIF_FB_EN)); 1179 } 1180 1181 static int gmc_v8_0_soft_reset(void *handle) 1182 { 1183 struct amdgpu_mode_mc_save save; 1184 u32 srbm_soft_reset = 0; 1185 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1186 u32 tmp = RREG32(mmSRBM_STATUS); 1187 1188 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1189 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1190 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1191 1192 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1193 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1194 if (!(adev->flags & AMD_IS_APU)) 1195 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1196 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1197 } 1198 1199 if (srbm_soft_reset) { 1200 gmc_v8_0_print_status((void *)adev); 1201 1202 gmc_v8_0_mc_stop(adev, &save); 1203 if (gmc_v8_0_wait_for_idle(adev)) { 1204 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1205 } 1206 1207 1208 tmp = RREG32(mmSRBM_SOFT_RESET); 1209 tmp |= srbm_soft_reset; 1210 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1211 WREG32(mmSRBM_SOFT_RESET, tmp); 1212 tmp = RREG32(mmSRBM_SOFT_RESET); 1213 1214 udelay(50); 1215 1216 tmp &= ~srbm_soft_reset; 1217 WREG32(mmSRBM_SOFT_RESET, tmp); 1218 tmp = RREG32(mmSRBM_SOFT_RESET); 1219 1220 /* Wait a little for things to settle down */ 1221 udelay(50); 1222 1223 gmc_v8_0_mc_resume(adev, &save); 1224 udelay(50); 1225 1226 gmc_v8_0_print_status((void *)adev); 1227 } 1228 1229 return 0; 1230 } 1231 1232 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1233 struct amdgpu_irq_src *src, 1234 unsigned type, 1235 enum amdgpu_interrupt_state state) 1236 { 1237 u32 tmp; 1238 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1239 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1240 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1241 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1242 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1243 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1244 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1245 1246 switch (state) { 1247 case AMDGPU_IRQ_STATE_DISABLE: 1248 /* system context */ 1249 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1250 tmp &= ~bits; 1251 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1252 /* VMs */ 1253 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1254 tmp &= ~bits; 1255 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1256 break; 1257 case AMDGPU_IRQ_STATE_ENABLE: 1258 /* system context */ 1259 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1260 tmp |= bits; 1261 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1262 /* VMs */ 1263 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1264 tmp |= bits; 1265 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1266 break; 1267 default: 1268 break; 1269 } 1270 1271 return 0; 1272 } 1273 1274 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1275 struct amdgpu_irq_src *source, 1276 struct amdgpu_iv_entry *entry) 1277 { 1278 u32 addr, status, mc_client; 1279 1280 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1281 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1282 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1283 /* reset addr and status */ 1284 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1285 1286 if (!addr && !status) 1287 return 0; 1288 1289 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1290 gmc_v8_0_set_fault_enable_default(adev, false); 1291 1292 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1293 entry->src_id, entry->src_data); 1294 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1295 addr); 1296 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1297 status); 1298 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); 1299 1300 return 0; 1301 } 1302 1303 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1304 bool enable) 1305 { 1306 uint32_t data; 1307 1308 if (enable) { 1309 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1310 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1311 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1312 1313 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1314 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1315 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1316 1317 data = RREG32(mmMC_HUB_MISC_VM_CG); 1318 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1319 WREG32(mmMC_HUB_MISC_VM_CG, data); 1320 1321 data = RREG32(mmMC_XPB_CLK_GAT); 1322 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1323 WREG32(mmMC_XPB_CLK_GAT, data); 1324 1325 data = RREG32(mmATC_MISC_CG); 1326 data |= ATC_MISC_CG__ENABLE_MASK; 1327 WREG32(mmATC_MISC_CG, data); 1328 1329 data = RREG32(mmMC_CITF_MISC_WR_CG); 1330 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1331 WREG32(mmMC_CITF_MISC_WR_CG, data); 1332 1333 data = RREG32(mmMC_CITF_MISC_RD_CG); 1334 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1335 WREG32(mmMC_CITF_MISC_RD_CG, data); 1336 1337 data = RREG32(mmMC_CITF_MISC_VM_CG); 1338 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1339 WREG32(mmMC_CITF_MISC_VM_CG, data); 1340 1341 data = RREG32(mmVM_L2_CG); 1342 data |= VM_L2_CG__ENABLE_MASK; 1343 WREG32(mmVM_L2_CG, data); 1344 } else { 1345 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1346 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1347 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1348 1349 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1350 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1351 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1352 1353 data = RREG32(mmMC_HUB_MISC_VM_CG); 1354 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1355 WREG32(mmMC_HUB_MISC_VM_CG, data); 1356 1357 data = RREG32(mmMC_XPB_CLK_GAT); 1358 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1359 WREG32(mmMC_XPB_CLK_GAT, data); 1360 1361 data = RREG32(mmATC_MISC_CG); 1362 data &= ~ATC_MISC_CG__ENABLE_MASK; 1363 WREG32(mmATC_MISC_CG, data); 1364 1365 data = RREG32(mmMC_CITF_MISC_WR_CG); 1366 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1367 WREG32(mmMC_CITF_MISC_WR_CG, data); 1368 1369 data = RREG32(mmMC_CITF_MISC_RD_CG); 1370 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1371 WREG32(mmMC_CITF_MISC_RD_CG, data); 1372 1373 data = RREG32(mmMC_CITF_MISC_VM_CG); 1374 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1375 WREG32(mmMC_CITF_MISC_VM_CG, data); 1376 1377 data = RREG32(mmVM_L2_CG); 1378 data &= ~VM_L2_CG__ENABLE_MASK; 1379 WREG32(mmVM_L2_CG, data); 1380 } 1381 } 1382 1383 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1384 bool enable) 1385 { 1386 uint32_t data; 1387 1388 if (enable) { 1389 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1390 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1391 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1392 1393 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1394 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1395 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1396 1397 data = RREG32(mmMC_HUB_MISC_VM_CG); 1398 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1399 WREG32(mmMC_HUB_MISC_VM_CG, data); 1400 1401 data = RREG32(mmMC_XPB_CLK_GAT); 1402 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1403 WREG32(mmMC_XPB_CLK_GAT, data); 1404 1405 data = RREG32(mmATC_MISC_CG); 1406 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1407 WREG32(mmATC_MISC_CG, data); 1408 1409 data = RREG32(mmMC_CITF_MISC_WR_CG); 1410 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1411 WREG32(mmMC_CITF_MISC_WR_CG, data); 1412 1413 data = RREG32(mmMC_CITF_MISC_RD_CG); 1414 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1415 WREG32(mmMC_CITF_MISC_RD_CG, data); 1416 1417 data = RREG32(mmMC_CITF_MISC_VM_CG); 1418 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1419 WREG32(mmMC_CITF_MISC_VM_CG, data); 1420 1421 data = RREG32(mmVM_L2_CG); 1422 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1423 WREG32(mmVM_L2_CG, data); 1424 } else { 1425 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1426 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1427 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1428 1429 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1430 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1431 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1432 1433 data = RREG32(mmMC_HUB_MISC_VM_CG); 1434 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1435 WREG32(mmMC_HUB_MISC_VM_CG, data); 1436 1437 data = RREG32(mmMC_XPB_CLK_GAT); 1438 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1439 WREG32(mmMC_XPB_CLK_GAT, data); 1440 1441 data = RREG32(mmATC_MISC_CG); 1442 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1443 WREG32(mmATC_MISC_CG, data); 1444 1445 data = RREG32(mmMC_CITF_MISC_WR_CG); 1446 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1447 WREG32(mmMC_CITF_MISC_WR_CG, data); 1448 1449 data = RREG32(mmMC_CITF_MISC_RD_CG); 1450 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1451 WREG32(mmMC_CITF_MISC_RD_CG, data); 1452 1453 data = RREG32(mmMC_CITF_MISC_VM_CG); 1454 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1455 WREG32(mmMC_CITF_MISC_VM_CG, data); 1456 1457 data = RREG32(mmVM_L2_CG); 1458 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1459 WREG32(mmVM_L2_CG, data); 1460 } 1461 } 1462 1463 static int gmc_v8_0_set_clockgating_state(void *handle, 1464 enum amd_clockgating_state state) 1465 { 1466 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1467 1468 switch (adev->asic_type) { 1469 case CHIP_FIJI: 1470 fiji_update_mc_medium_grain_clock_gating(adev, 1471 state == AMD_CG_STATE_GATE ? true : false); 1472 fiji_update_mc_light_sleep(adev, 1473 state == AMD_CG_STATE_GATE ? true : false); 1474 break; 1475 default: 1476 break; 1477 } 1478 return 0; 1479 } 1480 1481 static int gmc_v8_0_set_powergating_state(void *handle, 1482 enum amd_powergating_state state) 1483 { 1484 return 0; 1485 } 1486 1487 const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1488 .early_init = gmc_v8_0_early_init, 1489 .late_init = gmc_v8_0_late_init, 1490 .sw_init = gmc_v8_0_sw_init, 1491 .sw_fini = gmc_v8_0_sw_fini, 1492 .hw_init = gmc_v8_0_hw_init, 1493 .hw_fini = gmc_v8_0_hw_fini, 1494 .suspend = gmc_v8_0_suspend, 1495 .resume = gmc_v8_0_resume, 1496 .is_idle = gmc_v8_0_is_idle, 1497 .wait_for_idle = gmc_v8_0_wait_for_idle, 1498 .soft_reset = gmc_v8_0_soft_reset, 1499 .print_status = gmc_v8_0_print_status, 1500 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1501 .set_powergating_state = gmc_v8_0_set_powergating_state, 1502 }; 1503 1504 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { 1505 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, 1506 .set_pte_pde = gmc_v8_0_gart_set_pte_pde, 1507 }; 1508 1509 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1510 .set = gmc_v8_0_vm_fault_interrupt_state, 1511 .process = gmc_v8_0_process_interrupt, 1512 }; 1513 1514 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev) 1515 { 1516 if (adev->gart.gart_funcs == NULL) 1517 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs; 1518 } 1519 1520 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1521 { 1522 adev->mc.vm_fault.num_types = 1; 1523 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1524 } 1525