1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "gmc_v8_0.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_amdkfd.h" 33 #include "amdgpu_gem.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "bif/bif_5_0_d.h" 39 #include "bif/bif_5_0_sh_mask.h" 40 41 #include "oss/oss_3_0_d.h" 42 #include "oss/oss_3_0_sh_mask.h" 43 44 #include "dce/dce_10_0_d.h" 45 #include "dce/dce_10_0_sh_mask.h" 46 47 #include "vid.h" 48 #include "vi.h" 49 50 #include "amdgpu_atombios.h" 51 52 #include "ivsrcid/ivsrcid_vislands30.h" 53 54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 56 static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block); 57 58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); 66 67 static const u32 golden_settings_tonga_a11[] = { 68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 75 }; 76 77 static const u32 tonga_mgcg_cgcg_init[] = { 78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 79 }; 80 81 static const u32 golden_settings_fiji_a10[] = { 82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 86 }; 87 88 static const u32 fiji_mgcg_cgcg_init[] = { 89 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 90 }; 91 92 static const u32 golden_settings_polaris11_a11[] = { 93 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 94 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 95 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 96 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 97 }; 98 99 static const u32 golden_settings_polaris10_a11[] = { 100 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 101 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 102 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 103 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 104 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 105 }; 106 107 static const u32 cz_mgcg_cgcg_init[] = { 108 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 109 }; 110 111 static const u32 stoney_mgcg_cgcg_init[] = { 112 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 113 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 114 }; 115 116 static const u32 golden_settings_stoney_common[] = { 117 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 118 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 119 }; 120 121 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 122 { 123 switch (adev->asic_type) { 124 case CHIP_FIJI: 125 amdgpu_device_program_register_sequence(adev, 126 fiji_mgcg_cgcg_init, 127 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 128 amdgpu_device_program_register_sequence(adev, 129 golden_settings_fiji_a10, 130 ARRAY_SIZE(golden_settings_fiji_a10)); 131 break; 132 case CHIP_TONGA: 133 amdgpu_device_program_register_sequence(adev, 134 tonga_mgcg_cgcg_init, 135 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 136 amdgpu_device_program_register_sequence(adev, 137 golden_settings_tonga_a11, 138 ARRAY_SIZE(golden_settings_tonga_a11)); 139 break; 140 case CHIP_POLARIS11: 141 case CHIP_POLARIS12: 142 case CHIP_VEGAM: 143 amdgpu_device_program_register_sequence(adev, 144 golden_settings_polaris11_a11, 145 ARRAY_SIZE(golden_settings_polaris11_a11)); 146 break; 147 case CHIP_POLARIS10: 148 amdgpu_device_program_register_sequence(adev, 149 golden_settings_polaris10_a11, 150 ARRAY_SIZE(golden_settings_polaris10_a11)); 151 break; 152 case CHIP_CARRIZO: 153 amdgpu_device_program_register_sequence(adev, 154 cz_mgcg_cgcg_init, 155 ARRAY_SIZE(cz_mgcg_cgcg_init)); 156 break; 157 case CHIP_STONEY: 158 amdgpu_device_program_register_sequence(adev, 159 stoney_mgcg_cgcg_init, 160 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 161 amdgpu_device_program_register_sequence(adev, 162 golden_settings_stoney_common, 163 ARRAY_SIZE(golden_settings_stoney_common)); 164 break; 165 default: 166 break; 167 } 168 } 169 170 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 171 { 172 u32 blackout; 173 struct amdgpu_ip_block *ip_block; 174 175 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); 176 if (!ip_block) 177 return; 178 179 gmc_v8_0_wait_for_idle(ip_block); 180 181 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 182 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 183 /* Block CPU access */ 184 WREG32(mmBIF_FB_EN, 0); 185 /* blackout the MC */ 186 blackout = REG_SET_FIELD(blackout, 187 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 188 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 189 } 190 /* wait for the MC to settle */ 191 udelay(100); 192 } 193 194 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 195 { 196 u32 tmp; 197 198 /* unblackout the MC */ 199 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 200 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 201 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 202 /* allow CPU access */ 203 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 204 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 205 WREG32(mmBIF_FB_EN, tmp); 206 } 207 208 /** 209 * gmc_v8_0_init_microcode - load ucode images from disk 210 * 211 * @adev: amdgpu_device pointer 212 * 213 * Use the firmware interface to load the ucode images into 214 * the driver (not loaded into hw). 215 * Returns 0 on success, error on failure. 216 */ 217 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 218 { 219 const char *chip_name; 220 int err; 221 222 DRM_DEBUG("\n"); 223 224 switch (adev->asic_type) { 225 case CHIP_TONGA: 226 chip_name = "tonga"; 227 break; 228 case CHIP_POLARIS11: 229 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 230 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) 231 chip_name = "polaris11_k"; 232 else 233 chip_name = "polaris11"; 234 break; 235 case CHIP_POLARIS10: 236 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) 237 chip_name = "polaris10_k"; 238 else 239 chip_name = "polaris10"; 240 break; 241 case CHIP_POLARIS12: 242 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) { 243 chip_name = "polaris12_k"; 244 } else { 245 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159); 246 /* Polaris12 32bit ASIC needs a special MC firmware */ 247 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40) 248 chip_name = "polaris12_32"; 249 else 250 chip_name = "polaris12"; 251 } 252 break; 253 case CHIP_FIJI: 254 case CHIP_CARRIZO: 255 case CHIP_STONEY: 256 case CHIP_VEGAM: 257 return 0; 258 default: 259 return -EINVAL; 260 } 261 262 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, 263 "amdgpu/%s_mc.bin", chip_name); 264 if (err) { 265 pr_err("mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name); 266 amdgpu_ucode_release(&adev->gmc.fw); 267 } 268 return err; 269 } 270 271 /** 272 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 273 * 274 * @adev: amdgpu_device pointer 275 * 276 * Load the GDDR MC ucode into the hw (VI). 277 * Returns 0 on success, error on failure. 278 */ 279 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 280 { 281 const struct mc_firmware_header_v1_0 *hdr; 282 const __le32 *fw_data = NULL; 283 const __le32 *io_mc_regs = NULL; 284 u32 running; 285 int i, ucode_size, regs_size; 286 287 /* Skip MC ucode loading on SR-IOV capable boards. 288 * vbios does this for us in asic_init in that case. 289 * Skip MC ucode loading on VF, because hypervisor will do that 290 * for this adaptor. 291 */ 292 if (amdgpu_sriov_bios(adev)) 293 return 0; 294 295 if (!adev->gmc.fw) 296 return -EINVAL; 297 298 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 299 amdgpu_ucode_print_mc_hdr(&hdr->header); 300 301 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 302 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 303 io_mc_regs = (const __le32 *) 304 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 305 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 306 fw_data = (const __le32 *) 307 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 308 309 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 310 311 if (running == 0) { 312 /* reset the engine and set to writable */ 313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 315 316 /* load mc io regs */ 317 for (i = 0; i < regs_size; i++) { 318 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 319 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 320 } 321 /* load the MC ucode */ 322 for (i = 0; i < ucode_size; i++) 323 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 324 325 /* put the engine back into the active state */ 326 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 327 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 328 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 329 330 /* wait for training to complete */ 331 for (i = 0; i < adev->usec_timeout; i++) { 332 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 333 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 334 break; 335 udelay(1); 336 } 337 for (i = 0; i < adev->usec_timeout; i++) { 338 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 339 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 340 break; 341 udelay(1); 342 } 343 } 344 345 return 0; 346 } 347 348 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 349 { 350 const struct mc_firmware_header_v1_0 *hdr; 351 const __le32 *fw_data = NULL; 352 const __le32 *io_mc_regs = NULL; 353 u32 data; 354 int i, ucode_size, regs_size; 355 356 /* Skip MC ucode loading on SR-IOV capable boards. 357 * vbios does this for us in asic_init in that case. 358 * Skip MC ucode loading on VF, because hypervisor will do that 359 * for this adaptor. 360 */ 361 if (amdgpu_sriov_bios(adev)) 362 return 0; 363 364 if (!adev->gmc.fw) 365 return -EINVAL; 366 367 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 368 amdgpu_ucode_print_mc_hdr(&hdr->header); 369 370 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 371 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 372 io_mc_regs = (const __le32 *) 373 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 374 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 375 fw_data = (const __le32 *) 376 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 377 378 data = RREG32(mmMC_SEQ_MISC0); 379 data &= ~(0x40); 380 WREG32(mmMC_SEQ_MISC0, data); 381 382 /* load mc io regs */ 383 for (i = 0; i < regs_size; i++) { 384 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 385 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 386 } 387 388 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 389 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 390 391 /* load the MC ucode */ 392 for (i = 0; i < ucode_size; i++) 393 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 394 395 /* put the engine back into the active state */ 396 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 397 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 398 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 399 400 /* wait for training to complete */ 401 for (i = 0; i < adev->usec_timeout; i++) { 402 data = RREG32(mmMC_SEQ_MISC0); 403 if (data & 0x80) 404 break; 405 udelay(1); 406 } 407 408 return 0; 409 } 410 411 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 412 struct amdgpu_gmc *mc) 413 { 414 u64 base = 0; 415 416 if (!amdgpu_sriov_vf(adev)) 417 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 418 base <<= 24; 419 420 amdgpu_gmc_set_agp_default(adev, mc); 421 amdgpu_gmc_vram_location(adev, mc, base); 422 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 423 } 424 425 /** 426 * gmc_v8_0_mc_program - program the GPU memory controller 427 * 428 * @adev: amdgpu_device pointer 429 * 430 * Set the location of vram, gart, and AGP in the GPU's 431 * physical address space (VI). 432 */ 433 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 434 { 435 struct amdgpu_ip_block *ip_block; 436 u32 tmp; 437 int i, j; 438 439 /* Initialize HDP */ 440 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 441 WREG32((0xb05 + j), 0x00000000); 442 WREG32((0xb06 + j), 0x00000000); 443 WREG32((0xb07 + j), 0x00000000); 444 WREG32((0xb08 + j), 0x00000000); 445 WREG32((0xb09 + j), 0x00000000); 446 } 447 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 448 449 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); 450 if (!ip_block) 451 return; 452 453 if (gmc_v8_0_wait_for_idle(ip_block)) 454 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 455 456 if (adev->mode_info.num_crtc) { 457 /* Lockout access through VGA aperture*/ 458 tmp = RREG32(mmVGA_HDP_CONTROL); 459 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 460 WREG32(mmVGA_HDP_CONTROL, tmp); 461 462 /* disable VGA render */ 463 tmp = RREG32(mmVGA_RENDER_CONTROL); 464 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 465 WREG32(mmVGA_RENDER_CONTROL, tmp); 466 } 467 /* Update configuration */ 468 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 469 adev->gmc.vram_start >> 12); 470 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 471 adev->gmc.vram_end >> 12); 472 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 473 adev->mem_scratch.gpu_addr >> 12); 474 475 if (amdgpu_sriov_vf(adev)) { 476 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 477 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 478 WREG32(mmMC_VM_FB_LOCATION, tmp); 479 /* XXX double check these! */ 480 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 481 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 482 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 483 } 484 485 WREG32(mmMC_VM_AGP_BASE, 0); 486 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); 487 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); 488 if (gmc_v8_0_wait_for_idle(ip_block)) 489 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 490 491 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 492 493 tmp = RREG32(mmHDP_MISC_CNTL); 494 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 495 WREG32(mmHDP_MISC_CNTL, tmp); 496 497 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 498 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 499 } 500 501 /** 502 * gmc_v8_0_mc_init - initialize the memory controller driver params 503 * 504 * @adev: amdgpu_device pointer 505 * 506 * Look up the amount of vram, vram width, and decide how to place 507 * vram and gart within the GPU's physical address space (VI). 508 * Returns 0 for success. 509 */ 510 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 511 { 512 int r; 513 u32 tmp; 514 515 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 516 if (!adev->gmc.vram_width) { 517 int chansize, numchan; 518 519 /* Get VRAM informations */ 520 tmp = RREG32(mmMC_ARB_RAMCFG); 521 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) 522 chansize = 64; 523 else 524 chansize = 32; 525 526 tmp = RREG32(mmMC_SHARED_CHMAP); 527 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 528 case 0: 529 default: 530 numchan = 1; 531 break; 532 case 1: 533 numchan = 2; 534 break; 535 case 2: 536 numchan = 4; 537 break; 538 case 3: 539 numchan = 8; 540 break; 541 case 4: 542 numchan = 3; 543 break; 544 case 5: 545 numchan = 6; 546 break; 547 case 6: 548 numchan = 10; 549 break; 550 case 7: 551 numchan = 12; 552 break; 553 case 8: 554 numchan = 16; 555 break; 556 } 557 adev->gmc.vram_width = numchan * chansize; 558 } 559 /* size in MB on si */ 560 tmp = RREG32(mmCONFIG_MEMSIZE); 561 /* some boards may have garbage in the upper 16 bits */ 562 if (tmp & 0xffff0000) { 563 drm_info(adev_to_drm(adev), "Probably bad vram size: 0x%08x\n", tmp); 564 if (tmp & 0xffff) 565 tmp &= 0xffff; 566 } 567 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL; 568 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 569 570 if (!(adev->flags & AMD_IS_APU)) { 571 r = amdgpu_device_resize_fb_bar(adev); 572 if (r) 573 return r; 574 } 575 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 576 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 577 578 #ifdef CONFIG_X86_64 579 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 580 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 581 adev->gmc.aper_size = adev->gmc.real_vram_size; 582 } 583 #endif 584 585 adev->gmc.visible_vram_size = adev->gmc.aper_size; 586 587 /* set the gart size */ 588 switch (adev->asic_type) { 589 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 590 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 591 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 592 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 593 amdgpu_gmc_set_gart_size(adev, SZ_1G); 594 break; 595 case CHIP_POLARIS10: /* all engines support GPUVM */ 596 case CHIP_POLARIS11: /* all engines support GPUVM */ 597 case CHIP_POLARIS12: /* all engines support GPUVM */ 598 case CHIP_VEGAM: /* all engines support GPUVM */ 599 default: 600 amdgpu_gmc_set_gart_size(adev, SZ_256M); 601 break; 602 } 603 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 604 605 return 0; 606 } 607 608 /** 609 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid 610 * 611 * @adev: amdgpu_device pointer 612 * @pasid: pasid to be flush 613 * @flush_type: type of flush 614 * @all_hub: flush all hubs 615 * @inst: is used to select which instance of KIQ to use for the invalidation 616 * 617 * Flush the TLB for the requested pasid. 618 */ 619 static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 620 uint16_t pasid, uint32_t flush_type, 621 bool all_hub, uint32_t inst) 622 { 623 u32 mask = 0x0; 624 int vmid; 625 626 for (vmid = 1; vmid < 16; vmid++) { 627 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 628 629 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 630 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) 631 mask |= 1 << vmid; 632 } 633 634 WREG32(mmVM_INVALIDATE_REQUEST, mask); 635 RREG32(mmVM_INVALIDATE_RESPONSE); 636 } 637 638 /* 639 * GART 640 * VMID 0 is the physical GPU addresses as used by the kernel. 641 * VMIDs 1-15 are used for userspace clients and are handled 642 * by the amdgpu vm/hsa code. 643 */ 644 645 /** 646 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 647 * 648 * @adev: amdgpu_device pointer 649 * @vmid: vm instance to flush 650 * @vmhub: which hub to flush 651 * @flush_type: type of flush 652 * 653 * Flush the TLB for the requested page table (VI). 654 */ 655 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 656 uint32_t vmhub, uint32_t flush_type) 657 { 658 /* bits 0-15 are the VM contexts0-15 */ 659 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 660 } 661 662 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 663 unsigned int vmid, uint64_t pd_addr) 664 { 665 uint32_t reg; 666 667 if (vmid < 8) 668 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 669 else 670 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 671 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 672 673 /* bits 0-15 are the VM contexts0-15 */ 674 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 675 676 return pd_addr; 677 } 678 679 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 680 unsigned int pasid) 681 { 682 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 683 } 684 685 /* 686 * PTE format on VI: 687 * 63:40 reserved 688 * 39:12 4k physical page base address 689 * 11:7 fragment 690 * 6 write 691 * 5 read 692 * 4 exe 693 * 3 reserved 694 * 2 snooped 695 * 1 system 696 * 0 valid 697 * 698 * PDE format on VI: 699 * 63:59 block fragment size 700 * 58:40 reserved 701 * 39:1 physical base address of PTE 702 * bits 5:1 must be 0. 703 * 0 valid 704 */ 705 706 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 707 uint64_t *addr, uint64_t *flags) 708 { 709 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 710 } 711 712 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, 713 struct amdgpu_vm *vm, 714 struct amdgpu_bo *bo, 715 uint32_t vm_flags, 716 uint64_t *flags) 717 { 718 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 719 *flags |= AMDGPU_PTE_EXECUTABLE; 720 else 721 *flags &= ~AMDGPU_PTE_EXECUTABLE; 722 *flags &= ~AMDGPU_PTE_PRT; 723 } 724 725 /** 726 * gmc_v8_0_set_fault_enable_default - update VM fault handling 727 * 728 * @adev: amdgpu_device pointer 729 * @value: true redirects VM faults to the default page 730 */ 731 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 732 bool value) 733 { 734 u32 tmp; 735 736 tmp = RREG32(mmVM_CONTEXT1_CNTL); 737 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 738 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 739 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 740 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 741 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 742 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 743 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 744 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 745 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 746 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 747 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 748 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 750 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 751 WREG32(mmVM_CONTEXT1_CNTL, tmp); 752 } 753 754 /** 755 * gmc_v8_0_set_prt() - set PRT VM fault 756 * 757 * @adev: amdgpu_device pointer 758 * @enable: enable/disable VM fault handling for PRT 759 */ 760 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 761 { 762 u32 tmp; 763 764 if (enable && !adev->gmc.prt_warning) { 765 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 766 adev->gmc.prt_warning = true; 767 } 768 769 tmp = RREG32(mmVM_PRT_CNTL); 770 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 771 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 772 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 773 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 774 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 775 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 776 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 777 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 778 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 779 L2_CACHE_STORE_INVALID_ENTRIES, enable); 780 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 781 L1_TLB_STORE_INVALID_ENTRIES, enable); 782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 783 MASK_PDE0_FAULT, enable); 784 WREG32(mmVM_PRT_CNTL, tmp); 785 786 if (enable) { 787 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >> 788 AMDGPU_GPU_PAGE_SHIFT; 789 uint32_t high = adev->vm_manager.max_pfn - 790 (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT); 791 792 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 793 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 794 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 795 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 796 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 797 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 798 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 799 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 800 } else { 801 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 802 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 803 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 804 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 805 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 806 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 807 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 808 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 809 } 810 } 811 812 /** 813 * gmc_v8_0_gart_enable - gart enable 814 * 815 * @adev: amdgpu_device pointer 816 * 817 * This sets up the TLBs, programs the page tables for VMID0, 818 * sets up the hw for VMIDs 1-15 which are allocated on 819 * demand, and sets up the global locations for the LDS, GDS, 820 * and GPUVM for FSA64 clients (VI). 821 * Returns 0 for success, errors for failure. 822 */ 823 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 824 { 825 uint64_t table_addr; 826 u32 tmp, field; 827 int i; 828 829 if (adev->gart.bo == NULL) { 830 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 831 return -EINVAL; 832 } 833 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 834 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 835 836 /* Setup TLB control */ 837 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 838 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 839 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 840 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 841 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 842 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 843 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 844 /* Setup L2 cache */ 845 tmp = RREG32(mmVM_L2_CNTL); 846 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 847 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 848 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 849 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 850 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 851 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 853 WREG32(mmVM_L2_CNTL, tmp); 854 tmp = RREG32(mmVM_L2_CNTL2); 855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 857 WREG32(mmVM_L2_CNTL2, tmp); 858 859 field = adev->vm_manager.fragment_size; 860 tmp = RREG32(mmVM_L2_CNTL3); 861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 864 WREG32(mmVM_L2_CNTL3, tmp); 865 /* XXX: set to enable PTE/PDE in system memory */ 866 tmp = RREG32(mmVM_L2_CNTL4); 867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 870 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 871 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 879 WREG32(mmVM_L2_CNTL4, tmp); 880 /* setup context0 */ 881 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 882 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 883 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 884 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 885 (u32)(adev->dummy_page_addr >> 12)); 886 WREG32(mmVM_CONTEXT0_CNTL2, 0); 887 tmp = RREG32(mmVM_CONTEXT0_CNTL); 888 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 889 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 890 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 891 WREG32(mmVM_CONTEXT0_CNTL, tmp); 892 893 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 894 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 895 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 896 897 /* empty context1-15 */ 898 /* FIXME start with 4G, once using 2 level pt switch to full 899 * vm size space 900 */ 901 /* set vm size, must be a multiple of 4 */ 902 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 903 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 904 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 905 if (i < 8) 906 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 907 table_addr >> 12); 908 else 909 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 910 table_addr >> 12); 911 } 912 913 /* enable context1-15 */ 914 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 915 (u32)(adev->dummy_page_addr >> 12)); 916 WREG32(mmVM_CONTEXT1_CNTL2, 4); 917 tmp = RREG32(mmVM_CONTEXT1_CNTL); 918 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 919 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 920 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 921 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 922 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 923 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 924 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 925 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 926 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 927 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 928 adev->vm_manager.block_size - 9); 929 WREG32(mmVM_CONTEXT1_CNTL, tmp); 930 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 931 gmc_v8_0_set_fault_enable_default(adev, false); 932 else 933 gmc_v8_0_set_fault_enable_default(adev, true); 934 935 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); 936 drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", 937 (unsigned int)(adev->gmc.gart_size >> 20), 938 (unsigned long long)table_addr); 939 return 0; 940 } 941 942 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 943 { 944 int r; 945 946 if (adev->gart.bo) { 947 WARN(1, "R600 PCIE GART already initialized\n"); 948 return 0; 949 } 950 /* Initialize common gart structure */ 951 r = amdgpu_gart_init(adev); 952 if (r) 953 return r; 954 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 955 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 956 return amdgpu_gart_table_vram_alloc(adev); 957 } 958 959 /** 960 * gmc_v8_0_gart_disable - gart disable 961 * 962 * @adev: amdgpu_device pointer 963 * 964 * This disables all VM page table (VI). 965 */ 966 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 967 { 968 u32 tmp; 969 970 /* Disable all tables */ 971 WREG32(mmVM_CONTEXT0_CNTL, 0); 972 WREG32(mmVM_CONTEXT1_CNTL, 0); 973 /* Setup TLB control */ 974 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 975 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 976 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 977 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 978 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 979 /* Setup L2 cache */ 980 tmp = RREG32(mmVM_L2_CNTL); 981 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 982 WREG32(mmVM_L2_CNTL, tmp); 983 WREG32(mmVM_L2_CNTL2, 0); 984 } 985 986 /** 987 * gmc_v8_0_vm_decode_fault - print human readable fault info 988 * 989 * @adev: amdgpu_device pointer 990 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 991 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 992 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 993 * @pasid: debug logging only - no functional use 994 * 995 * Print human readable fault information (VI). 996 */ 997 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 998 u32 addr, u32 mc_client, unsigned int pasid) 999 { 1000 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 1001 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1002 PROTECTIONS); 1003 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 1004 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 1005 u32 mc_id; 1006 1007 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1008 MEMORY_CLIENT_ID); 1009 1010 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 1011 protections, vmid, pasid, addr, 1012 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1013 MEMORY_CLIENT_RW) ? 1014 "write" : "read", block, mc_client, mc_id); 1015 } 1016 1017 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1018 { 1019 switch (mc_seq_vram_type) { 1020 case MC_SEQ_MISC0__MT__GDDR1: 1021 return AMDGPU_VRAM_TYPE_GDDR1; 1022 case MC_SEQ_MISC0__MT__DDR2: 1023 return AMDGPU_VRAM_TYPE_DDR2; 1024 case MC_SEQ_MISC0__MT__GDDR3: 1025 return AMDGPU_VRAM_TYPE_GDDR3; 1026 case MC_SEQ_MISC0__MT__GDDR4: 1027 return AMDGPU_VRAM_TYPE_GDDR4; 1028 case MC_SEQ_MISC0__MT__GDDR5: 1029 return AMDGPU_VRAM_TYPE_GDDR5; 1030 case MC_SEQ_MISC0__MT__HBM: 1031 return AMDGPU_VRAM_TYPE_HBM; 1032 case MC_SEQ_MISC0__MT__DDR3: 1033 return AMDGPU_VRAM_TYPE_DDR3; 1034 default: 1035 return AMDGPU_VRAM_TYPE_UNKNOWN; 1036 } 1037 } 1038 1039 static int gmc_v8_0_early_init(struct amdgpu_ip_block *ip_block) 1040 { 1041 struct amdgpu_device *adev = ip_block->adev; 1042 1043 gmc_v8_0_set_gmc_funcs(adev); 1044 gmc_v8_0_set_irq_funcs(adev); 1045 1046 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1047 adev->gmc.shared_aperture_end = 1048 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1049 adev->gmc.private_aperture_start = 1050 adev->gmc.shared_aperture_end + 1; 1051 adev->gmc.private_aperture_end = 1052 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1053 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1054 1055 return 0; 1056 } 1057 1058 static int gmc_v8_0_late_init(struct amdgpu_ip_block *ip_block) 1059 { 1060 struct amdgpu_device *adev = ip_block->adev; 1061 1062 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1063 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1064 else 1065 return 0; 1066 } 1067 1068 static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1069 { 1070 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1071 unsigned int size; 1072 1073 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1074 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1075 } else { 1076 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1077 1078 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1079 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1080 4); 1081 } 1082 1083 return size; 1084 } 1085 1086 #define mmMC_SEQ_MISC0_FIJI 0xA71 1087 1088 static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block) 1089 { 1090 int r; 1091 struct amdgpu_device *adev = ip_block->adev; 1092 1093 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1094 1095 if (adev->flags & AMD_IS_APU) { 1096 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1097 } else { 1098 u32 tmp; 1099 1100 if ((adev->asic_type == CHIP_FIJI) || 1101 (adev->asic_type == CHIP_VEGAM)) 1102 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1103 else 1104 tmp = RREG32(mmMC_SEQ_MISC0); 1105 tmp &= MC_SEQ_MISC0__MT__MASK; 1106 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1107 } 1108 1109 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1110 if (r) 1111 return r; 1112 1113 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1114 if (r) 1115 return r; 1116 1117 /* Adjust VM size here. 1118 * Currently set to 4GB ((1 << 20) 4k pages). 1119 * Max GPUVM size for cayman and SI is 40 bits. 1120 */ 1121 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1122 1123 /* Set the internal MC address mask 1124 * This is the max address of the GPU's 1125 * internal address space. 1126 */ 1127 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1128 1129 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1130 if (r) { 1131 pr_warn("No suitable DMA available\n"); 1132 return r; 1133 } 1134 adev->need_swiotlb = drm_need_swiotlb(40); 1135 1136 r = gmc_v8_0_init_microcode(adev); 1137 if (r) { 1138 DRM_ERROR("Failed to load mc firmware!\n"); 1139 return r; 1140 } 1141 1142 r = gmc_v8_0_mc_init(adev); 1143 if (r) 1144 return r; 1145 1146 /* Memory manager */ 1147 r = amdgpu_bo_init(adev); 1148 if (r) 1149 return r; 1150 1151 r = gmc_v8_0_gart_init(adev); 1152 if (r) 1153 return r; 1154 1155 /* 1156 * number of VMs 1157 * VMID 0 is reserved for System 1158 * amdgpu graphics/compute will use VMIDs 1-7 1159 * amdkfd will use VMIDs 8-15 1160 */ 1161 adev->vm_manager.first_kfd_vmid = 8; 1162 amdgpu_vm_manager_init(adev); 1163 1164 /* base offset of vram pages */ 1165 if (adev->flags & AMD_IS_APU) { 1166 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1167 1168 tmp <<= 22; 1169 adev->vm_manager.vram_base_offset = tmp; 1170 } else { 1171 adev->vm_manager.vram_base_offset = 0; 1172 } 1173 1174 adev->gmc.vm_fault_info = kmalloc_obj(struct kfd_vm_fault_info); 1175 if (!adev->gmc.vm_fault_info) 1176 return -ENOMEM; 1177 atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); 1178 1179 return 0; 1180 } 1181 1182 static int gmc_v8_0_sw_fini(struct amdgpu_ip_block *ip_block) 1183 { 1184 struct amdgpu_device *adev = ip_block->adev; 1185 1186 amdgpu_gem_force_release(adev); 1187 amdgpu_vm_manager_fini(adev); 1188 kfree(adev->gmc.vm_fault_info); 1189 amdgpu_gart_table_vram_free(adev); 1190 amdgpu_bo_fini(adev); 1191 amdgpu_ucode_release(&adev->gmc.fw); 1192 1193 return 0; 1194 } 1195 1196 static int gmc_v8_0_hw_init(struct amdgpu_ip_block *ip_block) 1197 { 1198 int r; 1199 struct amdgpu_device *adev = ip_block->adev; 1200 1201 gmc_v8_0_init_golden_registers(adev); 1202 1203 gmc_v8_0_mc_program(adev); 1204 1205 if (adev->asic_type == CHIP_TONGA) { 1206 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1207 if (r) { 1208 DRM_ERROR("Failed to load MC firmware!\n"); 1209 return r; 1210 } 1211 } else if (adev->asic_type == CHIP_POLARIS11 || 1212 adev->asic_type == CHIP_POLARIS10 || 1213 adev->asic_type == CHIP_POLARIS12) { 1214 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1215 if (r) { 1216 DRM_ERROR("Failed to load MC firmware!\n"); 1217 return r; 1218 } 1219 } 1220 1221 r = gmc_v8_0_gart_enable(adev); 1222 if (r) 1223 return r; 1224 1225 if (amdgpu_emu_mode == 1) 1226 return amdgpu_gmc_vram_checking(adev); 1227 1228 return 0; 1229 } 1230 1231 static int gmc_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) 1232 { 1233 struct amdgpu_device *adev = ip_block->adev; 1234 1235 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1236 gmc_v8_0_gart_disable(adev); 1237 1238 return 0; 1239 } 1240 1241 static int gmc_v8_0_suspend(struct amdgpu_ip_block *ip_block) 1242 { 1243 gmc_v8_0_hw_fini(ip_block); 1244 1245 return 0; 1246 } 1247 1248 static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block) 1249 { 1250 int r; 1251 1252 r = gmc_v8_0_hw_init(ip_block); 1253 if (r) 1254 return r; 1255 1256 amdgpu_vmid_reset_all(ip_block->adev); 1257 1258 return 0; 1259 } 1260 1261 static bool gmc_v8_0_is_idle(struct amdgpu_ip_block *ip_block) 1262 { 1263 struct amdgpu_device *adev = ip_block->adev; 1264 u32 tmp = RREG32(mmSRBM_STATUS); 1265 1266 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1267 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1268 return false; 1269 1270 return true; 1271 } 1272 1273 static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1274 { 1275 unsigned int i; 1276 u32 tmp; 1277 struct amdgpu_device *adev = ip_block->adev; 1278 1279 for (i = 0; i < adev->usec_timeout; i++) { 1280 /* read MC_STATUS */ 1281 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1282 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1283 SRBM_STATUS__MCC_BUSY_MASK | 1284 SRBM_STATUS__MCD_BUSY_MASK | 1285 SRBM_STATUS__VMC_BUSY_MASK | 1286 SRBM_STATUS__VMC1_BUSY_MASK); 1287 if (!tmp) 1288 return 0; 1289 udelay(1); 1290 } 1291 return -ETIMEDOUT; 1292 1293 } 1294 1295 static bool gmc_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block) 1296 { 1297 u32 srbm_soft_reset = 0; 1298 struct amdgpu_device *adev = ip_block->adev; 1299 u32 tmp = RREG32(mmSRBM_STATUS); 1300 1301 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1302 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1303 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1304 1305 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1306 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1307 if (!(adev->flags & AMD_IS_APU)) 1308 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1309 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1310 } 1311 1312 if (srbm_soft_reset) { 1313 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1314 return true; 1315 } 1316 1317 adev->gmc.srbm_soft_reset = 0; 1318 1319 return false; 1320 } 1321 1322 static int gmc_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) 1323 { 1324 struct amdgpu_device *adev = ip_block->adev; 1325 1326 if (!adev->gmc.srbm_soft_reset) 1327 return 0; 1328 1329 gmc_v8_0_mc_stop(adev); 1330 if (gmc_v8_0_wait_for_idle(ip_block)) 1331 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1332 1333 return 0; 1334 } 1335 1336 static int gmc_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) 1337 { 1338 struct amdgpu_device *adev = ip_block->adev; 1339 u32 srbm_soft_reset; 1340 1341 if (!adev->gmc.srbm_soft_reset) 1342 return 0; 1343 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1344 1345 if (srbm_soft_reset) { 1346 u32 tmp; 1347 1348 tmp = RREG32(mmSRBM_SOFT_RESET); 1349 tmp |= srbm_soft_reset; 1350 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1351 WREG32(mmSRBM_SOFT_RESET, tmp); 1352 tmp = RREG32(mmSRBM_SOFT_RESET); 1353 1354 udelay(50); 1355 1356 tmp &= ~srbm_soft_reset; 1357 WREG32(mmSRBM_SOFT_RESET, tmp); 1358 tmp = RREG32(mmSRBM_SOFT_RESET); 1359 1360 /* Wait a little for things to settle down */ 1361 udelay(50); 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int gmc_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block) 1368 { 1369 struct amdgpu_device *adev = ip_block->adev; 1370 1371 if (!adev->gmc.srbm_soft_reset) 1372 return 0; 1373 1374 gmc_v8_0_mc_resume(adev); 1375 return 0; 1376 } 1377 1378 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1379 struct amdgpu_irq_src *src, 1380 unsigned int type, 1381 enum amdgpu_interrupt_state state) 1382 { 1383 u32 tmp; 1384 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1385 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1386 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1387 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1388 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1389 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1390 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1391 1392 switch (state) { 1393 case AMDGPU_IRQ_STATE_DISABLE: 1394 /* system context */ 1395 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1396 tmp &= ~bits; 1397 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1398 /* VMs */ 1399 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1400 tmp &= ~bits; 1401 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1402 break; 1403 case AMDGPU_IRQ_STATE_ENABLE: 1404 /* system context */ 1405 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1406 tmp |= bits; 1407 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1408 /* VMs */ 1409 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1410 tmp |= bits; 1411 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1412 break; 1413 default: 1414 break; 1415 } 1416 1417 return 0; 1418 } 1419 1420 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1421 struct amdgpu_irq_src *source, 1422 struct amdgpu_iv_entry *entry) 1423 { 1424 u32 addr, status, mc_client, vmid; 1425 1426 if (amdgpu_sriov_vf(adev)) { 1427 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1428 entry->src_id, entry->src_data[0]); 1429 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1430 return 0; 1431 } 1432 1433 /* Delegate to the soft IRQ handler ring */ 1434 if (adev->irq.ih_soft.enabled && entry->ih != &adev->irq.ih_soft) { 1435 amdgpu_irq_delegate(adev, entry, 4); 1436 return 1; 1437 } 1438 1439 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1440 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1441 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1442 /* reset addr and status */ 1443 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1444 1445 if (!addr && !status) 1446 return 0; 1447 1448 amdgpu_vm_update_fault_cache(adev, entry->pasid, 1449 ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); 1450 1451 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1452 gmc_v8_0_set_fault_enable_default(adev, false); 1453 1454 if (printk_ratelimit()) { 1455 struct amdgpu_task_info *task_info; 1456 1457 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1458 entry->src_id, entry->src_data[0]); 1459 1460 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1461 if (task_info) { 1462 amdgpu_vm_print_task_info(adev, task_info); 1463 amdgpu_vm_put_task_info(task_info); 1464 } 1465 1466 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1467 addr); 1468 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1469 status); 1470 1471 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1472 entry->pasid); 1473 } 1474 1475 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1476 VMID); 1477 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1478 && !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) { 1479 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1480 u32 protections = REG_GET_FIELD(status, 1481 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1482 PROTECTIONS); 1483 1484 info->vmid = vmid; 1485 info->mc_id = REG_GET_FIELD(status, 1486 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1487 MEMORY_CLIENT_ID); 1488 info->status = status; 1489 info->page_addr = addr; 1490 info->prot_valid = protections & 0x7 ? true : false; 1491 info->prot_read = protections & 0x8 ? true : false; 1492 info->prot_write = protections & 0x10 ? true : false; 1493 info->prot_exec = protections & 0x20 ? true : false; 1494 atomic_set_release(&adev->gmc.vm_fault_info_updated, 1); 1495 } 1496 1497 return 0; 1498 } 1499 1500 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1501 bool enable) 1502 { 1503 uint32_t data; 1504 1505 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1506 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1507 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1508 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1509 1510 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1511 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1512 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1513 1514 data = RREG32(mmMC_HUB_MISC_VM_CG); 1515 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1516 WREG32(mmMC_HUB_MISC_VM_CG, data); 1517 1518 data = RREG32(mmMC_XPB_CLK_GAT); 1519 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1520 WREG32(mmMC_XPB_CLK_GAT, data); 1521 1522 data = RREG32(mmATC_MISC_CG); 1523 data |= ATC_MISC_CG__ENABLE_MASK; 1524 WREG32(mmATC_MISC_CG, data); 1525 1526 data = RREG32(mmMC_CITF_MISC_WR_CG); 1527 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1528 WREG32(mmMC_CITF_MISC_WR_CG, data); 1529 1530 data = RREG32(mmMC_CITF_MISC_RD_CG); 1531 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1532 WREG32(mmMC_CITF_MISC_RD_CG, data); 1533 1534 data = RREG32(mmMC_CITF_MISC_VM_CG); 1535 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1536 WREG32(mmMC_CITF_MISC_VM_CG, data); 1537 1538 data = RREG32(mmVM_L2_CG); 1539 data |= VM_L2_CG__ENABLE_MASK; 1540 WREG32(mmVM_L2_CG, data); 1541 } else { 1542 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1543 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1544 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1545 1546 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1547 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1548 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1549 1550 data = RREG32(mmMC_HUB_MISC_VM_CG); 1551 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1552 WREG32(mmMC_HUB_MISC_VM_CG, data); 1553 1554 data = RREG32(mmMC_XPB_CLK_GAT); 1555 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1556 WREG32(mmMC_XPB_CLK_GAT, data); 1557 1558 data = RREG32(mmATC_MISC_CG); 1559 data &= ~ATC_MISC_CG__ENABLE_MASK; 1560 WREG32(mmATC_MISC_CG, data); 1561 1562 data = RREG32(mmMC_CITF_MISC_WR_CG); 1563 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1564 WREG32(mmMC_CITF_MISC_WR_CG, data); 1565 1566 data = RREG32(mmMC_CITF_MISC_RD_CG); 1567 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1568 WREG32(mmMC_CITF_MISC_RD_CG, data); 1569 1570 data = RREG32(mmMC_CITF_MISC_VM_CG); 1571 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1572 WREG32(mmMC_CITF_MISC_VM_CG, data); 1573 1574 data = RREG32(mmVM_L2_CG); 1575 data &= ~VM_L2_CG__ENABLE_MASK; 1576 WREG32(mmVM_L2_CG, data); 1577 } 1578 } 1579 1580 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1581 bool enable) 1582 { 1583 uint32_t data; 1584 1585 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1586 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1587 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1588 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1589 1590 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1591 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1592 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1593 1594 data = RREG32(mmMC_HUB_MISC_VM_CG); 1595 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1596 WREG32(mmMC_HUB_MISC_VM_CG, data); 1597 1598 data = RREG32(mmMC_XPB_CLK_GAT); 1599 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1600 WREG32(mmMC_XPB_CLK_GAT, data); 1601 1602 data = RREG32(mmATC_MISC_CG); 1603 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1604 WREG32(mmATC_MISC_CG, data); 1605 1606 data = RREG32(mmMC_CITF_MISC_WR_CG); 1607 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1608 WREG32(mmMC_CITF_MISC_WR_CG, data); 1609 1610 data = RREG32(mmMC_CITF_MISC_RD_CG); 1611 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1612 WREG32(mmMC_CITF_MISC_RD_CG, data); 1613 1614 data = RREG32(mmMC_CITF_MISC_VM_CG); 1615 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1616 WREG32(mmMC_CITF_MISC_VM_CG, data); 1617 1618 data = RREG32(mmVM_L2_CG); 1619 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1620 WREG32(mmVM_L2_CG, data); 1621 } else { 1622 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1623 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1624 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1625 1626 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1627 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1628 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1629 1630 data = RREG32(mmMC_HUB_MISC_VM_CG); 1631 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1632 WREG32(mmMC_HUB_MISC_VM_CG, data); 1633 1634 data = RREG32(mmMC_XPB_CLK_GAT); 1635 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1636 WREG32(mmMC_XPB_CLK_GAT, data); 1637 1638 data = RREG32(mmATC_MISC_CG); 1639 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1640 WREG32(mmATC_MISC_CG, data); 1641 1642 data = RREG32(mmMC_CITF_MISC_WR_CG); 1643 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1644 WREG32(mmMC_CITF_MISC_WR_CG, data); 1645 1646 data = RREG32(mmMC_CITF_MISC_RD_CG); 1647 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1648 WREG32(mmMC_CITF_MISC_RD_CG, data); 1649 1650 data = RREG32(mmMC_CITF_MISC_VM_CG); 1651 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1652 WREG32(mmMC_CITF_MISC_VM_CG, data); 1653 1654 data = RREG32(mmVM_L2_CG); 1655 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1656 WREG32(mmVM_L2_CG, data); 1657 } 1658 } 1659 1660 static int gmc_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1661 enum amd_clockgating_state state) 1662 { 1663 struct amdgpu_device *adev = ip_block->adev; 1664 1665 if (amdgpu_sriov_vf(adev)) 1666 return 0; 1667 1668 switch (adev->asic_type) { 1669 case CHIP_FIJI: 1670 fiji_update_mc_medium_grain_clock_gating(adev, 1671 state == AMD_CG_STATE_GATE); 1672 fiji_update_mc_light_sleep(adev, 1673 state == AMD_CG_STATE_GATE); 1674 break; 1675 default: 1676 break; 1677 } 1678 return 0; 1679 } 1680 1681 static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1682 enum amd_powergating_state state) 1683 { 1684 return 0; 1685 } 1686 1687 static void gmc_v8_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1688 { 1689 struct amdgpu_device *adev = ip_block->adev; 1690 int data; 1691 1692 if (amdgpu_sriov_vf(adev)) 1693 *flags = 0; 1694 1695 /* AMD_CG_SUPPORT_MC_MGCG */ 1696 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1697 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1698 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1699 1700 /* AMD_CG_SUPPORT_MC_LS */ 1701 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1702 *flags |= AMD_CG_SUPPORT_MC_LS; 1703 } 1704 1705 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1706 .name = "gmc_v8_0", 1707 .early_init = gmc_v8_0_early_init, 1708 .late_init = gmc_v8_0_late_init, 1709 .sw_init = gmc_v8_0_sw_init, 1710 .sw_fini = gmc_v8_0_sw_fini, 1711 .hw_init = gmc_v8_0_hw_init, 1712 .hw_fini = gmc_v8_0_hw_fini, 1713 .suspend = gmc_v8_0_suspend, 1714 .resume = gmc_v8_0_resume, 1715 .is_idle = gmc_v8_0_is_idle, 1716 .wait_for_idle = gmc_v8_0_wait_for_idle, 1717 .check_soft_reset = gmc_v8_0_check_soft_reset, 1718 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1719 .soft_reset = gmc_v8_0_soft_reset, 1720 .post_soft_reset = gmc_v8_0_post_soft_reset, 1721 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1722 .set_powergating_state = gmc_v8_0_set_powergating_state, 1723 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1724 }; 1725 1726 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1727 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1728 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid, 1729 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1730 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1731 .set_prt = gmc_v8_0_set_prt, 1732 .get_vm_pde = gmc_v8_0_get_vm_pde, 1733 .get_vm_pte = gmc_v8_0_get_vm_pte, 1734 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size, 1735 }; 1736 1737 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1738 .set = gmc_v8_0_vm_fault_interrupt_state, 1739 .process = gmc_v8_0_process_interrupt, 1740 }; 1741 1742 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1743 { 1744 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1745 } 1746 1747 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1748 { 1749 adev->gmc.vm_fault.num_types = 1; 1750 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1751 } 1752 1753 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = { 1754 .type = AMD_IP_BLOCK_TYPE_GMC, 1755 .major = 8, 1756 .minor = 0, 1757 .rev = 0, 1758 .funcs = &gmc_v8_0_ip_funcs, 1759 }; 1760 1761 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = { 1762 .type = AMD_IP_BLOCK_TYPE_GMC, 1763 .major = 8, 1764 .minor = 1, 1765 .rev = 0, 1766 .funcs = &gmc_v8_0_ip_funcs, 1767 }; 1768 1769 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = { 1770 .type = AMD_IP_BLOCK_TYPE_GMC, 1771 .major = 8, 1772 .minor = 5, 1773 .rev = 0, 1774 .funcs = &gmc_v8_0_ip_funcs, 1775 }; 1776