1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "gmc_v8_0.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_amdkfd.h" 33 #include "amdgpu_gem.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "bif/bif_5_0_d.h" 39 #include "bif/bif_5_0_sh_mask.h" 40 41 #include "oss/oss_3_0_d.h" 42 #include "oss/oss_3_0_sh_mask.h" 43 44 #include "dce/dce_10_0_d.h" 45 #include "dce/dce_10_0_sh_mask.h" 46 47 #include "vid.h" 48 #include "vi.h" 49 50 #include "amdgpu_atombios.h" 51 52 #include "ivsrcid/ivsrcid_vislands30.h" 53 54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 56 static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block); 57 58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); 66 67 static const u32 golden_settings_tonga_a11[] = { 68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 75 }; 76 77 static const u32 tonga_mgcg_cgcg_init[] = { 78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 79 }; 80 81 static const u32 golden_settings_fiji_a10[] = { 82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 86 }; 87 88 static const u32 fiji_mgcg_cgcg_init[] = { 89 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 90 }; 91 92 static const u32 golden_settings_polaris11_a11[] = { 93 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 94 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 95 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 96 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 97 }; 98 99 static const u32 golden_settings_polaris10_a11[] = { 100 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 101 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 102 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 103 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 104 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 105 }; 106 107 static const u32 cz_mgcg_cgcg_init[] = { 108 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 109 }; 110 111 static const u32 stoney_mgcg_cgcg_init[] = { 112 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 113 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 114 }; 115 116 static const u32 golden_settings_stoney_common[] = { 117 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 118 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 119 }; 120 121 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 122 { 123 switch (adev->asic_type) { 124 case CHIP_FIJI: 125 amdgpu_device_program_register_sequence(adev, 126 fiji_mgcg_cgcg_init, 127 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 128 amdgpu_device_program_register_sequence(adev, 129 golden_settings_fiji_a10, 130 ARRAY_SIZE(golden_settings_fiji_a10)); 131 break; 132 case CHIP_TONGA: 133 amdgpu_device_program_register_sequence(adev, 134 tonga_mgcg_cgcg_init, 135 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 136 amdgpu_device_program_register_sequence(adev, 137 golden_settings_tonga_a11, 138 ARRAY_SIZE(golden_settings_tonga_a11)); 139 break; 140 case CHIP_POLARIS11: 141 case CHIP_POLARIS12: 142 case CHIP_VEGAM: 143 amdgpu_device_program_register_sequence(adev, 144 golden_settings_polaris11_a11, 145 ARRAY_SIZE(golden_settings_polaris11_a11)); 146 break; 147 case CHIP_POLARIS10: 148 amdgpu_device_program_register_sequence(adev, 149 golden_settings_polaris10_a11, 150 ARRAY_SIZE(golden_settings_polaris10_a11)); 151 break; 152 case CHIP_CARRIZO: 153 amdgpu_device_program_register_sequence(adev, 154 cz_mgcg_cgcg_init, 155 ARRAY_SIZE(cz_mgcg_cgcg_init)); 156 break; 157 case CHIP_STONEY: 158 amdgpu_device_program_register_sequence(adev, 159 stoney_mgcg_cgcg_init, 160 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 161 amdgpu_device_program_register_sequence(adev, 162 golden_settings_stoney_common, 163 ARRAY_SIZE(golden_settings_stoney_common)); 164 break; 165 default: 166 break; 167 } 168 } 169 170 /** 171 * gmc_v8_0_init_microcode - load ucode images from disk 172 * 173 * @adev: amdgpu_device pointer 174 * 175 * Use the firmware interface to load the ucode images into 176 * the driver (not loaded into hw). 177 * Returns 0 on success, error on failure. 178 */ 179 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 180 { 181 const char *chip_name; 182 int err; 183 184 DRM_DEBUG("\n"); 185 186 switch (adev->asic_type) { 187 case CHIP_TONGA: 188 chip_name = "tonga"; 189 break; 190 case CHIP_POLARIS11: 191 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 192 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) 193 chip_name = "polaris11_k"; 194 else 195 chip_name = "polaris11"; 196 break; 197 case CHIP_POLARIS10: 198 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) 199 chip_name = "polaris10_k"; 200 else 201 chip_name = "polaris10"; 202 break; 203 case CHIP_POLARIS12: 204 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) { 205 chip_name = "polaris12_k"; 206 } else { 207 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159); 208 /* Polaris12 32bit ASIC needs a special MC firmware */ 209 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40) 210 chip_name = "polaris12_32"; 211 else 212 chip_name = "polaris12"; 213 } 214 break; 215 case CHIP_FIJI: 216 case CHIP_CARRIZO: 217 case CHIP_STONEY: 218 case CHIP_VEGAM: 219 return 0; 220 default: 221 return -EINVAL; 222 } 223 224 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, 225 "amdgpu/%s_mc.bin", chip_name); 226 if (err) { 227 pr_err("mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name); 228 amdgpu_ucode_release(&adev->gmc.fw); 229 } 230 return err; 231 } 232 233 /** 234 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 235 * 236 * @adev: amdgpu_device pointer 237 * 238 * Load the GDDR MC ucode into the hw (VI). 239 * Returns 0 on success, error on failure. 240 */ 241 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 242 { 243 const struct mc_firmware_header_v1_0 *hdr; 244 const __le32 *fw_data = NULL; 245 const __le32 *io_mc_regs = NULL; 246 u32 running; 247 int i, ucode_size, regs_size; 248 249 /* Skip MC ucode loading on SR-IOV capable boards. 250 * vbios does this for us in asic_init in that case. 251 * Skip MC ucode loading on VF, because hypervisor will do that 252 * for this adaptor. 253 */ 254 if (amdgpu_sriov_bios(adev)) 255 return 0; 256 257 if (!adev->gmc.fw) 258 return -EINVAL; 259 260 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 261 amdgpu_ucode_print_mc_hdr(&hdr->header); 262 263 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 264 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 265 io_mc_regs = (const __le32 *) 266 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 267 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 268 fw_data = (const __le32 *) 269 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 270 271 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 272 273 if (running == 0) { 274 /* reset the engine and set to writable */ 275 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 276 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 277 278 /* load mc io regs */ 279 for (i = 0; i < regs_size; i++) { 280 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 281 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 282 } 283 /* load the MC ucode */ 284 for (i = 0; i < ucode_size; i++) 285 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 286 287 /* put the engine back into the active state */ 288 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 289 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 290 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 291 292 /* wait for training to complete */ 293 for (i = 0; i < adev->usec_timeout; i++) { 294 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 295 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 296 break; 297 udelay(1); 298 } 299 for (i = 0; i < adev->usec_timeout; i++) { 300 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 301 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 302 break; 303 udelay(1); 304 } 305 } 306 307 return 0; 308 } 309 310 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 311 { 312 const struct mc_firmware_header_v1_0 *hdr; 313 const __le32 *fw_data = NULL; 314 const __le32 *io_mc_regs = NULL; 315 u32 data; 316 int i, ucode_size, regs_size; 317 318 /* Skip MC ucode loading on SR-IOV capable boards. 319 * vbios does this for us in asic_init in that case. 320 * Skip MC ucode loading on VF, because hypervisor will do that 321 * for this adaptor. 322 */ 323 if (amdgpu_sriov_bios(adev)) 324 return 0; 325 326 if (!adev->gmc.fw) 327 return -EINVAL; 328 329 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 330 amdgpu_ucode_print_mc_hdr(&hdr->header); 331 332 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 333 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 334 io_mc_regs = (const __le32 *) 335 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 336 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 337 fw_data = (const __le32 *) 338 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 339 340 data = RREG32(mmMC_SEQ_MISC0); 341 data &= ~(0x40); 342 WREG32(mmMC_SEQ_MISC0, data); 343 344 /* load mc io regs */ 345 for (i = 0; i < regs_size; i++) { 346 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 347 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 348 } 349 350 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 351 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 352 353 /* load the MC ucode */ 354 for (i = 0; i < ucode_size; i++) 355 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 356 357 /* put the engine back into the active state */ 358 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 359 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 360 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 361 362 /* wait for training to complete */ 363 for (i = 0; i < adev->usec_timeout; i++) { 364 data = RREG32(mmMC_SEQ_MISC0); 365 if (data & 0x80) 366 break; 367 udelay(1); 368 } 369 370 return 0; 371 } 372 373 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 374 struct amdgpu_gmc *mc) 375 { 376 u64 base = 0; 377 378 if (!amdgpu_sriov_vf(adev)) 379 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 380 base <<= 24; 381 382 amdgpu_gmc_set_agp_default(adev, mc); 383 amdgpu_gmc_vram_location(adev, mc, base); 384 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 385 } 386 387 /** 388 * gmc_v8_0_mc_program - program the GPU memory controller 389 * 390 * @adev: amdgpu_device pointer 391 * 392 * Set the location of vram, gart, and AGP in the GPU's 393 * physical address space (VI). 394 */ 395 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 396 { 397 struct amdgpu_ip_block *ip_block; 398 u32 tmp; 399 int i, j; 400 401 /* Initialize HDP */ 402 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 403 WREG32((0xb05 + j), 0x00000000); 404 WREG32((0xb06 + j), 0x00000000); 405 WREG32((0xb07 + j), 0x00000000); 406 WREG32((0xb08 + j), 0x00000000); 407 WREG32((0xb09 + j), 0x00000000); 408 } 409 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 410 411 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); 412 if (!ip_block) 413 return; 414 415 if (gmc_v8_0_wait_for_idle(ip_block)) 416 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 417 418 if (adev->mode_info.num_crtc) { 419 /* Lockout access through VGA aperture*/ 420 tmp = RREG32(mmVGA_HDP_CONTROL); 421 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 422 WREG32(mmVGA_HDP_CONTROL, tmp); 423 424 /* disable VGA render */ 425 tmp = RREG32(mmVGA_RENDER_CONTROL); 426 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 427 WREG32(mmVGA_RENDER_CONTROL, tmp); 428 } 429 /* Update configuration */ 430 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 431 adev->gmc.vram_start >> 12); 432 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 433 adev->gmc.vram_end >> 12); 434 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 435 adev->mem_scratch.gpu_addr >> 12); 436 437 if (amdgpu_sriov_vf(adev)) { 438 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 439 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 440 WREG32(mmMC_VM_FB_LOCATION, tmp); 441 /* XXX double check these! */ 442 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 443 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 444 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 445 } 446 447 WREG32(mmMC_VM_AGP_BASE, 0); 448 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); 449 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); 450 if (gmc_v8_0_wait_for_idle(ip_block)) 451 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 452 453 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 454 455 tmp = RREG32(mmHDP_MISC_CNTL); 456 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 457 WREG32(mmHDP_MISC_CNTL, tmp); 458 459 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 460 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 461 } 462 463 /** 464 * gmc_v8_0_mc_init - initialize the memory controller driver params 465 * 466 * @adev: amdgpu_device pointer 467 * 468 * Look up the amount of vram, vram width, and decide how to place 469 * vram and gart within the GPU's physical address space (VI). 470 * Returns 0 for success. 471 */ 472 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 473 { 474 int r; 475 u32 tmp; 476 477 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 478 if (!adev->gmc.vram_width) { 479 int chansize, numchan; 480 481 /* Get VRAM informations */ 482 tmp = RREG32(mmMC_ARB_RAMCFG); 483 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) 484 chansize = 64; 485 else 486 chansize = 32; 487 488 tmp = RREG32(mmMC_SHARED_CHMAP); 489 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 490 case 0: 491 default: 492 numchan = 1; 493 break; 494 case 1: 495 numchan = 2; 496 break; 497 case 2: 498 numchan = 4; 499 break; 500 case 3: 501 numchan = 8; 502 break; 503 case 4: 504 numchan = 3; 505 break; 506 case 5: 507 numchan = 6; 508 break; 509 case 6: 510 numchan = 10; 511 break; 512 case 7: 513 numchan = 12; 514 break; 515 case 8: 516 numchan = 16; 517 break; 518 } 519 adev->gmc.vram_width = numchan * chansize; 520 } 521 /* size in MB on si */ 522 tmp = RREG32(mmCONFIG_MEMSIZE); 523 /* some boards may have garbage in the upper 16 bits */ 524 if (tmp & 0xffff0000) { 525 drm_info(adev_to_drm(adev), "Probably bad vram size: 0x%08x\n", tmp); 526 if (tmp & 0xffff) 527 tmp &= 0xffff; 528 } 529 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL; 530 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 531 532 if (!(adev->flags & AMD_IS_APU)) { 533 r = amdgpu_device_resize_fb_bar(adev); 534 if (r) 535 return r; 536 } 537 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 538 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 539 540 #ifdef CONFIG_X86_64 541 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 542 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 543 adev->gmc.aper_size = adev->gmc.real_vram_size; 544 } 545 #endif 546 547 adev->gmc.visible_vram_size = adev->gmc.aper_size; 548 549 /* set the gart size */ 550 switch (adev->asic_type) { 551 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 552 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 553 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 554 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 555 amdgpu_gmc_set_gart_size(adev, SZ_1G); 556 break; 557 case CHIP_POLARIS10: /* all engines support GPUVM */ 558 case CHIP_POLARIS11: /* all engines support GPUVM */ 559 case CHIP_POLARIS12: /* all engines support GPUVM */ 560 case CHIP_VEGAM: /* all engines support GPUVM */ 561 default: 562 amdgpu_gmc_set_gart_size(adev, SZ_256M); 563 break; 564 } 565 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 566 567 return 0; 568 } 569 570 /** 571 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid 572 * 573 * @adev: amdgpu_device pointer 574 * @pasid: pasid to be flush 575 * @flush_type: type of flush 576 * @all_hub: flush all hubs 577 * @inst: is used to select which instance of KIQ to use for the invalidation 578 * 579 * Flush the TLB for the requested pasid. 580 */ 581 static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 582 uint16_t pasid, uint32_t flush_type, 583 bool all_hub, uint32_t inst) 584 { 585 u32 mask = 0x0; 586 int vmid; 587 588 for (vmid = 1; vmid < 16; vmid++) { 589 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 590 591 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 592 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) 593 mask |= 1 << vmid; 594 } 595 596 WREG32(mmVM_INVALIDATE_REQUEST, mask); 597 RREG32(mmVM_INVALIDATE_RESPONSE); 598 } 599 600 /* 601 * GART 602 * VMID 0 is the physical GPU addresses as used by the kernel. 603 * VMIDs 1-15 are used for userspace clients and are handled 604 * by the amdgpu vm/hsa code. 605 */ 606 607 /** 608 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 609 * 610 * @adev: amdgpu_device pointer 611 * @vmid: vm instance to flush 612 * @vmhub: which hub to flush 613 * @flush_type: type of flush 614 * 615 * Flush the TLB for the requested page table (VI). 616 */ 617 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 618 uint32_t vmhub, uint32_t flush_type) 619 { 620 /* bits 0-15 are the VM contexts0-15 */ 621 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 622 } 623 624 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 625 unsigned int vmid, uint64_t pd_addr) 626 { 627 uint32_t reg; 628 629 if (vmid < 8) 630 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 631 else 632 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 633 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 634 635 /* bits 0-15 are the VM contexts0-15 */ 636 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 637 638 return pd_addr; 639 } 640 641 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 642 unsigned int pasid) 643 { 644 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 645 } 646 647 /* 648 * PTE format on VI: 649 * 63:40 reserved 650 * 39:12 4k physical page base address 651 * 11:7 fragment 652 * 6 write 653 * 5 read 654 * 4 exe 655 * 3 reserved 656 * 2 snooped 657 * 1 system 658 * 0 valid 659 * 660 * PDE format on VI: 661 * 63:59 block fragment size 662 * 58:40 reserved 663 * 39:1 physical base address of PTE 664 * bits 5:1 must be 0. 665 * 0 valid 666 */ 667 668 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 669 uint64_t *addr, uint64_t *flags) 670 { 671 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 672 } 673 674 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, 675 struct amdgpu_vm *vm, 676 struct amdgpu_bo *bo, 677 uint32_t vm_flags, 678 uint64_t *flags) 679 { 680 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 681 *flags |= AMDGPU_PTE_EXECUTABLE; 682 else 683 *flags &= ~AMDGPU_PTE_EXECUTABLE; 684 *flags &= ~AMDGPU_PTE_PRT; 685 } 686 687 /** 688 * gmc_v8_0_set_fault_enable_default - update VM fault handling 689 * 690 * @adev: amdgpu_device pointer 691 * @value: true redirects VM faults to the default page 692 */ 693 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 694 bool value) 695 { 696 u32 tmp; 697 698 tmp = RREG32(mmVM_CONTEXT1_CNTL); 699 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 700 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 701 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 702 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 703 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 704 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 705 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 706 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 707 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 708 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 709 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 710 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 711 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 712 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 713 WREG32(mmVM_CONTEXT1_CNTL, tmp); 714 } 715 716 /** 717 * gmc_v8_0_set_prt() - set PRT VM fault 718 * 719 * @adev: amdgpu_device pointer 720 * @enable: enable/disable VM fault handling for PRT 721 */ 722 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 723 { 724 u32 tmp; 725 726 if (enable && !adev->gmc.prt_warning) { 727 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 728 adev->gmc.prt_warning = true; 729 } 730 731 tmp = RREG32(mmVM_PRT_CNTL); 732 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 733 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 734 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 735 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 736 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 737 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 738 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 739 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 740 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 741 L2_CACHE_STORE_INVALID_ENTRIES, enable); 742 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 743 L1_TLB_STORE_INVALID_ENTRIES, enable); 744 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 745 MASK_PDE0_FAULT, enable); 746 WREG32(mmVM_PRT_CNTL, tmp); 747 748 if (enable) { 749 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >> 750 AMDGPU_GPU_PAGE_SHIFT; 751 uint32_t high = adev->vm_manager.max_pfn - 752 (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT); 753 754 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 755 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 756 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 757 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 758 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 759 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 760 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 761 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 762 } else { 763 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 764 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 765 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 766 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 767 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 768 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 769 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 770 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 771 } 772 } 773 774 /** 775 * gmc_v8_0_gart_enable - gart enable 776 * 777 * @adev: amdgpu_device pointer 778 * 779 * This sets up the TLBs, programs the page tables for VMID0, 780 * sets up the hw for VMIDs 1-15 which are allocated on 781 * demand, and sets up the global locations for the LDS, GDS, 782 * and GPUVM for FSA64 clients (VI). 783 * Returns 0 for success, errors for failure. 784 */ 785 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 786 { 787 uint64_t table_addr; 788 u32 tmp, field; 789 int i; 790 791 if (adev->gart.bo == NULL) { 792 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 793 return -EINVAL; 794 } 795 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 796 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 797 798 /* Setup TLB control */ 799 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 800 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 801 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 802 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 803 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 804 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 805 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 806 /* Setup L2 cache */ 807 tmp = RREG32(mmVM_L2_CNTL); 808 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 809 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 810 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 811 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 812 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 813 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 814 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 815 WREG32(mmVM_L2_CNTL, tmp); 816 tmp = RREG32(mmVM_L2_CNTL2); 817 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 818 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 819 WREG32(mmVM_L2_CNTL2, tmp); 820 821 field = adev->vm_manager.fragment_size; 822 tmp = RREG32(mmVM_L2_CNTL3); 823 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 824 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 825 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 826 WREG32(mmVM_L2_CNTL3, tmp); 827 /* XXX: set to enable PTE/PDE in system memory */ 828 tmp = RREG32(mmVM_L2_CNTL4); 829 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 830 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 831 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 832 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 833 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 834 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 835 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 836 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 837 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 838 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 839 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 840 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 841 WREG32(mmVM_L2_CNTL4, tmp); 842 /* setup context0 */ 843 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 844 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 845 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 846 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 847 (u32)(adev->dummy_page_addr >> 12)); 848 WREG32(mmVM_CONTEXT0_CNTL2, 0); 849 tmp = RREG32(mmVM_CONTEXT0_CNTL); 850 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 851 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 852 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 853 WREG32(mmVM_CONTEXT0_CNTL, tmp); 854 855 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 856 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 857 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 858 859 /* empty context1-15 */ 860 /* FIXME start with 4G, once using 2 level pt switch to full 861 * vm size space 862 */ 863 /* set vm size, must be a multiple of 4 */ 864 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 865 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 866 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 867 if (i < 8) 868 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 869 table_addr >> 12); 870 else 871 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 872 table_addr >> 12); 873 } 874 875 /* enable context1-15 */ 876 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 877 (u32)(adev->dummy_page_addr >> 12)); 878 WREG32(mmVM_CONTEXT1_CNTL2, 4); 879 tmp = RREG32(mmVM_CONTEXT1_CNTL); 880 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 881 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 882 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 883 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 884 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 885 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 886 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 887 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 888 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 889 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 890 adev->vm_manager.block_size - 9); 891 WREG32(mmVM_CONTEXT1_CNTL, tmp); 892 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 893 gmc_v8_0_set_fault_enable_default(adev, false); 894 else 895 gmc_v8_0_set_fault_enable_default(adev, true); 896 897 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); 898 drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", 899 (unsigned int)(adev->gmc.gart_size >> 20), 900 (unsigned long long)table_addr); 901 return 0; 902 } 903 904 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 905 { 906 int r; 907 908 if (adev->gart.bo) { 909 WARN(1, "R600 PCIE GART already initialized\n"); 910 return 0; 911 } 912 /* Initialize common gart structure */ 913 r = amdgpu_gart_init(adev); 914 if (r) 915 return r; 916 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 917 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 918 return amdgpu_gart_table_vram_alloc(adev); 919 } 920 921 /** 922 * gmc_v8_0_gart_disable - gart disable 923 * 924 * @adev: amdgpu_device pointer 925 * 926 * This disables all VM page table (VI). 927 */ 928 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 929 { 930 u32 tmp; 931 932 /* Disable all tables */ 933 WREG32(mmVM_CONTEXT0_CNTL, 0); 934 WREG32(mmVM_CONTEXT1_CNTL, 0); 935 /* Setup TLB control */ 936 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 937 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 938 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 939 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 940 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 941 /* Setup L2 cache */ 942 tmp = RREG32(mmVM_L2_CNTL); 943 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 944 WREG32(mmVM_L2_CNTL, tmp); 945 WREG32(mmVM_L2_CNTL2, 0); 946 } 947 948 /** 949 * gmc_v8_0_vm_decode_fault - print human readable fault info 950 * 951 * @adev: amdgpu_device pointer 952 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 953 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 954 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 955 * @pasid: debug logging only - no functional use 956 * 957 * Print human readable fault information (VI). 958 */ 959 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 960 u32 addr, u32 mc_client, unsigned int pasid) 961 { 962 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 963 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 964 PROTECTIONS); 965 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 966 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 967 u32 mc_id; 968 969 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 970 MEMORY_CLIENT_ID); 971 972 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 973 protections, vmid, pasid, addr, 974 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 975 MEMORY_CLIENT_RW) ? 976 "write" : "read", block, mc_client, mc_id); 977 } 978 979 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 980 { 981 switch (mc_seq_vram_type) { 982 case MC_SEQ_MISC0__MT__GDDR1: 983 return AMDGPU_VRAM_TYPE_GDDR1; 984 case MC_SEQ_MISC0__MT__DDR2: 985 return AMDGPU_VRAM_TYPE_DDR2; 986 case MC_SEQ_MISC0__MT__GDDR3: 987 return AMDGPU_VRAM_TYPE_GDDR3; 988 case MC_SEQ_MISC0__MT__GDDR4: 989 return AMDGPU_VRAM_TYPE_GDDR4; 990 case MC_SEQ_MISC0__MT__GDDR5: 991 return AMDGPU_VRAM_TYPE_GDDR5; 992 case MC_SEQ_MISC0__MT__HBM: 993 return AMDGPU_VRAM_TYPE_HBM; 994 case MC_SEQ_MISC0__MT__DDR3: 995 return AMDGPU_VRAM_TYPE_DDR3; 996 default: 997 return AMDGPU_VRAM_TYPE_UNKNOWN; 998 } 999 } 1000 1001 static int gmc_v8_0_early_init(struct amdgpu_ip_block *ip_block) 1002 { 1003 struct amdgpu_device *adev = ip_block->adev; 1004 1005 gmc_v8_0_set_gmc_funcs(adev); 1006 gmc_v8_0_set_irq_funcs(adev); 1007 1008 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1009 adev->gmc.shared_aperture_end = 1010 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1011 adev->gmc.private_aperture_start = 1012 adev->gmc.shared_aperture_end + 1; 1013 adev->gmc.private_aperture_end = 1014 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1015 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 1016 1017 return 0; 1018 } 1019 1020 static int gmc_v8_0_late_init(struct amdgpu_ip_block *ip_block) 1021 { 1022 struct amdgpu_device *adev = ip_block->adev; 1023 1024 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1025 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1026 else 1027 return 0; 1028 } 1029 1030 static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1031 { 1032 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1033 unsigned int size; 1034 1035 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1036 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1037 } else { 1038 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1039 1040 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1041 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1042 4); 1043 } 1044 1045 return size; 1046 } 1047 1048 #define mmMC_SEQ_MISC0_FIJI 0xA71 1049 1050 static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block) 1051 { 1052 int r; 1053 struct amdgpu_device *adev = ip_block->adev; 1054 1055 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 1056 1057 if (adev->flags & AMD_IS_APU) { 1058 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1059 } else { 1060 u32 tmp; 1061 1062 if ((adev->asic_type == CHIP_FIJI) || 1063 (adev->asic_type == CHIP_VEGAM)) 1064 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1065 else 1066 tmp = RREG32(mmMC_SEQ_MISC0); 1067 tmp &= MC_SEQ_MISC0__MT__MASK; 1068 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1069 } 1070 1071 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1072 if (r) 1073 return r; 1074 1075 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1076 if (r) 1077 return r; 1078 1079 /* Adjust VM size here. 1080 * Currently set to 4GB ((1 << 20) 4k pages). 1081 * Max GPUVM size for cayman and SI is 40 bits. 1082 */ 1083 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1084 1085 /* Set the internal MC address mask 1086 * This is the max address of the GPU's 1087 * internal address space. 1088 */ 1089 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1090 adev->gmc.pte_addr_mask = 0x000000FFFFFFF000ULL; /* 40 bit PA */ 1091 1092 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1093 if (r) { 1094 pr_warn("No suitable DMA available\n"); 1095 return r; 1096 } 1097 adev->need_swiotlb = drm_need_swiotlb(40); 1098 1099 r = gmc_v8_0_init_microcode(adev); 1100 if (r) { 1101 DRM_ERROR("Failed to load mc firmware!\n"); 1102 return r; 1103 } 1104 1105 r = gmc_v8_0_mc_init(adev); 1106 if (r) 1107 return r; 1108 1109 /* Memory manager */ 1110 r = amdgpu_bo_init(adev); 1111 if (r) 1112 return r; 1113 1114 r = gmc_v8_0_gart_init(adev); 1115 if (r) 1116 return r; 1117 1118 /* 1119 * number of VMs 1120 * VMID 0 is reserved for System 1121 * amdgpu graphics/compute will use VMIDs 1-7 1122 * amdkfd will use VMIDs 8-15 1123 */ 1124 adev->vm_manager.first_kfd_vmid = 8; 1125 amdgpu_vm_manager_init(adev); 1126 1127 /* base offset of vram pages */ 1128 if (adev->flags & AMD_IS_APU) { 1129 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1130 1131 tmp <<= 22; 1132 adev->vm_manager.vram_base_offset = tmp; 1133 } else { 1134 adev->vm_manager.vram_base_offset = 0; 1135 } 1136 1137 adev->gmc.vm_fault_info = kmalloc_obj(struct kfd_vm_fault_info); 1138 if (!adev->gmc.vm_fault_info) 1139 return -ENOMEM; 1140 atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); 1141 1142 return 0; 1143 } 1144 1145 static int gmc_v8_0_sw_fini(struct amdgpu_ip_block *ip_block) 1146 { 1147 struct amdgpu_device *adev = ip_block->adev; 1148 1149 amdgpu_gem_force_release(adev); 1150 amdgpu_vm_manager_fini(adev); 1151 kfree(adev->gmc.vm_fault_info); 1152 amdgpu_gart_table_vram_free(adev); 1153 amdgpu_bo_fini(adev); 1154 amdgpu_ucode_release(&adev->gmc.fw); 1155 1156 return 0; 1157 } 1158 1159 static int gmc_v8_0_hw_init(struct amdgpu_ip_block *ip_block) 1160 { 1161 int r; 1162 struct amdgpu_device *adev = ip_block->adev; 1163 1164 gmc_v8_0_init_golden_registers(adev); 1165 1166 gmc_v8_0_mc_program(adev); 1167 1168 if (adev->asic_type == CHIP_TONGA) { 1169 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1170 if (r) { 1171 DRM_ERROR("Failed to load MC firmware!\n"); 1172 return r; 1173 } 1174 } else if (adev->asic_type == CHIP_POLARIS11 || 1175 adev->asic_type == CHIP_POLARIS10 || 1176 adev->asic_type == CHIP_POLARIS12) { 1177 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1178 if (r) { 1179 DRM_ERROR("Failed to load MC firmware!\n"); 1180 return r; 1181 } 1182 } 1183 1184 r = gmc_v8_0_gart_enable(adev); 1185 if (r) 1186 return r; 1187 1188 if (amdgpu_emu_mode == 1) 1189 return amdgpu_gmc_vram_checking(adev); 1190 1191 return 0; 1192 } 1193 1194 static int gmc_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) 1195 { 1196 struct amdgpu_device *adev = ip_block->adev; 1197 1198 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1199 gmc_v8_0_gart_disable(adev); 1200 1201 return 0; 1202 } 1203 1204 static int gmc_v8_0_suspend(struct amdgpu_ip_block *ip_block) 1205 { 1206 gmc_v8_0_hw_fini(ip_block); 1207 1208 return 0; 1209 } 1210 1211 static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block) 1212 { 1213 int r; 1214 1215 r = gmc_v8_0_hw_init(ip_block); 1216 if (r) 1217 return r; 1218 1219 amdgpu_vmid_reset_all(ip_block->adev); 1220 1221 return 0; 1222 } 1223 1224 static bool gmc_v8_0_is_idle(struct amdgpu_ip_block *ip_block) 1225 { 1226 struct amdgpu_device *adev = ip_block->adev; 1227 u32 tmp = RREG32(mmSRBM_STATUS); 1228 1229 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1230 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1231 return false; 1232 1233 return true; 1234 } 1235 1236 static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1237 { 1238 unsigned int i; 1239 u32 tmp; 1240 struct amdgpu_device *adev = ip_block->adev; 1241 1242 for (i = 0; i < adev->usec_timeout; i++) { 1243 /* read MC_STATUS */ 1244 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1245 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1246 SRBM_STATUS__MCC_BUSY_MASK | 1247 SRBM_STATUS__MCD_BUSY_MASK | 1248 SRBM_STATUS__VMC_BUSY_MASK | 1249 SRBM_STATUS__VMC1_BUSY_MASK); 1250 if (!tmp) 1251 return 0; 1252 udelay(1); 1253 } 1254 return -ETIMEDOUT; 1255 1256 } 1257 1258 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1259 struct amdgpu_irq_src *src, 1260 unsigned int type, 1261 enum amdgpu_interrupt_state state) 1262 { 1263 u32 tmp; 1264 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1265 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1266 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1267 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1268 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1269 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1270 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1271 1272 switch (state) { 1273 case AMDGPU_IRQ_STATE_DISABLE: 1274 /* system context */ 1275 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1276 tmp &= ~bits; 1277 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1278 /* VMs */ 1279 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1280 tmp &= ~bits; 1281 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1282 break; 1283 case AMDGPU_IRQ_STATE_ENABLE: 1284 /* system context */ 1285 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1286 tmp |= bits; 1287 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1288 /* VMs */ 1289 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1290 tmp |= bits; 1291 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1292 break; 1293 default: 1294 break; 1295 } 1296 1297 return 0; 1298 } 1299 1300 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1301 struct amdgpu_irq_src *source, 1302 struct amdgpu_iv_entry *entry) 1303 { 1304 u32 addr, status, mc_client, vmid; 1305 1306 if (amdgpu_sriov_vf(adev)) { 1307 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1308 entry->src_id, entry->src_data[0]); 1309 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1310 return 0; 1311 } 1312 1313 /* Delegate to the soft IRQ handler ring */ 1314 if (adev->irq.ih_soft.enabled && entry->ih != &adev->irq.ih_soft) { 1315 amdgpu_irq_delegate(adev, entry, 4); 1316 return 1; 1317 } 1318 1319 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1320 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1321 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1322 /* reset addr and status */ 1323 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1324 1325 if (!addr && !status) 1326 return 0; 1327 1328 amdgpu_vm_update_fault_cache(adev, entry->pasid, 1329 ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); 1330 1331 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1332 gmc_v8_0_set_fault_enable_default(adev, false); 1333 1334 if (printk_ratelimit()) { 1335 struct amdgpu_task_info *task_info; 1336 1337 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1338 entry->src_id, entry->src_data[0]); 1339 1340 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 1341 if (task_info) { 1342 amdgpu_vm_print_task_info(adev, task_info); 1343 amdgpu_vm_put_task_info(task_info); 1344 } 1345 1346 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1347 addr); 1348 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1349 status); 1350 1351 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1352 entry->pasid); 1353 } 1354 1355 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1356 VMID); 1357 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1358 && !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) { 1359 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1360 u32 protections = REG_GET_FIELD(status, 1361 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1362 PROTECTIONS); 1363 1364 info->vmid = vmid; 1365 info->mc_id = REG_GET_FIELD(status, 1366 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1367 MEMORY_CLIENT_ID); 1368 info->status = status; 1369 info->page_addr = addr; 1370 info->prot_valid = protections & 0x7 ? true : false; 1371 info->prot_read = protections & 0x8 ? true : false; 1372 info->prot_write = protections & 0x10 ? true : false; 1373 info->prot_exec = protections & 0x20 ? true : false; 1374 atomic_set_release(&adev->gmc.vm_fault_info_updated, 1); 1375 } 1376 1377 return 0; 1378 } 1379 1380 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1381 bool enable) 1382 { 1383 uint32_t data; 1384 1385 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1386 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1387 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1388 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1389 1390 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1391 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1392 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1393 1394 data = RREG32(mmMC_HUB_MISC_VM_CG); 1395 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1396 WREG32(mmMC_HUB_MISC_VM_CG, data); 1397 1398 data = RREG32(mmMC_XPB_CLK_GAT); 1399 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1400 WREG32(mmMC_XPB_CLK_GAT, data); 1401 1402 data = RREG32(mmATC_MISC_CG); 1403 data |= ATC_MISC_CG__ENABLE_MASK; 1404 WREG32(mmATC_MISC_CG, data); 1405 1406 data = RREG32(mmMC_CITF_MISC_WR_CG); 1407 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1408 WREG32(mmMC_CITF_MISC_WR_CG, data); 1409 1410 data = RREG32(mmMC_CITF_MISC_RD_CG); 1411 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1412 WREG32(mmMC_CITF_MISC_RD_CG, data); 1413 1414 data = RREG32(mmMC_CITF_MISC_VM_CG); 1415 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1416 WREG32(mmMC_CITF_MISC_VM_CG, data); 1417 1418 data = RREG32(mmVM_L2_CG); 1419 data |= VM_L2_CG__ENABLE_MASK; 1420 WREG32(mmVM_L2_CG, data); 1421 } else { 1422 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1423 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1424 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1425 1426 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1427 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1428 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1429 1430 data = RREG32(mmMC_HUB_MISC_VM_CG); 1431 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1432 WREG32(mmMC_HUB_MISC_VM_CG, data); 1433 1434 data = RREG32(mmMC_XPB_CLK_GAT); 1435 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1436 WREG32(mmMC_XPB_CLK_GAT, data); 1437 1438 data = RREG32(mmATC_MISC_CG); 1439 data &= ~ATC_MISC_CG__ENABLE_MASK; 1440 WREG32(mmATC_MISC_CG, data); 1441 1442 data = RREG32(mmMC_CITF_MISC_WR_CG); 1443 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1444 WREG32(mmMC_CITF_MISC_WR_CG, data); 1445 1446 data = RREG32(mmMC_CITF_MISC_RD_CG); 1447 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1448 WREG32(mmMC_CITF_MISC_RD_CG, data); 1449 1450 data = RREG32(mmMC_CITF_MISC_VM_CG); 1451 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1452 WREG32(mmMC_CITF_MISC_VM_CG, data); 1453 1454 data = RREG32(mmVM_L2_CG); 1455 data &= ~VM_L2_CG__ENABLE_MASK; 1456 WREG32(mmVM_L2_CG, data); 1457 } 1458 } 1459 1460 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1461 bool enable) 1462 { 1463 uint32_t data; 1464 1465 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1466 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1467 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1468 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1469 1470 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1471 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1472 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1473 1474 data = RREG32(mmMC_HUB_MISC_VM_CG); 1475 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1476 WREG32(mmMC_HUB_MISC_VM_CG, data); 1477 1478 data = RREG32(mmMC_XPB_CLK_GAT); 1479 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1480 WREG32(mmMC_XPB_CLK_GAT, data); 1481 1482 data = RREG32(mmATC_MISC_CG); 1483 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1484 WREG32(mmATC_MISC_CG, data); 1485 1486 data = RREG32(mmMC_CITF_MISC_WR_CG); 1487 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1488 WREG32(mmMC_CITF_MISC_WR_CG, data); 1489 1490 data = RREG32(mmMC_CITF_MISC_RD_CG); 1491 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1492 WREG32(mmMC_CITF_MISC_RD_CG, data); 1493 1494 data = RREG32(mmMC_CITF_MISC_VM_CG); 1495 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1496 WREG32(mmMC_CITF_MISC_VM_CG, data); 1497 1498 data = RREG32(mmVM_L2_CG); 1499 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1500 WREG32(mmVM_L2_CG, data); 1501 } else { 1502 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1503 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1504 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1505 1506 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1507 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1508 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1509 1510 data = RREG32(mmMC_HUB_MISC_VM_CG); 1511 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1512 WREG32(mmMC_HUB_MISC_VM_CG, data); 1513 1514 data = RREG32(mmMC_XPB_CLK_GAT); 1515 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1516 WREG32(mmMC_XPB_CLK_GAT, data); 1517 1518 data = RREG32(mmATC_MISC_CG); 1519 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1520 WREG32(mmATC_MISC_CG, data); 1521 1522 data = RREG32(mmMC_CITF_MISC_WR_CG); 1523 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1524 WREG32(mmMC_CITF_MISC_WR_CG, data); 1525 1526 data = RREG32(mmMC_CITF_MISC_RD_CG); 1527 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1528 WREG32(mmMC_CITF_MISC_RD_CG, data); 1529 1530 data = RREG32(mmMC_CITF_MISC_VM_CG); 1531 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1532 WREG32(mmMC_CITF_MISC_VM_CG, data); 1533 1534 data = RREG32(mmVM_L2_CG); 1535 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1536 WREG32(mmVM_L2_CG, data); 1537 } 1538 } 1539 1540 static int gmc_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1541 enum amd_clockgating_state state) 1542 { 1543 struct amdgpu_device *adev = ip_block->adev; 1544 1545 if (amdgpu_sriov_vf(adev)) 1546 return 0; 1547 1548 switch (adev->asic_type) { 1549 case CHIP_FIJI: 1550 fiji_update_mc_medium_grain_clock_gating(adev, 1551 state == AMD_CG_STATE_GATE); 1552 fiji_update_mc_light_sleep(adev, 1553 state == AMD_CG_STATE_GATE); 1554 break; 1555 default: 1556 break; 1557 } 1558 return 0; 1559 } 1560 1561 static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1562 enum amd_powergating_state state) 1563 { 1564 return 0; 1565 } 1566 1567 static void gmc_v8_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1568 { 1569 struct amdgpu_device *adev = ip_block->adev; 1570 int data; 1571 1572 if (amdgpu_sriov_vf(adev)) 1573 *flags = 0; 1574 1575 /* AMD_CG_SUPPORT_MC_MGCG */ 1576 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1577 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1578 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1579 1580 /* AMD_CG_SUPPORT_MC_LS */ 1581 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1582 *flags |= AMD_CG_SUPPORT_MC_LS; 1583 } 1584 1585 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1586 .name = "gmc_v8_0", 1587 .early_init = gmc_v8_0_early_init, 1588 .late_init = gmc_v8_0_late_init, 1589 .sw_init = gmc_v8_0_sw_init, 1590 .sw_fini = gmc_v8_0_sw_fini, 1591 .hw_init = gmc_v8_0_hw_init, 1592 .hw_fini = gmc_v8_0_hw_fini, 1593 .suspend = gmc_v8_0_suspend, 1594 .resume = gmc_v8_0_resume, 1595 .is_idle = gmc_v8_0_is_idle, 1596 .wait_for_idle = gmc_v8_0_wait_for_idle, 1597 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1598 .set_powergating_state = gmc_v8_0_set_powergating_state, 1599 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1600 }; 1601 1602 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1603 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1604 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid, 1605 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1606 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1607 .set_prt = gmc_v8_0_set_prt, 1608 .get_vm_pde = gmc_v8_0_get_vm_pde, 1609 .get_vm_pte = gmc_v8_0_get_vm_pte, 1610 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size, 1611 }; 1612 1613 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1614 .set = gmc_v8_0_vm_fault_interrupt_state, 1615 .process = gmc_v8_0_process_interrupt, 1616 }; 1617 1618 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1619 { 1620 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1621 } 1622 1623 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1624 { 1625 adev->gmc.vm_fault.num_types = 1; 1626 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1627 } 1628 1629 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = { 1630 .type = AMD_IP_BLOCK_TYPE_GMC, 1631 .major = 8, 1632 .minor = 0, 1633 .rev = 0, 1634 .funcs = &gmc_v8_0_ip_funcs, 1635 }; 1636 1637 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = { 1638 .type = AMD_IP_BLOCK_TYPE_GMC, 1639 .major = 8, 1640 .minor = 1, 1641 .rev = 0, 1642 .funcs = &gmc_v8_0_ip_funcs, 1643 }; 1644 1645 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = { 1646 .type = AMD_IP_BLOCK_TYPE_GMC, 1647 .major = 8, 1648 .minor = 5, 1649 .rev = 0, 1650 .funcs = &gmc_v8_0_ip_funcs, 1651 }; 1652