1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "gmc_v8_0.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_amdkfd.h" 33 #include "amdgpu_gem.h" 34 35 #include "gmc/gmc_8_1_d.h" 36 #include "gmc/gmc_8_1_sh_mask.h" 37 38 #include "bif/bif_5_0_d.h" 39 #include "bif/bif_5_0_sh_mask.h" 40 41 #include "oss/oss_3_0_d.h" 42 #include "oss/oss_3_0_sh_mask.h" 43 44 #include "dce/dce_10_0_d.h" 45 #include "dce/dce_10_0_sh_mask.h" 46 47 #include "vid.h" 48 #include "vi.h" 49 50 #include "amdgpu_atombios.h" 51 52 #include "ivsrcid/ivsrcid_vislands30.h" 53 54 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); 55 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 56 static int gmc_v8_0_wait_for_idle(void *handle); 57 58 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 60 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 61 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin"); 62 MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin"); 63 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin"); 64 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin"); 65 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin"); 66 67 static const u32 golden_settings_tonga_a11[] = 68 { 69 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 70 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 71 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 72 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 73 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 74 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 75 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 76 }; 77 78 static const u32 tonga_mgcg_cgcg_init[] = 79 { 80 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 81 }; 82 83 static const u32 golden_settings_fiji_a10[] = 84 { 85 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 86 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 87 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 88 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 89 }; 90 91 static const u32 fiji_mgcg_cgcg_init[] = 92 { 93 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 94 }; 95 96 static const u32 golden_settings_polaris11_a11[] = 97 { 98 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 99 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 100 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 101 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 102 }; 103 104 static const u32 golden_settings_polaris10_a11[] = 105 { 106 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 107 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 108 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 109 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 110 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 111 }; 112 113 static const u32 cz_mgcg_cgcg_init[] = 114 { 115 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 116 }; 117 118 static const u32 stoney_mgcg_cgcg_init[] = 119 { 120 mmATC_MISC_CG, 0xffffffff, 0x000c0200, 121 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 122 }; 123 124 static const u32 golden_settings_stoney_common[] = 125 { 126 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004, 127 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000 128 }; 129 130 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 131 { 132 switch (adev->asic_type) { 133 case CHIP_FIJI: 134 amdgpu_device_program_register_sequence(adev, 135 fiji_mgcg_cgcg_init, 136 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 137 amdgpu_device_program_register_sequence(adev, 138 golden_settings_fiji_a10, 139 ARRAY_SIZE(golden_settings_fiji_a10)); 140 break; 141 case CHIP_TONGA: 142 amdgpu_device_program_register_sequence(adev, 143 tonga_mgcg_cgcg_init, 144 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 145 amdgpu_device_program_register_sequence(adev, 146 golden_settings_tonga_a11, 147 ARRAY_SIZE(golden_settings_tonga_a11)); 148 break; 149 case CHIP_POLARIS11: 150 case CHIP_POLARIS12: 151 case CHIP_VEGAM: 152 amdgpu_device_program_register_sequence(adev, 153 golden_settings_polaris11_a11, 154 ARRAY_SIZE(golden_settings_polaris11_a11)); 155 break; 156 case CHIP_POLARIS10: 157 amdgpu_device_program_register_sequence(adev, 158 golden_settings_polaris10_a11, 159 ARRAY_SIZE(golden_settings_polaris10_a11)); 160 break; 161 case CHIP_CARRIZO: 162 amdgpu_device_program_register_sequence(adev, 163 cz_mgcg_cgcg_init, 164 ARRAY_SIZE(cz_mgcg_cgcg_init)); 165 break; 166 case CHIP_STONEY: 167 amdgpu_device_program_register_sequence(adev, 168 stoney_mgcg_cgcg_init, 169 ARRAY_SIZE(stoney_mgcg_cgcg_init)); 170 amdgpu_device_program_register_sequence(adev, 171 golden_settings_stoney_common, 172 ARRAY_SIZE(golden_settings_stoney_common)); 173 break; 174 default: 175 break; 176 } 177 } 178 179 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) 180 { 181 u32 blackout; 182 183 gmc_v8_0_wait_for_idle(adev); 184 185 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 186 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 187 /* Block CPU access */ 188 WREG32(mmBIF_FB_EN, 0); 189 /* blackout the MC */ 190 blackout = REG_SET_FIELD(blackout, 191 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 192 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 193 } 194 /* wait for the MC to settle */ 195 udelay(100); 196 } 197 198 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev) 199 { 200 u32 tmp; 201 202 /* unblackout the MC */ 203 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 204 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 205 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 206 /* allow CPU access */ 207 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 208 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 209 WREG32(mmBIF_FB_EN, tmp); 210 } 211 212 /** 213 * gmc_v8_0_init_microcode - load ucode images from disk 214 * 215 * @adev: amdgpu_device pointer 216 * 217 * Use the firmware interface to load the ucode images into 218 * the driver (not loaded into hw). 219 * Returns 0 on success, error on failure. 220 */ 221 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 222 { 223 const char *chip_name; 224 char fw_name[30]; 225 int err; 226 227 DRM_DEBUG("\n"); 228 229 switch (adev->asic_type) { 230 case CHIP_TONGA: 231 chip_name = "tonga"; 232 break; 233 case CHIP_POLARIS11: 234 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) || 235 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)) 236 chip_name = "polaris11_k"; 237 else 238 chip_name = "polaris11"; 239 break; 240 case CHIP_POLARIS10: 241 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision)) 242 chip_name = "polaris10_k"; 243 else 244 chip_name = "polaris10"; 245 break; 246 case CHIP_POLARIS12: 247 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) { 248 chip_name = "polaris12_k"; 249 } else { 250 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159); 251 /* Polaris12 32bit ASIC needs a special MC firmware */ 252 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40) 253 chip_name = "polaris12_32"; 254 else 255 chip_name = "polaris12"; 256 } 257 break; 258 case CHIP_FIJI: 259 case CHIP_CARRIZO: 260 case CHIP_STONEY: 261 case CHIP_VEGAM: 262 return 0; 263 default: BUG(); 264 } 265 266 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 267 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 268 if (err) 269 goto out; 270 err = amdgpu_ucode_validate(adev->gmc.fw); 271 272 out: 273 if (err) { 274 pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); 275 release_firmware(adev->gmc.fw); 276 adev->gmc.fw = NULL; 277 } 278 return err; 279 } 280 281 /** 282 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw 283 * 284 * @adev: amdgpu_device pointer 285 * 286 * Load the GDDR MC ucode into the hw (VI). 287 * Returns 0 on success, error on failure. 288 */ 289 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) 290 { 291 const struct mc_firmware_header_v1_0 *hdr; 292 const __le32 *fw_data = NULL; 293 const __le32 *io_mc_regs = NULL; 294 u32 running; 295 int i, ucode_size, regs_size; 296 297 /* Skip MC ucode loading on SR-IOV capable boards. 298 * vbios does this for us in asic_init in that case. 299 * Skip MC ucode loading on VF, because hypervisor will do that 300 * for this adaptor. 301 */ 302 if (amdgpu_sriov_bios(adev)) 303 return 0; 304 305 if (!adev->gmc.fw) 306 return -EINVAL; 307 308 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 309 amdgpu_ucode_print_mc_hdr(&hdr->header); 310 311 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 312 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 313 io_mc_regs = (const __le32 *) 314 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 315 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 316 fw_data = (const __le32 *) 317 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 318 319 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 320 321 if (running == 0) { 322 /* reset the engine and set to writable */ 323 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 324 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 325 326 /* load mc io regs */ 327 for (i = 0; i < regs_size; i++) { 328 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 329 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 330 } 331 /* load the MC ucode */ 332 for (i = 0; i < ucode_size; i++) 333 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 334 335 /* put the engine back into the active state */ 336 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 337 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 338 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 339 340 /* wait for training to complete */ 341 for (i = 0; i < adev->usec_timeout; i++) { 342 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 343 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 344 break; 345 udelay(1); 346 } 347 for (i = 0; i < adev->usec_timeout; i++) { 348 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 349 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 350 break; 351 udelay(1); 352 } 353 } 354 355 return 0; 356 } 357 358 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) 359 { 360 const struct mc_firmware_header_v1_0 *hdr; 361 const __le32 *fw_data = NULL; 362 const __le32 *io_mc_regs = NULL; 363 u32 data; 364 int i, ucode_size, regs_size; 365 366 /* Skip MC ucode loading on SR-IOV capable boards. 367 * vbios does this for us in asic_init in that case. 368 * Skip MC ucode loading on VF, because hypervisor will do that 369 * for this adaptor. 370 */ 371 if (amdgpu_sriov_bios(adev)) 372 return 0; 373 374 if (!adev->gmc.fw) 375 return -EINVAL; 376 377 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 378 amdgpu_ucode_print_mc_hdr(&hdr->header); 379 380 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 381 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 382 io_mc_regs = (const __le32 *) 383 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 384 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 385 fw_data = (const __le32 *) 386 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 387 388 data = RREG32(mmMC_SEQ_MISC0); 389 data &= ~(0x40); 390 WREG32(mmMC_SEQ_MISC0, data); 391 392 /* load mc io regs */ 393 for (i = 0; i < regs_size; i++) { 394 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 395 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 396 } 397 398 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 399 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 400 401 /* load the MC ucode */ 402 for (i = 0; i < ucode_size; i++) 403 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 404 405 /* put the engine back into the active state */ 406 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 407 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 408 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 409 410 /* wait for training to complete */ 411 for (i = 0; i < adev->usec_timeout; i++) { 412 data = RREG32(mmMC_SEQ_MISC0); 413 if (data & 0x80) 414 break; 415 udelay(1); 416 } 417 418 return 0; 419 } 420 421 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 422 struct amdgpu_gmc *mc) 423 { 424 u64 base = 0; 425 426 if (!amdgpu_sriov_vf(adev)) 427 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 428 base <<= 24; 429 430 amdgpu_gmc_vram_location(adev, mc, base); 431 amdgpu_gmc_gart_location(adev, mc); 432 } 433 434 /** 435 * gmc_v8_0_mc_program - program the GPU memory controller 436 * 437 * @adev: amdgpu_device pointer 438 * 439 * Set the location of vram, gart, and AGP in the GPU's 440 * physical address space (VI). 441 */ 442 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 443 { 444 u32 tmp; 445 int i, j; 446 447 /* Initialize HDP */ 448 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 449 WREG32((0xb05 + j), 0x00000000); 450 WREG32((0xb06 + j), 0x00000000); 451 WREG32((0xb07 + j), 0x00000000); 452 WREG32((0xb08 + j), 0x00000000); 453 WREG32((0xb09 + j), 0x00000000); 454 } 455 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 456 457 if (gmc_v8_0_wait_for_idle((void *)adev)) { 458 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 459 } 460 if (adev->mode_info.num_crtc) { 461 /* Lockout access through VGA aperture*/ 462 tmp = RREG32(mmVGA_HDP_CONTROL); 463 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 464 WREG32(mmVGA_HDP_CONTROL, tmp); 465 466 /* disable VGA render */ 467 tmp = RREG32(mmVGA_RENDER_CONTROL); 468 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 469 WREG32(mmVGA_RENDER_CONTROL, tmp); 470 } 471 /* Update configuration */ 472 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 473 adev->gmc.vram_start >> 12); 474 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 475 adev->gmc.vram_end >> 12); 476 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 477 adev->mem_scratch.gpu_addr >> 12); 478 479 if (amdgpu_sriov_vf(adev)) { 480 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; 481 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); 482 WREG32(mmMC_VM_FB_LOCATION, tmp); 483 /* XXX double check these! */ 484 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); 485 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 486 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 487 } 488 489 WREG32(mmMC_VM_AGP_BASE, 0); 490 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 491 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 492 if (gmc_v8_0_wait_for_idle((void *)adev)) { 493 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 494 } 495 496 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 497 498 tmp = RREG32(mmHDP_MISC_CNTL); 499 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 500 WREG32(mmHDP_MISC_CNTL, tmp); 501 502 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 503 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 504 } 505 506 /** 507 * gmc_v8_0_mc_init - initialize the memory controller driver params 508 * 509 * @adev: amdgpu_device pointer 510 * 511 * Look up the amount of vram, vram width, and decide how to place 512 * vram and gart within the GPU's physical address space (VI). 513 * Returns 0 for success. 514 */ 515 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 516 { 517 int r; 518 u32 tmp; 519 520 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 521 if (!adev->gmc.vram_width) { 522 int chansize, numchan; 523 524 /* Get VRAM informations */ 525 tmp = RREG32(mmMC_ARB_RAMCFG); 526 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 527 chansize = 64; 528 } else { 529 chansize = 32; 530 } 531 tmp = RREG32(mmMC_SHARED_CHMAP); 532 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 533 case 0: 534 default: 535 numchan = 1; 536 break; 537 case 1: 538 numchan = 2; 539 break; 540 case 2: 541 numchan = 4; 542 break; 543 case 3: 544 numchan = 8; 545 break; 546 case 4: 547 numchan = 3; 548 break; 549 case 5: 550 numchan = 6; 551 break; 552 case 6: 553 numchan = 10; 554 break; 555 case 7: 556 numchan = 12; 557 break; 558 case 8: 559 numchan = 16; 560 break; 561 } 562 adev->gmc.vram_width = numchan * chansize; 563 } 564 /* size in MB on si */ 565 tmp = RREG32(mmCONFIG_MEMSIZE); 566 /* some boards may have garbage in the upper 16 bits */ 567 if (tmp & 0xffff0000) { 568 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); 569 if (tmp & 0xffff) 570 tmp &= 0xffff; 571 } 572 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL; 573 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 574 575 if (!(adev->flags & AMD_IS_APU)) { 576 r = amdgpu_device_resize_fb_bar(adev); 577 if (r) 578 return r; 579 } 580 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 581 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 582 583 #ifdef CONFIG_X86_64 584 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 585 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 586 adev->gmc.aper_size = adev->gmc.real_vram_size; 587 } 588 #endif 589 590 adev->gmc.visible_vram_size = adev->gmc.aper_size; 591 592 /* set the gart size */ 593 if (amdgpu_gart_size == -1) { 594 switch (adev->asic_type) { 595 case CHIP_POLARIS10: /* all engines support GPUVM */ 596 case CHIP_POLARIS11: /* all engines support GPUVM */ 597 case CHIP_POLARIS12: /* all engines support GPUVM */ 598 case CHIP_VEGAM: /* all engines support GPUVM */ 599 default: 600 adev->gmc.gart_size = 256ULL << 20; 601 break; 602 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ 603 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ 604 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ 605 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ 606 adev->gmc.gart_size = 1024ULL << 20; 607 break; 608 } 609 } else { 610 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 611 } 612 613 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 614 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); 615 616 return 0; 617 } 618 619 /** 620 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid 621 * 622 * @adev: amdgpu_device pointer 623 * @pasid: pasid to be flush 624 * @flush_type: type of flush 625 * @all_hub: flush all hubs 626 * 627 * Flush the TLB for the requested pasid. 628 */ 629 static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 630 uint16_t pasid, uint32_t flush_type, 631 bool all_hub) 632 { 633 int vmid; 634 unsigned int tmp; 635 636 if (amdgpu_in_reset(adev)) 637 return -EIO; 638 639 for (vmid = 1; vmid < 16; vmid++) { 640 641 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 642 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 643 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 644 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 645 RREG32(mmVM_INVALIDATE_RESPONSE); 646 break; 647 } 648 } 649 650 return 0; 651 652 } 653 654 /* 655 * GART 656 * VMID 0 is the physical GPU addresses as used by the kernel. 657 * VMIDs 1-15 are used for userspace clients and are handled 658 * by the amdgpu vm/hsa code. 659 */ 660 661 /** 662 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback 663 * 664 * @adev: amdgpu_device pointer 665 * @vmid: vm instance to flush 666 * @vmhub: which hub to flush 667 * @flush_type: type of flush 668 * 669 * Flush the TLB for the requested page table (VI). 670 */ 671 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 672 uint32_t vmhub, uint32_t flush_type) 673 { 674 /* bits 0-15 are the VM contexts0-15 */ 675 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 676 } 677 678 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 679 unsigned vmid, uint64_t pd_addr) 680 { 681 uint32_t reg; 682 683 if (vmid < 8) 684 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 685 else 686 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 687 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 688 689 /* bits 0-15 are the VM contexts0-15 */ 690 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 691 692 return pd_addr; 693 } 694 695 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 696 unsigned pasid) 697 { 698 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 699 } 700 701 /* 702 * PTE format on VI: 703 * 63:40 reserved 704 * 39:12 4k physical page base address 705 * 11:7 fragment 706 * 6 write 707 * 5 read 708 * 4 exe 709 * 3 reserved 710 * 2 snooped 711 * 1 system 712 * 0 valid 713 * 714 * PDE format on VI: 715 * 63:59 block fragment size 716 * 58:40 reserved 717 * 39:1 physical base address of PTE 718 * bits 5:1 must be 0. 719 * 0 valid 720 */ 721 722 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level, 723 uint64_t *addr, uint64_t *flags) 724 { 725 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 726 } 727 728 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev, 729 struct amdgpu_bo_va_mapping *mapping, 730 uint64_t *flags) 731 { 732 *flags &= ~AMDGPU_PTE_EXECUTABLE; 733 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 734 *flags &= ~AMDGPU_PTE_PRT; 735 } 736 737 /** 738 * gmc_v8_0_set_fault_enable_default - update VM fault handling 739 * 740 * @adev: amdgpu_device pointer 741 * @value: true redirects VM faults to the default page 742 */ 743 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 744 bool value) 745 { 746 u32 tmp; 747 748 tmp = RREG32(mmVM_CONTEXT1_CNTL); 749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 750 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 751 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 752 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 753 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 754 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 755 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 756 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 757 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 758 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 759 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 760 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 761 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 762 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 763 WREG32(mmVM_CONTEXT1_CNTL, tmp); 764 } 765 766 /** 767 * gmc_v8_0_set_prt - set PRT VM fault 768 * 769 * @adev: amdgpu_device pointer 770 * @enable: enable/disable VM fault handling for PRT 771 */ 772 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) 773 { 774 u32 tmp; 775 776 if (enable && !adev->gmc.prt_warning) { 777 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 778 adev->gmc.prt_warning = true; 779 } 780 781 tmp = RREG32(mmVM_PRT_CNTL); 782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 783 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 784 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 785 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 786 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 787 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 788 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 789 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 790 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 791 L2_CACHE_STORE_INVALID_ENTRIES, enable); 792 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 793 L1_TLB_STORE_INVALID_ENTRIES, enable); 794 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 795 MASK_PDE0_FAULT, enable); 796 WREG32(mmVM_PRT_CNTL, tmp); 797 798 if (enable) { 799 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 800 uint32_t high = adev->vm_manager.max_pfn - 801 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 802 803 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 804 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 805 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 806 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 807 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 808 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 809 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 810 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 811 } else { 812 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 813 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 814 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 815 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 816 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 817 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 818 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 819 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 820 } 821 } 822 823 /** 824 * gmc_v8_0_gart_enable - gart enable 825 * 826 * @adev: amdgpu_device pointer 827 * 828 * This sets up the TLBs, programs the page tables for VMID0, 829 * sets up the hw for VMIDs 1-15 which are allocated on 830 * demand, and sets up the global locations for the LDS, GDS, 831 * and GPUVM for FSA64 clients (VI). 832 * Returns 0 for success, errors for failure. 833 */ 834 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 835 { 836 uint64_t table_addr; 837 u32 tmp, field; 838 int i; 839 840 if (adev->gart.bo == NULL) { 841 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 842 return -EINVAL; 843 } 844 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 845 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 846 847 /* Setup TLB control */ 848 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 849 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 850 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 851 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 852 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 853 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 854 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 855 /* Setup L2 cache */ 856 tmp = RREG32(mmVM_L2_CNTL); 857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 859 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 863 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 864 WREG32(mmVM_L2_CNTL, tmp); 865 tmp = RREG32(mmVM_L2_CNTL2); 866 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 868 WREG32(mmVM_L2_CNTL2, tmp); 869 870 field = adev->vm_manager.fragment_size; 871 tmp = RREG32(mmVM_L2_CNTL3); 872 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 875 WREG32(mmVM_L2_CNTL3, tmp); 876 /* XXX: set to enable PTE/PDE in system memory */ 877 tmp = RREG32(mmVM_L2_CNTL4); 878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 880 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 881 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 884 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 885 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 886 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 887 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 888 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 889 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 890 WREG32(mmVM_L2_CNTL4, tmp); 891 /* setup context0 */ 892 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 893 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 894 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 895 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 896 (u32)(adev->dummy_page_addr >> 12)); 897 WREG32(mmVM_CONTEXT0_CNTL2, 0); 898 tmp = RREG32(mmVM_CONTEXT0_CNTL); 899 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 900 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 901 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 902 WREG32(mmVM_CONTEXT0_CNTL, tmp); 903 904 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 905 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 906 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 907 908 /* empty context1-15 */ 909 /* FIXME start with 4G, once using 2 level pt switch to full 910 * vm size space 911 */ 912 /* set vm size, must be a multiple of 4 */ 913 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 914 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 915 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 916 if (i < 8) 917 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 918 table_addr >> 12); 919 else 920 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 921 table_addr >> 12); 922 } 923 924 /* enable context1-15 */ 925 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 926 (u32)(adev->dummy_page_addr >> 12)); 927 WREG32(mmVM_CONTEXT1_CNTL2, 4); 928 tmp = RREG32(mmVM_CONTEXT1_CNTL); 929 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 930 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 931 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 933 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 934 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 935 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 936 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 937 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 938 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 939 adev->vm_manager.block_size - 9); 940 WREG32(mmVM_CONTEXT1_CNTL, tmp); 941 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 942 gmc_v8_0_set_fault_enable_default(adev, false); 943 else 944 gmc_v8_0_set_fault_enable_default(adev, true); 945 946 gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0); 947 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 948 (unsigned)(adev->gmc.gart_size >> 20), 949 (unsigned long long)table_addr); 950 return 0; 951 } 952 953 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 954 { 955 int r; 956 957 if (adev->gart.bo) { 958 WARN(1, "R600 PCIE GART already initialized\n"); 959 return 0; 960 } 961 /* Initialize common gart structure */ 962 r = amdgpu_gart_init(adev); 963 if (r) 964 return r; 965 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 966 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; 967 return amdgpu_gart_table_vram_alloc(adev); 968 } 969 970 /** 971 * gmc_v8_0_gart_disable - gart disable 972 * 973 * @adev: amdgpu_device pointer 974 * 975 * This disables all VM page table (VI). 976 */ 977 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 978 { 979 u32 tmp; 980 981 /* Disable all tables */ 982 WREG32(mmVM_CONTEXT0_CNTL, 0); 983 WREG32(mmVM_CONTEXT1_CNTL, 0); 984 /* Setup TLB control */ 985 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 986 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 987 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 988 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 989 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 990 /* Setup L2 cache */ 991 tmp = RREG32(mmVM_L2_CNTL); 992 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 993 WREG32(mmVM_L2_CNTL, tmp); 994 WREG32(mmVM_L2_CNTL2, 0); 995 } 996 997 /** 998 * gmc_v8_0_vm_decode_fault - print human readable fault info 999 * 1000 * @adev: amdgpu_device pointer 1001 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 1002 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 1003 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 1004 * @pasid: debug logging only - no functional use 1005 * 1006 * Print human readable fault information (VI). 1007 */ 1008 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 1009 u32 addr, u32 mc_client, unsigned pasid) 1010 { 1011 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 1012 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1013 PROTECTIONS); 1014 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 1015 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 1016 u32 mc_id; 1017 1018 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1019 MEMORY_CLIENT_ID); 1020 1021 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 1022 protections, vmid, pasid, addr, 1023 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1024 MEMORY_CLIENT_RW) ? 1025 "write" : "read", block, mc_client, mc_id); 1026 } 1027 1028 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 1029 { 1030 switch (mc_seq_vram_type) { 1031 case MC_SEQ_MISC0__MT__GDDR1: 1032 return AMDGPU_VRAM_TYPE_GDDR1; 1033 case MC_SEQ_MISC0__MT__DDR2: 1034 return AMDGPU_VRAM_TYPE_DDR2; 1035 case MC_SEQ_MISC0__MT__GDDR3: 1036 return AMDGPU_VRAM_TYPE_GDDR3; 1037 case MC_SEQ_MISC0__MT__GDDR4: 1038 return AMDGPU_VRAM_TYPE_GDDR4; 1039 case MC_SEQ_MISC0__MT__GDDR5: 1040 return AMDGPU_VRAM_TYPE_GDDR5; 1041 case MC_SEQ_MISC0__MT__HBM: 1042 return AMDGPU_VRAM_TYPE_HBM; 1043 case MC_SEQ_MISC0__MT__DDR3: 1044 return AMDGPU_VRAM_TYPE_DDR3; 1045 default: 1046 return AMDGPU_VRAM_TYPE_UNKNOWN; 1047 } 1048 } 1049 1050 static int gmc_v8_0_early_init(void *handle) 1051 { 1052 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1053 1054 gmc_v8_0_set_gmc_funcs(adev); 1055 gmc_v8_0_set_irq_funcs(adev); 1056 1057 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 1058 adev->gmc.shared_aperture_end = 1059 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 1060 adev->gmc.private_aperture_start = 1061 adev->gmc.shared_aperture_end + 1; 1062 adev->gmc.private_aperture_end = 1063 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 1064 1065 return 0; 1066 } 1067 1068 static int gmc_v8_0_late_init(void *handle) 1069 { 1070 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1071 1072 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 1073 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 1074 else 1075 return 0; 1076 } 1077 1078 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) 1079 { 1080 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 1081 unsigned size; 1082 1083 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 1084 size = AMDGPU_VBIOS_VGA_ALLOCATION; 1085 } else { 1086 u32 viewport = RREG32(mmVIEWPORT_SIZE); 1087 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 1088 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 1089 4); 1090 } 1091 1092 return size; 1093 } 1094 1095 #define mmMC_SEQ_MISC0_FIJI 0xA71 1096 1097 static int gmc_v8_0_sw_init(void *handle) 1098 { 1099 int r; 1100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1101 1102 adev->num_vmhubs = 1; 1103 1104 if (adev->flags & AMD_IS_APU) { 1105 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 1106 } else { 1107 u32 tmp; 1108 1109 if ((adev->asic_type == CHIP_FIJI) || 1110 (adev->asic_type == CHIP_VEGAM)) 1111 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 1112 else 1113 tmp = RREG32(mmMC_SEQ_MISC0); 1114 tmp &= MC_SEQ_MISC0__MT__MASK; 1115 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); 1116 } 1117 1118 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 1119 if (r) 1120 return r; 1121 1122 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1123 if (r) 1124 return r; 1125 1126 /* Adjust VM size here. 1127 * Currently set to 4GB ((1 << 20) 4k pages). 1128 * Max GPUVM size for cayman and SI is 40 bits. 1129 */ 1130 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1131 1132 /* Set the internal MC address mask 1133 * This is the max address of the GPU's 1134 * internal address space. 1135 */ 1136 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1137 1138 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1139 if (r) { 1140 pr_warn("No suitable DMA available\n"); 1141 return r; 1142 } 1143 adev->need_swiotlb = drm_need_swiotlb(40); 1144 1145 r = gmc_v8_0_init_microcode(adev); 1146 if (r) { 1147 DRM_ERROR("Failed to load mc firmware!\n"); 1148 return r; 1149 } 1150 1151 r = gmc_v8_0_mc_init(adev); 1152 if (r) 1153 return r; 1154 1155 amdgpu_gmc_get_vbios_allocations(adev); 1156 1157 /* Memory manager */ 1158 r = amdgpu_bo_init(adev); 1159 if (r) 1160 return r; 1161 1162 r = gmc_v8_0_gart_init(adev); 1163 if (r) 1164 return r; 1165 1166 /* 1167 * number of VMs 1168 * VMID 0 is reserved for System 1169 * amdgpu graphics/compute will use VMIDs 1-7 1170 * amdkfd will use VMIDs 8-15 1171 */ 1172 adev->vm_manager.first_kfd_vmid = 8; 1173 amdgpu_vm_manager_init(adev); 1174 1175 /* base offset of vram pages */ 1176 if (adev->flags & AMD_IS_APU) { 1177 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1178 1179 tmp <<= 22; 1180 adev->vm_manager.vram_base_offset = tmp; 1181 } else { 1182 adev->vm_manager.vram_base_offset = 0; 1183 } 1184 1185 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1186 GFP_KERNEL); 1187 if (!adev->gmc.vm_fault_info) 1188 return -ENOMEM; 1189 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1190 1191 return 0; 1192 } 1193 1194 static int gmc_v8_0_sw_fini(void *handle) 1195 { 1196 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1197 1198 amdgpu_gem_force_release(adev); 1199 amdgpu_vm_manager_fini(adev); 1200 kfree(adev->gmc.vm_fault_info); 1201 amdgpu_gart_table_vram_free(adev); 1202 amdgpu_bo_fini(adev); 1203 release_firmware(adev->gmc.fw); 1204 adev->gmc.fw = NULL; 1205 1206 return 0; 1207 } 1208 1209 static int gmc_v8_0_hw_init(void *handle) 1210 { 1211 int r; 1212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1213 1214 gmc_v8_0_init_golden_registers(adev); 1215 1216 gmc_v8_0_mc_program(adev); 1217 1218 if (adev->asic_type == CHIP_TONGA) { 1219 r = gmc_v8_0_tonga_mc_load_microcode(adev); 1220 if (r) { 1221 DRM_ERROR("Failed to load MC firmware!\n"); 1222 return r; 1223 } 1224 } else if (adev->asic_type == CHIP_POLARIS11 || 1225 adev->asic_type == CHIP_POLARIS10 || 1226 adev->asic_type == CHIP_POLARIS12) { 1227 r = gmc_v8_0_polaris_mc_load_microcode(adev); 1228 if (r) { 1229 DRM_ERROR("Failed to load MC firmware!\n"); 1230 return r; 1231 } 1232 } 1233 1234 r = gmc_v8_0_gart_enable(adev); 1235 if (r) 1236 return r; 1237 1238 if (amdgpu_emu_mode == 1) 1239 return amdgpu_gmc_vram_checking(adev); 1240 else 1241 return r; 1242 } 1243 1244 static int gmc_v8_0_hw_fini(void *handle) 1245 { 1246 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1247 1248 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1249 gmc_v8_0_gart_disable(adev); 1250 1251 return 0; 1252 } 1253 1254 static int gmc_v8_0_suspend(void *handle) 1255 { 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1257 1258 gmc_v8_0_hw_fini(adev); 1259 1260 return 0; 1261 } 1262 1263 static int gmc_v8_0_resume(void *handle) 1264 { 1265 int r; 1266 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1267 1268 r = gmc_v8_0_hw_init(adev); 1269 if (r) 1270 return r; 1271 1272 amdgpu_vmid_reset_all(adev); 1273 1274 return 0; 1275 } 1276 1277 static bool gmc_v8_0_is_idle(void *handle) 1278 { 1279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1280 u32 tmp = RREG32(mmSRBM_STATUS); 1281 1282 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1283 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1284 return false; 1285 1286 return true; 1287 } 1288 1289 static int gmc_v8_0_wait_for_idle(void *handle) 1290 { 1291 unsigned i; 1292 u32 tmp; 1293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1294 1295 for (i = 0; i < adev->usec_timeout; i++) { 1296 /* read MC_STATUS */ 1297 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1298 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1299 SRBM_STATUS__MCC_BUSY_MASK | 1300 SRBM_STATUS__MCD_BUSY_MASK | 1301 SRBM_STATUS__VMC_BUSY_MASK | 1302 SRBM_STATUS__VMC1_BUSY_MASK); 1303 if (!tmp) 1304 return 0; 1305 udelay(1); 1306 } 1307 return -ETIMEDOUT; 1308 1309 } 1310 1311 static bool gmc_v8_0_check_soft_reset(void *handle) 1312 { 1313 u32 srbm_soft_reset = 0; 1314 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1315 u32 tmp = RREG32(mmSRBM_STATUS); 1316 1317 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1318 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1319 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1320 1321 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1322 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1323 if (!(adev->flags & AMD_IS_APU)) 1324 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1325 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1326 } 1327 if (srbm_soft_reset) { 1328 adev->gmc.srbm_soft_reset = srbm_soft_reset; 1329 return true; 1330 } else { 1331 adev->gmc.srbm_soft_reset = 0; 1332 return false; 1333 } 1334 } 1335 1336 static int gmc_v8_0_pre_soft_reset(void *handle) 1337 { 1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1339 1340 if (!adev->gmc.srbm_soft_reset) 1341 return 0; 1342 1343 gmc_v8_0_mc_stop(adev); 1344 if (gmc_v8_0_wait_for_idle(adev)) { 1345 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1346 } 1347 1348 return 0; 1349 } 1350 1351 static int gmc_v8_0_soft_reset(void *handle) 1352 { 1353 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1354 u32 srbm_soft_reset; 1355 1356 if (!adev->gmc.srbm_soft_reset) 1357 return 0; 1358 srbm_soft_reset = adev->gmc.srbm_soft_reset; 1359 1360 if (srbm_soft_reset) { 1361 u32 tmp; 1362 1363 tmp = RREG32(mmSRBM_SOFT_RESET); 1364 tmp |= srbm_soft_reset; 1365 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1366 WREG32(mmSRBM_SOFT_RESET, tmp); 1367 tmp = RREG32(mmSRBM_SOFT_RESET); 1368 1369 udelay(50); 1370 1371 tmp &= ~srbm_soft_reset; 1372 WREG32(mmSRBM_SOFT_RESET, tmp); 1373 tmp = RREG32(mmSRBM_SOFT_RESET); 1374 1375 /* Wait a little for things to settle down */ 1376 udelay(50); 1377 } 1378 1379 return 0; 1380 } 1381 1382 static int gmc_v8_0_post_soft_reset(void *handle) 1383 { 1384 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1385 1386 if (!adev->gmc.srbm_soft_reset) 1387 return 0; 1388 1389 gmc_v8_0_mc_resume(adev); 1390 return 0; 1391 } 1392 1393 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1394 struct amdgpu_irq_src *src, 1395 unsigned type, 1396 enum amdgpu_interrupt_state state) 1397 { 1398 u32 tmp; 1399 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1400 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1401 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1402 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1403 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1404 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1405 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1406 1407 switch (state) { 1408 case AMDGPU_IRQ_STATE_DISABLE: 1409 /* system context */ 1410 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1411 tmp &= ~bits; 1412 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1413 /* VMs */ 1414 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1415 tmp &= ~bits; 1416 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1417 break; 1418 case AMDGPU_IRQ_STATE_ENABLE: 1419 /* system context */ 1420 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1421 tmp |= bits; 1422 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1423 /* VMs */ 1424 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1425 tmp |= bits; 1426 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1427 break; 1428 default: 1429 break; 1430 } 1431 1432 return 0; 1433 } 1434 1435 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1436 struct amdgpu_irq_src *source, 1437 struct amdgpu_iv_entry *entry) 1438 { 1439 u32 addr, status, mc_client, vmid; 1440 1441 if (amdgpu_sriov_vf(adev)) { 1442 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1443 entry->src_id, entry->src_data[0]); 1444 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n"); 1445 return 0; 1446 } 1447 1448 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1449 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1450 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1451 /* reset addr and status */ 1452 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1453 1454 if (!addr && !status) 1455 return 0; 1456 1457 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1458 gmc_v8_0_set_fault_enable_default(adev, false); 1459 1460 if (printk_ratelimit()) { 1461 struct amdgpu_task_info task_info; 1462 1463 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 1464 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 1465 1466 dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n", 1467 entry->src_id, entry->src_data[0], task_info.process_name, 1468 task_info.tgid, task_info.task_name, task_info.pid); 1469 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1470 addr); 1471 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1472 status); 1473 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client, 1474 entry->pasid); 1475 } 1476 1477 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1478 VMID); 1479 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1480 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1481 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1482 u32 protections = REG_GET_FIELD(status, 1483 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1484 PROTECTIONS); 1485 1486 info->vmid = vmid; 1487 info->mc_id = REG_GET_FIELD(status, 1488 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1489 MEMORY_CLIENT_ID); 1490 info->status = status; 1491 info->page_addr = addr; 1492 info->prot_valid = protections & 0x7 ? true : false; 1493 info->prot_read = protections & 0x8 ? true : false; 1494 info->prot_write = protections & 0x10 ? true : false; 1495 info->prot_exec = protections & 0x20 ? true : false; 1496 mb(); 1497 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1498 } 1499 1500 return 0; 1501 } 1502 1503 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1504 bool enable) 1505 { 1506 uint32_t data; 1507 1508 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1509 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1510 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1511 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1512 1513 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1514 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1515 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1516 1517 data = RREG32(mmMC_HUB_MISC_VM_CG); 1518 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1519 WREG32(mmMC_HUB_MISC_VM_CG, data); 1520 1521 data = RREG32(mmMC_XPB_CLK_GAT); 1522 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1523 WREG32(mmMC_XPB_CLK_GAT, data); 1524 1525 data = RREG32(mmATC_MISC_CG); 1526 data |= ATC_MISC_CG__ENABLE_MASK; 1527 WREG32(mmATC_MISC_CG, data); 1528 1529 data = RREG32(mmMC_CITF_MISC_WR_CG); 1530 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1531 WREG32(mmMC_CITF_MISC_WR_CG, data); 1532 1533 data = RREG32(mmMC_CITF_MISC_RD_CG); 1534 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1535 WREG32(mmMC_CITF_MISC_RD_CG, data); 1536 1537 data = RREG32(mmMC_CITF_MISC_VM_CG); 1538 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1539 WREG32(mmMC_CITF_MISC_VM_CG, data); 1540 1541 data = RREG32(mmVM_L2_CG); 1542 data |= VM_L2_CG__ENABLE_MASK; 1543 WREG32(mmVM_L2_CG, data); 1544 } else { 1545 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1546 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1547 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1548 1549 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1550 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1551 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1552 1553 data = RREG32(mmMC_HUB_MISC_VM_CG); 1554 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1555 WREG32(mmMC_HUB_MISC_VM_CG, data); 1556 1557 data = RREG32(mmMC_XPB_CLK_GAT); 1558 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1559 WREG32(mmMC_XPB_CLK_GAT, data); 1560 1561 data = RREG32(mmATC_MISC_CG); 1562 data &= ~ATC_MISC_CG__ENABLE_MASK; 1563 WREG32(mmATC_MISC_CG, data); 1564 1565 data = RREG32(mmMC_CITF_MISC_WR_CG); 1566 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1567 WREG32(mmMC_CITF_MISC_WR_CG, data); 1568 1569 data = RREG32(mmMC_CITF_MISC_RD_CG); 1570 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1571 WREG32(mmMC_CITF_MISC_RD_CG, data); 1572 1573 data = RREG32(mmMC_CITF_MISC_VM_CG); 1574 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1575 WREG32(mmMC_CITF_MISC_VM_CG, data); 1576 1577 data = RREG32(mmVM_L2_CG); 1578 data &= ~VM_L2_CG__ENABLE_MASK; 1579 WREG32(mmVM_L2_CG, data); 1580 } 1581 } 1582 1583 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1584 bool enable) 1585 { 1586 uint32_t data; 1587 1588 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1589 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1590 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1591 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1592 1593 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1594 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1595 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1596 1597 data = RREG32(mmMC_HUB_MISC_VM_CG); 1598 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1599 WREG32(mmMC_HUB_MISC_VM_CG, data); 1600 1601 data = RREG32(mmMC_XPB_CLK_GAT); 1602 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1603 WREG32(mmMC_XPB_CLK_GAT, data); 1604 1605 data = RREG32(mmATC_MISC_CG); 1606 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1607 WREG32(mmATC_MISC_CG, data); 1608 1609 data = RREG32(mmMC_CITF_MISC_WR_CG); 1610 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1611 WREG32(mmMC_CITF_MISC_WR_CG, data); 1612 1613 data = RREG32(mmMC_CITF_MISC_RD_CG); 1614 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1615 WREG32(mmMC_CITF_MISC_RD_CG, data); 1616 1617 data = RREG32(mmMC_CITF_MISC_VM_CG); 1618 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1619 WREG32(mmMC_CITF_MISC_VM_CG, data); 1620 1621 data = RREG32(mmVM_L2_CG); 1622 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1623 WREG32(mmVM_L2_CG, data); 1624 } else { 1625 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1626 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1627 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1628 1629 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1630 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1631 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1632 1633 data = RREG32(mmMC_HUB_MISC_VM_CG); 1634 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1635 WREG32(mmMC_HUB_MISC_VM_CG, data); 1636 1637 data = RREG32(mmMC_XPB_CLK_GAT); 1638 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1639 WREG32(mmMC_XPB_CLK_GAT, data); 1640 1641 data = RREG32(mmATC_MISC_CG); 1642 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1643 WREG32(mmATC_MISC_CG, data); 1644 1645 data = RREG32(mmMC_CITF_MISC_WR_CG); 1646 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1647 WREG32(mmMC_CITF_MISC_WR_CG, data); 1648 1649 data = RREG32(mmMC_CITF_MISC_RD_CG); 1650 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1651 WREG32(mmMC_CITF_MISC_RD_CG, data); 1652 1653 data = RREG32(mmMC_CITF_MISC_VM_CG); 1654 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1655 WREG32(mmMC_CITF_MISC_VM_CG, data); 1656 1657 data = RREG32(mmVM_L2_CG); 1658 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1659 WREG32(mmVM_L2_CG, data); 1660 } 1661 } 1662 1663 static int gmc_v8_0_set_clockgating_state(void *handle, 1664 enum amd_clockgating_state state) 1665 { 1666 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1667 1668 if (amdgpu_sriov_vf(adev)) 1669 return 0; 1670 1671 switch (adev->asic_type) { 1672 case CHIP_FIJI: 1673 fiji_update_mc_medium_grain_clock_gating(adev, 1674 state == AMD_CG_STATE_GATE); 1675 fiji_update_mc_light_sleep(adev, 1676 state == AMD_CG_STATE_GATE); 1677 break; 1678 default: 1679 break; 1680 } 1681 return 0; 1682 } 1683 1684 static int gmc_v8_0_set_powergating_state(void *handle, 1685 enum amd_powergating_state state) 1686 { 1687 return 0; 1688 } 1689 1690 static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags) 1691 { 1692 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1693 int data; 1694 1695 if (amdgpu_sriov_vf(adev)) 1696 *flags = 0; 1697 1698 /* AMD_CG_SUPPORT_MC_MGCG */ 1699 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1700 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK) 1701 *flags |= AMD_CG_SUPPORT_MC_MGCG; 1702 1703 /* AMD_CG_SUPPORT_MC_LS */ 1704 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK) 1705 *flags |= AMD_CG_SUPPORT_MC_LS; 1706 } 1707 1708 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1709 .name = "gmc_v8_0", 1710 .early_init = gmc_v8_0_early_init, 1711 .late_init = gmc_v8_0_late_init, 1712 .sw_init = gmc_v8_0_sw_init, 1713 .sw_fini = gmc_v8_0_sw_fini, 1714 .hw_init = gmc_v8_0_hw_init, 1715 .hw_fini = gmc_v8_0_hw_fini, 1716 .suspend = gmc_v8_0_suspend, 1717 .resume = gmc_v8_0_resume, 1718 .is_idle = gmc_v8_0_is_idle, 1719 .wait_for_idle = gmc_v8_0_wait_for_idle, 1720 .check_soft_reset = gmc_v8_0_check_soft_reset, 1721 .pre_soft_reset = gmc_v8_0_pre_soft_reset, 1722 .soft_reset = gmc_v8_0_soft_reset, 1723 .post_soft_reset = gmc_v8_0_post_soft_reset, 1724 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1725 .set_powergating_state = gmc_v8_0_set_powergating_state, 1726 .get_clockgating_state = gmc_v8_0_get_clockgating_state, 1727 }; 1728 1729 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { 1730 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, 1731 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid, 1732 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb, 1733 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping, 1734 .set_prt = gmc_v8_0_set_prt, 1735 .get_vm_pde = gmc_v8_0_get_vm_pde, 1736 .get_vm_pte = gmc_v8_0_get_vm_pte, 1737 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size, 1738 }; 1739 1740 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1741 .set = gmc_v8_0_vm_fault_interrupt_state, 1742 .process = gmc_v8_0_process_interrupt, 1743 }; 1744 1745 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) 1746 { 1747 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; 1748 } 1749 1750 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1751 { 1752 adev->gmc.vm_fault.num_types = 1; 1753 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1754 } 1755 1756 const struct amdgpu_ip_block_version gmc_v8_0_ip_block = 1757 { 1758 .type = AMD_IP_BLOCK_TYPE_GMC, 1759 .major = 8, 1760 .minor = 0, 1761 .rev = 0, 1762 .funcs = &gmc_v8_0_ip_funcs, 1763 }; 1764 1765 const struct amdgpu_ip_block_version gmc_v8_1_ip_block = 1766 { 1767 .type = AMD_IP_BLOCK_TYPE_GMC, 1768 .major = 8, 1769 .minor = 1, 1770 .rev = 0, 1771 .funcs = &gmc_v8_0_ip_funcs, 1772 }; 1773 1774 const struct amdgpu_ip_block_version gmc_v8_5_ip_block = 1775 { 1776 .type = AMD_IP_BLOCK_TYPE_GMC, 1777 .major = 8, 1778 .minor = 5, 1779 .rev = 0, 1780 .funcs = &gmc_v8_0_ip_funcs, 1781 }; 1782