1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "gmc_v8_0.h" 27 #include "amdgpu_ucode.h" 28 29 #include "gmc/gmc_8_1_d.h" 30 #include "gmc/gmc_8_1_sh_mask.h" 31 32 #include "bif/bif_5_0_d.h" 33 #include "bif/bif_5_0_sh_mask.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "vid.h" 39 #include "vi.h" 40 41 42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); 43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 44 45 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 46 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 47 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 48 49 static const u32 golden_settings_tonga_a11[] = 50 { 51 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 52 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 53 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 54 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 55 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 56 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 57 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 58 }; 59 60 static const u32 tonga_mgcg_cgcg_init[] = 61 { 62 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 63 }; 64 65 static const u32 golden_settings_fiji_a10[] = 66 { 67 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 68 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 69 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 70 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 71 }; 72 73 static const u32 fiji_mgcg_cgcg_init[] = 74 { 75 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 76 }; 77 78 static const u32 golden_settings_polaris11_a11[] = 79 { 80 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 81 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 82 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 83 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 84 }; 85 86 static const u32 golden_settings_polaris10_a11[] = 87 { 88 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 89 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 90 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 91 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 92 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 93 }; 94 95 static const u32 cz_mgcg_cgcg_init[] = 96 { 97 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 98 }; 99 100 static const u32 stoney_mgcg_cgcg_init[] = 101 { 102 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 103 }; 104 105 106 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 107 { 108 switch (adev->asic_type) { 109 case CHIP_FIJI: 110 amdgpu_program_register_sequence(adev, 111 fiji_mgcg_cgcg_init, 112 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 113 amdgpu_program_register_sequence(adev, 114 golden_settings_fiji_a10, 115 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 116 break; 117 case CHIP_TONGA: 118 amdgpu_program_register_sequence(adev, 119 tonga_mgcg_cgcg_init, 120 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 121 amdgpu_program_register_sequence(adev, 122 golden_settings_tonga_a11, 123 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 124 break; 125 case CHIP_POLARIS11: 126 amdgpu_program_register_sequence(adev, 127 golden_settings_polaris11_a11, 128 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 129 break; 130 case CHIP_POLARIS10: 131 amdgpu_program_register_sequence(adev, 132 golden_settings_polaris10_a11, 133 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 134 break; 135 case CHIP_CARRIZO: 136 amdgpu_program_register_sequence(adev, 137 cz_mgcg_cgcg_init, 138 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 139 break; 140 case CHIP_STONEY: 141 amdgpu_program_register_sequence(adev, 142 stoney_mgcg_cgcg_init, 143 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 144 break; 145 default: 146 break; 147 } 148 } 149 150 /** 151 * gmc8_mc_wait_for_idle - wait for MC idle callback. 152 * 153 * @adev: amdgpu_device pointer 154 * 155 * Wait for the MC (memory controller) to be idle. 156 * (evergreen+). 157 * Returns 0 if the MC is idle, -1 if not. 158 */ 159 int gmc_v8_0_mc_wait_for_idle(struct amdgpu_device *adev) 160 { 161 unsigned i; 162 u32 tmp; 163 164 for (i = 0; i < adev->usec_timeout; i++) { 165 /* read MC_STATUS */ 166 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__VMC_BUSY_MASK | 167 SRBM_STATUS__MCB_BUSY_MASK | 168 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 169 SRBM_STATUS__MCC_BUSY_MASK | 170 SRBM_STATUS__MCD_BUSY_MASK | 171 SRBM_STATUS__VMC1_BUSY_MASK); 172 if (!tmp) 173 return 0; 174 udelay(1); 175 } 176 return -1; 177 } 178 179 void gmc_v8_0_mc_stop(struct amdgpu_device *adev, 180 struct amdgpu_mode_mc_save *save) 181 { 182 u32 blackout; 183 184 if (adev->mode_info.num_crtc) 185 amdgpu_display_stop_mc_access(adev, save); 186 187 amdgpu_asic_wait_for_mc_idle(adev); 188 189 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 190 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 191 /* Block CPU access */ 192 WREG32(mmBIF_FB_EN, 0); 193 /* blackout the MC */ 194 blackout = REG_SET_FIELD(blackout, 195 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 196 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 197 } 198 /* wait for the MC to settle */ 199 udelay(100); 200 } 201 202 void gmc_v8_0_mc_resume(struct amdgpu_device *adev, 203 struct amdgpu_mode_mc_save *save) 204 { 205 u32 tmp; 206 207 /* unblackout the MC */ 208 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 209 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 210 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 211 /* allow CPU access */ 212 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 213 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 214 WREG32(mmBIF_FB_EN, tmp); 215 216 if (adev->mode_info.num_crtc) 217 amdgpu_display_resume_mc_access(adev, save); 218 } 219 220 /** 221 * gmc_v8_0_init_microcode - load ucode images from disk 222 * 223 * @adev: amdgpu_device pointer 224 * 225 * Use the firmware interface to load the ucode images into 226 * the driver (not loaded into hw). 227 * Returns 0 on success, error on failure. 228 */ 229 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 230 { 231 const char *chip_name; 232 char fw_name[30]; 233 int err; 234 235 DRM_DEBUG("\n"); 236 237 switch (adev->asic_type) { 238 case CHIP_TONGA: 239 chip_name = "tonga"; 240 break; 241 case CHIP_POLARIS11: 242 chip_name = "polaris11"; 243 break; 244 case CHIP_POLARIS10: 245 chip_name = "polaris10"; 246 break; 247 case CHIP_FIJI: 248 case CHIP_CARRIZO: 249 case CHIP_STONEY: 250 return 0; 251 default: BUG(); 252 } 253 254 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 255 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 256 if (err) 257 goto out; 258 err = amdgpu_ucode_validate(adev->mc.fw); 259 260 out: 261 if (err) { 262 printk(KERN_ERR 263 "mc: Failed to load firmware \"%s\"\n", 264 fw_name); 265 release_firmware(adev->mc.fw); 266 adev->mc.fw = NULL; 267 } 268 return err; 269 } 270 271 /** 272 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw 273 * 274 * @adev: amdgpu_device pointer 275 * 276 * Load the GDDR MC ucode into the hw (CIK). 277 * Returns 0 on success, error on failure. 278 */ 279 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev) 280 { 281 const struct mc_firmware_header_v1_0 *hdr; 282 const __le32 *fw_data = NULL; 283 const __le32 *io_mc_regs = NULL; 284 u32 running, blackout = 0; 285 int i, ucode_size, regs_size; 286 287 if (!adev->mc.fw) 288 return -EINVAL; 289 290 /* Skip MC ucode loading on SR-IOV capable boards. 291 * vbios does this for us in asic_init in that case. 292 */ 293 if (adev->virtualization.supports_sr_iov) 294 return 0; 295 296 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 297 amdgpu_ucode_print_mc_hdr(&hdr->header); 298 299 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 300 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 301 io_mc_regs = (const __le32 *) 302 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 303 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 304 fw_data = (const __le32 *) 305 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 306 307 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 308 309 if (running == 0) { 310 if (running) { 311 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 312 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 313 } 314 315 /* reset the engine and set to writable */ 316 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 317 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 318 319 /* load mc io regs */ 320 for (i = 0; i < regs_size; i++) { 321 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 322 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 323 } 324 /* load the MC ucode */ 325 for (i = 0; i < ucode_size; i++) 326 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 327 328 /* put the engine back into the active state */ 329 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 330 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 331 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 332 333 /* wait for training to complete */ 334 for (i = 0; i < adev->usec_timeout; i++) { 335 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 336 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 337 break; 338 udelay(1); 339 } 340 for (i = 0; i < adev->usec_timeout; i++) { 341 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 342 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 343 break; 344 udelay(1); 345 } 346 347 if (running) 348 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 349 } 350 351 return 0; 352 } 353 354 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 355 struct amdgpu_mc *mc) 356 { 357 if (mc->mc_vram_size > 0xFFC0000000ULL) { 358 /* leave room for at least 1024M GTT */ 359 dev_warn(adev->dev, "limiting VRAM\n"); 360 mc->real_vram_size = 0xFFC0000000ULL; 361 mc->mc_vram_size = 0xFFC0000000ULL; 362 } 363 amdgpu_vram_location(adev, &adev->mc, 0); 364 adev->mc.gtt_base_align = 0; 365 amdgpu_gtt_location(adev, mc); 366 } 367 368 /** 369 * gmc_v8_0_mc_program - program the GPU memory controller 370 * 371 * @adev: amdgpu_device pointer 372 * 373 * Set the location of vram, gart, and AGP in the GPU's 374 * physical address space (CIK). 375 */ 376 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 377 { 378 struct amdgpu_mode_mc_save save; 379 u32 tmp; 380 int i, j; 381 382 /* Initialize HDP */ 383 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 384 WREG32((0xb05 + j), 0x00000000); 385 WREG32((0xb06 + j), 0x00000000); 386 WREG32((0xb07 + j), 0x00000000); 387 WREG32((0xb08 + j), 0x00000000); 388 WREG32((0xb09 + j), 0x00000000); 389 } 390 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 391 392 if (adev->mode_info.num_crtc) 393 amdgpu_display_set_vga_render_state(adev, false); 394 395 gmc_v8_0_mc_stop(adev, &save); 396 if (amdgpu_asic_wait_for_mc_idle(adev)) { 397 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 398 } 399 /* Update configuration */ 400 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 401 adev->mc.vram_start >> 12); 402 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 403 adev->mc.vram_end >> 12); 404 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 405 adev->vram_scratch.gpu_addr >> 12); 406 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 407 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 408 WREG32(mmMC_VM_FB_LOCATION, tmp); 409 /* XXX double check these! */ 410 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 411 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 412 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 413 WREG32(mmMC_VM_AGP_BASE, 0); 414 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 415 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 416 if (amdgpu_asic_wait_for_mc_idle(adev)) { 417 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 418 } 419 gmc_v8_0_mc_resume(adev, &save); 420 421 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 422 423 tmp = RREG32(mmHDP_MISC_CNTL); 424 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 425 WREG32(mmHDP_MISC_CNTL, tmp); 426 427 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 428 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 429 } 430 431 /** 432 * gmc_v8_0_mc_init - initialize the memory controller driver params 433 * 434 * @adev: amdgpu_device pointer 435 * 436 * Look up the amount of vram, vram width, and decide how to place 437 * vram and gart within the GPU's physical address space (CIK). 438 * Returns 0 for success. 439 */ 440 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 441 { 442 u32 tmp; 443 int chansize, numchan; 444 445 /* Get VRAM informations */ 446 tmp = RREG32(mmMC_ARB_RAMCFG); 447 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 448 chansize = 64; 449 } else { 450 chansize = 32; 451 } 452 tmp = RREG32(mmMC_SHARED_CHMAP); 453 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 454 case 0: 455 default: 456 numchan = 1; 457 break; 458 case 1: 459 numchan = 2; 460 break; 461 case 2: 462 numchan = 4; 463 break; 464 case 3: 465 numchan = 8; 466 break; 467 case 4: 468 numchan = 3; 469 break; 470 case 5: 471 numchan = 6; 472 break; 473 case 6: 474 numchan = 10; 475 break; 476 case 7: 477 numchan = 12; 478 break; 479 case 8: 480 numchan = 16; 481 break; 482 } 483 adev->mc.vram_width = numchan * chansize; 484 /* Could aper size report 0 ? */ 485 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 486 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 487 /* size in MB on si */ 488 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 489 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 490 adev->mc.visible_vram_size = adev->mc.aper_size; 491 492 /* In case the PCI BAR is larger than the actual amount of vram */ 493 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 494 adev->mc.visible_vram_size = adev->mc.real_vram_size; 495 496 /* unless the user had overridden it, set the gart 497 * size equal to the 1024 or vram, whichever is larger. 498 */ 499 if (amdgpu_gart_size == -1) 500 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 501 else 502 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 503 504 gmc_v8_0_vram_gtt_location(adev, &adev->mc); 505 506 return 0; 507 } 508 509 /* 510 * GART 511 * VMID 0 is the physical GPU addresses as used by the kernel. 512 * VMIDs 1-15 are used for userspace clients and are handled 513 * by the amdgpu vm/hsa code. 514 */ 515 516 /** 517 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback 518 * 519 * @adev: amdgpu_device pointer 520 * @vmid: vm instance to flush 521 * 522 * Flush the TLB for the requested page table (CIK). 523 */ 524 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 525 uint32_t vmid) 526 { 527 /* flush hdp cache */ 528 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 529 530 /* bits 0-15 are the VM contexts0-15 */ 531 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 532 } 533 534 /** 535 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO 536 * 537 * @adev: amdgpu_device pointer 538 * @cpu_pt_addr: cpu address of the page table 539 * @gpu_page_idx: entry in the page table to update 540 * @addr: dst addr to write into pte/pde 541 * @flags: access flags 542 * 543 * Update the page tables using the CPU. 544 */ 545 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, 546 void *cpu_pt_addr, 547 uint32_t gpu_page_idx, 548 uint64_t addr, 549 uint32_t flags) 550 { 551 void __iomem *ptr = (void *)cpu_pt_addr; 552 uint64_t value; 553 554 /* 555 * PTE format on VI: 556 * 63:40 reserved 557 * 39:12 4k physical page base address 558 * 11:7 fragment 559 * 6 write 560 * 5 read 561 * 4 exe 562 * 3 reserved 563 * 2 snooped 564 * 1 system 565 * 0 valid 566 * 567 * PDE format on VI: 568 * 63:59 block fragment size 569 * 58:40 reserved 570 * 39:1 physical base address of PTE 571 * bits 5:1 must be 0. 572 * 0 valid 573 */ 574 value = addr & 0x000000FFFFFFF000ULL; 575 value |= flags; 576 writeq(value, ptr + (gpu_page_idx * 8)); 577 578 return 0; 579 } 580 581 /** 582 * gmc_v8_0_set_fault_enable_default - update VM fault handling 583 * 584 * @adev: amdgpu_device pointer 585 * @value: true redirects VM faults to the default page 586 */ 587 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 588 bool value) 589 { 590 u32 tmp; 591 592 tmp = RREG32(mmVM_CONTEXT1_CNTL); 593 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 594 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 595 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 596 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 597 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 598 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 599 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 600 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 601 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 602 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 603 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 604 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 605 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 606 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 607 WREG32(mmVM_CONTEXT1_CNTL, tmp); 608 } 609 610 /** 611 * gmc_v8_0_gart_enable - gart enable 612 * 613 * @adev: amdgpu_device pointer 614 * 615 * This sets up the TLBs, programs the page tables for VMID0, 616 * sets up the hw for VMIDs 1-15 which are allocated on 617 * demand, and sets up the global locations for the LDS, GDS, 618 * and GPUVM for FSA64 clients (CIK). 619 * Returns 0 for success, errors for failure. 620 */ 621 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 622 { 623 int r, i; 624 u32 tmp; 625 626 if (adev->gart.robj == NULL) { 627 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 628 return -EINVAL; 629 } 630 r = amdgpu_gart_table_vram_pin(adev); 631 if (r) 632 return r; 633 /* Setup TLB control */ 634 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 635 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 636 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 637 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 638 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 639 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 640 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 641 /* Setup L2 cache */ 642 tmp = RREG32(mmVM_L2_CNTL); 643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 646 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 647 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 648 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 649 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 650 WREG32(mmVM_L2_CNTL, tmp); 651 tmp = RREG32(mmVM_L2_CNTL2); 652 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 653 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 654 WREG32(mmVM_L2_CNTL2, tmp); 655 tmp = RREG32(mmVM_L2_CNTL3); 656 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 657 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); 658 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); 659 WREG32(mmVM_L2_CNTL3, tmp); 660 /* XXX: set to enable PTE/PDE in system memory */ 661 tmp = RREG32(mmVM_L2_CNTL4); 662 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 663 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 664 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 665 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 666 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 667 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 668 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 669 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 670 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 671 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 672 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 673 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 674 WREG32(mmVM_L2_CNTL4, tmp); 675 /* setup context0 */ 676 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 677 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 678 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 679 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 680 (u32)(adev->dummy_page.addr >> 12)); 681 WREG32(mmVM_CONTEXT0_CNTL2, 0); 682 tmp = RREG32(mmVM_CONTEXT0_CNTL); 683 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 684 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 685 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 686 WREG32(mmVM_CONTEXT0_CNTL, tmp); 687 688 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 689 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 690 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 691 692 /* empty context1-15 */ 693 /* FIXME start with 4G, once using 2 level pt switch to full 694 * vm size space 695 */ 696 /* set vm size, must be a multiple of 4 */ 697 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 698 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 699 for (i = 1; i < 16; i++) { 700 if (i < 8) 701 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 702 adev->gart.table_addr >> 12); 703 else 704 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 705 adev->gart.table_addr >> 12); 706 } 707 708 /* enable context1-15 */ 709 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 710 (u32)(adev->dummy_page.addr >> 12)); 711 WREG32(mmVM_CONTEXT1_CNTL2, 4); 712 tmp = RREG32(mmVM_CONTEXT1_CNTL); 713 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 714 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 715 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 716 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 717 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 718 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 719 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 720 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 721 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 722 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 723 amdgpu_vm_block_size - 9); 724 WREG32(mmVM_CONTEXT1_CNTL, tmp); 725 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 726 gmc_v8_0_set_fault_enable_default(adev, false); 727 else 728 gmc_v8_0_set_fault_enable_default(adev, true); 729 730 gmc_v8_0_gart_flush_gpu_tlb(adev, 0); 731 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 732 (unsigned)(adev->mc.gtt_size >> 20), 733 (unsigned long long)adev->gart.table_addr); 734 adev->gart.ready = true; 735 return 0; 736 } 737 738 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 739 { 740 int r; 741 742 if (adev->gart.robj) { 743 WARN(1, "R600 PCIE GART already initialized\n"); 744 return 0; 745 } 746 /* Initialize common gart structure */ 747 r = amdgpu_gart_init(adev); 748 if (r) 749 return r; 750 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 751 return amdgpu_gart_table_vram_alloc(adev); 752 } 753 754 /** 755 * gmc_v8_0_gart_disable - gart disable 756 * 757 * @adev: amdgpu_device pointer 758 * 759 * This disables all VM page table (CIK). 760 */ 761 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 762 { 763 u32 tmp; 764 765 /* Disable all tables */ 766 WREG32(mmVM_CONTEXT0_CNTL, 0); 767 WREG32(mmVM_CONTEXT1_CNTL, 0); 768 /* Setup TLB control */ 769 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 770 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 771 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 772 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 773 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 774 /* Setup L2 cache */ 775 tmp = RREG32(mmVM_L2_CNTL); 776 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 777 WREG32(mmVM_L2_CNTL, tmp); 778 WREG32(mmVM_L2_CNTL2, 0); 779 amdgpu_gart_table_vram_unpin(adev); 780 } 781 782 /** 783 * gmc_v8_0_gart_fini - vm fini callback 784 * 785 * @adev: amdgpu_device pointer 786 * 787 * Tears down the driver GART/VM setup (CIK). 788 */ 789 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) 790 { 791 amdgpu_gart_table_vram_free(adev); 792 amdgpu_gart_fini(adev); 793 } 794 795 /* 796 * vm 797 * VMID 0 is the physical GPU addresses as used by the kernel. 798 * VMIDs 1-15 are used for userspace clients and are handled 799 * by the amdgpu vm/hsa code. 800 */ 801 /** 802 * gmc_v8_0_vm_init - cik vm init callback 803 * 804 * @adev: amdgpu_device pointer 805 * 806 * Inits cik specific vm parameters (number of VMs, base of vram for 807 * VMIDs 1-15) (CIK). 808 * Returns 0 for success. 809 */ 810 static int gmc_v8_0_vm_init(struct amdgpu_device *adev) 811 { 812 /* 813 * number of VMs 814 * VMID 0 is reserved for System 815 * amdgpu graphics/compute will use VMIDs 1-7 816 * amdkfd will use VMIDs 8-15 817 */ 818 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 819 amdgpu_vm_manager_init(adev); 820 821 /* base offset of vram pages */ 822 if (adev->flags & AMD_IS_APU) { 823 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 824 tmp <<= 22; 825 adev->vm_manager.vram_base_offset = tmp; 826 } else 827 adev->vm_manager.vram_base_offset = 0; 828 829 return 0; 830 } 831 832 /** 833 * gmc_v8_0_vm_fini - cik vm fini callback 834 * 835 * @adev: amdgpu_device pointer 836 * 837 * Tear down any asic specific VM setup (CIK). 838 */ 839 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev) 840 { 841 } 842 843 /** 844 * gmc_v8_0_vm_decode_fault - print human readable fault info 845 * 846 * @adev: amdgpu_device pointer 847 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 848 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 849 * 850 * Print human readable fault information (CIK). 851 */ 852 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, 853 u32 status, u32 addr, u32 mc_client) 854 { 855 u32 mc_id; 856 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 857 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 858 PROTECTIONS); 859 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 860 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 861 862 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 863 MEMORY_CLIENT_ID); 864 865 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 866 protections, vmid, addr, 867 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 868 MEMORY_CLIENT_RW) ? 869 "write" : "read", block, mc_client, mc_id); 870 } 871 872 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 873 { 874 switch (mc_seq_vram_type) { 875 case MC_SEQ_MISC0__MT__GDDR1: 876 return AMDGPU_VRAM_TYPE_GDDR1; 877 case MC_SEQ_MISC0__MT__DDR2: 878 return AMDGPU_VRAM_TYPE_DDR2; 879 case MC_SEQ_MISC0__MT__GDDR3: 880 return AMDGPU_VRAM_TYPE_GDDR3; 881 case MC_SEQ_MISC0__MT__GDDR4: 882 return AMDGPU_VRAM_TYPE_GDDR4; 883 case MC_SEQ_MISC0__MT__GDDR5: 884 return AMDGPU_VRAM_TYPE_GDDR5; 885 case MC_SEQ_MISC0__MT__HBM: 886 return AMDGPU_VRAM_TYPE_HBM; 887 case MC_SEQ_MISC0__MT__DDR3: 888 return AMDGPU_VRAM_TYPE_DDR3; 889 default: 890 return AMDGPU_VRAM_TYPE_UNKNOWN; 891 } 892 } 893 894 static int gmc_v8_0_early_init(void *handle) 895 { 896 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 897 898 gmc_v8_0_set_gart_funcs(adev); 899 gmc_v8_0_set_irq_funcs(adev); 900 901 return 0; 902 } 903 904 static int gmc_v8_0_late_init(void *handle) 905 { 906 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 907 908 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 909 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 910 else 911 return 0; 912 } 913 914 #define mmMC_SEQ_MISC0_FIJI 0xA71 915 916 static int gmc_v8_0_sw_init(void *handle) 917 { 918 int r; 919 int dma_bits; 920 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 921 922 if (adev->flags & AMD_IS_APU) { 923 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 924 } else { 925 u32 tmp; 926 927 if (adev->asic_type == CHIP_FIJI) 928 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 929 else 930 tmp = RREG32(mmMC_SEQ_MISC0); 931 tmp &= MC_SEQ_MISC0__MT__MASK; 932 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); 933 } 934 935 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); 936 if (r) 937 return r; 938 939 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); 940 if (r) 941 return r; 942 943 /* Adjust VM size here. 944 * Currently set to 4GB ((1 << 20) 4k pages). 945 * Max GPUVM size for cayman and SI is 40 bits. 946 */ 947 adev->vm_manager.max_pfn = amdgpu_vm_size << 18; 948 949 /* Set the internal MC address mask 950 * This is the max address of the GPU's 951 * internal address space. 952 */ 953 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 954 955 /* set DMA mask + need_dma32 flags. 956 * PCIE - can handle 40-bits. 957 * IGP - can handle 40-bits 958 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 959 */ 960 adev->need_dma32 = false; 961 dma_bits = adev->need_dma32 ? 32 : 40; 962 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 963 if (r) { 964 adev->need_dma32 = true; 965 dma_bits = 32; 966 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 967 } 968 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 969 if (r) { 970 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 971 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 972 } 973 974 r = gmc_v8_0_init_microcode(adev); 975 if (r) { 976 DRM_ERROR("Failed to load mc firmware!\n"); 977 return r; 978 } 979 980 r = gmc_v8_0_mc_init(adev); 981 if (r) 982 return r; 983 984 /* Memory manager */ 985 r = amdgpu_bo_init(adev); 986 if (r) 987 return r; 988 989 r = gmc_v8_0_gart_init(adev); 990 if (r) 991 return r; 992 993 if (!adev->vm_manager.enabled) { 994 r = gmc_v8_0_vm_init(adev); 995 if (r) { 996 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 997 return r; 998 } 999 adev->vm_manager.enabled = true; 1000 } 1001 1002 return r; 1003 } 1004 1005 static int gmc_v8_0_sw_fini(void *handle) 1006 { 1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1008 1009 if (adev->vm_manager.enabled) { 1010 amdgpu_vm_manager_fini(adev); 1011 gmc_v8_0_vm_fini(adev); 1012 adev->vm_manager.enabled = false; 1013 } 1014 gmc_v8_0_gart_fini(adev); 1015 amdgpu_gem_force_release(adev); 1016 amdgpu_bo_fini(adev); 1017 1018 return 0; 1019 } 1020 1021 static int gmc_v8_0_hw_init(void *handle) 1022 { 1023 int r; 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1025 1026 gmc_v8_0_init_golden_registers(adev); 1027 1028 gmc_v8_0_mc_program(adev); 1029 1030 if (adev->asic_type == CHIP_TONGA) { 1031 r = gmc_v8_0_mc_load_microcode(adev); 1032 if (r) { 1033 DRM_ERROR("Failed to load MC firmware!\n"); 1034 return r; 1035 } 1036 } 1037 1038 r = gmc_v8_0_gart_enable(adev); 1039 if (r) 1040 return r; 1041 1042 return r; 1043 } 1044 1045 static int gmc_v8_0_hw_fini(void *handle) 1046 { 1047 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1048 1049 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1050 gmc_v8_0_gart_disable(adev); 1051 1052 return 0; 1053 } 1054 1055 static int gmc_v8_0_suspend(void *handle) 1056 { 1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1058 1059 if (adev->vm_manager.enabled) { 1060 gmc_v8_0_vm_fini(adev); 1061 adev->vm_manager.enabled = false; 1062 } 1063 gmc_v8_0_hw_fini(adev); 1064 1065 return 0; 1066 } 1067 1068 static int gmc_v8_0_resume(void *handle) 1069 { 1070 int r; 1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1072 1073 r = gmc_v8_0_hw_init(adev); 1074 if (r) 1075 return r; 1076 1077 if (!adev->vm_manager.enabled) { 1078 r = gmc_v8_0_vm_init(adev); 1079 if (r) { 1080 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 1081 return r; 1082 } 1083 adev->vm_manager.enabled = true; 1084 } 1085 1086 return r; 1087 } 1088 1089 static bool gmc_v8_0_is_idle(void *handle) 1090 { 1091 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1092 u32 tmp = RREG32(mmSRBM_STATUS); 1093 1094 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1095 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1096 return false; 1097 1098 return true; 1099 } 1100 1101 static int gmc_v8_0_wait_for_idle(void *handle) 1102 { 1103 unsigned i; 1104 u32 tmp; 1105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1106 1107 for (i = 0; i < adev->usec_timeout; i++) { 1108 /* read MC_STATUS */ 1109 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1110 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1111 SRBM_STATUS__MCC_BUSY_MASK | 1112 SRBM_STATUS__MCD_BUSY_MASK | 1113 SRBM_STATUS__VMC_BUSY_MASK | 1114 SRBM_STATUS__VMC1_BUSY_MASK); 1115 if (!tmp) 1116 return 0; 1117 udelay(1); 1118 } 1119 return -ETIMEDOUT; 1120 1121 } 1122 1123 static int gmc_v8_0_soft_reset(void *handle) 1124 { 1125 struct amdgpu_mode_mc_save save; 1126 u32 srbm_soft_reset = 0; 1127 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1128 u32 tmp = RREG32(mmSRBM_STATUS); 1129 1130 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1131 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1132 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1133 1134 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1135 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1136 if (!(adev->flags & AMD_IS_APU)) 1137 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1138 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1139 } 1140 1141 if (srbm_soft_reset) { 1142 gmc_v8_0_mc_stop(adev, &save); 1143 if (gmc_v8_0_wait_for_idle(adev)) { 1144 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1145 } 1146 1147 1148 tmp = RREG32(mmSRBM_SOFT_RESET); 1149 tmp |= srbm_soft_reset; 1150 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1151 WREG32(mmSRBM_SOFT_RESET, tmp); 1152 tmp = RREG32(mmSRBM_SOFT_RESET); 1153 1154 udelay(50); 1155 1156 tmp &= ~srbm_soft_reset; 1157 WREG32(mmSRBM_SOFT_RESET, tmp); 1158 tmp = RREG32(mmSRBM_SOFT_RESET); 1159 1160 /* Wait a little for things to settle down */ 1161 udelay(50); 1162 1163 gmc_v8_0_mc_resume(adev, &save); 1164 udelay(50); 1165 } 1166 1167 return 0; 1168 } 1169 1170 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1171 struct amdgpu_irq_src *src, 1172 unsigned type, 1173 enum amdgpu_interrupt_state state) 1174 { 1175 u32 tmp; 1176 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1177 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1178 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1179 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1180 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1181 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1182 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1183 1184 switch (state) { 1185 case AMDGPU_IRQ_STATE_DISABLE: 1186 /* system context */ 1187 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1188 tmp &= ~bits; 1189 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1190 /* VMs */ 1191 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1192 tmp &= ~bits; 1193 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1194 break; 1195 case AMDGPU_IRQ_STATE_ENABLE: 1196 /* system context */ 1197 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1198 tmp |= bits; 1199 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1200 /* VMs */ 1201 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1202 tmp |= bits; 1203 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1204 break; 1205 default: 1206 break; 1207 } 1208 1209 return 0; 1210 } 1211 1212 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1213 struct amdgpu_irq_src *source, 1214 struct amdgpu_iv_entry *entry) 1215 { 1216 u32 addr, status, mc_client; 1217 1218 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1219 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1220 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1221 /* reset addr and status */ 1222 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1223 1224 if (!addr && !status) 1225 return 0; 1226 1227 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1228 gmc_v8_0_set_fault_enable_default(adev, false); 1229 1230 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1231 entry->src_id, entry->src_data); 1232 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1233 addr); 1234 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1235 status); 1236 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); 1237 1238 return 0; 1239 } 1240 1241 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1242 bool enable) 1243 { 1244 uint32_t data; 1245 1246 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1247 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1248 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1249 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1250 1251 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1252 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1253 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1254 1255 data = RREG32(mmMC_HUB_MISC_VM_CG); 1256 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1257 WREG32(mmMC_HUB_MISC_VM_CG, data); 1258 1259 data = RREG32(mmMC_XPB_CLK_GAT); 1260 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1261 WREG32(mmMC_XPB_CLK_GAT, data); 1262 1263 data = RREG32(mmATC_MISC_CG); 1264 data |= ATC_MISC_CG__ENABLE_MASK; 1265 WREG32(mmATC_MISC_CG, data); 1266 1267 data = RREG32(mmMC_CITF_MISC_WR_CG); 1268 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1269 WREG32(mmMC_CITF_MISC_WR_CG, data); 1270 1271 data = RREG32(mmMC_CITF_MISC_RD_CG); 1272 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1273 WREG32(mmMC_CITF_MISC_RD_CG, data); 1274 1275 data = RREG32(mmMC_CITF_MISC_VM_CG); 1276 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1277 WREG32(mmMC_CITF_MISC_VM_CG, data); 1278 1279 data = RREG32(mmVM_L2_CG); 1280 data |= VM_L2_CG__ENABLE_MASK; 1281 WREG32(mmVM_L2_CG, data); 1282 } else { 1283 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1284 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1285 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1286 1287 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1288 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1289 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1290 1291 data = RREG32(mmMC_HUB_MISC_VM_CG); 1292 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1293 WREG32(mmMC_HUB_MISC_VM_CG, data); 1294 1295 data = RREG32(mmMC_XPB_CLK_GAT); 1296 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1297 WREG32(mmMC_XPB_CLK_GAT, data); 1298 1299 data = RREG32(mmATC_MISC_CG); 1300 data &= ~ATC_MISC_CG__ENABLE_MASK; 1301 WREG32(mmATC_MISC_CG, data); 1302 1303 data = RREG32(mmMC_CITF_MISC_WR_CG); 1304 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1305 WREG32(mmMC_CITF_MISC_WR_CG, data); 1306 1307 data = RREG32(mmMC_CITF_MISC_RD_CG); 1308 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1309 WREG32(mmMC_CITF_MISC_RD_CG, data); 1310 1311 data = RREG32(mmMC_CITF_MISC_VM_CG); 1312 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1313 WREG32(mmMC_CITF_MISC_VM_CG, data); 1314 1315 data = RREG32(mmVM_L2_CG); 1316 data &= ~VM_L2_CG__ENABLE_MASK; 1317 WREG32(mmVM_L2_CG, data); 1318 } 1319 } 1320 1321 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1322 bool enable) 1323 { 1324 uint32_t data; 1325 1326 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1327 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1328 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1329 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1330 1331 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1332 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1333 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1334 1335 data = RREG32(mmMC_HUB_MISC_VM_CG); 1336 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1337 WREG32(mmMC_HUB_MISC_VM_CG, data); 1338 1339 data = RREG32(mmMC_XPB_CLK_GAT); 1340 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1341 WREG32(mmMC_XPB_CLK_GAT, data); 1342 1343 data = RREG32(mmATC_MISC_CG); 1344 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1345 WREG32(mmATC_MISC_CG, data); 1346 1347 data = RREG32(mmMC_CITF_MISC_WR_CG); 1348 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1349 WREG32(mmMC_CITF_MISC_WR_CG, data); 1350 1351 data = RREG32(mmMC_CITF_MISC_RD_CG); 1352 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1353 WREG32(mmMC_CITF_MISC_RD_CG, data); 1354 1355 data = RREG32(mmMC_CITF_MISC_VM_CG); 1356 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1357 WREG32(mmMC_CITF_MISC_VM_CG, data); 1358 1359 data = RREG32(mmVM_L2_CG); 1360 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1361 WREG32(mmVM_L2_CG, data); 1362 } else { 1363 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1364 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1365 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1366 1367 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1368 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1369 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1370 1371 data = RREG32(mmMC_HUB_MISC_VM_CG); 1372 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1373 WREG32(mmMC_HUB_MISC_VM_CG, data); 1374 1375 data = RREG32(mmMC_XPB_CLK_GAT); 1376 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1377 WREG32(mmMC_XPB_CLK_GAT, data); 1378 1379 data = RREG32(mmATC_MISC_CG); 1380 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1381 WREG32(mmATC_MISC_CG, data); 1382 1383 data = RREG32(mmMC_CITF_MISC_WR_CG); 1384 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1385 WREG32(mmMC_CITF_MISC_WR_CG, data); 1386 1387 data = RREG32(mmMC_CITF_MISC_RD_CG); 1388 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1389 WREG32(mmMC_CITF_MISC_RD_CG, data); 1390 1391 data = RREG32(mmMC_CITF_MISC_VM_CG); 1392 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1393 WREG32(mmMC_CITF_MISC_VM_CG, data); 1394 1395 data = RREG32(mmVM_L2_CG); 1396 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1397 WREG32(mmVM_L2_CG, data); 1398 } 1399 } 1400 1401 static int gmc_v8_0_set_clockgating_state(void *handle, 1402 enum amd_clockgating_state state) 1403 { 1404 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1405 1406 switch (adev->asic_type) { 1407 case CHIP_FIJI: 1408 fiji_update_mc_medium_grain_clock_gating(adev, 1409 state == AMD_CG_STATE_GATE ? true : false); 1410 fiji_update_mc_light_sleep(adev, 1411 state == AMD_CG_STATE_GATE ? true : false); 1412 break; 1413 default: 1414 break; 1415 } 1416 return 0; 1417 } 1418 1419 static int gmc_v8_0_set_powergating_state(void *handle, 1420 enum amd_powergating_state state) 1421 { 1422 return 0; 1423 } 1424 1425 const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1426 .name = "gmc_v8_0", 1427 .early_init = gmc_v8_0_early_init, 1428 .late_init = gmc_v8_0_late_init, 1429 .sw_init = gmc_v8_0_sw_init, 1430 .sw_fini = gmc_v8_0_sw_fini, 1431 .hw_init = gmc_v8_0_hw_init, 1432 .hw_fini = gmc_v8_0_hw_fini, 1433 .suspend = gmc_v8_0_suspend, 1434 .resume = gmc_v8_0_resume, 1435 .is_idle = gmc_v8_0_is_idle, 1436 .wait_for_idle = gmc_v8_0_wait_for_idle, 1437 .soft_reset = gmc_v8_0_soft_reset, 1438 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1439 .set_powergating_state = gmc_v8_0_set_powergating_state, 1440 }; 1441 1442 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { 1443 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, 1444 .set_pte_pde = gmc_v8_0_gart_set_pte_pde, 1445 }; 1446 1447 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1448 .set = gmc_v8_0_vm_fault_interrupt_state, 1449 .process = gmc_v8_0_process_interrupt, 1450 }; 1451 1452 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev) 1453 { 1454 if (adev->gart.gart_funcs == NULL) 1455 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs; 1456 } 1457 1458 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1459 { 1460 adev->mc.vm_fault.num_types = 1; 1461 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1462 } 1463