1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "gmc_v8_0.h" 27 #include "amdgpu_ucode.h" 28 29 #include "gmc/gmc_8_1_d.h" 30 #include "gmc/gmc_8_1_sh_mask.h" 31 32 #include "bif/bif_5_0_d.h" 33 #include "bif/bif_5_0_sh_mask.h" 34 35 #include "oss/oss_3_0_d.h" 36 #include "oss/oss_3_0_sh_mask.h" 37 38 #include "vid.h" 39 #include "vi.h" 40 41 42 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); 43 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); 44 static int gmc_v8_0_wait_for_idle(void *handle); 45 46 MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); 47 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); 48 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); 49 50 static const u32 golden_settings_tonga_a11[] = 51 { 52 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 53 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028, 54 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991, 55 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 56 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 57 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 58 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 59 }; 60 61 static const u32 tonga_mgcg_cgcg_init[] = 62 { 63 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 64 }; 65 66 static const u32 golden_settings_fiji_a10[] = 67 { 68 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 69 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 70 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 71 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 72 }; 73 74 static const u32 fiji_mgcg_cgcg_init[] = 75 { 76 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 77 }; 78 79 static const u32 golden_settings_polaris11_a11[] = 80 { 81 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 82 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 83 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 84 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 85 }; 86 87 static const u32 golden_settings_polaris10_a11[] = 88 { 89 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, 90 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 91 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 92 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 93 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 94 }; 95 96 static const u32 cz_mgcg_cgcg_init[] = 97 { 98 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 99 }; 100 101 static const u32 stoney_mgcg_cgcg_init[] = 102 { 103 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 104 }; 105 106 107 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) 108 { 109 switch (adev->asic_type) { 110 case CHIP_FIJI: 111 amdgpu_program_register_sequence(adev, 112 fiji_mgcg_cgcg_init, 113 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 114 amdgpu_program_register_sequence(adev, 115 golden_settings_fiji_a10, 116 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 117 break; 118 case CHIP_TONGA: 119 amdgpu_program_register_sequence(adev, 120 tonga_mgcg_cgcg_init, 121 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 122 amdgpu_program_register_sequence(adev, 123 golden_settings_tonga_a11, 124 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 125 break; 126 case CHIP_POLARIS11: 127 amdgpu_program_register_sequence(adev, 128 golden_settings_polaris11_a11, 129 (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); 130 break; 131 case CHIP_POLARIS10: 132 amdgpu_program_register_sequence(adev, 133 golden_settings_polaris10_a11, 134 (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); 135 break; 136 case CHIP_CARRIZO: 137 amdgpu_program_register_sequence(adev, 138 cz_mgcg_cgcg_init, 139 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 140 break; 141 case CHIP_STONEY: 142 amdgpu_program_register_sequence(adev, 143 stoney_mgcg_cgcg_init, 144 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); 145 break; 146 default: 147 break; 148 } 149 } 150 151 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev, 152 struct amdgpu_mode_mc_save *save) 153 { 154 u32 blackout; 155 156 if (adev->mode_info.num_crtc) 157 amdgpu_display_stop_mc_access(adev, save); 158 159 gmc_v8_0_wait_for_idle(adev); 160 161 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 162 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 163 /* Block CPU access */ 164 WREG32(mmBIF_FB_EN, 0); 165 /* blackout the MC */ 166 blackout = REG_SET_FIELD(blackout, 167 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1); 168 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 169 } 170 /* wait for the MC to settle */ 171 udelay(100); 172 } 173 174 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev, 175 struct amdgpu_mode_mc_save *save) 176 { 177 u32 tmp; 178 179 /* unblackout the MC */ 180 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 181 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 182 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 183 /* allow CPU access */ 184 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 185 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 186 WREG32(mmBIF_FB_EN, tmp); 187 188 if (adev->mode_info.num_crtc) 189 amdgpu_display_resume_mc_access(adev, save); 190 } 191 192 /** 193 * gmc_v8_0_init_microcode - load ucode images from disk 194 * 195 * @adev: amdgpu_device pointer 196 * 197 * Use the firmware interface to load the ucode images into 198 * the driver (not loaded into hw). 199 * Returns 0 on success, error on failure. 200 */ 201 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) 202 { 203 const char *chip_name; 204 char fw_name[30]; 205 int err; 206 207 DRM_DEBUG("\n"); 208 209 switch (adev->asic_type) { 210 case CHIP_TONGA: 211 chip_name = "tonga"; 212 break; 213 case CHIP_POLARIS11: 214 chip_name = "polaris11"; 215 break; 216 case CHIP_POLARIS10: 217 chip_name = "polaris10"; 218 break; 219 case CHIP_FIJI: 220 case CHIP_CARRIZO: 221 case CHIP_STONEY: 222 return 0; 223 default: BUG(); 224 } 225 226 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 227 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 228 if (err) 229 goto out; 230 err = amdgpu_ucode_validate(adev->mc.fw); 231 232 out: 233 if (err) { 234 printk(KERN_ERR 235 "mc: Failed to load firmware \"%s\"\n", 236 fw_name); 237 release_firmware(adev->mc.fw); 238 adev->mc.fw = NULL; 239 } 240 return err; 241 } 242 243 /** 244 * gmc_v8_0_mc_load_microcode - load MC ucode into the hw 245 * 246 * @adev: amdgpu_device pointer 247 * 248 * Load the GDDR MC ucode into the hw (CIK). 249 * Returns 0 on success, error on failure. 250 */ 251 static int gmc_v8_0_mc_load_microcode(struct amdgpu_device *adev) 252 { 253 const struct mc_firmware_header_v1_0 *hdr; 254 const __le32 *fw_data = NULL; 255 const __le32 *io_mc_regs = NULL; 256 u32 running, blackout = 0; 257 int i, ucode_size, regs_size; 258 259 if (!adev->mc.fw) 260 return -EINVAL; 261 262 /* Skip MC ucode loading on SR-IOV capable boards. 263 * vbios does this for us in asic_init in that case. 264 */ 265 if (adev->virtualization.supports_sr_iov) 266 return 0; 267 268 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 269 amdgpu_ucode_print_mc_hdr(&hdr->header); 270 271 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 272 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 273 io_mc_regs = (const __le32 *) 274 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 275 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 276 fw_data = (const __le32 *) 277 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 278 279 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 280 281 if (running == 0) { 282 if (running) { 283 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 284 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 285 } 286 287 /* reset the engine and set to writable */ 288 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 289 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 290 291 /* load mc io regs */ 292 for (i = 0; i < regs_size; i++) { 293 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 294 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 295 } 296 /* load the MC ucode */ 297 for (i = 0; i < ucode_size; i++) 298 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 299 300 /* put the engine back into the active state */ 301 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 302 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 303 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 304 305 /* wait for training to complete */ 306 for (i = 0; i < adev->usec_timeout; i++) { 307 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 308 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 309 break; 310 udelay(1); 311 } 312 for (i = 0; i < adev->usec_timeout; i++) { 313 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 314 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 315 break; 316 udelay(1); 317 } 318 319 if (running) 320 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout); 321 } 322 323 return 0; 324 } 325 326 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, 327 struct amdgpu_mc *mc) 328 { 329 if (mc->mc_vram_size > 0xFFC0000000ULL) { 330 /* leave room for at least 1024M GTT */ 331 dev_warn(adev->dev, "limiting VRAM\n"); 332 mc->real_vram_size = 0xFFC0000000ULL; 333 mc->mc_vram_size = 0xFFC0000000ULL; 334 } 335 amdgpu_vram_location(adev, &adev->mc, 0); 336 adev->mc.gtt_base_align = 0; 337 amdgpu_gtt_location(adev, mc); 338 } 339 340 /** 341 * gmc_v8_0_mc_program - program the GPU memory controller 342 * 343 * @adev: amdgpu_device pointer 344 * 345 * Set the location of vram, gart, and AGP in the GPU's 346 * physical address space (CIK). 347 */ 348 static void gmc_v8_0_mc_program(struct amdgpu_device *adev) 349 { 350 struct amdgpu_mode_mc_save save; 351 u32 tmp; 352 int i, j; 353 354 /* Initialize HDP */ 355 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 356 WREG32((0xb05 + j), 0x00000000); 357 WREG32((0xb06 + j), 0x00000000); 358 WREG32((0xb07 + j), 0x00000000); 359 WREG32((0xb08 + j), 0x00000000); 360 WREG32((0xb09 + j), 0x00000000); 361 } 362 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 363 364 if (adev->mode_info.num_crtc) 365 amdgpu_display_set_vga_render_state(adev, false); 366 367 gmc_v8_0_mc_stop(adev, &save); 368 if (gmc_v8_0_wait_for_idle((void *)adev)) { 369 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 370 } 371 /* Update configuration */ 372 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 373 adev->mc.vram_start >> 12); 374 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 375 adev->mc.vram_end >> 12); 376 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 377 adev->vram_scratch.gpu_addr >> 12); 378 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 379 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 380 WREG32(mmMC_VM_FB_LOCATION, tmp); 381 /* XXX double check these! */ 382 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 383 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 384 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 385 WREG32(mmMC_VM_AGP_BASE, 0); 386 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 387 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 388 if (gmc_v8_0_wait_for_idle((void *)adev)) { 389 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 390 } 391 gmc_v8_0_mc_resume(adev, &save); 392 393 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 394 395 tmp = RREG32(mmHDP_MISC_CNTL); 396 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 397 WREG32(mmHDP_MISC_CNTL, tmp); 398 399 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 400 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 401 } 402 403 /** 404 * gmc_v8_0_mc_init - initialize the memory controller driver params 405 * 406 * @adev: amdgpu_device pointer 407 * 408 * Look up the amount of vram, vram width, and decide how to place 409 * vram and gart within the GPU's physical address space (CIK). 410 * Returns 0 for success. 411 */ 412 static int gmc_v8_0_mc_init(struct amdgpu_device *adev) 413 { 414 u32 tmp; 415 int chansize, numchan; 416 417 /* Get VRAM informations */ 418 tmp = RREG32(mmMC_ARB_RAMCFG); 419 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 420 chansize = 64; 421 } else { 422 chansize = 32; 423 } 424 tmp = RREG32(mmMC_SHARED_CHMAP); 425 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 426 case 0: 427 default: 428 numchan = 1; 429 break; 430 case 1: 431 numchan = 2; 432 break; 433 case 2: 434 numchan = 4; 435 break; 436 case 3: 437 numchan = 8; 438 break; 439 case 4: 440 numchan = 3; 441 break; 442 case 5: 443 numchan = 6; 444 break; 445 case 6: 446 numchan = 10; 447 break; 448 case 7: 449 numchan = 12; 450 break; 451 case 8: 452 numchan = 16; 453 break; 454 } 455 adev->mc.vram_width = numchan * chansize; 456 /* Could aper size report 0 ? */ 457 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 458 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 459 /* size in MB on si */ 460 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 461 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 462 adev->mc.visible_vram_size = adev->mc.aper_size; 463 464 /* In case the PCI BAR is larger than the actual amount of vram */ 465 if (adev->mc.visible_vram_size > adev->mc.real_vram_size) 466 adev->mc.visible_vram_size = adev->mc.real_vram_size; 467 468 /* unless the user had overridden it, set the gart 469 * size equal to the 1024 or vram, whichever is larger. 470 */ 471 if (amdgpu_gart_size == -1) 472 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 473 else 474 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 475 476 gmc_v8_0_vram_gtt_location(adev, &adev->mc); 477 478 return 0; 479 } 480 481 /* 482 * GART 483 * VMID 0 is the physical GPU addresses as used by the kernel. 484 * VMIDs 1-15 are used for userspace clients and are handled 485 * by the amdgpu vm/hsa code. 486 */ 487 488 /** 489 * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback 490 * 491 * @adev: amdgpu_device pointer 492 * @vmid: vm instance to flush 493 * 494 * Flush the TLB for the requested page table (CIK). 495 */ 496 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 497 uint32_t vmid) 498 { 499 /* flush hdp cache */ 500 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 501 502 /* bits 0-15 are the VM contexts0-15 */ 503 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 504 } 505 506 /** 507 * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO 508 * 509 * @adev: amdgpu_device pointer 510 * @cpu_pt_addr: cpu address of the page table 511 * @gpu_page_idx: entry in the page table to update 512 * @addr: dst addr to write into pte/pde 513 * @flags: access flags 514 * 515 * Update the page tables using the CPU. 516 */ 517 static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, 518 void *cpu_pt_addr, 519 uint32_t gpu_page_idx, 520 uint64_t addr, 521 uint32_t flags) 522 { 523 void __iomem *ptr = (void *)cpu_pt_addr; 524 uint64_t value; 525 526 /* 527 * PTE format on VI: 528 * 63:40 reserved 529 * 39:12 4k physical page base address 530 * 11:7 fragment 531 * 6 write 532 * 5 read 533 * 4 exe 534 * 3 reserved 535 * 2 snooped 536 * 1 system 537 * 0 valid 538 * 539 * PDE format on VI: 540 * 63:59 block fragment size 541 * 58:40 reserved 542 * 39:1 physical base address of PTE 543 * bits 5:1 must be 0. 544 * 0 valid 545 */ 546 value = addr & 0x000000FFFFFFF000ULL; 547 value |= flags; 548 writeq(value, ptr + (gpu_page_idx * 8)); 549 550 return 0; 551 } 552 553 /** 554 * gmc_v8_0_set_fault_enable_default - update VM fault handling 555 * 556 * @adev: amdgpu_device pointer 557 * @value: true redirects VM faults to the default page 558 */ 559 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, 560 bool value) 561 { 562 u32 tmp; 563 564 tmp = RREG32(mmVM_CONTEXT1_CNTL); 565 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 566 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 567 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 568 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 569 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 570 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 571 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 572 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 573 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 574 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 575 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 576 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 577 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 578 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 579 WREG32(mmVM_CONTEXT1_CNTL, tmp); 580 } 581 582 /** 583 * gmc_v8_0_gart_enable - gart enable 584 * 585 * @adev: amdgpu_device pointer 586 * 587 * This sets up the TLBs, programs the page tables for VMID0, 588 * sets up the hw for VMIDs 1-15 which are allocated on 589 * demand, and sets up the global locations for the LDS, GDS, 590 * and GPUVM for FSA64 clients (CIK). 591 * Returns 0 for success, errors for failure. 592 */ 593 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) 594 { 595 int r, i; 596 u32 tmp; 597 598 if (adev->gart.robj == NULL) { 599 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 600 return -EINVAL; 601 } 602 r = amdgpu_gart_table_vram_pin(adev); 603 if (r) 604 return r; 605 /* Setup TLB control */ 606 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 607 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 608 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 609 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 610 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 611 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 612 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 613 /* Setup L2 cache */ 614 tmp = RREG32(mmVM_L2_CNTL); 615 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 616 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 617 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 618 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 619 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 620 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 621 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 622 WREG32(mmVM_L2_CNTL, tmp); 623 tmp = RREG32(mmVM_L2_CNTL2); 624 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 626 WREG32(mmVM_L2_CNTL2, tmp); 627 tmp = RREG32(mmVM_L2_CNTL3); 628 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 4); 630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 4); 631 WREG32(mmVM_L2_CNTL3, tmp); 632 /* XXX: set to enable PTE/PDE in system memory */ 633 tmp = RREG32(mmVM_L2_CNTL4); 634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0); 635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0); 636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0); 637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0); 638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0); 639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0); 640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0); 641 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0); 642 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0); 643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0); 644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0); 645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); 646 WREG32(mmVM_L2_CNTL4, tmp); 647 /* setup context0 */ 648 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 649 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 650 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 651 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 652 (u32)(adev->dummy_page.addr >> 12)); 653 WREG32(mmVM_CONTEXT0_CNTL2, 0); 654 tmp = RREG32(mmVM_CONTEXT0_CNTL); 655 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 656 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 657 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 658 WREG32(mmVM_CONTEXT0_CNTL, tmp); 659 660 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0); 661 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0); 662 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0); 663 664 /* empty context1-15 */ 665 /* FIXME start with 4G, once using 2 level pt switch to full 666 * vm size space 667 */ 668 /* set vm size, must be a multiple of 4 */ 669 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 670 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 671 for (i = 1; i < 16; i++) { 672 if (i < 8) 673 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 674 adev->gart.table_addr >> 12); 675 else 676 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 677 adev->gart.table_addr >> 12); 678 } 679 680 /* enable context1-15 */ 681 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 682 (u32)(adev->dummy_page.addr >> 12)); 683 WREG32(mmVM_CONTEXT1_CNTL2, 4); 684 tmp = RREG32(mmVM_CONTEXT1_CNTL); 685 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 686 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 687 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 688 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 689 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 690 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 691 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 692 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 693 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 694 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 695 amdgpu_vm_block_size - 9); 696 WREG32(mmVM_CONTEXT1_CNTL, tmp); 697 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 698 gmc_v8_0_set_fault_enable_default(adev, false); 699 else 700 gmc_v8_0_set_fault_enable_default(adev, true); 701 702 gmc_v8_0_gart_flush_gpu_tlb(adev, 0); 703 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 704 (unsigned)(adev->mc.gtt_size >> 20), 705 (unsigned long long)adev->gart.table_addr); 706 adev->gart.ready = true; 707 return 0; 708 } 709 710 static int gmc_v8_0_gart_init(struct amdgpu_device *adev) 711 { 712 int r; 713 714 if (adev->gart.robj) { 715 WARN(1, "R600 PCIE GART already initialized\n"); 716 return 0; 717 } 718 /* Initialize common gart structure */ 719 r = amdgpu_gart_init(adev); 720 if (r) 721 return r; 722 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 723 return amdgpu_gart_table_vram_alloc(adev); 724 } 725 726 /** 727 * gmc_v8_0_gart_disable - gart disable 728 * 729 * @adev: amdgpu_device pointer 730 * 731 * This disables all VM page table (CIK). 732 */ 733 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev) 734 { 735 u32 tmp; 736 737 /* Disable all tables */ 738 WREG32(mmVM_CONTEXT0_CNTL, 0); 739 WREG32(mmVM_CONTEXT1_CNTL, 0); 740 /* Setup TLB control */ 741 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 742 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 743 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 744 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 745 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 746 /* Setup L2 cache */ 747 tmp = RREG32(mmVM_L2_CNTL); 748 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 749 WREG32(mmVM_L2_CNTL, tmp); 750 WREG32(mmVM_L2_CNTL2, 0); 751 amdgpu_gart_table_vram_unpin(adev); 752 } 753 754 /** 755 * gmc_v8_0_gart_fini - vm fini callback 756 * 757 * @adev: amdgpu_device pointer 758 * 759 * Tears down the driver GART/VM setup (CIK). 760 */ 761 static void gmc_v8_0_gart_fini(struct amdgpu_device *adev) 762 { 763 amdgpu_gart_table_vram_free(adev); 764 amdgpu_gart_fini(adev); 765 } 766 767 /* 768 * vm 769 * VMID 0 is the physical GPU addresses as used by the kernel. 770 * VMIDs 1-15 are used for userspace clients and are handled 771 * by the amdgpu vm/hsa code. 772 */ 773 /** 774 * gmc_v8_0_vm_init - cik vm init callback 775 * 776 * @adev: amdgpu_device pointer 777 * 778 * Inits cik specific vm parameters (number of VMs, base of vram for 779 * VMIDs 1-15) (CIK). 780 * Returns 0 for success. 781 */ 782 static int gmc_v8_0_vm_init(struct amdgpu_device *adev) 783 { 784 /* 785 * number of VMs 786 * VMID 0 is reserved for System 787 * amdgpu graphics/compute will use VMIDs 1-7 788 * amdkfd will use VMIDs 8-15 789 */ 790 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 791 amdgpu_vm_manager_init(adev); 792 793 /* base offset of vram pages */ 794 if (adev->flags & AMD_IS_APU) { 795 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 796 tmp <<= 22; 797 adev->vm_manager.vram_base_offset = tmp; 798 } else 799 adev->vm_manager.vram_base_offset = 0; 800 801 return 0; 802 } 803 804 /** 805 * gmc_v8_0_vm_fini - cik vm fini callback 806 * 807 * @adev: amdgpu_device pointer 808 * 809 * Tear down any asic specific VM setup (CIK). 810 */ 811 static void gmc_v8_0_vm_fini(struct amdgpu_device *adev) 812 { 813 } 814 815 /** 816 * gmc_v8_0_vm_decode_fault - print human readable fault info 817 * 818 * @adev: amdgpu_device pointer 819 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 820 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 821 * 822 * Print human readable fault information (CIK). 823 */ 824 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, 825 u32 status, u32 addr, u32 mc_client) 826 { 827 u32 mc_id; 828 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 829 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 830 PROTECTIONS); 831 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 832 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 833 834 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 835 MEMORY_CLIENT_ID); 836 837 printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 838 protections, vmid, addr, 839 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 840 MEMORY_CLIENT_RW) ? 841 "write" : "read", block, mc_client, mc_id); 842 } 843 844 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) 845 { 846 switch (mc_seq_vram_type) { 847 case MC_SEQ_MISC0__MT__GDDR1: 848 return AMDGPU_VRAM_TYPE_GDDR1; 849 case MC_SEQ_MISC0__MT__DDR2: 850 return AMDGPU_VRAM_TYPE_DDR2; 851 case MC_SEQ_MISC0__MT__GDDR3: 852 return AMDGPU_VRAM_TYPE_GDDR3; 853 case MC_SEQ_MISC0__MT__GDDR4: 854 return AMDGPU_VRAM_TYPE_GDDR4; 855 case MC_SEQ_MISC0__MT__GDDR5: 856 return AMDGPU_VRAM_TYPE_GDDR5; 857 case MC_SEQ_MISC0__MT__HBM: 858 return AMDGPU_VRAM_TYPE_HBM; 859 case MC_SEQ_MISC0__MT__DDR3: 860 return AMDGPU_VRAM_TYPE_DDR3; 861 default: 862 return AMDGPU_VRAM_TYPE_UNKNOWN; 863 } 864 } 865 866 static int gmc_v8_0_early_init(void *handle) 867 { 868 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 869 870 gmc_v8_0_set_gart_funcs(adev); 871 gmc_v8_0_set_irq_funcs(adev); 872 873 return 0; 874 } 875 876 static int gmc_v8_0_late_init(void *handle) 877 { 878 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 879 880 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 881 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 882 else 883 return 0; 884 } 885 886 #define mmMC_SEQ_MISC0_FIJI 0xA71 887 888 static int gmc_v8_0_sw_init(void *handle) 889 { 890 int r; 891 int dma_bits; 892 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 893 894 if (adev->flags & AMD_IS_APU) { 895 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 896 } else { 897 u32 tmp; 898 899 if (adev->asic_type == CHIP_FIJI) 900 tmp = RREG32(mmMC_SEQ_MISC0_FIJI); 901 else 902 tmp = RREG32(mmMC_SEQ_MISC0); 903 tmp &= MC_SEQ_MISC0__MT__MASK; 904 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); 905 } 906 907 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); 908 if (r) 909 return r; 910 911 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); 912 if (r) 913 return r; 914 915 /* Adjust VM size here. 916 * Currently set to 4GB ((1 << 20) 4k pages). 917 * Max GPUVM size for cayman and SI is 40 bits. 918 */ 919 adev->vm_manager.max_pfn = amdgpu_vm_size << 18; 920 921 /* Set the internal MC address mask 922 * This is the max address of the GPU's 923 * internal address space. 924 */ 925 adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 926 927 /* set DMA mask + need_dma32 flags. 928 * PCIE - can handle 40-bits. 929 * IGP - can handle 40-bits 930 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 931 */ 932 adev->need_dma32 = false; 933 dma_bits = adev->need_dma32 ? 32 : 40; 934 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 935 if (r) { 936 adev->need_dma32 = true; 937 dma_bits = 32; 938 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 939 } 940 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 941 if (r) { 942 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 943 printk(KERN_WARNING "amdgpu: No coherent DMA available.\n"); 944 } 945 946 r = gmc_v8_0_init_microcode(adev); 947 if (r) { 948 DRM_ERROR("Failed to load mc firmware!\n"); 949 return r; 950 } 951 952 r = gmc_v8_0_mc_init(adev); 953 if (r) 954 return r; 955 956 /* Memory manager */ 957 r = amdgpu_bo_init(adev); 958 if (r) 959 return r; 960 961 r = gmc_v8_0_gart_init(adev); 962 if (r) 963 return r; 964 965 if (!adev->vm_manager.enabled) { 966 r = gmc_v8_0_vm_init(adev); 967 if (r) { 968 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 969 return r; 970 } 971 adev->vm_manager.enabled = true; 972 } 973 974 return r; 975 } 976 977 static int gmc_v8_0_sw_fini(void *handle) 978 { 979 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 980 981 if (adev->vm_manager.enabled) { 982 amdgpu_vm_manager_fini(adev); 983 gmc_v8_0_vm_fini(adev); 984 adev->vm_manager.enabled = false; 985 } 986 gmc_v8_0_gart_fini(adev); 987 amdgpu_gem_force_release(adev); 988 amdgpu_bo_fini(adev); 989 990 return 0; 991 } 992 993 static int gmc_v8_0_hw_init(void *handle) 994 { 995 int r; 996 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 997 998 gmc_v8_0_init_golden_registers(adev); 999 1000 gmc_v8_0_mc_program(adev); 1001 1002 if (adev->asic_type == CHIP_TONGA) { 1003 r = gmc_v8_0_mc_load_microcode(adev); 1004 if (r) { 1005 DRM_ERROR("Failed to load MC firmware!\n"); 1006 return r; 1007 } 1008 } 1009 1010 r = gmc_v8_0_gart_enable(adev); 1011 if (r) 1012 return r; 1013 1014 return r; 1015 } 1016 1017 static int gmc_v8_0_hw_fini(void *handle) 1018 { 1019 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1020 1021 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 1022 gmc_v8_0_gart_disable(adev); 1023 1024 return 0; 1025 } 1026 1027 static int gmc_v8_0_suspend(void *handle) 1028 { 1029 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1030 1031 if (adev->vm_manager.enabled) { 1032 gmc_v8_0_vm_fini(adev); 1033 adev->vm_manager.enabled = false; 1034 } 1035 gmc_v8_0_hw_fini(adev); 1036 1037 return 0; 1038 } 1039 1040 static int gmc_v8_0_resume(void *handle) 1041 { 1042 int r; 1043 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1044 1045 r = gmc_v8_0_hw_init(adev); 1046 if (r) 1047 return r; 1048 1049 if (!adev->vm_manager.enabled) { 1050 r = gmc_v8_0_vm_init(adev); 1051 if (r) { 1052 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 1053 return r; 1054 } 1055 adev->vm_manager.enabled = true; 1056 } 1057 1058 return r; 1059 } 1060 1061 static bool gmc_v8_0_is_idle(void *handle) 1062 { 1063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1064 u32 tmp = RREG32(mmSRBM_STATUS); 1065 1066 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1067 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1068 return false; 1069 1070 return true; 1071 } 1072 1073 static int gmc_v8_0_wait_for_idle(void *handle) 1074 { 1075 unsigned i; 1076 u32 tmp; 1077 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1078 1079 for (i = 0; i < adev->usec_timeout; i++) { 1080 /* read MC_STATUS */ 1081 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1082 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1083 SRBM_STATUS__MCC_BUSY_MASK | 1084 SRBM_STATUS__MCD_BUSY_MASK | 1085 SRBM_STATUS__VMC_BUSY_MASK | 1086 SRBM_STATUS__VMC1_BUSY_MASK); 1087 if (!tmp) 1088 return 0; 1089 udelay(1); 1090 } 1091 return -ETIMEDOUT; 1092 1093 } 1094 1095 static int gmc_v8_0_soft_reset(void *handle) 1096 { 1097 struct amdgpu_mode_mc_save save; 1098 u32 srbm_soft_reset = 0; 1099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1100 u32 tmp = RREG32(mmSRBM_STATUS); 1101 1102 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1103 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1104 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1105 1106 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1107 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1108 if (!(adev->flags & AMD_IS_APU)) 1109 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1110 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1111 } 1112 1113 if (srbm_soft_reset) { 1114 gmc_v8_0_mc_stop(adev, &save); 1115 if (gmc_v8_0_wait_for_idle((void *)adev)) { 1116 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1117 } 1118 1119 1120 tmp = RREG32(mmSRBM_SOFT_RESET); 1121 tmp |= srbm_soft_reset; 1122 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1123 WREG32(mmSRBM_SOFT_RESET, tmp); 1124 tmp = RREG32(mmSRBM_SOFT_RESET); 1125 1126 udelay(50); 1127 1128 tmp &= ~srbm_soft_reset; 1129 WREG32(mmSRBM_SOFT_RESET, tmp); 1130 tmp = RREG32(mmSRBM_SOFT_RESET); 1131 1132 /* Wait a little for things to settle down */ 1133 udelay(50); 1134 1135 gmc_v8_0_mc_resume(adev, &save); 1136 udelay(50); 1137 } 1138 1139 return 0; 1140 } 1141 1142 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1143 struct amdgpu_irq_src *src, 1144 unsigned type, 1145 enum amdgpu_interrupt_state state) 1146 { 1147 u32 tmp; 1148 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1149 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1150 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1151 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1152 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1153 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1154 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1155 1156 switch (state) { 1157 case AMDGPU_IRQ_STATE_DISABLE: 1158 /* system context */ 1159 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1160 tmp &= ~bits; 1161 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1162 /* VMs */ 1163 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1164 tmp &= ~bits; 1165 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1166 break; 1167 case AMDGPU_IRQ_STATE_ENABLE: 1168 /* system context */ 1169 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1170 tmp |= bits; 1171 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1172 /* VMs */ 1173 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1174 tmp |= bits; 1175 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1176 break; 1177 default: 1178 break; 1179 } 1180 1181 return 0; 1182 } 1183 1184 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, 1185 struct amdgpu_irq_src *source, 1186 struct amdgpu_iv_entry *entry) 1187 { 1188 u32 addr, status, mc_client; 1189 1190 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1191 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1192 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1193 /* reset addr and status */ 1194 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1195 1196 if (!addr && !status) 1197 return 0; 1198 1199 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1200 gmc_v8_0_set_fault_enable_default(adev, false); 1201 1202 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1203 entry->src_id, entry->src_data); 1204 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1205 addr); 1206 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1207 status); 1208 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); 1209 1210 return 0; 1211 } 1212 1213 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev, 1214 bool enable) 1215 { 1216 uint32_t data; 1217 1218 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { 1219 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1220 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1221 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1222 1223 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1224 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1225 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1226 1227 data = RREG32(mmMC_HUB_MISC_VM_CG); 1228 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK; 1229 WREG32(mmMC_HUB_MISC_VM_CG, data); 1230 1231 data = RREG32(mmMC_XPB_CLK_GAT); 1232 data |= MC_XPB_CLK_GAT__ENABLE_MASK; 1233 WREG32(mmMC_XPB_CLK_GAT, data); 1234 1235 data = RREG32(mmATC_MISC_CG); 1236 data |= ATC_MISC_CG__ENABLE_MASK; 1237 WREG32(mmATC_MISC_CG, data); 1238 1239 data = RREG32(mmMC_CITF_MISC_WR_CG); 1240 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK; 1241 WREG32(mmMC_CITF_MISC_WR_CG, data); 1242 1243 data = RREG32(mmMC_CITF_MISC_RD_CG); 1244 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK; 1245 WREG32(mmMC_CITF_MISC_RD_CG, data); 1246 1247 data = RREG32(mmMC_CITF_MISC_VM_CG); 1248 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK; 1249 WREG32(mmMC_CITF_MISC_VM_CG, data); 1250 1251 data = RREG32(mmVM_L2_CG); 1252 data |= VM_L2_CG__ENABLE_MASK; 1253 WREG32(mmVM_L2_CG, data); 1254 } else { 1255 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1256 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK; 1257 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1258 1259 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1260 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK; 1261 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1262 1263 data = RREG32(mmMC_HUB_MISC_VM_CG); 1264 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK; 1265 WREG32(mmMC_HUB_MISC_VM_CG, data); 1266 1267 data = RREG32(mmMC_XPB_CLK_GAT); 1268 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK; 1269 WREG32(mmMC_XPB_CLK_GAT, data); 1270 1271 data = RREG32(mmATC_MISC_CG); 1272 data &= ~ATC_MISC_CG__ENABLE_MASK; 1273 WREG32(mmATC_MISC_CG, data); 1274 1275 data = RREG32(mmMC_CITF_MISC_WR_CG); 1276 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK; 1277 WREG32(mmMC_CITF_MISC_WR_CG, data); 1278 1279 data = RREG32(mmMC_CITF_MISC_RD_CG); 1280 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK; 1281 WREG32(mmMC_CITF_MISC_RD_CG, data); 1282 1283 data = RREG32(mmMC_CITF_MISC_VM_CG); 1284 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK; 1285 WREG32(mmMC_CITF_MISC_VM_CG, data); 1286 1287 data = RREG32(mmVM_L2_CG); 1288 data &= ~VM_L2_CG__ENABLE_MASK; 1289 WREG32(mmVM_L2_CG, data); 1290 } 1291 } 1292 1293 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev, 1294 bool enable) 1295 { 1296 uint32_t data; 1297 1298 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) { 1299 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1300 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1301 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1302 1303 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1304 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1305 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1306 1307 data = RREG32(mmMC_HUB_MISC_VM_CG); 1308 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1309 WREG32(mmMC_HUB_MISC_VM_CG, data); 1310 1311 data = RREG32(mmMC_XPB_CLK_GAT); 1312 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1313 WREG32(mmMC_XPB_CLK_GAT, data); 1314 1315 data = RREG32(mmATC_MISC_CG); 1316 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1317 WREG32(mmATC_MISC_CG, data); 1318 1319 data = RREG32(mmMC_CITF_MISC_WR_CG); 1320 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1321 WREG32(mmMC_CITF_MISC_WR_CG, data); 1322 1323 data = RREG32(mmMC_CITF_MISC_RD_CG); 1324 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1325 WREG32(mmMC_CITF_MISC_RD_CG, data); 1326 1327 data = RREG32(mmMC_CITF_MISC_VM_CG); 1328 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1329 WREG32(mmMC_CITF_MISC_VM_CG, data); 1330 1331 data = RREG32(mmVM_L2_CG); 1332 data |= VM_L2_CG__MEM_LS_ENABLE_MASK; 1333 WREG32(mmVM_L2_CG, data); 1334 } else { 1335 data = RREG32(mmMC_HUB_MISC_HUB_CG); 1336 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK; 1337 WREG32(mmMC_HUB_MISC_HUB_CG, data); 1338 1339 data = RREG32(mmMC_HUB_MISC_SIP_CG); 1340 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK; 1341 WREG32(mmMC_HUB_MISC_SIP_CG, data); 1342 1343 data = RREG32(mmMC_HUB_MISC_VM_CG); 1344 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1345 WREG32(mmMC_HUB_MISC_VM_CG, data); 1346 1347 data = RREG32(mmMC_XPB_CLK_GAT); 1348 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK; 1349 WREG32(mmMC_XPB_CLK_GAT, data); 1350 1351 data = RREG32(mmATC_MISC_CG); 1352 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK; 1353 WREG32(mmATC_MISC_CG, data); 1354 1355 data = RREG32(mmMC_CITF_MISC_WR_CG); 1356 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK; 1357 WREG32(mmMC_CITF_MISC_WR_CG, data); 1358 1359 data = RREG32(mmMC_CITF_MISC_RD_CG); 1360 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK; 1361 WREG32(mmMC_CITF_MISC_RD_CG, data); 1362 1363 data = RREG32(mmMC_CITF_MISC_VM_CG); 1364 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK; 1365 WREG32(mmMC_CITF_MISC_VM_CG, data); 1366 1367 data = RREG32(mmVM_L2_CG); 1368 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK; 1369 WREG32(mmVM_L2_CG, data); 1370 } 1371 } 1372 1373 static int gmc_v8_0_set_clockgating_state(void *handle, 1374 enum amd_clockgating_state state) 1375 { 1376 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1377 1378 switch (adev->asic_type) { 1379 case CHIP_FIJI: 1380 fiji_update_mc_medium_grain_clock_gating(adev, 1381 state == AMD_CG_STATE_GATE ? true : false); 1382 fiji_update_mc_light_sleep(adev, 1383 state == AMD_CG_STATE_GATE ? true : false); 1384 break; 1385 default: 1386 break; 1387 } 1388 return 0; 1389 } 1390 1391 static int gmc_v8_0_set_powergating_state(void *handle, 1392 enum amd_powergating_state state) 1393 { 1394 return 0; 1395 } 1396 1397 const struct amd_ip_funcs gmc_v8_0_ip_funcs = { 1398 .name = "gmc_v8_0", 1399 .early_init = gmc_v8_0_early_init, 1400 .late_init = gmc_v8_0_late_init, 1401 .sw_init = gmc_v8_0_sw_init, 1402 .sw_fini = gmc_v8_0_sw_fini, 1403 .hw_init = gmc_v8_0_hw_init, 1404 .hw_fini = gmc_v8_0_hw_fini, 1405 .suspend = gmc_v8_0_suspend, 1406 .resume = gmc_v8_0_resume, 1407 .is_idle = gmc_v8_0_is_idle, 1408 .wait_for_idle = gmc_v8_0_wait_for_idle, 1409 .soft_reset = gmc_v8_0_soft_reset, 1410 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1411 .set_powergating_state = gmc_v8_0_set_powergating_state, 1412 }; 1413 1414 static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { 1415 .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, 1416 .set_pte_pde = gmc_v8_0_gart_set_pte_pde, 1417 }; 1418 1419 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { 1420 .set = gmc_v8_0_vm_fault_interrupt_state, 1421 .process = gmc_v8_0_process_interrupt, 1422 }; 1423 1424 static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev) 1425 { 1426 if (adev->gart.gart_funcs == NULL) 1427 adev->gart.gart_funcs = &gmc_v8_0_gart_funcs; 1428 } 1429 1430 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) 1431 { 1432 adev->mc.vm_fault.num_types = 1; 1433 adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; 1434 } 1435