1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "gmc_v7_0.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_amdkfd.h" 35 #include "amdgpu_gem.h" 36 37 #include "bif/bif_4_1_d.h" 38 #include "bif/bif_4_1_sh_mask.h" 39 40 #include "gmc/gmc_7_1_d.h" 41 #include "gmc/gmc_7_1_sh_mask.h" 42 43 #include "oss/oss_2_0_d.h" 44 #include "oss/oss_2_0_sh_mask.h" 45 46 #include "dce/dce_8_0_d.h" 47 #include "dce/dce_8_0_sh_mask.h" 48 49 #include "amdgpu_atombios.h" 50 51 #include "ivsrcid/ivsrcid_vislands30.h" 52 53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block); 56 57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 60 61 static const u32 golden_settings_iceland_a11[] = { 62 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 63 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 64 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 65 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 66 }; 67 68 static const u32 iceland_mgcg_cgcg_init[] = { 69 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 70 }; 71 72 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 73 { 74 switch (adev->asic_type) { 75 case CHIP_TOPAZ: 76 amdgpu_device_program_register_sequence(adev, 77 iceland_mgcg_cgcg_init, 78 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 79 amdgpu_device_program_register_sequence(adev, 80 golden_settings_iceland_a11, 81 ARRAY_SIZE(golden_settings_iceland_a11)); 82 break; 83 default: 84 break; 85 } 86 } 87 88 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 89 { 90 struct amdgpu_ip_block *ip_block; 91 u32 blackout; 92 93 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); 94 if (!ip_block) 95 return; 96 97 gmc_v7_0_wait_for_idle(ip_block); 98 99 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 100 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 101 /* Block CPU access */ 102 WREG32(mmBIF_FB_EN, 0); 103 /* blackout the MC */ 104 blackout = REG_SET_FIELD(blackout, 105 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 106 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 107 } 108 /* wait for the MC to settle */ 109 udelay(100); 110 } 111 112 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 113 { 114 u32 tmp; 115 116 /* unblackout the MC */ 117 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 118 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 119 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 120 /* allow CPU access */ 121 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 122 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 123 WREG32(mmBIF_FB_EN, tmp); 124 } 125 126 /** 127 * gmc_v7_0_init_microcode - load ucode images from disk 128 * 129 * @adev: amdgpu_device pointer 130 * 131 * Use the firmware interface to load the ucode images into 132 * the driver (not loaded into hw). 133 * Returns 0 on success, error on failure. 134 */ 135 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 136 { 137 const char *chip_name; 138 int err; 139 140 DRM_DEBUG("\n"); 141 142 switch (adev->asic_type) { 143 case CHIP_BONAIRE: 144 chip_name = "bonaire"; 145 break; 146 case CHIP_HAWAII: 147 chip_name = "hawaii"; 148 break; 149 case CHIP_TOPAZ: 150 chip_name = "topaz"; 151 break; 152 case CHIP_KAVERI: 153 case CHIP_KABINI: 154 case CHIP_MULLINS: 155 return 0; 156 default: 157 return -EINVAL; 158 } 159 160 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, 161 "amdgpu/%s_mc.bin", chip_name); 162 if (err) { 163 pr_err("cik_mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name); 164 amdgpu_ucode_release(&adev->gmc.fw); 165 } 166 return err; 167 } 168 169 /** 170 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 171 * 172 * @adev: amdgpu_device pointer 173 * 174 * Load the GDDR MC ucode into the hw (CIK). 175 * Returns 0 on success, error on failure. 176 */ 177 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 178 { 179 const struct mc_firmware_header_v1_0 *hdr; 180 const __le32 *fw_data = NULL; 181 const __le32 *io_mc_regs = NULL; 182 u32 running; 183 int i, ucode_size, regs_size; 184 185 if (!adev->gmc.fw) 186 return -EINVAL; 187 188 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 189 amdgpu_ucode_print_mc_hdr(&hdr->header); 190 191 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 192 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 193 io_mc_regs = (const __le32 *) 194 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 195 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 196 fw_data = (const __le32 *) 197 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 198 199 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 200 201 if (running == 0) { 202 /* reset the engine and set to writable */ 203 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 204 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 205 206 /* load mc io regs */ 207 for (i = 0; i < regs_size; i++) { 208 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 209 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 210 } 211 /* load the MC ucode */ 212 for (i = 0; i < ucode_size; i++) 213 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 214 215 /* put the engine back into the active state */ 216 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 217 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 218 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 219 220 /* wait for training to complete */ 221 for (i = 0; i < adev->usec_timeout; i++) { 222 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 223 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 224 break; 225 udelay(1); 226 } 227 for (i = 0; i < adev->usec_timeout; i++) { 228 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 229 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 230 break; 231 udelay(1); 232 } 233 } 234 235 return 0; 236 } 237 238 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 239 struct amdgpu_gmc *mc) 240 { 241 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 242 243 base <<= 24; 244 245 amdgpu_gmc_set_agp_default(adev, mc); 246 amdgpu_gmc_vram_location(adev, mc, base); 247 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 248 } 249 250 /** 251 * gmc_v7_0_mc_program - program the GPU memory controller 252 * 253 * @adev: amdgpu_device pointer 254 * 255 * Set the location of vram, gart, and AGP in the GPU's 256 * physical address space (CIK). 257 */ 258 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 259 { 260 struct amdgpu_ip_block *ip_block; 261 u32 tmp; 262 int i, j; 263 264 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); 265 if (!ip_block) 266 return; 267 268 /* Initialize HDP */ 269 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 270 WREG32((0xb05 + j), 0x00000000); 271 WREG32((0xb06 + j), 0x00000000); 272 WREG32((0xb07 + j), 0x00000000); 273 WREG32((0xb08 + j), 0x00000000); 274 WREG32((0xb09 + j), 0x00000000); 275 } 276 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 277 278 if (gmc_v7_0_wait_for_idle(ip_block)) 279 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 280 281 if (adev->mode_info.num_crtc) { 282 /* Lockout access through VGA aperture*/ 283 tmp = RREG32(mmVGA_HDP_CONTROL); 284 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 285 WREG32(mmVGA_HDP_CONTROL, tmp); 286 287 /* disable VGA render */ 288 tmp = RREG32(mmVGA_RENDER_CONTROL); 289 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 290 WREG32(mmVGA_RENDER_CONTROL, tmp); 291 } 292 /* Update configuration */ 293 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 294 adev->gmc.vram_start >> 12); 295 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 296 adev->gmc.vram_end >> 12); 297 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 298 adev->mem_scratch.gpu_addr >> 12); 299 WREG32(mmMC_VM_AGP_BASE, 0); 300 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); 301 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); 302 if (gmc_v7_0_wait_for_idle(ip_block)) 303 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 304 305 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 306 307 tmp = RREG32(mmHDP_MISC_CNTL); 308 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 309 WREG32(mmHDP_MISC_CNTL, tmp); 310 311 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 312 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 313 } 314 315 /** 316 * gmc_v7_0_mc_init - initialize the memory controller driver params 317 * 318 * @adev: amdgpu_device pointer 319 * 320 * Look up the amount of vram, vram width, and decide how to place 321 * vram and gart within the GPU's physical address space (CIK). 322 * Returns 0 for success. 323 */ 324 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 325 { 326 int r; 327 328 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 329 if (!adev->gmc.vram_width) { 330 u32 tmp; 331 int chansize, numchan; 332 333 /* Get VRAM informations */ 334 tmp = RREG32(mmMC_ARB_RAMCFG); 335 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) 336 chansize = 64; 337 else 338 chansize = 32; 339 340 tmp = RREG32(mmMC_SHARED_CHMAP); 341 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 342 case 0: 343 default: 344 numchan = 1; 345 break; 346 case 1: 347 numchan = 2; 348 break; 349 case 2: 350 numchan = 4; 351 break; 352 case 3: 353 numchan = 8; 354 break; 355 case 4: 356 numchan = 3; 357 break; 358 case 5: 359 numchan = 6; 360 break; 361 case 6: 362 numchan = 10; 363 break; 364 case 7: 365 numchan = 12; 366 break; 367 case 8: 368 numchan = 16; 369 break; 370 } 371 adev->gmc.vram_width = numchan * chansize; 372 } 373 /* size in MB on si */ 374 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 375 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 376 377 if (!(adev->flags & AMD_IS_APU)) { 378 r = amdgpu_device_resize_fb_bar(adev); 379 if (r) 380 return r; 381 } 382 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 383 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 384 385 #ifdef CONFIG_X86_64 386 if ((adev->flags & AMD_IS_APU) && 387 adev->gmc.real_vram_size > adev->gmc.aper_size && 388 !amdgpu_passthrough(adev)) { 389 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 390 adev->gmc.aper_size = adev->gmc.real_vram_size; 391 } 392 #endif 393 394 adev->gmc.visible_vram_size = adev->gmc.aper_size; 395 396 /* set the gart size */ 397 switch (adev->asic_type) { 398 #ifdef CONFIG_DRM_AMDGPU_CIK 399 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 400 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 401 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 402 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 403 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 404 amdgpu_gmc_set_gart_size(adev, SZ_1G); 405 break; 406 #endif 407 case CHIP_TOPAZ: /* no MM engines */ 408 default: 409 amdgpu_gmc_set_gart_size(adev, SZ_256M); 410 break; 411 } 412 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 413 414 return 0; 415 } 416 417 /** 418 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid 419 * 420 * @adev: amdgpu_device pointer 421 * @pasid: pasid to be flush 422 * @flush_type: type of flush 423 * @all_hub: flush all hubs 424 * @inst: is used to select which instance of KIQ to use for the invalidation 425 * 426 * Flush the TLB for the requested pasid. 427 */ 428 static void gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 429 uint16_t pasid, uint32_t flush_type, 430 bool all_hub, uint32_t inst) 431 { 432 u32 mask = 0x0; 433 int vmid; 434 435 for (vmid = 1; vmid < 16; vmid++) { 436 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 437 438 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 439 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) 440 mask |= 1 << vmid; 441 } 442 443 WREG32(mmVM_INVALIDATE_REQUEST, mask); 444 RREG32(mmVM_INVALIDATE_RESPONSE); 445 } 446 447 /* 448 * GART 449 * VMID 0 is the physical GPU addresses as used by the kernel. 450 * VMIDs 1-15 are used for userspace clients and are handled 451 * by the amdgpu vm/hsa code. 452 */ 453 454 /** 455 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 456 * 457 * @adev: amdgpu_device pointer 458 * @vmid: vm instance to flush 459 * @vmhub: which hub to flush 460 * @flush_type: type of flush 461 * * 462 * Flush the TLB for the requested page table (CIK). 463 */ 464 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 465 uint32_t vmhub, uint32_t flush_type) 466 { 467 /* bits 0-15 are the VM contexts0-15 */ 468 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 469 } 470 471 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 472 unsigned int vmid, uint64_t pd_addr) 473 { 474 uint32_t reg; 475 476 if (vmid < 8) 477 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 478 else 479 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 480 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 481 482 /* bits 0-15 are the VM contexts0-15 */ 483 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 484 485 return pd_addr; 486 } 487 488 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 489 unsigned int pasid) 490 { 491 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 492 } 493 494 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 495 uint64_t *addr, uint64_t *flags) 496 { 497 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 498 } 499 500 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev, 501 struct amdgpu_vm *vm, 502 struct amdgpu_bo *bo, 503 uint32_t vm_flags, 504 uint64_t *flags) 505 { 506 *flags &= ~AMDGPU_PTE_EXECUTABLE; 507 *flags &= ~AMDGPU_PTE_PRT; 508 } 509 510 /** 511 * gmc_v7_0_set_fault_enable_default - update VM fault handling 512 * 513 * @adev: amdgpu_device pointer 514 * @value: true redirects VM faults to the default page 515 */ 516 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 517 bool value) 518 { 519 u32 tmp; 520 521 tmp = RREG32(mmVM_CONTEXT1_CNTL); 522 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 523 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 524 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 525 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 526 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 527 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 528 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 529 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 530 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 531 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 532 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 533 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 534 WREG32(mmVM_CONTEXT1_CNTL, tmp); 535 } 536 537 /** 538 * gmc_v7_0_set_prt - set PRT VM fault 539 * 540 * @adev: amdgpu_device pointer 541 * @enable: enable/disable VM fault handling for PRT 542 */ 543 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 544 { 545 uint32_t tmp; 546 547 if (enable && !adev->gmc.prt_warning) { 548 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 549 adev->gmc.prt_warning = true; 550 } 551 552 tmp = RREG32(mmVM_PRT_CNTL); 553 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 554 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 555 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 556 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 557 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 558 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 559 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 560 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 561 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 562 L2_CACHE_STORE_INVALID_ENTRIES, enable); 563 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 564 L1_TLB_STORE_INVALID_ENTRIES, enable); 565 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 566 MASK_PDE0_FAULT, enable); 567 WREG32(mmVM_PRT_CNTL, tmp); 568 569 if (enable) { 570 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >> 571 AMDGPU_GPU_PAGE_SHIFT; 572 uint32_t high = adev->vm_manager.max_pfn - 573 (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT); 574 575 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 576 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 577 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 578 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 579 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 580 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 581 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 582 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 583 } else { 584 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 585 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 586 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 587 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 588 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 589 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 590 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 591 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 592 } 593 } 594 595 /** 596 * gmc_v7_0_gart_enable - gart enable 597 * 598 * @adev: amdgpu_device pointer 599 * 600 * This sets up the TLBs, programs the page tables for VMID0, 601 * sets up the hw for VMIDs 1-15 which are allocated on 602 * demand, and sets up the global locations for the LDS, GDS, 603 * and GPUVM for FSA64 clients (CIK). 604 * Returns 0 for success, errors for failure. 605 */ 606 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 607 { 608 uint64_t table_addr; 609 u32 tmp, field; 610 int i; 611 612 if (adev->gart.bo == NULL) { 613 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 614 return -EINVAL; 615 } 616 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 617 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 618 619 /* Setup TLB control */ 620 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 621 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 622 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 623 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 624 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 625 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 626 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 627 /* Setup L2 cache */ 628 tmp = RREG32(mmVM_L2_CNTL); 629 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 630 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 631 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 632 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 633 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 636 WREG32(mmVM_L2_CNTL, tmp); 637 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 639 WREG32(mmVM_L2_CNTL2, tmp); 640 641 field = adev->vm_manager.fragment_size; 642 tmp = RREG32(mmVM_L2_CNTL3); 643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 644 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 645 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 646 WREG32(mmVM_L2_CNTL3, tmp); 647 /* setup context0 */ 648 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 649 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 650 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 651 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 652 (u32)(adev->dummy_page_addr >> 12)); 653 WREG32(mmVM_CONTEXT0_CNTL2, 0); 654 tmp = RREG32(mmVM_CONTEXT0_CNTL); 655 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 656 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 657 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 658 WREG32(mmVM_CONTEXT0_CNTL, tmp); 659 660 WREG32(0x575, 0); 661 WREG32(0x576, 0); 662 WREG32(0x577, 0); 663 664 /* empty context1-15 */ 665 /* FIXME start with 4G, once using 2 level pt switch to full 666 * vm size space 667 */ 668 /* set vm size, must be a multiple of 4 */ 669 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 670 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 671 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 672 if (i < 8) 673 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 674 table_addr >> 12); 675 else 676 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 677 table_addr >> 12); 678 } 679 680 /* enable context1-15 */ 681 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 682 (u32)(adev->dummy_page_addr >> 12)); 683 WREG32(mmVM_CONTEXT1_CNTL2, 4); 684 tmp = RREG32(mmVM_CONTEXT1_CNTL); 685 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 686 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 687 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 688 adev->vm_manager.block_size - 9); 689 WREG32(mmVM_CONTEXT1_CNTL, tmp); 690 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 691 gmc_v7_0_set_fault_enable_default(adev, false); 692 else 693 gmc_v7_0_set_fault_enable_default(adev, true); 694 695 if (adev->asic_type == CHIP_KAVERI) { 696 tmp = RREG32(mmCHUB_CONTROL); 697 tmp &= ~BYPASS_VM; 698 WREG32(mmCHUB_CONTROL, tmp); 699 } 700 701 gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0); 702 drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", 703 (unsigned int)(adev->gmc.gart_size >> 20), 704 (unsigned long long)table_addr); 705 return 0; 706 } 707 708 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 709 { 710 int r; 711 712 if (adev->gart.bo) { 713 WARN(1, "R600 PCIE GART already initialized\n"); 714 return 0; 715 } 716 /* Initialize common gart structure */ 717 r = amdgpu_gart_init(adev); 718 if (r) 719 return r; 720 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 721 adev->gart.gart_pte_flags = 0; 722 return amdgpu_gart_table_vram_alloc(adev); 723 } 724 725 /** 726 * gmc_v7_0_gart_disable - gart disable 727 * 728 * @adev: amdgpu_device pointer 729 * 730 * This disables all VM page table (CIK). 731 */ 732 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 733 { 734 u32 tmp; 735 736 /* Disable all tables */ 737 WREG32(mmVM_CONTEXT0_CNTL, 0); 738 WREG32(mmVM_CONTEXT1_CNTL, 0); 739 /* Setup TLB control */ 740 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 741 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 742 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 743 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 744 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 745 /* Setup L2 cache */ 746 tmp = RREG32(mmVM_L2_CNTL); 747 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 748 WREG32(mmVM_L2_CNTL, tmp); 749 WREG32(mmVM_L2_CNTL2, 0); 750 } 751 752 /** 753 * gmc_v7_0_vm_decode_fault - print human readable fault info 754 * 755 * @adev: amdgpu_device pointer 756 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 757 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 758 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 759 * @pasid: debug logging only - no functional use 760 * 761 * Print human readable fault information (CIK). 762 */ 763 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 764 u32 addr, u32 mc_client, unsigned int pasid) 765 { 766 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 767 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 768 PROTECTIONS); 769 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 770 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 771 u32 mc_id; 772 773 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 774 MEMORY_CLIENT_ID); 775 776 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 777 protections, vmid, pasid, addr, 778 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 779 MEMORY_CLIENT_RW) ? 780 "write" : "read", block, mc_client, mc_id); 781 } 782 783 784 static const u32 mc_cg_registers[] = { 785 mmMC_HUB_MISC_HUB_CG, 786 mmMC_HUB_MISC_SIP_CG, 787 mmMC_HUB_MISC_VM_CG, 788 mmMC_XPB_CLK_GAT, 789 mmATC_MISC_CG, 790 mmMC_CITF_MISC_WR_CG, 791 mmMC_CITF_MISC_RD_CG, 792 mmMC_CITF_MISC_VM_CG, 793 mmVM_L2_CG, 794 }; 795 796 static const u32 mc_cg_ls_en[] = { 797 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 798 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 799 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 800 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 801 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 802 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 803 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 804 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 805 VM_L2_CG__MEM_LS_ENABLE_MASK, 806 }; 807 808 static const u32 mc_cg_en[] = { 809 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 810 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 811 MC_HUB_MISC_VM_CG__ENABLE_MASK, 812 MC_XPB_CLK_GAT__ENABLE_MASK, 813 ATC_MISC_CG__ENABLE_MASK, 814 MC_CITF_MISC_WR_CG__ENABLE_MASK, 815 MC_CITF_MISC_RD_CG__ENABLE_MASK, 816 MC_CITF_MISC_VM_CG__ENABLE_MASK, 817 VM_L2_CG__ENABLE_MASK, 818 }; 819 820 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 821 bool enable) 822 { 823 int i; 824 u32 orig, data; 825 826 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 827 orig = data = RREG32(mc_cg_registers[i]); 828 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 829 data |= mc_cg_ls_en[i]; 830 else 831 data &= ~mc_cg_ls_en[i]; 832 if (data != orig) 833 WREG32(mc_cg_registers[i], data); 834 } 835 } 836 837 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 838 bool enable) 839 { 840 int i; 841 u32 orig, data; 842 843 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 844 orig = data = RREG32(mc_cg_registers[i]); 845 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 846 data |= mc_cg_en[i]; 847 else 848 data &= ~mc_cg_en[i]; 849 if (data != orig) 850 WREG32(mc_cg_registers[i], data); 851 } 852 } 853 854 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 855 bool enable) 856 { 857 u32 orig, data; 858 859 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 860 861 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 862 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 863 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 864 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 865 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 866 } else { 867 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 868 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 869 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 870 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 871 } 872 873 if (orig != data) 874 WREG32_PCIE(ixPCIE_CNTL2, data); 875 } 876 877 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 878 bool enable) 879 { 880 u32 orig, data; 881 882 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 883 884 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 885 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 886 else 887 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 888 889 if (orig != data) 890 WREG32(mmHDP_HOST_PATH_CNTL, data); 891 } 892 893 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 894 bool enable) 895 { 896 u32 orig, data; 897 898 orig = data = RREG32(mmHDP_MEM_POWER_LS); 899 900 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 901 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 902 else 903 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 904 905 if (orig != data) 906 WREG32(mmHDP_MEM_POWER_LS, data); 907 } 908 909 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 910 { 911 switch (mc_seq_vram_type) { 912 case MC_SEQ_MISC0__MT__GDDR1: 913 return AMDGPU_VRAM_TYPE_GDDR1; 914 case MC_SEQ_MISC0__MT__DDR2: 915 return AMDGPU_VRAM_TYPE_DDR2; 916 case MC_SEQ_MISC0__MT__GDDR3: 917 return AMDGPU_VRAM_TYPE_GDDR3; 918 case MC_SEQ_MISC0__MT__GDDR4: 919 return AMDGPU_VRAM_TYPE_GDDR4; 920 case MC_SEQ_MISC0__MT__GDDR5: 921 return AMDGPU_VRAM_TYPE_GDDR5; 922 case MC_SEQ_MISC0__MT__HBM: 923 return AMDGPU_VRAM_TYPE_HBM; 924 case MC_SEQ_MISC0__MT__DDR3: 925 return AMDGPU_VRAM_TYPE_DDR3; 926 default: 927 return AMDGPU_VRAM_TYPE_UNKNOWN; 928 } 929 } 930 931 static int gmc_v7_0_early_init(struct amdgpu_ip_block *ip_block) 932 { 933 struct amdgpu_device *adev = ip_block->adev; 934 935 gmc_v7_0_set_gmc_funcs(adev); 936 gmc_v7_0_set_irq_funcs(adev); 937 938 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 939 adev->gmc.shared_aperture_end = 940 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 941 adev->gmc.private_aperture_start = 942 adev->gmc.shared_aperture_end + 1; 943 adev->gmc.private_aperture_end = 944 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 945 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 946 947 return 0; 948 } 949 950 static int gmc_v7_0_late_init(struct amdgpu_ip_block *ip_block) 951 { 952 struct amdgpu_device *adev = ip_block->adev; 953 954 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 955 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 956 else 957 return 0; 958 } 959 960 static unsigned int gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 961 { 962 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 963 unsigned int size; 964 965 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 966 size = AMDGPU_VBIOS_VGA_ALLOCATION; 967 } else { 968 u32 viewport = RREG32(mmVIEWPORT_SIZE); 969 970 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 971 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 972 4); 973 } 974 975 return size; 976 } 977 978 static int gmc_v7_0_sw_init(struct amdgpu_ip_block *ip_block) 979 { 980 int r; 981 struct amdgpu_device *adev = ip_block->adev; 982 983 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 984 985 if (adev->flags & AMD_IS_APU) { 986 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 987 } else { 988 u32 tmp = RREG32(mmMC_SEQ_MISC0); 989 990 tmp &= MC_SEQ_MISC0__MT__MASK; 991 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 992 } 993 994 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 995 if (r) 996 return r; 997 998 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 999 if (r) 1000 return r; 1001 1002 /* Adjust VM size here. 1003 * Currently set to 4GB ((1 << 20) 4k pages). 1004 * Max GPUVM size for cayman and SI is 40 bits. 1005 */ 1006 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1007 1008 /* Set the internal MC address mask 1009 * This is the max address of the GPU's 1010 * internal address space. 1011 */ 1012 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1013 1014 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1015 if (r) { 1016 pr_warn("No suitable DMA available\n"); 1017 return r; 1018 } 1019 adev->need_swiotlb = drm_need_swiotlb(40); 1020 1021 r = gmc_v7_0_init_microcode(adev); 1022 if (r) { 1023 DRM_ERROR("Failed to load mc firmware!\n"); 1024 return r; 1025 } 1026 1027 r = gmc_v7_0_mc_init(adev); 1028 if (r) 1029 return r; 1030 1031 /* Memory manager */ 1032 r = amdgpu_bo_init(adev); 1033 if (r) 1034 return r; 1035 1036 r = gmc_v7_0_gart_init(adev); 1037 if (r) 1038 return r; 1039 1040 /* 1041 * number of VMs 1042 * VMID 0 is reserved for System 1043 * amdgpu graphics/compute will use VMIDs 1-7 1044 * amdkfd will use VMIDs 8-15 1045 */ 1046 adev->vm_manager.first_kfd_vmid = 8; 1047 amdgpu_vm_manager_init(adev); 1048 1049 /* base offset of vram pages */ 1050 if (adev->flags & AMD_IS_APU) { 1051 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1052 1053 tmp <<= 22; 1054 adev->vm_manager.vram_base_offset = tmp; 1055 } else { 1056 adev->vm_manager.vram_base_offset = 0; 1057 } 1058 1059 adev->gmc.vm_fault_info = kmalloc_obj(struct kfd_vm_fault_info); 1060 if (!adev->gmc.vm_fault_info) 1061 return -ENOMEM; 1062 atomic_set_release(&adev->gmc.vm_fault_info_updated, 0); 1063 1064 return 0; 1065 } 1066 1067 static int gmc_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) 1068 { 1069 struct amdgpu_device *adev = ip_block->adev; 1070 1071 amdgpu_gem_force_release(adev); 1072 amdgpu_vm_manager_fini(adev); 1073 kfree(adev->gmc.vm_fault_info); 1074 amdgpu_gart_table_vram_free(adev); 1075 amdgpu_bo_fini(adev); 1076 amdgpu_ucode_release(&adev->gmc.fw); 1077 1078 return 0; 1079 } 1080 1081 static int gmc_v7_0_hw_init(struct amdgpu_ip_block *ip_block) 1082 { 1083 int r; 1084 struct amdgpu_device *adev = ip_block->adev; 1085 1086 gmc_v7_0_init_golden_registers(adev); 1087 1088 gmc_v7_0_mc_program(adev); 1089 1090 if (!(adev->flags & AMD_IS_APU)) { 1091 r = gmc_v7_0_mc_load_microcode(adev); 1092 if (r) { 1093 DRM_ERROR("Failed to load MC firmware!\n"); 1094 return r; 1095 } 1096 } 1097 1098 r = gmc_v7_0_gart_enable(adev); 1099 if (r) 1100 return r; 1101 1102 if (amdgpu_emu_mode == 1) 1103 return amdgpu_gmc_vram_checking(adev); 1104 1105 return 0; 1106 } 1107 1108 static int gmc_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) 1109 { 1110 struct amdgpu_device *adev = ip_block->adev; 1111 1112 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1113 gmc_v7_0_gart_disable(adev); 1114 1115 return 0; 1116 } 1117 1118 static int gmc_v7_0_suspend(struct amdgpu_ip_block *ip_block) 1119 { 1120 gmc_v7_0_hw_fini(ip_block); 1121 1122 return 0; 1123 } 1124 1125 static int gmc_v7_0_resume(struct amdgpu_ip_block *ip_block) 1126 { 1127 int r; 1128 1129 r = gmc_v7_0_hw_init(ip_block); 1130 if (r) 1131 return r; 1132 1133 amdgpu_vmid_reset_all(ip_block->adev); 1134 1135 return 0; 1136 } 1137 1138 static bool gmc_v7_0_is_idle(struct amdgpu_ip_block *ip_block) 1139 { 1140 struct amdgpu_device *adev = ip_block->adev; 1141 u32 tmp = RREG32(mmSRBM_STATUS); 1142 1143 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1144 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1145 return false; 1146 1147 return true; 1148 } 1149 1150 static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1151 { 1152 unsigned int i; 1153 struct amdgpu_device *adev = ip_block->adev; 1154 1155 for (i = 0; i < adev->usec_timeout; i++) { 1156 if (gmc_v7_0_is_idle(ip_block)) 1157 return 0; 1158 udelay(1); 1159 } 1160 return -ETIMEDOUT; 1161 1162 } 1163 1164 static int gmc_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) 1165 { 1166 struct amdgpu_device *adev = ip_block->adev; 1167 u32 srbm_soft_reset = 0; 1168 u32 tmp = RREG32(mmSRBM_STATUS); 1169 1170 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1171 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1172 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1173 1174 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1175 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1176 if (!(adev->flags & AMD_IS_APU)) 1177 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1178 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1179 } 1180 1181 if (srbm_soft_reset) { 1182 gmc_v7_0_mc_stop(adev); 1183 if (gmc_v7_0_wait_for_idle(ip_block)) 1184 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1185 1186 tmp = RREG32(mmSRBM_SOFT_RESET); 1187 tmp |= srbm_soft_reset; 1188 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1189 WREG32(mmSRBM_SOFT_RESET, tmp); 1190 tmp = RREG32(mmSRBM_SOFT_RESET); 1191 1192 udelay(50); 1193 1194 tmp &= ~srbm_soft_reset; 1195 WREG32(mmSRBM_SOFT_RESET, tmp); 1196 tmp = RREG32(mmSRBM_SOFT_RESET); 1197 1198 /* Wait a little for things to settle down */ 1199 udelay(50); 1200 1201 gmc_v7_0_mc_resume(adev); 1202 udelay(50); 1203 } 1204 1205 return 0; 1206 } 1207 1208 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1209 struct amdgpu_irq_src *src, 1210 unsigned int type, 1211 enum amdgpu_interrupt_state state) 1212 { 1213 u32 tmp; 1214 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1215 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1216 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1217 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1218 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1219 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1220 1221 switch (state) { 1222 case AMDGPU_IRQ_STATE_DISABLE: 1223 /* system context */ 1224 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1225 tmp &= ~bits; 1226 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1227 /* VMs */ 1228 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1229 tmp &= ~bits; 1230 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1231 break; 1232 case AMDGPU_IRQ_STATE_ENABLE: 1233 /* system context */ 1234 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1235 tmp |= bits; 1236 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1237 /* VMs */ 1238 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1239 tmp |= bits; 1240 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1241 break; 1242 default: 1243 break; 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1250 struct amdgpu_irq_src *source, 1251 struct amdgpu_iv_entry *entry) 1252 { 1253 u32 addr, status, mc_client, vmid; 1254 1255 /* Delegate to the soft IRQ handler ring */ 1256 if (adev->irq.ih_soft.enabled && entry->ih != &adev->irq.ih_soft) { 1257 amdgpu_irq_delegate(adev, entry, 4); 1258 return 1; 1259 } 1260 1261 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1262 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1263 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1264 /* reset addr and status */ 1265 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1266 1267 if (!addr && !status) 1268 return 0; 1269 1270 amdgpu_vm_update_fault_cache(adev, entry->pasid, 1271 ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); 1272 1273 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1274 gmc_v7_0_set_fault_enable_default(adev, false); 1275 1276 if (printk_ratelimit()) { 1277 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1278 entry->src_id, entry->src_data[0]); 1279 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1280 addr); 1281 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1282 status); 1283 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1284 entry->pasid); 1285 } 1286 1287 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1288 VMID); 1289 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1290 && !atomic_read_acquire(&adev->gmc.vm_fault_info_updated)) { 1291 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1292 u32 protections = REG_GET_FIELD(status, 1293 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1294 PROTECTIONS); 1295 1296 info->vmid = vmid; 1297 info->mc_id = REG_GET_FIELD(status, 1298 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1299 MEMORY_CLIENT_ID); 1300 info->status = status; 1301 info->page_addr = addr; 1302 info->prot_valid = protections & 0x7 ? true : false; 1303 info->prot_read = protections & 0x8 ? true : false; 1304 info->prot_write = protections & 0x10 ? true : false; 1305 info->prot_exec = protections & 0x20 ? true : false; 1306 atomic_set_release(&adev->gmc.vm_fault_info_updated, 1); 1307 } 1308 1309 return 0; 1310 } 1311 1312 static int gmc_v7_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1313 enum amd_clockgating_state state) 1314 { 1315 bool gate = false; 1316 struct amdgpu_device *adev = ip_block->adev; 1317 1318 if (state == AMD_CG_STATE_GATE) 1319 gate = true; 1320 1321 if (!(adev->flags & AMD_IS_APU)) { 1322 gmc_v7_0_enable_mc_mgcg(adev, gate); 1323 gmc_v7_0_enable_mc_ls(adev, gate); 1324 } 1325 gmc_v7_0_enable_bif_mgls(adev, gate); 1326 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1327 gmc_v7_0_enable_hdp_ls(adev, gate); 1328 1329 return 0; 1330 } 1331 1332 static int gmc_v7_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1333 enum amd_powergating_state state) 1334 { 1335 return 0; 1336 } 1337 1338 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1339 .name = "gmc_v7_0", 1340 .early_init = gmc_v7_0_early_init, 1341 .late_init = gmc_v7_0_late_init, 1342 .sw_init = gmc_v7_0_sw_init, 1343 .sw_fini = gmc_v7_0_sw_fini, 1344 .hw_init = gmc_v7_0_hw_init, 1345 .hw_fini = gmc_v7_0_hw_fini, 1346 .suspend = gmc_v7_0_suspend, 1347 .resume = gmc_v7_0_resume, 1348 .is_idle = gmc_v7_0_is_idle, 1349 .wait_for_idle = gmc_v7_0_wait_for_idle, 1350 .soft_reset = gmc_v7_0_soft_reset, 1351 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1352 .set_powergating_state = gmc_v7_0_set_powergating_state, 1353 }; 1354 1355 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1356 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1357 .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid, 1358 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1359 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1360 .set_prt = gmc_v7_0_set_prt, 1361 .get_vm_pde = gmc_v7_0_get_vm_pde, 1362 .get_vm_pte = gmc_v7_0_get_vm_pte, 1363 .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size, 1364 }; 1365 1366 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1367 .set = gmc_v7_0_vm_fault_interrupt_state, 1368 .process = gmc_v7_0_process_interrupt, 1369 }; 1370 1371 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1372 { 1373 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1374 } 1375 1376 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1377 { 1378 adev->gmc.vm_fault.num_types = 1; 1379 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1380 } 1381 1382 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = { 1383 .type = AMD_IP_BLOCK_TYPE_GMC, 1384 .major = 7, 1385 .minor = 0, 1386 .rev = 0, 1387 .funcs = &gmc_v7_0_ip_funcs, 1388 }; 1389 1390 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = { 1391 .type = AMD_IP_BLOCK_TYPE_GMC, 1392 .major = 7, 1393 .minor = 4, 1394 .rev = 0, 1395 .funcs = &gmc_v7_0_ip_funcs, 1396 }; 1397