1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "cikd.h" 31 #include "cik.h" 32 #include "gmc_v7_0.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_amdkfd.h" 35 #include "amdgpu_gem.h" 36 37 #include "bif/bif_4_1_d.h" 38 #include "bif/bif_4_1_sh_mask.h" 39 40 #include "gmc/gmc_7_1_d.h" 41 #include "gmc/gmc_7_1_sh_mask.h" 42 43 #include "oss/oss_2_0_d.h" 44 #include "oss/oss_2_0_sh_mask.h" 45 46 #include "dce/dce_8_0_d.h" 47 #include "dce/dce_8_0_sh_mask.h" 48 49 #include "amdgpu_atombios.h" 50 51 #include "ivsrcid/ivsrcid_vislands30.h" 52 53 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); 54 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int gmc_v7_0_wait_for_idle(void *handle); 56 57 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); 58 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); 59 MODULE_FIRMWARE("amdgpu/topaz_mc.bin"); 60 61 static const u32 golden_settings_iceland_a11[] = 62 { 63 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, 64 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 65 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 66 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff 67 }; 68 69 static const u32 iceland_mgcg_cgcg_init[] = 70 { 71 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 72 }; 73 74 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) 75 { 76 switch (adev->asic_type) { 77 case CHIP_TOPAZ: 78 amdgpu_device_program_register_sequence(adev, 79 iceland_mgcg_cgcg_init, 80 ARRAY_SIZE(iceland_mgcg_cgcg_init)); 81 amdgpu_device_program_register_sequence(adev, 82 golden_settings_iceland_a11, 83 ARRAY_SIZE(golden_settings_iceland_a11)); 84 break; 85 default: 86 break; 87 } 88 } 89 90 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev) 91 { 92 u32 blackout; 93 94 gmc_v7_0_wait_for_idle((void *)adev); 95 96 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 97 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 98 /* Block CPU access */ 99 WREG32(mmBIF_FB_EN, 0); 100 /* blackout the MC */ 101 blackout = REG_SET_FIELD(blackout, 102 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 103 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 104 } 105 /* wait for the MC to settle */ 106 udelay(100); 107 } 108 109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev) 110 { 111 u32 tmp; 112 113 /* unblackout the MC */ 114 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 115 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 116 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 117 /* allow CPU access */ 118 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 119 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 120 WREG32(mmBIF_FB_EN, tmp); 121 } 122 123 /** 124 * gmc_v7_0_init_microcode - load ucode images from disk 125 * 126 * @adev: amdgpu_device pointer 127 * 128 * Use the firmware interface to load the ucode images into 129 * the driver (not loaded into hw). 130 * Returns 0 on success, error on failure. 131 */ 132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) 133 { 134 const char *chip_name; 135 char fw_name[30]; 136 int err; 137 138 DRM_DEBUG("\n"); 139 140 switch (adev->asic_type) { 141 case CHIP_BONAIRE: 142 chip_name = "bonaire"; 143 break; 144 case CHIP_HAWAII: 145 chip_name = "hawaii"; 146 break; 147 case CHIP_TOPAZ: 148 chip_name = "topaz"; 149 break; 150 case CHIP_KAVERI: 151 case CHIP_KABINI: 152 case CHIP_MULLINS: 153 return 0; 154 default: BUG(); 155 } 156 157 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); 158 159 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); 160 if (err) 161 goto out; 162 err = amdgpu_ucode_validate(adev->gmc.fw); 163 164 out: 165 if (err) { 166 pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); 167 release_firmware(adev->gmc.fw); 168 adev->gmc.fw = NULL; 169 } 170 return err; 171 } 172 173 /** 174 * gmc_v7_0_mc_load_microcode - load MC ucode into the hw 175 * 176 * @adev: amdgpu_device pointer 177 * 178 * Load the GDDR MC ucode into the hw (CIK). 179 * Returns 0 on success, error on failure. 180 */ 181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) 182 { 183 const struct mc_firmware_header_v1_0 *hdr; 184 const __le32 *fw_data = NULL; 185 const __le32 *io_mc_regs = NULL; 186 u32 running; 187 int i, ucode_size, regs_size; 188 189 if (!adev->gmc.fw) 190 return -EINVAL; 191 192 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 193 amdgpu_ucode_print_mc_hdr(&hdr->header); 194 195 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 196 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 197 io_mc_regs = (const __le32 *) 198 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 199 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 200 fw_data = (const __le32 *) 201 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 202 203 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); 204 205 if (running == 0) { 206 /* reset the engine and set to writable */ 207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 209 210 /* load mc io regs */ 211 for (i = 0; i < regs_size; i++) { 212 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++)); 213 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++)); 214 } 215 /* load the MC ucode */ 216 for (i = 0; i < ucode_size; i++) 217 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++)); 218 219 /* put the engine back into the active state */ 220 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 221 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 222 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 223 224 /* wait for training to complete */ 225 for (i = 0; i < adev->usec_timeout; i++) { 226 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 227 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0)) 228 break; 229 udelay(1); 230 } 231 for (i = 0; i < adev->usec_timeout; i++) { 232 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL), 233 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1)) 234 break; 235 udelay(1); 236 } 237 } 238 239 return 0; 240 } 241 242 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, 243 struct amdgpu_gmc *mc) 244 { 245 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 246 base <<= 24; 247 248 amdgpu_gmc_vram_location(adev, mc, base); 249 amdgpu_gmc_gart_location(adev, mc); 250 } 251 252 /** 253 * gmc_v7_0_mc_program - program the GPU memory controller 254 * 255 * @adev: amdgpu_device pointer 256 * 257 * Set the location of vram, gart, and AGP in the GPU's 258 * physical address space (CIK). 259 */ 260 static void gmc_v7_0_mc_program(struct amdgpu_device *adev) 261 { 262 u32 tmp; 263 int i, j; 264 265 /* Initialize HDP */ 266 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 267 WREG32((0xb05 + j), 0x00000000); 268 WREG32((0xb06 + j), 0x00000000); 269 WREG32((0xb07 + j), 0x00000000); 270 WREG32((0xb08 + j), 0x00000000); 271 WREG32((0xb09 + j), 0x00000000); 272 } 273 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 274 275 if (gmc_v7_0_wait_for_idle((void *)adev)) { 276 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 277 } 278 if (adev->mode_info.num_crtc) { 279 /* Lockout access through VGA aperture*/ 280 tmp = RREG32(mmVGA_HDP_CONTROL); 281 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 282 WREG32(mmVGA_HDP_CONTROL, tmp); 283 284 /* disable VGA render */ 285 tmp = RREG32(mmVGA_RENDER_CONTROL); 286 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 287 WREG32(mmVGA_RENDER_CONTROL, tmp); 288 } 289 /* Update configuration */ 290 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 291 adev->gmc.vram_start >> 12); 292 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 293 adev->gmc.vram_end >> 12); 294 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 295 adev->mem_scratch.gpu_addr >> 12); 296 WREG32(mmMC_VM_AGP_BASE, 0); 297 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 298 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 299 if (gmc_v7_0_wait_for_idle((void *)adev)) { 300 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 301 } 302 303 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); 304 305 tmp = RREG32(mmHDP_MISC_CNTL); 306 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0); 307 WREG32(mmHDP_MISC_CNTL, tmp); 308 309 tmp = RREG32(mmHDP_HOST_PATH_CNTL); 310 WREG32(mmHDP_HOST_PATH_CNTL, tmp); 311 } 312 313 /** 314 * gmc_v7_0_mc_init - initialize the memory controller driver params 315 * 316 * @adev: amdgpu_device pointer 317 * 318 * Look up the amount of vram, vram width, and decide how to place 319 * vram and gart within the GPU's physical address space (CIK). 320 * Returns 0 for success. 321 */ 322 static int gmc_v7_0_mc_init(struct amdgpu_device *adev) 323 { 324 int r; 325 326 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); 327 if (!adev->gmc.vram_width) { 328 u32 tmp; 329 int chansize, numchan; 330 331 /* Get VRAM informations */ 332 tmp = RREG32(mmMC_ARB_RAMCFG); 333 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) { 334 chansize = 64; 335 } else { 336 chansize = 32; 337 } 338 tmp = RREG32(mmMC_SHARED_CHMAP); 339 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 340 case 0: 341 default: 342 numchan = 1; 343 break; 344 case 1: 345 numchan = 2; 346 break; 347 case 2: 348 numchan = 4; 349 break; 350 case 3: 351 numchan = 8; 352 break; 353 case 4: 354 numchan = 3; 355 break; 356 case 5: 357 numchan = 6; 358 break; 359 case 6: 360 numchan = 10; 361 break; 362 case 7: 363 numchan = 12; 364 break; 365 case 8: 366 numchan = 16; 367 break; 368 } 369 adev->gmc.vram_width = numchan * chansize; 370 } 371 /* size in MB on si */ 372 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 373 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 374 375 if (!(adev->flags & AMD_IS_APU)) { 376 r = amdgpu_device_resize_fb_bar(adev); 377 if (r) 378 return r; 379 } 380 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 381 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 382 383 #ifdef CONFIG_X86_64 384 if ((adev->flags & AMD_IS_APU) && 385 adev->gmc.real_vram_size > adev->gmc.aper_size && 386 !amdgpu_passthrough(adev)) { 387 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; 388 adev->gmc.aper_size = adev->gmc.real_vram_size; 389 } 390 #endif 391 392 adev->gmc.visible_vram_size = adev->gmc.aper_size; 393 394 /* set the gart size */ 395 if (amdgpu_gart_size == -1) { 396 switch (adev->asic_type) { 397 case CHIP_TOPAZ: /* no MM engines */ 398 default: 399 adev->gmc.gart_size = 256ULL << 20; 400 break; 401 #ifdef CONFIG_DRM_AMDGPU_CIK 402 case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ 403 case CHIP_HAWAII: /* UVD, VCE do not support GPUVM */ 404 case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ 405 case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ 406 case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ 407 adev->gmc.gart_size = 1024ULL << 20; 408 break; 409 #endif 410 } 411 } else { 412 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 413 } 414 415 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; 416 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); 417 418 return 0; 419 } 420 421 /** 422 * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid 423 * 424 * @adev: amdgpu_device pointer 425 * @pasid: pasid to be flush 426 * @flush_type: type of flush 427 * @all_hub: flush all hubs 428 * 429 * Flush the TLB for the requested pasid. 430 */ 431 static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 432 uint16_t pasid, uint32_t flush_type, 433 bool all_hub) 434 { 435 int vmid; 436 unsigned int tmp; 437 438 if (amdgpu_in_reset(adev)) 439 return -EIO; 440 441 for (vmid = 1; vmid < 16; vmid++) { 442 443 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 444 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 445 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 446 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 447 RREG32(mmVM_INVALIDATE_RESPONSE); 448 break; 449 } 450 } 451 452 return 0; 453 } 454 455 /* 456 * GART 457 * VMID 0 is the physical GPU addresses as used by the kernel. 458 * VMIDs 1-15 are used for userspace clients and are handled 459 * by the amdgpu vm/hsa code. 460 */ 461 462 /** 463 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback 464 * 465 * @adev: amdgpu_device pointer 466 * @vmid: vm instance to flush 467 * @vmhub: which hub to flush 468 * @flush_type: type of flush 469 * * 470 * Flush the TLB for the requested page table (CIK). 471 */ 472 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 473 uint32_t vmhub, uint32_t flush_type) 474 { 475 /* bits 0-15 are the VM contexts0-15 */ 476 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 477 } 478 479 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 480 unsigned vmid, uint64_t pd_addr) 481 { 482 uint32_t reg; 483 484 if (vmid < 8) 485 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 486 else 487 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8; 488 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 489 490 /* bits 0-15 are the VM contexts0-15 */ 491 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 492 493 return pd_addr; 494 } 495 496 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 497 unsigned pasid) 498 { 499 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); 500 } 501 502 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level, 503 uint64_t *addr, uint64_t *flags) 504 { 505 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 506 } 507 508 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev, 509 struct amdgpu_bo_va_mapping *mapping, 510 uint64_t *flags) 511 { 512 *flags &= ~AMDGPU_PTE_EXECUTABLE; 513 *flags &= ~AMDGPU_PTE_PRT; 514 } 515 516 /** 517 * gmc_v7_0_set_fault_enable_default - update VM fault handling 518 * 519 * @adev: amdgpu_device pointer 520 * @value: true redirects VM faults to the default page 521 */ 522 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, 523 bool value) 524 { 525 u32 tmp; 526 527 tmp = RREG32(mmVM_CONTEXT1_CNTL); 528 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 529 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 530 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 531 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 532 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 533 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 534 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 535 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 536 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 537 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 538 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 539 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 540 WREG32(mmVM_CONTEXT1_CNTL, tmp); 541 } 542 543 /** 544 * gmc_v7_0_set_prt - set PRT VM fault 545 * 546 * @adev: amdgpu_device pointer 547 * @enable: enable/disable VM fault handling for PRT 548 */ 549 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) 550 { 551 uint32_t tmp; 552 553 if (enable && !adev->gmc.prt_warning) { 554 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 555 adev->gmc.prt_warning = true; 556 } 557 558 tmp = RREG32(mmVM_PRT_CNTL); 559 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 560 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 561 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 562 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 563 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 564 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable); 565 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 566 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable); 567 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 568 L2_CACHE_STORE_INVALID_ENTRIES, enable); 569 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 570 L1_TLB_STORE_INVALID_ENTRIES, enable); 571 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 572 MASK_PDE0_FAULT, enable); 573 WREG32(mmVM_PRT_CNTL, tmp); 574 575 if (enable) { 576 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT; 577 uint32_t high = adev->vm_manager.max_pfn - 578 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT); 579 580 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 581 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 582 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 583 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 584 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 585 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 586 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 587 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 588 } else { 589 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 590 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 591 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 592 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 593 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 594 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 595 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 596 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 597 } 598 } 599 600 /** 601 * gmc_v7_0_gart_enable - gart enable 602 * 603 * @adev: amdgpu_device pointer 604 * 605 * This sets up the TLBs, programs the page tables for VMID0, 606 * sets up the hw for VMIDs 1-15 which are allocated on 607 * demand, and sets up the global locations for the LDS, GDS, 608 * and GPUVM for FSA64 clients (CIK). 609 * Returns 0 for success, errors for failure. 610 */ 611 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) 612 { 613 uint64_t table_addr; 614 u32 tmp, field; 615 int i; 616 617 if (adev->gart.bo == NULL) { 618 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 619 return -EINVAL; 620 } 621 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 622 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 623 624 /* Setup TLB control */ 625 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 626 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 627 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1); 628 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 629 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1); 630 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 631 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 632 /* Setup L2 cache */ 633 tmp = RREG32(mmVM_L2_CNTL); 634 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 635 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 636 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); 637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1); 638 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7); 639 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 640 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 641 WREG32(mmVM_L2_CNTL, tmp); 642 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 644 WREG32(mmVM_L2_CNTL2, tmp); 645 646 field = adev->vm_manager.fragment_size; 647 tmp = RREG32(mmVM_L2_CNTL3); 648 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1); 649 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); 650 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); 651 WREG32(mmVM_L2_CNTL3, tmp); 652 /* setup context0 */ 653 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 654 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 655 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 656 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 657 (u32)(adev->dummy_page_addr >> 12)); 658 WREG32(mmVM_CONTEXT0_CNTL2, 0); 659 tmp = RREG32(mmVM_CONTEXT0_CNTL); 660 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 661 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 662 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 663 WREG32(mmVM_CONTEXT0_CNTL, tmp); 664 665 WREG32(0x575, 0); 666 WREG32(0x576, 0); 667 WREG32(0x577, 0); 668 669 /* empty context1-15 */ 670 /* FIXME start with 4G, once using 2 level pt switch to full 671 * vm size space 672 */ 673 /* set vm size, must be a multiple of 4 */ 674 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 675 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 676 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 677 if (i < 8) 678 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 679 table_addr >> 12); 680 else 681 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 682 table_addr >> 12); 683 } 684 685 /* enable context1-15 */ 686 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 687 (u32)(adev->dummy_page_addr >> 12)); 688 WREG32(mmVM_CONTEXT1_CNTL2, 4); 689 tmp = RREG32(mmVM_CONTEXT1_CNTL); 690 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 691 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); 692 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, 693 adev->vm_manager.block_size - 9); 694 WREG32(mmVM_CONTEXT1_CNTL, tmp); 695 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 696 gmc_v7_0_set_fault_enable_default(adev, false); 697 else 698 gmc_v7_0_set_fault_enable_default(adev, true); 699 700 if (adev->asic_type == CHIP_KAVERI) { 701 tmp = RREG32(mmCHUB_CONTROL); 702 tmp &= ~BYPASS_VM; 703 WREG32(mmCHUB_CONTROL, tmp); 704 } 705 706 gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0); 707 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 708 (unsigned)(adev->gmc.gart_size >> 20), 709 (unsigned long long)table_addr); 710 return 0; 711 } 712 713 static int gmc_v7_0_gart_init(struct amdgpu_device *adev) 714 { 715 int r; 716 717 if (adev->gart.bo) { 718 WARN(1, "R600 PCIE GART already initialized\n"); 719 return 0; 720 } 721 /* Initialize common gart structure */ 722 r = amdgpu_gart_init(adev); 723 if (r) 724 return r; 725 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 726 adev->gart.gart_pte_flags = 0; 727 return amdgpu_gart_table_vram_alloc(adev); 728 } 729 730 /** 731 * gmc_v7_0_gart_disable - gart disable 732 * 733 * @adev: amdgpu_device pointer 734 * 735 * This disables all VM page table (CIK). 736 */ 737 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev) 738 { 739 u32 tmp; 740 741 /* Disable all tables */ 742 WREG32(mmVM_CONTEXT0_CNTL, 0); 743 WREG32(mmVM_CONTEXT1_CNTL, 0); 744 /* Setup TLB control */ 745 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL); 746 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 747 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0); 748 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0); 749 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp); 750 /* Setup L2 cache */ 751 tmp = RREG32(mmVM_L2_CNTL); 752 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 753 WREG32(mmVM_L2_CNTL, tmp); 754 WREG32(mmVM_L2_CNTL2, 0); 755 } 756 757 /** 758 * gmc_v7_0_vm_decode_fault - print human readable fault info 759 * 760 * @adev: amdgpu_device pointer 761 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value 762 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value 763 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value 764 * @pasid: debug logging only - no functional use 765 * 766 * Print human readable fault information (CIK). 767 */ 768 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status, 769 u32 addr, u32 mc_client, unsigned pasid) 770 { 771 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 772 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 773 PROTECTIONS); 774 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 775 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 776 u32 mc_id; 777 778 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 779 MEMORY_CLIENT_ID); 780 781 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 782 protections, vmid, pasid, addr, 783 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 784 MEMORY_CLIENT_RW) ? 785 "write" : "read", block, mc_client, mc_id); 786 } 787 788 789 static const u32 mc_cg_registers[] = { 790 mmMC_HUB_MISC_HUB_CG, 791 mmMC_HUB_MISC_SIP_CG, 792 mmMC_HUB_MISC_VM_CG, 793 mmMC_XPB_CLK_GAT, 794 mmATC_MISC_CG, 795 mmMC_CITF_MISC_WR_CG, 796 mmMC_CITF_MISC_RD_CG, 797 mmMC_CITF_MISC_VM_CG, 798 mmVM_L2_CG, 799 }; 800 801 static const u32 mc_cg_ls_en[] = { 802 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 803 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 804 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 805 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 806 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 807 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 808 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 809 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 810 VM_L2_CG__MEM_LS_ENABLE_MASK, 811 }; 812 813 static const u32 mc_cg_en[] = { 814 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 815 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 816 MC_HUB_MISC_VM_CG__ENABLE_MASK, 817 MC_XPB_CLK_GAT__ENABLE_MASK, 818 ATC_MISC_CG__ENABLE_MASK, 819 MC_CITF_MISC_WR_CG__ENABLE_MASK, 820 MC_CITF_MISC_RD_CG__ENABLE_MASK, 821 MC_CITF_MISC_VM_CG__ENABLE_MASK, 822 VM_L2_CG__ENABLE_MASK, 823 }; 824 825 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev, 826 bool enable) 827 { 828 int i; 829 u32 orig, data; 830 831 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 832 orig = data = RREG32(mc_cg_registers[i]); 833 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 834 data |= mc_cg_ls_en[i]; 835 else 836 data &= ~mc_cg_ls_en[i]; 837 if (data != orig) 838 WREG32(mc_cg_registers[i], data); 839 } 840 } 841 842 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev, 843 bool enable) 844 { 845 int i; 846 u32 orig, data; 847 848 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 849 orig = data = RREG32(mc_cg_registers[i]); 850 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 851 data |= mc_cg_en[i]; 852 else 853 data &= ~mc_cg_en[i]; 854 if (data != orig) 855 WREG32(mc_cg_registers[i], data); 856 } 857 } 858 859 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev, 860 bool enable) 861 { 862 u32 orig, data; 863 864 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 865 866 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 867 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 868 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 869 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 870 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 871 } else { 872 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 873 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 874 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 875 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 876 } 877 878 if (orig != data) 879 WREG32_PCIE(ixPCIE_CNTL2, data); 880 } 881 882 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev, 883 bool enable) 884 { 885 u32 orig, data; 886 887 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 888 889 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 890 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 891 else 892 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 893 894 if (orig != data) 895 WREG32(mmHDP_HOST_PATH_CNTL, data); 896 } 897 898 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev, 899 bool enable) 900 { 901 u32 orig, data; 902 903 orig = data = RREG32(mmHDP_MEM_POWER_LS); 904 905 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 906 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 907 else 908 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 909 910 if (orig != data) 911 WREG32(mmHDP_MEM_POWER_LS, data); 912 } 913 914 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) 915 { 916 switch (mc_seq_vram_type) { 917 case MC_SEQ_MISC0__MT__GDDR1: 918 return AMDGPU_VRAM_TYPE_GDDR1; 919 case MC_SEQ_MISC0__MT__DDR2: 920 return AMDGPU_VRAM_TYPE_DDR2; 921 case MC_SEQ_MISC0__MT__GDDR3: 922 return AMDGPU_VRAM_TYPE_GDDR3; 923 case MC_SEQ_MISC0__MT__GDDR4: 924 return AMDGPU_VRAM_TYPE_GDDR4; 925 case MC_SEQ_MISC0__MT__GDDR5: 926 return AMDGPU_VRAM_TYPE_GDDR5; 927 case MC_SEQ_MISC0__MT__HBM: 928 return AMDGPU_VRAM_TYPE_HBM; 929 case MC_SEQ_MISC0__MT__DDR3: 930 return AMDGPU_VRAM_TYPE_DDR3; 931 default: 932 return AMDGPU_VRAM_TYPE_UNKNOWN; 933 } 934 } 935 936 static int gmc_v7_0_early_init(void *handle) 937 { 938 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 939 940 gmc_v7_0_set_gmc_funcs(adev); 941 gmc_v7_0_set_irq_funcs(adev); 942 943 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 944 adev->gmc.shared_aperture_end = 945 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 946 adev->gmc.private_aperture_start = 947 adev->gmc.shared_aperture_end + 1; 948 adev->gmc.private_aperture_end = 949 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 950 951 return 0; 952 } 953 954 static int gmc_v7_0_late_init(void *handle) 955 { 956 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 957 958 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 959 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 960 else 961 return 0; 962 } 963 964 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) 965 { 966 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 967 unsigned size; 968 969 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 970 size = AMDGPU_VBIOS_VGA_ALLOCATION; 971 } else { 972 u32 viewport = RREG32(mmVIEWPORT_SIZE); 973 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 974 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 975 4); 976 } 977 978 return size; 979 } 980 981 static int gmc_v7_0_sw_init(void *handle) 982 { 983 int r; 984 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 985 986 adev->num_vmhubs = 1; 987 988 if (adev->flags & AMD_IS_APU) { 989 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 990 } else { 991 u32 tmp = RREG32(mmMC_SEQ_MISC0); 992 tmp &= MC_SEQ_MISC0__MT__MASK; 993 adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); 994 } 995 996 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); 997 if (r) 998 return r; 999 1000 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); 1001 if (r) 1002 return r; 1003 1004 /* Adjust VM size here. 1005 * Currently set to 4GB ((1 << 20) 4k pages). 1006 * Max GPUVM size for cayman and SI is 40 bits. 1007 */ 1008 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 1009 1010 /* Set the internal MC address mask 1011 * This is the max address of the GPU's 1012 * internal address space. 1013 */ 1014 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1015 1016 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 1017 if (r) { 1018 pr_warn("No suitable DMA available\n"); 1019 return r; 1020 } 1021 adev->need_swiotlb = drm_need_swiotlb(40); 1022 1023 r = gmc_v7_0_init_microcode(adev); 1024 if (r) { 1025 DRM_ERROR("Failed to load mc firmware!\n"); 1026 return r; 1027 } 1028 1029 r = gmc_v7_0_mc_init(adev); 1030 if (r) 1031 return r; 1032 1033 amdgpu_gmc_get_vbios_allocations(adev); 1034 1035 /* Memory manager */ 1036 r = amdgpu_bo_init(adev); 1037 if (r) 1038 return r; 1039 1040 r = gmc_v7_0_gart_init(adev); 1041 if (r) 1042 return r; 1043 1044 /* 1045 * number of VMs 1046 * VMID 0 is reserved for System 1047 * amdgpu graphics/compute will use VMIDs 1-7 1048 * amdkfd will use VMIDs 8-15 1049 */ 1050 adev->vm_manager.first_kfd_vmid = 8; 1051 amdgpu_vm_manager_init(adev); 1052 1053 /* base offset of vram pages */ 1054 if (adev->flags & AMD_IS_APU) { 1055 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 1056 1057 tmp <<= 22; 1058 adev->vm_manager.vram_base_offset = tmp; 1059 } else { 1060 adev->vm_manager.vram_base_offset = 0; 1061 } 1062 1063 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), 1064 GFP_KERNEL); 1065 if (!adev->gmc.vm_fault_info) 1066 return -ENOMEM; 1067 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 1068 1069 return 0; 1070 } 1071 1072 static int gmc_v7_0_sw_fini(void *handle) 1073 { 1074 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1075 1076 amdgpu_gem_force_release(adev); 1077 amdgpu_vm_manager_fini(adev); 1078 kfree(adev->gmc.vm_fault_info); 1079 amdgpu_gart_table_vram_free(adev); 1080 amdgpu_bo_fini(adev); 1081 release_firmware(adev->gmc.fw); 1082 adev->gmc.fw = NULL; 1083 1084 return 0; 1085 } 1086 1087 static int gmc_v7_0_hw_init(void *handle) 1088 { 1089 int r; 1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1091 1092 gmc_v7_0_init_golden_registers(adev); 1093 1094 gmc_v7_0_mc_program(adev); 1095 1096 if (!(adev->flags & AMD_IS_APU)) { 1097 r = gmc_v7_0_mc_load_microcode(adev); 1098 if (r) { 1099 DRM_ERROR("Failed to load MC firmware!\n"); 1100 return r; 1101 } 1102 } 1103 1104 r = gmc_v7_0_gart_enable(adev); 1105 if (r) 1106 return r; 1107 1108 if (amdgpu_emu_mode == 1) 1109 return amdgpu_gmc_vram_checking(adev); 1110 else 1111 return r; 1112 } 1113 1114 static int gmc_v7_0_hw_fini(void *handle) 1115 { 1116 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1117 1118 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1119 gmc_v7_0_gart_disable(adev); 1120 1121 return 0; 1122 } 1123 1124 static int gmc_v7_0_suspend(void *handle) 1125 { 1126 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1127 1128 gmc_v7_0_hw_fini(adev); 1129 1130 return 0; 1131 } 1132 1133 static int gmc_v7_0_resume(void *handle) 1134 { 1135 int r; 1136 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1137 1138 r = gmc_v7_0_hw_init(adev); 1139 if (r) 1140 return r; 1141 1142 amdgpu_vmid_reset_all(adev); 1143 1144 return 0; 1145 } 1146 1147 static bool gmc_v7_0_is_idle(void *handle) 1148 { 1149 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1150 u32 tmp = RREG32(mmSRBM_STATUS); 1151 1152 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1153 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 1154 return false; 1155 1156 return true; 1157 } 1158 1159 static int gmc_v7_0_wait_for_idle(void *handle) 1160 { 1161 unsigned i; 1162 u32 tmp; 1163 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1164 1165 for (i = 0; i < adev->usec_timeout; i++) { 1166 /* read MC_STATUS */ 1167 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 1168 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1169 SRBM_STATUS__MCC_BUSY_MASK | 1170 SRBM_STATUS__MCD_BUSY_MASK | 1171 SRBM_STATUS__VMC_BUSY_MASK); 1172 if (!tmp) 1173 return 0; 1174 udelay(1); 1175 } 1176 return -ETIMEDOUT; 1177 1178 } 1179 1180 static int gmc_v7_0_soft_reset(void *handle) 1181 { 1182 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1183 u32 srbm_soft_reset = 0; 1184 u32 tmp = RREG32(mmSRBM_STATUS); 1185 1186 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1187 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1188 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 1189 1190 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1191 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1192 if (!(adev->flags & AMD_IS_APU)) 1193 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1194 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1195 } 1196 1197 if (srbm_soft_reset) { 1198 gmc_v7_0_mc_stop(adev); 1199 if (gmc_v7_0_wait_for_idle((void *)adev)) { 1200 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1201 } 1202 1203 1204 tmp = RREG32(mmSRBM_SOFT_RESET); 1205 tmp |= srbm_soft_reset; 1206 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1207 WREG32(mmSRBM_SOFT_RESET, tmp); 1208 tmp = RREG32(mmSRBM_SOFT_RESET); 1209 1210 udelay(50); 1211 1212 tmp &= ~srbm_soft_reset; 1213 WREG32(mmSRBM_SOFT_RESET, tmp); 1214 tmp = RREG32(mmSRBM_SOFT_RESET); 1215 1216 /* Wait a little for things to settle down */ 1217 udelay(50); 1218 1219 gmc_v7_0_mc_resume(adev); 1220 udelay(50); 1221 } 1222 1223 return 0; 1224 } 1225 1226 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1227 struct amdgpu_irq_src *src, 1228 unsigned type, 1229 enum amdgpu_interrupt_state state) 1230 { 1231 u32 tmp; 1232 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1233 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1234 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1235 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1236 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1237 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1238 1239 switch (state) { 1240 case AMDGPU_IRQ_STATE_DISABLE: 1241 /* system context */ 1242 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1243 tmp &= ~bits; 1244 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1245 /* VMs */ 1246 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1247 tmp &= ~bits; 1248 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1249 break; 1250 case AMDGPU_IRQ_STATE_ENABLE: 1251 /* system context */ 1252 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1253 tmp |= bits; 1254 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1255 /* VMs */ 1256 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1257 tmp |= bits; 1258 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1259 break; 1260 default: 1261 break; 1262 } 1263 1264 return 0; 1265 } 1266 1267 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, 1268 struct amdgpu_irq_src *source, 1269 struct amdgpu_iv_entry *entry) 1270 { 1271 u32 addr, status, mc_client, vmid; 1272 1273 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1274 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1275 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); 1276 /* reset addr and status */ 1277 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1278 1279 if (!addr && !status) 1280 return 0; 1281 1282 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1283 gmc_v7_0_set_fault_enable_default(adev, false); 1284 1285 if (printk_ratelimit()) { 1286 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1287 entry->src_id, entry->src_data[0]); 1288 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1289 addr); 1290 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1291 status); 1292 gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client, 1293 entry->pasid); 1294 } 1295 1296 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1297 VMID); 1298 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid) 1299 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { 1300 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; 1301 u32 protections = REG_GET_FIELD(status, 1302 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1303 PROTECTIONS); 1304 1305 info->vmid = vmid; 1306 info->mc_id = REG_GET_FIELD(status, 1307 VM_CONTEXT1_PROTECTION_FAULT_STATUS, 1308 MEMORY_CLIENT_ID); 1309 info->status = status; 1310 info->page_addr = addr; 1311 info->prot_valid = protections & 0x7 ? true : false; 1312 info->prot_read = protections & 0x8 ? true : false; 1313 info->prot_write = protections & 0x10 ? true : false; 1314 info->prot_exec = protections & 0x20 ? true : false; 1315 mb(); 1316 atomic_set(&adev->gmc.vm_fault_info_updated, 1); 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int gmc_v7_0_set_clockgating_state(void *handle, 1323 enum amd_clockgating_state state) 1324 { 1325 bool gate = false; 1326 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1327 1328 if (state == AMD_CG_STATE_GATE) 1329 gate = true; 1330 1331 if (!(adev->flags & AMD_IS_APU)) { 1332 gmc_v7_0_enable_mc_mgcg(adev, gate); 1333 gmc_v7_0_enable_mc_ls(adev, gate); 1334 } 1335 gmc_v7_0_enable_bif_mgls(adev, gate); 1336 gmc_v7_0_enable_hdp_mgcg(adev, gate); 1337 gmc_v7_0_enable_hdp_ls(adev, gate); 1338 1339 return 0; 1340 } 1341 1342 static int gmc_v7_0_set_powergating_state(void *handle, 1343 enum amd_powergating_state state) 1344 { 1345 return 0; 1346 } 1347 1348 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { 1349 .name = "gmc_v7_0", 1350 .early_init = gmc_v7_0_early_init, 1351 .late_init = gmc_v7_0_late_init, 1352 .sw_init = gmc_v7_0_sw_init, 1353 .sw_fini = gmc_v7_0_sw_fini, 1354 .hw_init = gmc_v7_0_hw_init, 1355 .hw_fini = gmc_v7_0_hw_fini, 1356 .suspend = gmc_v7_0_suspend, 1357 .resume = gmc_v7_0_resume, 1358 .is_idle = gmc_v7_0_is_idle, 1359 .wait_for_idle = gmc_v7_0_wait_for_idle, 1360 .soft_reset = gmc_v7_0_soft_reset, 1361 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1362 .set_powergating_state = gmc_v7_0_set_powergating_state, 1363 }; 1364 1365 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { 1366 .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, 1367 .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid, 1368 .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb, 1369 .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping, 1370 .set_prt = gmc_v7_0_set_prt, 1371 .get_vm_pde = gmc_v7_0_get_vm_pde, 1372 .get_vm_pte = gmc_v7_0_get_vm_pte, 1373 .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size, 1374 }; 1375 1376 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { 1377 .set = gmc_v7_0_vm_fault_interrupt_state, 1378 .process = gmc_v7_0_process_interrupt, 1379 }; 1380 1381 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) 1382 { 1383 adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; 1384 } 1385 1386 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1387 { 1388 adev->gmc.vm_fault.num_types = 1; 1389 adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; 1390 } 1391 1392 const struct amdgpu_ip_block_version gmc_v7_0_ip_block = 1393 { 1394 .type = AMD_IP_BLOCK_TYPE_GMC, 1395 .major = 7, 1396 .minor = 0, 1397 .rev = 0, 1398 .funcs = &gmc_v7_0_ip_funcs, 1399 }; 1400 1401 const struct amdgpu_ip_block_version gmc_v7_4_ip_block = 1402 { 1403 .type = AMD_IP_BLOCK_TYPE_GMC, 1404 .major = 7, 1405 .minor = 4, 1406 .rev = 0, 1407 .funcs = &gmc_v7_0_ip_funcs, 1408 }; 1409