1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include "drmP.h" 25 #include "amdgpu.h" 26 #include "gmc_v6_0.h" 27 #include "amdgpu_ucode.h" 28 29 #include "bif/bif_3_0_d.h" 30 #include "bif/bif_3_0_sh_mask.h" 31 #include "oss/oss_1_0_d.h" 32 #include "oss/oss_1_0_sh_mask.h" 33 #include "gmc/gmc_6_0_d.h" 34 #include "gmc/gmc_6_0_sh_mask.h" 35 #include "dce/dce_6_0_d.h" 36 #include "dce/dce_6_0_sh_mask.h" 37 #include "si_enums.h" 38 39 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev); 40 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); 41 static int gmc_v6_0_wait_for_idle(void *handle); 42 43 MODULE_FIRMWARE("radeon/tahiti_mc.bin"); 44 MODULE_FIRMWARE("radeon/pitcairn_mc.bin"); 45 MODULE_FIRMWARE("radeon/verde_mc.bin"); 46 MODULE_FIRMWARE("radeon/oland_mc.bin"); 47 MODULE_FIRMWARE("radeon/si58_mc.bin"); 48 49 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 50 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 51 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 52 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 53 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 54 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 55 #define MC_SEQ_MISC0__MT__HBM 0x60000000 56 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 57 58 59 static const u32 crtc_offsets[6] = 60 { 61 SI_CRTC0_REGISTER_OFFSET, 62 SI_CRTC1_REGISTER_OFFSET, 63 SI_CRTC2_REGISTER_OFFSET, 64 SI_CRTC3_REGISTER_OFFSET, 65 SI_CRTC4_REGISTER_OFFSET, 66 SI_CRTC5_REGISTER_OFFSET 67 }; 68 69 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev, 70 struct amdgpu_mode_mc_save *save) 71 { 72 u32 blackout; 73 74 if (adev->mode_info.num_crtc) 75 amdgpu_display_stop_mc_access(adev, save); 76 77 gmc_v6_0_wait_for_idle((void *)adev); 78 79 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 80 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 81 /* Block CPU access */ 82 WREG32(mmBIF_FB_EN, 0); 83 /* blackout the MC */ 84 blackout = REG_SET_FIELD(blackout, 85 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 86 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 87 } 88 /* wait for the MC to settle */ 89 udelay(100); 90 91 } 92 93 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev, 94 struct amdgpu_mode_mc_save *save) 95 { 96 u32 tmp; 97 98 /* unblackout the MC */ 99 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 100 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 101 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 102 /* allow CPU access */ 103 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 104 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 105 WREG32(mmBIF_FB_EN, tmp); 106 107 if (adev->mode_info.num_crtc) 108 amdgpu_display_resume_mc_access(adev, save); 109 110 } 111 112 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) 113 { 114 const char *chip_name; 115 char fw_name[30]; 116 int err; 117 bool is_58_fw = false; 118 119 DRM_DEBUG("\n"); 120 121 switch (adev->asic_type) { 122 case CHIP_TAHITI: 123 chip_name = "tahiti"; 124 break; 125 case CHIP_PITCAIRN: 126 chip_name = "pitcairn"; 127 break; 128 case CHIP_VERDE: 129 chip_name = "verde"; 130 break; 131 case CHIP_OLAND: 132 chip_name = "oland"; 133 break; 134 case CHIP_HAINAN: 135 chip_name = "hainan"; 136 break; 137 default: BUG(); 138 } 139 140 /* this memory configuration requires special firmware */ 141 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) 142 is_58_fw = true; 143 144 if (is_58_fw) 145 snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin"); 146 else 147 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); 148 err = request_firmware(&adev->mc.fw, fw_name, adev->dev); 149 if (err) 150 goto out; 151 152 err = amdgpu_ucode_validate(adev->mc.fw); 153 154 out: 155 if (err) { 156 dev_err(adev->dev, 157 "si_mc: Failed to load firmware \"%s\"\n", 158 fw_name); 159 release_firmware(adev->mc.fw); 160 adev->mc.fw = NULL; 161 } 162 return err; 163 } 164 165 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) 166 { 167 const __le32 *new_fw_data = NULL; 168 u32 running; 169 const __le32 *new_io_mc_regs = NULL; 170 int i, regs_size, ucode_size; 171 const struct mc_firmware_header_v1_0 *hdr; 172 173 if (!adev->mc.fw) 174 return -EINVAL; 175 176 hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; 177 178 amdgpu_ucode_print_mc_hdr(&hdr->header); 179 180 adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); 181 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 182 new_io_mc_regs = (const __le32 *) 183 (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 184 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 185 new_fw_data = (const __le32 *) 186 (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 187 188 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; 189 190 if (running == 0) { 191 192 /* reset the engine and set to writable */ 193 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 194 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 195 196 /* load mc io regs */ 197 for (i = 0; i < regs_size; i++) { 198 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); 199 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); 200 } 201 /* load the MC ucode */ 202 for (i = 0; i < ucode_size; i++) { 203 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); 204 } 205 206 /* put the engine back into the active state */ 207 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 208 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 209 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 210 211 /* wait for training to complete */ 212 for (i = 0; i < adev->usec_timeout; i++) { 213 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) 214 break; 215 udelay(1); 216 } 217 for (i = 0; i < adev->usec_timeout; i++) { 218 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) 219 break; 220 udelay(1); 221 } 222 223 } 224 225 return 0; 226 } 227 228 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, 229 struct amdgpu_mc *mc) 230 { 231 if (mc->mc_vram_size > 0xFFC0000000ULL) { 232 dev_warn(adev->dev, "limiting VRAM\n"); 233 mc->real_vram_size = 0xFFC0000000ULL; 234 mc->mc_vram_size = 0xFFC0000000ULL; 235 } 236 amdgpu_vram_location(adev, &adev->mc, 0); 237 adev->mc.gtt_base_align = 0; 238 amdgpu_gtt_location(adev, mc); 239 } 240 241 static void gmc_v6_0_mc_program(struct amdgpu_device *adev) 242 { 243 struct amdgpu_mode_mc_save save; 244 u32 tmp; 245 int i, j; 246 247 /* Initialize HDP */ 248 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 249 WREG32((0xb05 + j), 0x00000000); 250 WREG32((0xb06 + j), 0x00000000); 251 WREG32((0xb07 + j), 0x00000000); 252 WREG32((0xb08 + j), 0x00000000); 253 WREG32((0xb09 + j), 0x00000000); 254 } 255 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 256 257 if (adev->mode_info.num_crtc) 258 amdgpu_display_set_vga_render_state(adev, false); 259 260 gmc_v6_0_mc_stop(adev, &save); 261 262 if (gmc_v6_0_wait_for_idle((void *)adev)) { 263 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 264 } 265 266 WREG32(mmVGA_HDP_CONTROL, VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK); 267 /* Update configuration */ 268 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 269 adev->mc.vram_start >> 12); 270 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 271 adev->mc.vram_end >> 12); 272 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 273 adev->vram_scratch.gpu_addr >> 12); 274 tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; 275 tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); 276 WREG32(mmMC_VM_FB_LOCATION, tmp); 277 /* XXX double check these! */ 278 WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); 279 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 280 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); 281 WREG32(mmMC_VM_AGP_BASE, 0); 282 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF); 283 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF); 284 285 if (gmc_v6_0_wait_for_idle((void *)adev)) { 286 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 287 } 288 gmc_v6_0_mc_resume(adev, &save); 289 } 290 291 static int gmc_v6_0_mc_init(struct amdgpu_device *adev) 292 { 293 294 u32 tmp; 295 int chansize, numchan; 296 297 tmp = RREG32(mmMC_ARB_RAMCFG); 298 if (tmp & (1 << 11)) { 299 chansize = 16; 300 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) { 301 chansize = 64; 302 } else { 303 chansize = 32; 304 } 305 tmp = RREG32(mmMC_SHARED_CHMAP); 306 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 307 case 0: 308 default: 309 numchan = 1; 310 break; 311 case 1: 312 numchan = 2; 313 break; 314 case 2: 315 numchan = 4; 316 break; 317 case 3: 318 numchan = 8; 319 break; 320 case 4: 321 numchan = 3; 322 break; 323 case 5: 324 numchan = 6; 325 break; 326 case 6: 327 numchan = 10; 328 break; 329 case 7: 330 numchan = 12; 331 break; 332 case 8: 333 numchan = 16; 334 break; 335 } 336 adev->mc.vram_width = numchan * chansize; 337 /* Could aper size report 0 ? */ 338 adev->mc.aper_base = pci_resource_start(adev->pdev, 0); 339 adev->mc.aper_size = pci_resource_len(adev->pdev, 0); 340 /* size in MB on si */ 341 adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 342 adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 343 adev->mc.visible_vram_size = adev->mc.aper_size; 344 345 /* unless the user had overridden it, set the gart 346 * size equal to the 1024 or vram, whichever is larger. 347 */ 348 if (amdgpu_gart_size == -1) 349 adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size); 350 else 351 adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20; 352 353 gmc_v6_0_vram_gtt_location(adev, &adev->mc); 354 355 return 0; 356 } 357 358 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, 359 uint32_t vmid) 360 { 361 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); 362 363 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 364 } 365 366 static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, 367 void *cpu_pt_addr, 368 uint32_t gpu_page_idx, 369 uint64_t addr, 370 uint32_t flags) 371 { 372 void __iomem *ptr = (void *)cpu_pt_addr; 373 uint64_t value; 374 375 value = addr & 0xFFFFFFFFFFFFF000ULL; 376 value |= flags; 377 writeq(value, ptr + (gpu_page_idx * 8)); 378 379 return 0; 380 } 381 382 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, 383 bool value) 384 { 385 u32 tmp; 386 387 tmp = RREG32(mmVM_CONTEXT1_CNTL); 388 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 389 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 390 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 391 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 392 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 393 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 394 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 395 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 396 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 397 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 398 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 399 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 400 WREG32(mmVM_CONTEXT1_CNTL, tmp); 401 } 402 403 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 404 { 405 int r, i; 406 407 if (adev->gart.robj == NULL) { 408 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 409 return -EINVAL; 410 } 411 r = amdgpu_gart_table_vram_pin(adev); 412 if (r) 413 return r; 414 /* Setup TLB control */ 415 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 416 (0xA << 7) | 417 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | 418 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | 419 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 420 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | 421 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 422 /* Setup L2 cache */ 423 WREG32(mmVM_L2_CNTL, 424 VM_L2_CNTL__ENABLE_L2_CACHE_MASK | 425 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | 426 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 427 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 428 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 429 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 430 WREG32(mmVM_L2_CNTL2, 431 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | 432 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); 433 WREG32(mmVM_L2_CNTL3, 434 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 435 (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) | 436 (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 437 /* setup context0 */ 438 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gtt_start >> 12); 439 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gtt_end >> 12); 440 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); 441 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 442 (u32)(adev->dummy_page.addr >> 12)); 443 WREG32(mmVM_CONTEXT0_CNTL2, 0); 444 WREG32(mmVM_CONTEXT0_CNTL, 445 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | 446 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 447 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); 448 449 WREG32(0x575, 0); 450 WREG32(0x576, 0); 451 WREG32(0x577, 0); 452 453 /* empty context1-15 */ 454 /* set vm size, must be a multiple of 4 */ 455 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 456 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 457 /* Assign the pt base to something valid for now; the pts used for 458 * the VMs are determined by the application and setup and assigned 459 * on the fly in the vm part of radeon_gart.c 460 */ 461 for (i = 1; i < 16; i++) { 462 if (i < 8) 463 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 464 adev->gart.table_addr >> 12); 465 else 466 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 467 adev->gart.table_addr >> 12); 468 } 469 470 /* enable context1-15 */ 471 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 472 (u32)(adev->dummy_page.addr >> 12)); 473 WREG32(mmVM_CONTEXT1_CNTL2, 4); 474 WREG32(mmVM_CONTEXT1_CNTL, 475 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | 476 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 477 ((amdgpu_vm_block_size - 9) << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); 478 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 479 gmc_v6_0_set_fault_enable_default(adev, false); 480 else 481 gmc_v6_0_set_fault_enable_default(adev, true); 482 483 gmc_v6_0_gart_flush_gpu_tlb(adev, 0); 484 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 485 (unsigned)(adev->mc.gtt_size >> 20), 486 (unsigned long long)adev->gart.table_addr); 487 adev->gart.ready = true; 488 return 0; 489 } 490 491 static int gmc_v6_0_gart_init(struct amdgpu_device *adev) 492 { 493 int r; 494 495 if (adev->gart.robj) { 496 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); 497 return 0; 498 } 499 r = amdgpu_gart_init(adev); 500 if (r) 501 return r; 502 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 503 return amdgpu_gart_table_vram_alloc(adev); 504 } 505 506 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) 507 { 508 /*unsigned i; 509 510 for (i = 1; i < 16; ++i) { 511 uint32_t reg; 512 if (i < 8) 513 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ; 514 else 515 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8); 516 adev->vm_manager.saved_table_addr[i] = RREG32(reg); 517 }*/ 518 519 /* Disable all tables */ 520 WREG32(mmVM_CONTEXT0_CNTL, 0); 521 WREG32(mmVM_CONTEXT1_CNTL, 0); 522 /* Setup TLB control */ 523 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 524 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 525 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 526 /* Setup L2 cache */ 527 WREG32(mmVM_L2_CNTL, 528 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 529 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 530 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 531 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 532 WREG32(mmVM_L2_CNTL2, 0); 533 WREG32(mmVM_L2_CNTL3, 534 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 535 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 536 amdgpu_gart_table_vram_unpin(adev); 537 } 538 539 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev) 540 { 541 amdgpu_gart_table_vram_free(adev); 542 amdgpu_gart_fini(adev); 543 } 544 545 static int gmc_v6_0_vm_init(struct amdgpu_device *adev) 546 { 547 /* 548 * number of VMs 549 * VMID 0 is reserved for System 550 * amdgpu graphics/compute will use VMIDs 1-7 551 * amdkfd will use VMIDs 8-15 552 */ 553 adev->vm_manager.num_ids = AMDGPU_NUM_OF_VMIDS; 554 amdgpu_vm_manager_init(adev); 555 556 /* base offset of vram pages */ 557 if (adev->flags & AMD_IS_APU) { 558 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 559 tmp <<= 22; 560 adev->vm_manager.vram_base_offset = tmp; 561 } else 562 adev->vm_manager.vram_base_offset = 0; 563 564 return 0; 565 } 566 567 static void gmc_v6_0_vm_fini(struct amdgpu_device *adev) 568 { 569 } 570 571 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, 572 u32 status, u32 addr, u32 mc_client) 573 { 574 u32 mc_id; 575 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 576 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 577 PROTECTIONS); 578 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff, 579 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 }; 580 581 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 582 MEMORY_CLIENT_ID); 583 584 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n", 585 protections, vmid, addr, 586 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 587 MEMORY_CLIENT_RW) ? 588 "write" : "read", block, mc_client, mc_id); 589 } 590 591 /* 592 static const u32 mc_cg_registers[] = { 593 MC_HUB_MISC_HUB_CG, 594 MC_HUB_MISC_SIP_CG, 595 MC_HUB_MISC_VM_CG, 596 MC_XPB_CLK_GAT, 597 ATC_MISC_CG, 598 MC_CITF_MISC_WR_CG, 599 MC_CITF_MISC_RD_CG, 600 MC_CITF_MISC_VM_CG, 601 VM_L2_CG, 602 }; 603 604 static const u32 mc_cg_ls_en[] = { 605 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 606 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 607 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 608 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 609 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 610 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 611 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 612 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 613 VM_L2_CG__MEM_LS_ENABLE_MASK, 614 }; 615 616 static const u32 mc_cg_en[] = { 617 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 618 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 619 MC_HUB_MISC_VM_CG__ENABLE_MASK, 620 MC_XPB_CLK_GAT__ENABLE_MASK, 621 ATC_MISC_CG__ENABLE_MASK, 622 MC_CITF_MISC_WR_CG__ENABLE_MASK, 623 MC_CITF_MISC_RD_CG__ENABLE_MASK, 624 MC_CITF_MISC_VM_CG__ENABLE_MASK, 625 VM_L2_CG__ENABLE_MASK, 626 }; 627 628 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev, 629 bool enable) 630 { 631 int i; 632 u32 orig, data; 633 634 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 635 orig = data = RREG32(mc_cg_registers[i]); 636 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS)) 637 data |= mc_cg_ls_en[i]; 638 else 639 data &= ~mc_cg_ls_en[i]; 640 if (data != orig) 641 WREG32(mc_cg_registers[i], data); 642 } 643 } 644 645 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev, 646 bool enable) 647 { 648 int i; 649 u32 orig, data; 650 651 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 652 orig = data = RREG32(mc_cg_registers[i]); 653 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG)) 654 data |= mc_cg_en[i]; 655 else 656 data &= ~mc_cg_en[i]; 657 if (data != orig) 658 WREG32(mc_cg_registers[i], data); 659 } 660 } 661 662 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev, 663 bool enable) 664 { 665 u32 orig, data; 666 667 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 668 669 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) { 670 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 671 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 672 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 673 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 674 } else { 675 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 676 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 677 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 678 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 679 } 680 681 if (orig != data) 682 WREG32_PCIE(ixPCIE_CNTL2, data); 683 } 684 685 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, 686 bool enable) 687 { 688 u32 orig, data; 689 690 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 691 692 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG)) 693 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 694 else 695 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 696 697 if (orig != data) 698 WREG32(mmHDP_HOST_PATH_CNTL, data); 699 } 700 701 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, 702 bool enable) 703 { 704 u32 orig, data; 705 706 orig = data = RREG32(mmHDP_MEM_POWER_LS); 707 708 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS)) 709 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 710 else 711 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 712 713 if (orig != data) 714 WREG32(mmHDP_MEM_POWER_LS, data); 715 } 716 */ 717 718 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) 719 { 720 switch (mc_seq_vram_type) { 721 case MC_SEQ_MISC0__MT__GDDR1: 722 return AMDGPU_VRAM_TYPE_GDDR1; 723 case MC_SEQ_MISC0__MT__DDR2: 724 return AMDGPU_VRAM_TYPE_DDR2; 725 case MC_SEQ_MISC0__MT__GDDR3: 726 return AMDGPU_VRAM_TYPE_GDDR3; 727 case MC_SEQ_MISC0__MT__GDDR4: 728 return AMDGPU_VRAM_TYPE_GDDR4; 729 case MC_SEQ_MISC0__MT__GDDR5: 730 return AMDGPU_VRAM_TYPE_GDDR5; 731 case MC_SEQ_MISC0__MT__DDR3: 732 return AMDGPU_VRAM_TYPE_DDR3; 733 default: 734 return AMDGPU_VRAM_TYPE_UNKNOWN; 735 } 736 } 737 738 static int gmc_v6_0_early_init(void *handle) 739 { 740 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 741 742 gmc_v6_0_set_gart_funcs(adev); 743 gmc_v6_0_set_irq_funcs(adev); 744 745 if (adev->flags & AMD_IS_APU) { 746 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 747 } else { 748 u32 tmp = RREG32(mmMC_SEQ_MISC0); 749 tmp &= MC_SEQ_MISC0__MT__MASK; 750 adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); 751 } 752 753 return 0; 754 } 755 756 static int gmc_v6_0_late_init(void *handle) 757 { 758 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 759 760 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 761 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 762 else 763 return 0; 764 } 765 766 static int gmc_v6_0_sw_init(void *handle) 767 { 768 int r; 769 int dma_bits; 770 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 771 772 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); 773 if (r) 774 return r; 775 776 r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault); 777 if (r) 778 return r; 779 780 adev->vm_manager.max_pfn = amdgpu_vm_size << 18; 781 782 adev->mc.mc_mask = 0xffffffffffULL; 783 784 adev->need_dma32 = false; 785 dma_bits = adev->need_dma32 ? 32 : 40; 786 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 787 if (r) { 788 adev->need_dma32 = true; 789 dma_bits = 32; 790 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 791 } 792 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits)); 793 if (r) { 794 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32)); 795 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n"); 796 } 797 798 r = gmc_v6_0_init_microcode(adev); 799 if (r) { 800 dev_err(adev->dev, "Failed to load mc firmware!\n"); 801 return r; 802 } 803 804 r = gmc_v6_0_mc_init(adev); 805 if (r) 806 return r; 807 808 r = amdgpu_bo_init(adev); 809 if (r) 810 return r; 811 812 r = gmc_v6_0_gart_init(adev); 813 if (r) 814 return r; 815 816 if (!adev->vm_manager.enabled) { 817 r = gmc_v6_0_vm_init(adev); 818 if (r) { 819 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 820 return r; 821 } 822 adev->vm_manager.enabled = true; 823 } 824 825 return r; 826 } 827 828 static int gmc_v6_0_sw_fini(void *handle) 829 { 830 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 831 832 if (adev->vm_manager.enabled) { 833 gmc_v6_0_vm_fini(adev); 834 adev->vm_manager.enabled = false; 835 } 836 gmc_v6_0_gart_fini(adev); 837 amdgpu_gem_force_release(adev); 838 amdgpu_bo_fini(adev); 839 840 return 0; 841 } 842 843 static int gmc_v6_0_hw_init(void *handle) 844 { 845 int r; 846 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 847 848 gmc_v6_0_mc_program(adev); 849 850 if (!(adev->flags & AMD_IS_APU)) { 851 r = gmc_v6_0_mc_load_microcode(adev); 852 if (r) { 853 dev_err(adev->dev, "Failed to load MC firmware!\n"); 854 return r; 855 } 856 } 857 858 r = gmc_v6_0_gart_enable(adev); 859 if (r) 860 return r; 861 862 return r; 863 } 864 865 static int gmc_v6_0_hw_fini(void *handle) 866 { 867 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 868 869 amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); 870 gmc_v6_0_gart_disable(adev); 871 872 return 0; 873 } 874 875 static int gmc_v6_0_suspend(void *handle) 876 { 877 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 878 879 if (adev->vm_manager.enabled) { 880 gmc_v6_0_vm_fini(adev); 881 adev->vm_manager.enabled = false; 882 } 883 gmc_v6_0_hw_fini(adev); 884 885 return 0; 886 } 887 888 static int gmc_v6_0_resume(void *handle) 889 { 890 int r; 891 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 892 893 r = gmc_v6_0_hw_init(adev); 894 if (r) 895 return r; 896 897 if (!adev->vm_manager.enabled) { 898 r = gmc_v6_0_vm_init(adev); 899 if (r) { 900 dev_err(adev->dev, "vm manager initialization failed (%d).\n", r); 901 return r; 902 } 903 adev->vm_manager.enabled = true; 904 } 905 906 return r; 907 } 908 909 static bool gmc_v6_0_is_idle(void *handle) 910 { 911 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 912 u32 tmp = RREG32(mmSRBM_STATUS); 913 914 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 915 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 916 return false; 917 918 return true; 919 } 920 921 static int gmc_v6_0_wait_for_idle(void *handle) 922 { 923 unsigned i; 924 u32 tmp; 925 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 926 927 for (i = 0; i < adev->usec_timeout; i++) { 928 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK | 929 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 930 SRBM_STATUS__MCC_BUSY_MASK | 931 SRBM_STATUS__MCD_BUSY_MASK | 932 SRBM_STATUS__VMC_BUSY_MASK); 933 if (!tmp) 934 return 0; 935 udelay(1); 936 } 937 return -ETIMEDOUT; 938 939 } 940 941 static int gmc_v6_0_soft_reset(void *handle) 942 { 943 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 944 struct amdgpu_mode_mc_save save; 945 u32 srbm_soft_reset = 0; 946 u32 tmp = RREG32(mmSRBM_STATUS); 947 948 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 949 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 950 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 951 952 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 953 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 954 if (!(adev->flags & AMD_IS_APU)) 955 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 956 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 957 } 958 959 if (srbm_soft_reset) { 960 gmc_v6_0_mc_stop(adev, &save); 961 if (gmc_v6_0_wait_for_idle(adev)) { 962 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 963 } 964 965 966 tmp = RREG32(mmSRBM_SOFT_RESET); 967 tmp |= srbm_soft_reset; 968 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 969 WREG32(mmSRBM_SOFT_RESET, tmp); 970 tmp = RREG32(mmSRBM_SOFT_RESET); 971 972 udelay(50); 973 974 tmp &= ~srbm_soft_reset; 975 WREG32(mmSRBM_SOFT_RESET, tmp); 976 tmp = RREG32(mmSRBM_SOFT_RESET); 977 978 udelay(50); 979 980 gmc_v6_0_mc_resume(adev, &save); 981 udelay(50); 982 } 983 984 return 0; 985 } 986 987 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 988 struct amdgpu_irq_src *src, 989 unsigned type, 990 enum amdgpu_interrupt_state state) 991 { 992 u32 tmp; 993 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 994 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 995 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 996 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 997 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 998 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 999 1000 switch (state) { 1001 case AMDGPU_IRQ_STATE_DISABLE: 1002 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1003 tmp &= ~bits; 1004 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1005 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1006 tmp &= ~bits; 1007 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1008 break; 1009 case AMDGPU_IRQ_STATE_ENABLE: 1010 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1011 tmp |= bits; 1012 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1013 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1014 tmp |= bits; 1015 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1016 break; 1017 default: 1018 break; 1019 } 1020 1021 return 0; 1022 } 1023 1024 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, 1025 struct amdgpu_irq_src *source, 1026 struct amdgpu_iv_entry *entry) 1027 { 1028 u32 addr, status; 1029 1030 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1031 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1032 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1033 1034 if (!addr && !status) 1035 return 0; 1036 1037 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1038 gmc_v6_0_set_fault_enable_default(adev, false); 1039 1040 if (printk_ratelimit()) { 1041 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1042 entry->src_id, entry->src_data); 1043 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1044 addr); 1045 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1046 status); 1047 gmc_v6_0_vm_decode_fault(adev, status, addr, 0); 1048 } 1049 1050 return 0; 1051 } 1052 1053 static int gmc_v6_0_set_clockgating_state(void *handle, 1054 enum amd_clockgating_state state) 1055 { 1056 return 0; 1057 } 1058 1059 static int gmc_v6_0_set_powergating_state(void *handle, 1060 enum amd_powergating_state state) 1061 { 1062 return 0; 1063 } 1064 1065 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { 1066 .name = "gmc_v6_0", 1067 .early_init = gmc_v6_0_early_init, 1068 .late_init = gmc_v6_0_late_init, 1069 .sw_init = gmc_v6_0_sw_init, 1070 .sw_fini = gmc_v6_0_sw_fini, 1071 .hw_init = gmc_v6_0_hw_init, 1072 .hw_fini = gmc_v6_0_hw_fini, 1073 .suspend = gmc_v6_0_suspend, 1074 .resume = gmc_v6_0_resume, 1075 .is_idle = gmc_v6_0_is_idle, 1076 .wait_for_idle = gmc_v6_0_wait_for_idle, 1077 .soft_reset = gmc_v6_0_soft_reset, 1078 .set_clockgating_state = gmc_v6_0_set_clockgating_state, 1079 .set_powergating_state = gmc_v6_0_set_powergating_state, 1080 }; 1081 1082 static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = { 1083 .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb, 1084 .set_pte_pde = gmc_v6_0_gart_set_pte_pde, 1085 }; 1086 1087 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { 1088 .set = gmc_v6_0_vm_fault_interrupt_state, 1089 .process = gmc_v6_0_process_interrupt, 1090 }; 1091 1092 static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev) 1093 { 1094 if (adev->gart.gart_funcs == NULL) 1095 adev->gart.gart_funcs = &gmc_v6_0_gart_funcs; 1096 } 1097 1098 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1099 { 1100 adev->mc.vm_fault.num_types = 1; 1101 adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs; 1102 } 1103 1104 const struct amdgpu_ip_block_version gmc_v6_0_ip_block = 1105 { 1106 .type = AMD_IP_BLOCK_TYPE_GMC, 1107 .major = 6, 1108 .minor = 0, 1109 .rev = 0, 1110 .funcs = &gmc_v6_0_ip_funcs, 1111 }; 1112