1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/drm_cache.h> 29 #include "amdgpu.h" 30 #include "gmc_v6_0.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_gem.h" 33 34 #include "bif/bif_3_0_d.h" 35 #include "bif/bif_3_0_sh_mask.h" 36 #include "oss/oss_1_0_d.h" 37 #include "oss/oss_1_0_sh_mask.h" 38 #include "gmc/gmc_6_0_d.h" 39 #include "gmc/gmc_6_0_sh_mask.h" 40 #include "dce/dce_6_0_d.h" 41 #include "dce/dce_6_0_sh_mask.h" 42 #include "si_enums.h" 43 44 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev); 45 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); 46 static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block); 47 48 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin"); 49 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin"); 50 MODULE_FIRMWARE("amdgpu/verde_mc.bin"); 51 MODULE_FIRMWARE("amdgpu/oland_mc.bin"); 52 MODULE_FIRMWARE("amdgpu/hainan_mc.bin"); 53 MODULE_FIRMWARE("amdgpu/si58_mc.bin"); 54 55 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 56 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 57 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 58 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 59 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 60 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 61 #define MC_SEQ_MISC0__MT__HBM 0x60000000 62 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 63 64 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) 65 { 66 u32 blackout; 67 struct amdgpu_ip_block *ip_block; 68 69 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); 70 if (!ip_block) 71 return; 72 73 gmc_v6_0_wait_for_idle(ip_block); 74 75 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 76 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { 77 /* Block CPU access */ 78 WREG32(mmBIF_FB_EN, 0); 79 /* blackout the MC */ 80 blackout = REG_SET_FIELD(blackout, 81 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 82 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1); 83 } 84 /* wait for the MC to settle */ 85 udelay(100); 86 87 } 88 89 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev) 90 { 91 u32 tmp; 92 93 /* unblackout the MC */ 94 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL); 95 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0); 96 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp); 97 /* allow CPU access */ 98 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1); 99 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1); 100 WREG32(mmBIF_FB_EN, tmp); 101 } 102 103 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) 104 { 105 const char *chip_name; 106 int err; 107 108 DRM_DEBUG("\n"); 109 110 switch (adev->asic_type) { 111 case CHIP_TAHITI: 112 chip_name = "tahiti"; 113 break; 114 case CHIP_PITCAIRN: 115 chip_name = "pitcairn"; 116 break; 117 case CHIP_VERDE: 118 chip_name = "verde"; 119 break; 120 case CHIP_OLAND: 121 chip_name = "oland"; 122 break; 123 case CHIP_HAINAN: 124 chip_name = "hainan"; 125 break; 126 default: 127 BUG(); 128 } 129 130 /* this memory configuration requires special firmware */ 131 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) 132 chip_name = "si58"; 133 134 err = amdgpu_ucode_request(adev, &adev->gmc.fw, AMDGPU_UCODE_REQUIRED, 135 "amdgpu/%s_mc.bin", chip_name); 136 if (err) { 137 dev_err(adev->dev, 138 "si_mc: Failed to load firmware \"%s_mc.bin\"\n", 139 chip_name); 140 amdgpu_ucode_release(&adev->gmc.fw); 141 } 142 return err; 143 } 144 145 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) 146 { 147 const __le32 *new_fw_data = NULL; 148 u32 running; 149 const __le32 *new_io_mc_regs = NULL; 150 int i, regs_size, ucode_size; 151 const struct mc_firmware_header_v1_0 *hdr; 152 153 if (!adev->gmc.fw) 154 return -EINVAL; 155 156 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; 157 158 amdgpu_ucode_print_mc_hdr(&hdr->header); 159 160 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); 161 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); 162 new_io_mc_regs = (const __le32 *) 163 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); 164 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 165 new_fw_data = (const __le32 *) 166 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 167 168 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; 169 170 if (running == 0) { 171 172 /* reset the engine and set to writable */ 173 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 174 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010); 175 176 /* load mc io regs */ 177 for (i = 0; i < regs_size; i++) { 178 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); 179 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); 180 } 181 /* load the MC ucode */ 182 for (i = 0; i < ucode_size; i++) 183 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); 184 185 /* put the engine back into the active state */ 186 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008); 187 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004); 188 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001); 189 190 /* wait for training to complete */ 191 for (i = 0; i < adev->usec_timeout; i++) { 192 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK) 193 break; 194 udelay(1); 195 } 196 for (i = 0; i < adev->usec_timeout; i++) { 197 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK) 198 break; 199 udelay(1); 200 } 201 202 } 203 204 return 0; 205 } 206 207 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, 208 struct amdgpu_gmc *mc) 209 { 210 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; 211 212 base <<= 24; 213 214 amdgpu_gmc_set_agp_default(adev, mc); 215 amdgpu_gmc_vram_location(adev, mc, base); 216 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); 217 } 218 219 static void gmc_v6_0_mc_program(struct amdgpu_device *adev) 220 { 221 int i, j; 222 struct amdgpu_ip_block *ip_block; 223 224 225 /* Initialize HDP */ 226 for (i = 0, j = 0; i < 32; i++, j += 0x6) { 227 WREG32((0xb05 + j), 0x00000000); 228 WREG32((0xb06 + j), 0x00000000); 229 WREG32((0xb07 + j), 0x00000000); 230 WREG32((0xb08 + j), 0x00000000); 231 WREG32((0xb09 + j), 0x00000000); 232 } 233 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); 234 235 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); 236 if (!ip_block) 237 return; 238 239 if (gmc_v6_0_wait_for_idle(ip_block)) 240 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 241 242 if (adev->mode_info.num_crtc) { 243 u32 tmp; 244 245 /* Lockout access through VGA aperture*/ 246 tmp = RREG32(mmVGA_HDP_CONTROL); 247 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK; 248 WREG32(mmVGA_HDP_CONTROL, tmp); 249 250 /* disable VGA render */ 251 tmp = RREG32(mmVGA_RENDER_CONTROL); 252 tmp &= VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK; 253 WREG32(mmVGA_RENDER_CONTROL, tmp); 254 } 255 /* Update configuration */ 256 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 257 adev->gmc.vram_start >> 12); 258 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 259 adev->gmc.vram_end >> 12); 260 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 261 adev->mem_scratch.gpu_addr >> 12); 262 WREG32(mmMC_VM_AGP_BASE, 0); 263 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); 264 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); 265 266 if (gmc_v6_0_wait_for_idle(ip_block)) 267 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 268 } 269 270 static int gmc_v6_0_mc_init(struct amdgpu_device *adev) 271 { 272 273 u32 tmp; 274 int chansize, numchan; 275 int r; 276 277 tmp = RREG32(mmMC_ARB_RAMCFG); 278 if (tmp & (1 << 11)) 279 chansize = 16; 280 else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) 281 chansize = 64; 282 else 283 chansize = 32; 284 285 tmp = RREG32(mmMC_SHARED_CHMAP); 286 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 287 case 0: 288 default: 289 numchan = 1; 290 break; 291 case 1: 292 numchan = 2; 293 break; 294 case 2: 295 numchan = 4; 296 break; 297 case 3: 298 numchan = 8; 299 break; 300 case 4: 301 numchan = 3; 302 break; 303 case 5: 304 numchan = 6; 305 break; 306 case 6: 307 numchan = 10; 308 break; 309 case 7: 310 numchan = 12; 311 break; 312 case 8: 313 numchan = 16; 314 break; 315 } 316 adev->gmc.vram_width = numchan * chansize; 317 /* size in MB on si */ 318 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 319 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; 320 321 if (!(adev->flags & AMD_IS_APU)) { 322 r = amdgpu_device_resize_fb_bar(adev); 323 if (r) 324 return r; 325 } 326 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 327 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 328 adev->gmc.visible_vram_size = adev->gmc.aper_size; 329 330 /* set the gart size */ 331 switch (adev->asic_type) { 332 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ 333 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ 334 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ 335 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ 336 amdgpu_gmc_set_gart_size(adev, SZ_1G); 337 break; 338 case CHIP_HAINAN: /* no MM engines */ 339 default: 340 amdgpu_gmc_set_gart_size(adev, SZ_256M); 341 break; 342 } 343 gmc_v6_0_vram_gtt_location(adev, &adev->gmc); 344 345 return 0; 346 } 347 348 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 349 uint32_t vmhub, uint32_t flush_type) 350 { 351 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 352 } 353 354 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 355 unsigned int vmid, uint64_t pd_addr) 356 { 357 uint32_t reg; 358 359 /* write new base address */ 360 if (vmid < 8) 361 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid; 362 else 363 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8); 364 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); 365 366 /* bits 0-15 are the VM contexts0-15 */ 367 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); 368 369 return pd_addr; 370 } 371 372 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level, 373 uint64_t *addr, uint64_t *flags) 374 { 375 BUG_ON(*addr & 0xFFFFFF0000000FFFULL); 376 } 377 378 static void gmc_v6_0_get_vm_pte(struct amdgpu_device *adev, 379 struct amdgpu_vm *vm, 380 struct amdgpu_bo *bo, 381 uint32_t vm_flags, 382 uint64_t *flags) 383 { 384 *flags &= ~AMDGPU_PTE_EXECUTABLE; 385 *flags &= ~AMDGPU_PTE_PRT; 386 } 387 388 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev, 389 bool value) 390 { 391 u32 tmp; 392 393 tmp = RREG32(mmVM_CONTEXT1_CNTL); 394 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 395 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 396 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 397 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 398 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 399 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 400 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 401 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 402 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 403 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 404 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 405 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 406 WREG32(mmVM_CONTEXT1_CNTL, tmp); 407 } 408 409 /** 410 * gmc_v8_0_set_prt() - set PRT VM fault 411 * 412 * @adev: amdgpu_device pointer 413 * @enable: enable/disable VM fault handling for PRT 414 */ 415 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) 416 { 417 u32 tmp; 418 419 if (enable && !adev->gmc.prt_warning) { 420 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); 421 adev->gmc.prt_warning = true; 422 } 423 424 tmp = RREG32(mmVM_PRT_CNTL); 425 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 426 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 427 enable); 428 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 429 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS, 430 enable); 431 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 432 L2_CACHE_STORE_INVALID_ENTRIES, 433 enable); 434 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL, 435 L1_TLB_STORE_INVALID_ENTRIES, 436 enable); 437 WREG32(mmVM_PRT_CNTL, tmp); 438 439 if (enable) { 440 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >> 441 AMDGPU_GPU_PAGE_SHIFT; 442 uint32_t high = adev->vm_manager.max_pfn - 443 (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT); 444 445 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low); 446 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low); 447 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low); 448 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low); 449 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high); 450 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high); 451 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high); 452 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high); 453 } else { 454 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff); 455 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff); 456 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff); 457 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff); 458 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0); 459 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0); 460 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0); 461 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0); 462 } 463 } 464 465 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 466 { 467 uint64_t table_addr; 468 u32 field; 469 int i; 470 471 if (adev->gart.bo == NULL) { 472 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 473 return -EINVAL; 474 } 475 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 476 477 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 478 479 /* Setup TLB control */ 480 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 481 (0xA << 7) | 482 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK | 483 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK | 484 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 485 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK | 486 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 487 /* Setup L2 cache */ 488 WREG32(mmVM_L2_CNTL, 489 VM_L2_CNTL__ENABLE_L2_CACHE_MASK | 490 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK | 491 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 492 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 493 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 494 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 495 WREG32(mmVM_L2_CNTL2, 496 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK | 497 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK); 498 499 field = adev->vm_manager.fragment_size; 500 WREG32(mmVM_L2_CNTL3, 501 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 502 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | 503 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 504 /* setup context0 */ 505 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); 506 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); 507 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12); 508 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 509 (u32)(adev->dummy_page_addr >> 12)); 510 WREG32(mmVM_CONTEXT0_CNTL2, 0); 511 WREG32(mmVM_CONTEXT0_CNTL, 512 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK | 513 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 514 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK); 515 516 WREG32(0x575, 0); 517 WREG32(0x576, 0); 518 WREG32(0x577, 0); 519 520 /* empty context1-15 */ 521 /* set vm size, must be a multiple of 4 */ 522 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 523 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); 524 /* Assign the pt base to something valid for now; the pts used for 525 * the VMs are determined by the application and setup and assigned 526 * on the fly in the vm part of radeon_gart.c 527 */ 528 for (i = 1; i < AMDGPU_NUM_VMID; i++) { 529 if (i < 8) 530 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i, 531 table_addr >> 12); 532 else 533 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8, 534 table_addr >> 12); 535 } 536 537 /* enable context1-15 */ 538 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 539 (u32)(adev->dummy_page_addr >> 12)); 540 WREG32(mmVM_CONTEXT1_CNTL2, 4); 541 WREG32(mmVM_CONTEXT1_CNTL, 542 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK | 543 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) | 544 ((adev->vm_manager.block_size - 9) 545 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT)); 546 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 547 gmc_v6_0_set_fault_enable_default(adev, false); 548 else 549 gmc_v6_0_set_fault_enable_default(adev, true); 550 551 gmc_v6_0_flush_gpu_tlb(adev, 0, 0, 0); 552 drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", 553 (unsigned int)(adev->gmc.gart_size >> 20), 554 (unsigned long long)table_addr); 555 return 0; 556 } 557 558 static int gmc_v6_0_gart_init(struct amdgpu_device *adev) 559 { 560 int r; 561 562 if (adev->gart.bo) { 563 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); 564 return 0; 565 } 566 r = amdgpu_gart_init(adev); 567 if (r) 568 return r; 569 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 570 adev->gart.gart_pte_flags = 0; 571 return amdgpu_gart_table_vram_alloc(adev); 572 } 573 574 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev) 575 { 576 /*unsigned i; 577 578 for (i = 1; i < 16; ++i) { 579 uint32_t reg; 580 if (i < 8) 581 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ; 582 else 583 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8); 584 adev->vm_manager.saved_table_addr[i] = RREG32(reg); 585 }*/ 586 587 /* Disable all tables */ 588 WREG32(mmVM_CONTEXT0_CNTL, 0); 589 WREG32(mmVM_CONTEXT1_CNTL, 0); 590 /* Setup TLB control */ 591 WREG32(mmMC_VM_MX_L1_TLB_CNTL, 592 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK | 593 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT)); 594 /* Setup L2 cache */ 595 WREG32(mmVM_L2_CNTL, 596 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK | 597 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK | 598 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) | 599 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT)); 600 WREG32(mmVM_L2_CNTL2, 0); 601 WREG32(mmVM_L2_CNTL3, 602 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK | 603 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); 604 } 605 606 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev, 607 u32 status, u32 addr) 608 { 609 u32 mc_id; 610 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 611 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 612 PROTECTIONS); 613 614 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 615 MEMORY_CLIENT_ID); 616 617 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from %d\n", 618 protections, vmid, addr, 619 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, 620 MEMORY_CLIENT_RW) ? 621 "write" : "read", mc_id); 622 } 623 624 static const u32 mc_cg_registers[] = { 625 mmMC_HUB_MISC_HUB_CG, 626 mmMC_HUB_MISC_SIP_CG, 627 mmMC_HUB_MISC_VM_CG, 628 mmMC_XPB_CLK_GAT, 629 mmATC_MISC_CG, 630 mmMC_CITF_MISC_WR_CG, 631 mmMC_CITF_MISC_RD_CG, 632 mmMC_CITF_MISC_VM_CG, 633 mmVM_L2_CG, 634 }; 635 636 static const u32 mc_cg_ls_en[] = { 637 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK, 638 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK, 639 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK, 640 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK, 641 ATC_MISC_CG__MEM_LS_ENABLE_MASK, 642 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK, 643 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK, 644 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK, 645 VM_L2_CG__MEM_LS_ENABLE_MASK, 646 }; 647 648 static const u32 mc_cg_en[] = { 649 MC_HUB_MISC_HUB_CG__ENABLE_MASK, 650 MC_HUB_MISC_SIP_CG__ENABLE_MASK, 651 MC_HUB_MISC_VM_CG__ENABLE_MASK, 652 MC_XPB_CLK_GAT__ENABLE_MASK, 653 ATC_MISC_CG__ENABLE_MASK, 654 MC_CITF_MISC_WR_CG__ENABLE_MASK, 655 MC_CITF_MISC_RD_CG__ENABLE_MASK, 656 MC_CITF_MISC_VM_CG__ENABLE_MASK, 657 VM_L2_CG__ENABLE_MASK, 658 }; 659 660 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev, 661 bool enable) 662 { 663 int i; 664 u32 orig, data; 665 666 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 667 orig = data = RREG32(mc_cg_registers[i]); 668 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) 669 data |= mc_cg_ls_en[i]; 670 else 671 data &= ~mc_cg_ls_en[i]; 672 if (data != orig) 673 WREG32(mc_cg_registers[i], data); 674 } 675 } 676 677 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev, 678 bool enable) 679 { 680 int i; 681 u32 orig, data; 682 683 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { 684 orig = data = RREG32(mc_cg_registers[i]); 685 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) 686 data |= mc_cg_en[i]; 687 else 688 data &= ~mc_cg_en[i]; 689 if (data != orig) 690 WREG32(mc_cg_registers[i], data); 691 } 692 } 693 694 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev, 695 bool enable) 696 { 697 u32 orig, data; 698 699 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 700 701 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) { 702 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1); 703 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1); 704 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1); 705 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1); 706 } else { 707 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0); 708 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0); 709 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0); 710 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0); 711 } 712 713 if (orig != data) 714 WREG32_PCIE(ixPCIE_CNTL2, data); 715 } 716 717 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev, 718 bool enable) 719 { 720 u32 orig, data; 721 722 orig = data = RREG32(mmHDP_HOST_PATH_CNTL); 723 724 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG)) 725 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0); 726 else 727 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1); 728 729 if (orig != data) 730 WREG32(mmHDP_HOST_PATH_CNTL, data); 731 } 732 733 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev, 734 bool enable) 735 { 736 u32 orig, data; 737 738 orig = data = RREG32(mmHDP_MEM_POWER_LS); 739 740 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) 741 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1); 742 else 743 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0); 744 745 if (orig != data) 746 WREG32(mmHDP_MEM_POWER_LS, data); 747 } 748 749 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) 750 { 751 switch (mc_seq_vram_type) { 752 case MC_SEQ_MISC0__MT__GDDR1: 753 return AMDGPU_VRAM_TYPE_GDDR1; 754 case MC_SEQ_MISC0__MT__DDR2: 755 return AMDGPU_VRAM_TYPE_DDR2; 756 case MC_SEQ_MISC0__MT__GDDR3: 757 return AMDGPU_VRAM_TYPE_GDDR3; 758 case MC_SEQ_MISC0__MT__GDDR4: 759 return AMDGPU_VRAM_TYPE_GDDR4; 760 case MC_SEQ_MISC0__MT__GDDR5: 761 return AMDGPU_VRAM_TYPE_GDDR5; 762 case MC_SEQ_MISC0__MT__DDR3: 763 return AMDGPU_VRAM_TYPE_DDR3; 764 default: 765 return AMDGPU_VRAM_TYPE_UNKNOWN; 766 } 767 } 768 769 static int gmc_v6_0_early_init(struct amdgpu_ip_block *ip_block) 770 { 771 struct amdgpu_device *adev = ip_block->adev; 772 773 gmc_v6_0_set_gmc_funcs(adev); 774 gmc_v6_0_set_irq_funcs(adev); 775 776 return 0; 777 } 778 779 static int gmc_v6_0_late_init(struct amdgpu_ip_block *ip_block) 780 { 781 struct amdgpu_device *adev = ip_block->adev; 782 783 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) 784 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 785 else 786 return 0; 787 } 788 789 static unsigned int gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev) 790 { 791 u32 d1vga_control = RREG32(mmD1VGA_CONTROL); 792 unsigned int size; 793 794 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 795 size = AMDGPU_VBIOS_VGA_ALLOCATION; 796 } else { 797 u32 viewport = RREG32(mmVIEWPORT_SIZE); 798 799 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) * 800 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) * 801 4); 802 } 803 return size; 804 } 805 806 static int gmc_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 807 { 808 int r; 809 struct amdgpu_device *adev = ip_block->adev; 810 811 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 812 813 if (adev->flags & AMD_IS_APU) { 814 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 815 } else { 816 u32 tmp = RREG32(mmMC_SEQ_MISC0); 817 818 tmp &= MC_SEQ_MISC0__MT__MASK; 819 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp); 820 } 821 822 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); 823 if (r) 824 return r; 825 826 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); 827 if (r) 828 return r; 829 830 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); 831 832 adev->gmc.mc_mask = 0xffffffffffULL; 833 834 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40)); 835 if (r) { 836 dev_warn(adev->dev, "No suitable DMA available.\n"); 837 return r; 838 } 839 adev->need_swiotlb = drm_need_swiotlb(40); 840 841 r = gmc_v6_0_init_microcode(adev); 842 if (r) { 843 dev_err(adev->dev, "Failed to load mc firmware!\n"); 844 return r; 845 } 846 847 r = gmc_v6_0_mc_init(adev); 848 if (r) 849 return r; 850 851 r = amdgpu_bo_init(adev); 852 if (r) 853 return r; 854 855 r = gmc_v6_0_gart_init(adev); 856 if (r) 857 return r; 858 859 /* 860 * number of VMs 861 * VMID 0 is reserved for System 862 * amdgpu graphics/compute will use VMIDs 1-7 863 * amdkfd will use VMIDs 8-15 864 */ 865 adev->vm_manager.first_kfd_vmid = 8; 866 amdgpu_vm_manager_init(adev); 867 868 /* base offset of vram pages */ 869 if (adev->flags & AMD_IS_APU) { 870 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 871 872 tmp <<= 22; 873 adev->vm_manager.vram_base_offset = tmp; 874 } else { 875 adev->vm_manager.vram_base_offset = 0; 876 } 877 878 return 0; 879 } 880 881 static int gmc_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) 882 { 883 struct amdgpu_device *adev = ip_block->adev; 884 885 amdgpu_gem_force_release(adev); 886 amdgpu_vm_manager_fini(adev); 887 amdgpu_gart_table_vram_free(adev); 888 amdgpu_bo_fini(adev); 889 amdgpu_ucode_release(&adev->gmc.fw); 890 891 return 0; 892 } 893 894 static int gmc_v6_0_hw_init(struct amdgpu_ip_block *ip_block) 895 { 896 int r; 897 struct amdgpu_device *adev = ip_block->adev; 898 899 gmc_v6_0_mc_program(adev); 900 901 if (!(adev->flags & AMD_IS_APU)) { 902 r = gmc_v6_0_mc_load_microcode(adev); 903 if (r) { 904 dev_err(adev->dev, "Failed to load MC firmware!\n"); 905 return r; 906 } 907 } 908 909 r = gmc_v6_0_gart_enable(adev); 910 if (r) 911 return r; 912 913 if (amdgpu_emu_mode == 1) 914 return amdgpu_gmc_vram_checking(adev); 915 916 return 0; 917 } 918 919 static int gmc_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) 920 { 921 struct amdgpu_device *adev = ip_block->adev; 922 923 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 924 gmc_v6_0_gart_disable(adev); 925 926 return 0; 927 } 928 929 static int gmc_v6_0_suspend(struct amdgpu_ip_block *ip_block) 930 { 931 gmc_v6_0_hw_fini(ip_block); 932 933 return 0; 934 } 935 936 static int gmc_v6_0_resume(struct amdgpu_ip_block *ip_block) 937 { 938 int r; 939 struct amdgpu_device *adev = ip_block->adev; 940 941 r = gmc_v6_0_hw_init(ip_block); 942 if (r) 943 return r; 944 945 amdgpu_vmid_reset_all(adev); 946 947 return 0; 948 } 949 950 static bool gmc_v6_0_is_idle(struct amdgpu_ip_block *ip_block) 951 { 952 struct amdgpu_device *adev = ip_block->adev; 953 954 u32 tmp = RREG32(mmSRBM_STATUS); 955 956 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 957 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK)) 958 return false; 959 960 return true; 961 } 962 963 static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 964 { 965 unsigned int i; 966 struct amdgpu_device *adev = ip_block->adev; 967 968 for (i = 0; i < adev->usec_timeout; i++) { 969 if (gmc_v6_0_is_idle(ip_block)) 970 return 0; 971 udelay(1); 972 } 973 return -ETIMEDOUT; 974 975 } 976 977 static int gmc_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) 978 { 979 struct amdgpu_device *adev = ip_block->adev; 980 981 u32 srbm_soft_reset = 0; 982 u32 tmp = RREG32(mmSRBM_STATUS); 983 984 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 985 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 986 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1); 987 988 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 989 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 990 if (!(adev->flags & AMD_IS_APU)) 991 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 992 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 993 } 994 995 if (srbm_soft_reset) { 996 gmc_v6_0_mc_stop(adev); 997 998 if (gmc_v6_0_wait_for_idle(ip_block)) 999 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1000 1001 tmp = RREG32(mmSRBM_SOFT_RESET); 1002 tmp |= srbm_soft_reset; 1003 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1004 WREG32(mmSRBM_SOFT_RESET, tmp); 1005 tmp = RREG32(mmSRBM_SOFT_RESET); 1006 1007 udelay(50); 1008 1009 tmp &= ~srbm_soft_reset; 1010 WREG32(mmSRBM_SOFT_RESET, tmp); 1011 tmp = RREG32(mmSRBM_SOFT_RESET); 1012 1013 udelay(50); 1014 1015 gmc_v6_0_mc_resume(adev); 1016 udelay(50); 1017 } 1018 1019 return 0; 1020 } 1021 1022 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 1023 struct amdgpu_irq_src *src, 1024 unsigned int type, 1025 enum amdgpu_interrupt_state state) 1026 { 1027 u32 tmp; 1028 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1029 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1030 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1031 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1032 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 1033 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK); 1034 1035 switch (state) { 1036 case AMDGPU_IRQ_STATE_DISABLE: 1037 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1038 tmp &= ~bits; 1039 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1040 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1041 tmp &= ~bits; 1042 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1043 break; 1044 case AMDGPU_IRQ_STATE_ENABLE: 1045 tmp = RREG32(mmVM_CONTEXT0_CNTL); 1046 tmp |= bits; 1047 WREG32(mmVM_CONTEXT0_CNTL, tmp); 1048 tmp = RREG32(mmVM_CONTEXT1_CNTL); 1049 tmp |= bits; 1050 WREG32(mmVM_CONTEXT1_CNTL, tmp); 1051 break; 1052 default: 1053 break; 1054 } 1055 1056 return 0; 1057 } 1058 1059 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev, 1060 struct amdgpu_irq_src *source, 1061 struct amdgpu_iv_entry *entry) 1062 { 1063 u32 addr, status; 1064 1065 /* Delegate to the soft IRQ handler ring */ 1066 if (adev->irq.ih_soft.enabled && entry->ih != &adev->irq.ih_soft) { 1067 amdgpu_irq_delegate(adev, entry, 4); 1068 return 1; 1069 } 1070 1071 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); 1072 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 1073 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); 1074 1075 if (!addr && !status) 1076 return 0; 1077 1078 amdgpu_vm_update_fault_cache(adev, entry->pasid, 1079 ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, 1080 status, AMDGPU_GFXHUB(0)); 1081 1082 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) 1083 gmc_v6_0_set_fault_enable_default(adev, false); 1084 1085 if (printk_ratelimit()) { 1086 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", 1087 entry->src_id, entry->src_data[0]); 1088 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1089 addr); 1090 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1091 status); 1092 gmc_v6_0_vm_decode_fault(adev, status, addr); 1093 } 1094 1095 return 0; 1096 } 1097 1098 static int gmc_v6_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1099 enum amd_clockgating_state state) 1100 { 1101 struct amdgpu_device *adev = ip_block->adev; 1102 bool gate = false; 1103 1104 if (state == AMD_CG_STATE_GATE) 1105 gate = true; 1106 1107 if (!(adev->flags & AMD_IS_APU)) { 1108 gmc_v6_0_enable_mc_mgcg(adev, gate); 1109 gmc_v6_0_enable_mc_ls(adev, gate); 1110 } 1111 gmc_v6_0_enable_bif_mgls(adev, gate); 1112 gmc_v6_0_enable_hdp_mgcg(adev, gate); 1113 gmc_v6_0_enable_hdp_ls(adev, gate); 1114 1115 return 0; 1116 } 1117 1118 static int gmc_v6_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1119 enum amd_powergating_state state) 1120 { 1121 return 0; 1122 } 1123 1124 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { 1125 .name = "gmc_v6_0", 1126 .early_init = gmc_v6_0_early_init, 1127 .late_init = gmc_v6_0_late_init, 1128 .sw_init = gmc_v6_0_sw_init, 1129 .sw_fini = gmc_v6_0_sw_fini, 1130 .hw_init = gmc_v6_0_hw_init, 1131 .hw_fini = gmc_v6_0_hw_fini, 1132 .suspend = gmc_v6_0_suspend, 1133 .resume = gmc_v6_0_resume, 1134 .is_idle = gmc_v6_0_is_idle, 1135 .wait_for_idle = gmc_v6_0_wait_for_idle, 1136 .soft_reset = gmc_v6_0_soft_reset, 1137 .set_clockgating_state = gmc_v6_0_set_clockgating_state, 1138 .set_powergating_state = gmc_v6_0_set_powergating_state, 1139 }; 1140 1141 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = { 1142 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb, 1143 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb, 1144 .set_prt = gmc_v6_0_set_prt, 1145 .get_vm_pde = gmc_v6_0_get_vm_pde, 1146 .get_vm_pte = gmc_v6_0_get_vm_pte, 1147 .get_vbios_fb_size = gmc_v6_0_get_vbios_fb_size, 1148 }; 1149 1150 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { 1151 .set = gmc_v6_0_vm_fault_interrupt_state, 1152 .process = gmc_v6_0_process_interrupt, 1153 }; 1154 1155 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev) 1156 { 1157 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; 1158 } 1159 1160 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) 1161 { 1162 adev->gmc.vm_fault.num_types = 1; 1163 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs; 1164 } 1165 1166 const struct amdgpu_ip_block_version gmc_v6_0_ip_block = { 1167 .type = AMD_IP_BLOCK_TYPE_GMC, 1168 .major = 6, 1169 .minor = 0, 1170 .rev = 0, 1171 .funcs = &gmc_v6_0_ip_funcs, 1172 }; 1173