1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "gmc_v12_1.h" 25 #include "soc15_common.h" 26 #include "soc_v1_0_enum.h" 27 #include "oss/osssys_7_1_0_offset.h" 28 #include "oss/osssys_7_1_0_sh_mask.h" 29 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 30 31 static int gmc_v12_1_vm_fault_interrupt_state(struct amdgpu_device *adev, 32 struct amdgpu_irq_src *src, 33 unsigned int type, 34 enum amdgpu_interrupt_state state) 35 { 36 struct amdgpu_vmhub *hub; 37 u32 tmp, reg, i, j; 38 39 switch (state) { 40 case AMDGPU_IRQ_STATE_DISABLE: 41 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 42 hub = &adev->vmhub[j]; 43 for (i = 0; i < 16; i++) { 44 reg = hub->vm_context0_cntl + i; 45 46 /* This works because this interrupt is only 47 * enabled at init/resume and disabled in 48 * fini/suspend, so the overall state doesn't 49 * change over the course of suspend/resume. 50 */ 51 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 52 continue; 53 54 if (j >= AMDGPU_MMHUB0(0)) 55 tmp = RREG32_SOC15_IP(MMHUB, reg); 56 else 57 tmp = RREG32_XCC(reg, j); 58 59 tmp &= ~hub->vm_cntx_cntl_vm_fault; 60 61 if (j >= AMDGPU_MMHUB0(0)) 62 WREG32_SOC15_IP(MMHUB, reg, tmp); 63 else 64 WREG32_XCC(reg, tmp, j); 65 } 66 } 67 break; 68 case AMDGPU_IRQ_STATE_ENABLE: 69 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 70 hub = &adev->vmhub[j]; 71 for (i = 0; i < 16; i++) { 72 reg = hub->vm_context0_cntl + i; 73 74 /* This works because this interrupt is only 75 * enabled at init/resume and disabled in 76 * fini/suspend, so the overall state doesn't 77 * change over the course of suspend/resume. 78 */ 79 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0))) 80 continue; 81 82 if (j >= AMDGPU_MMHUB0(0)) 83 tmp = RREG32_SOC15_IP(MMHUB, reg); 84 else 85 tmp = RREG32_XCC(reg, j); 86 87 tmp |= hub->vm_cntx_cntl_vm_fault; 88 89 if (j >= AMDGPU_MMHUB0(0)) 90 WREG32_SOC15_IP(MMHUB, reg, tmp); 91 else 92 WREG32_XCC(reg, tmp, j); 93 } 94 } 95 break; 96 default: 97 break; 98 } 99 100 return 0; 101 } 102 103 static int gmc_v12_1_process_interrupt(struct amdgpu_device *adev, 104 struct amdgpu_irq_src *source, 105 struct amdgpu_iv_entry *entry) 106 { 107 struct amdgpu_task_info *task_info; 108 bool retry_fault = false, write_fault = false; 109 unsigned int vmhub, node_id; 110 struct amdgpu_vmhub *hub; 111 uint32_t cam_index = 0; 112 const char *hub_name; 113 int ret, xcc_id = 0; 114 uint32_t status = 0; 115 u64 addr; 116 117 node_id = entry->node_id; 118 119 addr = (u64)entry->src_data[0] << 12; 120 addr |= ((u64)entry->src_data[1] & 0x1fff) << 44; 121 122 if (entry->src_id == UTCL2_1_0__SRCID__RETRY) { 123 retry_fault = true; 124 write_fault = !!(entry->src_data[1] & AMDGPU_GMC121_FAULT_SOURCE_DATA_WRITE); 125 } 126 127 if (entry->client_id == SOC_V1_0_IH_CLIENTID_VMC) { 128 hub_name = "mmhub0"; 129 vmhub = AMDGPU_MMHUB0(node_id / 4); 130 } else { 131 hub_name = "gfxhub0"; 132 if (adev->gfx.funcs->ih_node_to_logical_xcc) { 133 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, 134 node_id); 135 if (xcc_id < 0) 136 xcc_id = 0; 137 } 138 vmhub = xcc_id; 139 } 140 141 hub = &adev->vmhub[vmhub]; 142 143 if (retry_fault) { 144 if (adev->irq.retry_cam_enabled) { 145 /* Delegate it to a different ring if the hardware hasn't 146 * already done it. 147 */ 148 if (entry->ih == &adev->irq.ih) { 149 amdgpu_irq_delegate(adev, entry, 8); 150 return 1; 151 } 152 153 cam_index = entry->src_data[3] & 0x3ff; 154 155 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 156 addr, entry->timestamp, write_fault); 157 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 158 if (ret) 159 return 1; 160 } else { 161 /* Process it onyl if it's the first fault for this address */ 162 if (entry->ih != &adev->irq.ih_soft && 163 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 164 entry->timestamp)) 165 return 1; 166 167 /* Delegate it to a different ring if the hardware hasn't 168 * already done it. 169 */ 170 if (entry->ih == &adev->irq.ih) { 171 amdgpu_irq_delegate(adev, entry, 8); 172 return 1; 173 } 174 175 /* Try to handle the recoverable page faults by filling page 176 * tables 177 */ 178 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, 179 addr, entry->timestamp, write_fault)) 180 return 1; 181 } 182 } 183 184 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault)) 185 return 1; 186 187 if (!printk_ratelimit()) 188 return 0; 189 190 dev_err(adev->dev, 191 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name, 192 retry_fault ? "retry" : "no-retry", 193 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 194 195 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 196 if (task_info) { 197 amdgpu_vm_print_task_info(adev, task_info); 198 amdgpu_vm_put_task_info(task_info); 199 } 200 201 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client %d (%s)\n", 202 addr, entry->client_id, soc_v1_0_ih_clientid_name[entry->client_id]); 203 204 if (amdgpu_sriov_vf(adev)) 205 return 0; 206 207 /* 208 * Issue a dummy read to wait for the status register to 209 * be updated to avoid reading an incorrect value due to 210 * the new fast GRBM interface. 211 */ 212 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 213 RREG32(hub->vm_l2_pro_fault_status); 214 215 status = RREG32(hub->vm_l2_pro_fault_status); 216 217 /* Only print L2 fault status if the status register could be read and 218 * contains useful information 219 */ 220 if (!status) 221 return 0; 222 223 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 224 225 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub); 226 227 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 228 229 return 0; 230 } 231 232 static bool gmc_v12_1_get_vmid_pasid_mapping_info(struct amdgpu_device *adev, 233 uint8_t vmid, uint8_t inst, 234 uint16_t *p_pasid) 235 { 236 uint16_t index; 237 238 if (inst/4) 239 index = 0xA + inst%4; 240 else 241 index = 0x2 + inst%4; 242 243 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), index); 244 245 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 246 247 return !!(*p_pasid); 248 } 249 250 /* 251 * GART 252 * VMID 0 is the physical GPU addresses as used by the kernel. 253 * VMIDs 1-15 are used for userspace clients and are handled 254 * by the amdgpu vm/hsa code. 255 */ 256 257 static void gmc_v12_1_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 258 unsigned int vmhub, uint32_t flush_type) 259 { 260 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 261 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 262 u32 tmp; 263 /* Use register 17 for GART */ 264 const unsigned eng = 17; 265 unsigned int i; 266 unsigned char hub_ip = 0; 267 268 hub_ip = (AMDGPU_IS_GFXHUB(vmhub)) ? 269 GC_HWIP : MMHUB_HWIP; 270 271 spin_lock(&adev->gmc.invalidate_lock); 272 273 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 274 275 /* Wait for ACK with a delay.*/ 276 for (i = 0; i < adev->usec_timeout; i++) { 277 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 278 hub->eng_distance * eng, hub_ip); 279 tmp &= 1 << vmid; 280 if (tmp) 281 break; 282 283 udelay(1); 284 } 285 286 /* Issue additional private vm invalidation to MMHUB */ 287 if (!AMDGPU_IS_GFXHUB(vmhub) && 288 (hub->vm_l2_bank_select_reserved_cid2) && 289 !amdgpu_sriov_vf(adev)) { 290 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 291 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 292 inv_req |= (1 << 25); 293 /* Issue private invalidation */ 294 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 295 /* Read back to ensure invalidation is done*/ 296 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 297 } 298 299 spin_unlock(&adev->gmc.invalidate_lock); 300 301 if (i < adev->usec_timeout) 302 return; 303 304 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 305 } 306 307 /** 308 * gmc_v12_1_flush_gpu_tlb - gart tlb flush callback 309 * 310 * @adev: amdgpu_device pointer 311 * @vmid: vm instance to flush 312 * @vmhub: which hub to flush 313 * @flush_type: the flush type 314 * 315 * Flush the TLB for the requested page table. 316 */ 317 static void gmc_v12_1_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 318 uint32_t vmhub, uint32_t flush_type) 319 { 320 u32 inst; 321 322 if (AMDGPU_IS_GFXHUB(vmhub) && 323 !adev->gfx.is_poweron) 324 return; 325 326 if (vmhub >= AMDGPU_MMHUB0(0)) 327 inst = 0; 328 else 329 inst = vmhub; 330 331 /* This is necessary for SRIOV as well as for GFXOFF to function 332 * properly under bare metal 333 */ 334 if (((adev->gfx.kiq[inst].ring.sched.ready || 335 adev->mes.ring[MES_PIPE_INST(inst, 0)].sched.ready) && 336 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)))) { 337 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 338 const unsigned eng = 17; 339 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 340 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 341 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 342 343 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 344 1 << vmid, inst); 345 return; 346 } 347 348 gmc_v12_1_flush_vm_hub(adev, vmid, vmhub, 0); 349 return; 350 } 351 352 /** 353 * gmc_v12_1_flush_gpu_tlb_pasid - tlb flush via pasid 354 * 355 * @adev: amdgpu_device pointer 356 * @pasid: pasid to be flush 357 * @flush_type: the flush type 358 * @all_hub: flush all hubs 359 * @inst: is used to select which instance of KIQ to use for the invalidation 360 * 361 * Flush the TLB for the requested pasid. 362 */ 363 static void gmc_v12_1_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 364 uint16_t pasid, uint32_t flush_type, 365 bool all_hub, uint32_t inst) 366 { 367 uint16_t queried; 368 int vmid, i; 369 370 if (adev->enable_uni_mes && adev->mes.ring[0].sched.ready && 371 (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x6f) { 372 struct mes_inv_tlbs_pasid_input input = {0}; 373 input.xcc_id = inst; 374 input.pasid = pasid; 375 input.flush_type = flush_type; 376 377 /* MES will invalidate hubs for the device(including slave xcc) from master, ignore request from slave */ 378 if (!amdgpu_gfx_is_master_xcc(adev, inst)) 379 return; 380 381 input.hub_id = AMDGPU_GFXHUB(0); 382 adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); 383 384 if (all_hub) { 385 /* invalidate mm_hub */ 386 if (test_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask)) { 387 input.hub_id = AMDGPU_MMHUB0(0); 388 adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); 389 } 390 if (test_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask)) { 391 input.hub_id = AMDGPU_MMHUB1(0); 392 adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); 393 } 394 } 395 return; 396 } 397 398 for (vmid = 1; vmid < 16; vmid++) { 399 bool valid; 400 401 valid = gmc_v12_1_get_vmid_pasid_mapping_info(adev, vmid, inst, 402 &queried); 403 if (!valid || queried != pasid) 404 continue; 405 406 if (all_hub) { 407 for_each_set_bit(i, adev->vmhubs_mask, 408 AMDGPU_MAX_VMHUBS) 409 gmc_v12_1_flush_gpu_tlb(adev, vmid, i, 410 flush_type); 411 } else { 412 gmc_v12_1_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(inst), 413 flush_type); 414 } 415 } 416 } 417 418 static uint64_t gmc_v12_1_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 419 unsigned vmid, uint64_t pd_addr) 420 { 421 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 422 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 423 unsigned eng = ring->vm_inv_eng; 424 425 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 426 (hub->ctx_addr_distance * vmid), 427 lower_32_bits(pd_addr)); 428 429 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 430 (hub->ctx_addr_distance * vmid), 431 upper_32_bits(pd_addr)); 432 433 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 434 hub->eng_distance * eng, 435 hub->vm_inv_eng0_ack + 436 hub->eng_distance * eng, 437 req, 1 << vmid); 438 439 return pd_addr; 440 } 441 442 static void gmc_v12_1_emit_pasid_mapping(struct amdgpu_ring *ring, 443 unsigned vmid, unsigned pasid) 444 { 445 struct amdgpu_device *adev = ring->adev; 446 uint32_t reg; 447 448 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 449 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 450 else 451 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 452 453 amdgpu_ring_emit_wreg(ring, reg, pasid); 454 } 455 456 /* 457 * PTE format: 458 * 63 P 459 * 62:59 reserved 460 * 58 D 461 * 57 G 462 * 56 T 463 * 55:54 M 464 * 53:52 SW 465 * 51:48 reserved for future 466 * 47:12 4k physical page base address 467 * 11:7 fragment 468 * 6 write 469 * 5 read 470 * 4 exe 471 * 3 Z 472 * 2 snooped 473 * 1 system 474 * 0 valid 475 * 476 * PDE format: 477 * 63 P 478 * 62:58 block fragment size 479 * 57 reserved 480 * 56 A 481 * 55:54 M 482 * 53:52 reserved 483 * 51:48 reserved for future 484 * 47:6 physical base address of PD or PTE 485 * 5:3 reserved 486 * 2 C 487 * 1 system 488 * 0 valid 489 */ 490 491 static void gmc_v12_1_get_vm_pde(struct amdgpu_device *adev, int level, 492 uint64_t *addr, uint64_t *flags) 493 { 494 if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM)) 495 *addr = adev->vm_manager.vram_base_offset + *addr - 496 adev->gmc.vram_start; 497 BUG_ON(*addr & 0xFFFF00000000003FULL); 498 499 *flags |= AMDGPU_PTE_SNOOPED; 500 501 if (!adev->gmc.translate_further) 502 return; 503 504 if (level == AMDGPU_VM_PDB1) { 505 /* Set the block fragment size */ 506 if (!(*flags & AMDGPU_PDE_PTE_GFX12)) 507 *flags |= AMDGPU_PDE_BFS_GFX12(0x9); 508 509 } else if (level == AMDGPU_VM_PDB0) { 510 if (*flags & AMDGPU_PDE_PTE_GFX12) 511 *flags &= ~AMDGPU_PDE_PTE_GFX12; 512 } 513 } 514 515 static void gmc_v12_1_get_coherence_flags(struct amdgpu_device *adev, 516 struct amdgpu_bo *bo, 517 uint64_t *flags) 518 { 519 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 520 bool is_vram = bo->tbo.resource && 521 bo->tbo.resource->mem_type == TTM_PL_VRAM; 522 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 523 AMDGPU_GEM_CREATE_EXT_COHERENT); 524 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT; 525 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 526 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED; 527 unsigned int mtype, mtype_local, mtype_remote; 528 bool snoop = false; 529 bool is_local = false; 530 bool is_aid_a1; 531 532 switch (gc_ip_version) { 533 case IP_VERSION(12, 1, 0): 534 is_aid_a1 = (adev->rev_id & 0x10); 535 536 mtype_local = is_aid_a1 ? MTYPE_RW : MTYPE_NC; 537 mtype_remote = is_aid_a1 ? MTYPE_NC : MTYPE_UC; 538 if (amdgpu_mtype_local == 0) { 539 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n"); 540 mtype_local = MTYPE_RW; 541 } else if (amdgpu_mtype_local == 1) { 542 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n"); 543 mtype_local = MTYPE_NC; 544 } else if (amdgpu_mtype_local == 2) { 545 DRM_INFO_ONCE("MTYPE_CC not supported, using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC"); 546 } else { 547 DRM_INFO_ONCE("Using %s for local memory\n", is_aid_a1 ? "MTYPE_RW" : "MTYPE_NC"); 548 } 549 550 is_local = (is_vram && adev == bo_adev); 551 snoop = true; 552 if (uncached) { 553 mtype = MTYPE_UC; 554 } else if (ext_coherent) { 555 mtype = is_local ? mtype_local : MTYPE_UC; 556 } else { 557 mtype = is_local ? mtype_local : mtype_remote; 558 } 559 break; 560 default: 561 if (uncached || coherent) 562 mtype = MTYPE_UC; 563 else 564 mtype = MTYPE_NC; 565 } 566 567 if (mtype != MTYPE_NC) 568 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, mtype); 569 570 if (is_local || adev->have_atomics_support) 571 *flags |= AMDGPU_PTE_BUS_ATOMICS; 572 573 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0; 574 } 575 576 static void gmc_v12_1_get_vm_pte(struct amdgpu_device *adev, 577 struct amdgpu_vm *vm, 578 struct amdgpu_bo *bo, 579 uint32_t vm_flags, 580 uint64_t *flags) 581 { 582 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 583 *flags |= AMDGPU_PTE_EXECUTABLE; 584 else 585 *flags &= ~AMDGPU_PTE_EXECUTABLE; 586 587 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 588 case AMDGPU_VM_MTYPE_DEFAULT: 589 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 590 break; 591 case AMDGPU_VM_MTYPE_NC: 592 default: 593 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 594 break; 595 case AMDGPU_VM_MTYPE_RW: 596 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_RW); 597 break; 598 case AMDGPU_VM_MTYPE_UC: 599 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 600 break; 601 } 602 603 if ((*flags & AMDGPU_PTE_VALID) && bo) 604 gmc_v12_1_get_coherence_flags(adev, bo, flags); 605 } 606 607 static const struct amdgpu_gmc_funcs gmc_v12_1_gmc_funcs = { 608 .flush_gpu_tlb = gmc_v12_1_flush_gpu_tlb, 609 .flush_gpu_tlb_pasid = gmc_v12_1_flush_gpu_tlb_pasid, 610 .emit_flush_gpu_tlb = gmc_v12_1_emit_flush_gpu_tlb, 611 .emit_pasid_mapping = gmc_v12_1_emit_pasid_mapping, 612 .get_vm_pde = gmc_v12_1_get_vm_pde, 613 .get_vm_pte = gmc_v12_1_get_vm_pte, 614 .query_mem_partition_mode = &amdgpu_gmc_query_memory_partition, 615 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, 616 }; 617 618 void gmc_v12_1_set_gmc_funcs(struct amdgpu_device *adev) 619 { 620 adev->gmc.gmc_funcs = &gmc_v12_1_gmc_funcs; 621 } 622 623 static const struct amdgpu_irq_src_funcs gmc_v12_1_irq_funcs = { 624 .set = gmc_v12_1_vm_fault_interrupt_state, 625 .process = gmc_v12_1_process_interrupt, 626 }; 627 628 static const struct amdgpu_irq_src_funcs gmc_v12_1_ecc_funcs = { 629 .process = amdgpu_umc_uniras_process_ecc_irq, 630 }; 631 632 void gmc_v12_1_set_irq_funcs(struct amdgpu_device *adev) 633 { 634 adev->gmc.vm_fault.num_types = 1; 635 adev->gmc.vm_fault.funcs = &gmc_v12_1_irq_funcs; 636 637 adev->gmc.ecc_irq.num_types = 1; 638 adev->gmc.ecc_irq.funcs = &gmc_v12_1_ecc_funcs; 639 } 640 641 void gmc_v12_1_init_vram_info(struct amdgpu_device *adev) 642 { 643 /* TODO: query vram_info from ip discovery binary */ 644 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM4; 645 adev->gmc.vram_width = 384 * 64; 646 } 647