1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v12_0.h" 31 #include "athub/athub_4_1_0_sh_mask.h" 32 #include "athub/athub_4_1_0_offset.h" 33 #include "oss/osssys_7_0_0_offset.h" 34 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 35 #include "soc24_enum.h" 36 #include "soc24.h" 37 #include "soc15d.h" 38 #include "soc15_common.h" 39 #include "nbif_v6_3_1.h" 40 #include "gfxhub_v12_0.h" 41 #include "mmhub_v4_1_0.h" 42 #include "athub_v4_1_0.h" 43 44 45 static int gmc_v12_0_ecc_interrupt_state(struct amdgpu_device *adev, 46 struct amdgpu_irq_src *src, 47 unsigned type, 48 enum amdgpu_interrupt_state state) 49 { 50 return 0; 51 } 52 53 static int gmc_v12_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, unsigned type, 55 enum amdgpu_interrupt_state state) 56 { 57 switch (state) { 58 case AMDGPU_IRQ_STATE_DISABLE: 59 /* MM HUB */ 60 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 61 /* GFX HUB */ 62 /* This works because this interrupt is only 63 * enabled at init/resume and disabled in 64 * fini/suspend, so the overall state doesn't 65 * change over the course of suspend/resume. 66 */ 67 if (!adev->in_s0ix) 68 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 69 break; 70 case AMDGPU_IRQ_STATE_ENABLE: 71 /* MM HUB */ 72 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 73 /* GFX HUB */ 74 /* This works because this interrupt is only 75 * enabled at init/resume and disabled in 76 * fini/suspend, so the overall state doesn't 77 * change over the course of suspend/resume. 78 */ 79 if (!adev->in_s0ix) 80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 81 break; 82 default: 83 break; 84 } 85 86 return 0; 87 } 88 89 static int gmc_v12_0_process_interrupt(struct amdgpu_device *adev, 90 struct amdgpu_irq_src *source, 91 struct amdgpu_iv_entry *entry) 92 { 93 struct amdgpu_vmhub *hub; 94 uint32_t status = 0; 95 u64 addr; 96 97 addr = (u64)entry->src_data[0] << 12; 98 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 99 100 if (entry->client_id == SOC21_IH_CLIENTID_VMC) 101 hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 102 else 103 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 104 105 if (!amdgpu_sriov_vf(adev)) { 106 /* 107 * Issue a dummy read to wait for the status register to 108 * be updated to avoid reading an incorrect value due to 109 * the new fast GRBM interface. 110 */ 111 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 112 RREG32(hub->vm_l2_pro_fault_status); 113 114 status = RREG32(hub->vm_l2_pro_fault_status); 115 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 116 117 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 118 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 119 } 120 121 if (printk_ratelimit()) { 122 struct amdgpu_task_info *task_info; 123 124 dev_err(adev->dev, 125 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 126 entry->vmid_src ? "mmhub" : "gfxhub", 127 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 128 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 129 if (task_info) { 130 dev_err(adev->dev, 131 " in process %s pid %d thread %s pid %d)\n", 132 task_info->process_name, task_info->tgid, 133 task_info->task_name, task_info->pid); 134 amdgpu_vm_put_task_info(task_info); 135 } 136 137 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 138 addr, entry->client_id); 139 140 if (!amdgpu_sriov_vf(adev)) 141 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 142 } 143 144 return 0; 145 } 146 147 static const struct amdgpu_irq_src_funcs gmc_v12_0_irq_funcs = { 148 .set = gmc_v12_0_vm_fault_interrupt_state, 149 .process = gmc_v12_0_process_interrupt, 150 }; 151 152 static const struct amdgpu_irq_src_funcs gmc_v12_0_ecc_funcs = { 153 .set = gmc_v12_0_ecc_interrupt_state, 154 .process = amdgpu_umc_process_ecc_irq, 155 }; 156 157 static void gmc_v12_0_set_irq_funcs(struct amdgpu_device *adev) 158 { 159 adev->gmc.vm_fault.num_types = 1; 160 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; 161 162 if (!amdgpu_sriov_vf(adev)) { 163 adev->gmc.ecc_irq.num_types = 1; 164 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; 165 } 166 } 167 168 /** 169 * gmc_v12_0_use_invalidate_semaphore - judge whether to use semaphore 170 * 171 * @adev: amdgpu_device pointer 172 * @vmhub: vmhub type 173 * 174 */ 175 static bool gmc_v12_0_use_invalidate_semaphore(struct amdgpu_device *adev, 176 uint32_t vmhub) 177 { 178 return ((vmhub == AMDGPU_MMHUB0(0)) && 179 (!amdgpu_sriov_vf(adev))); 180 } 181 182 static bool gmc_v12_0_get_vmid_pasid_mapping_info( 183 struct amdgpu_device *adev, 184 uint8_t vmid, uint16_t *p_pasid) 185 { 186 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 187 188 return !!(*p_pasid); 189 } 190 191 /* 192 * GART 193 * VMID 0 is the physical GPU addresses as used by the kernel. 194 * VMIDs 1-15 are used for userspace clients and are handled 195 * by the amdgpu vm/hsa code. 196 */ 197 198 static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 199 unsigned int vmhub, uint32_t flush_type) 200 { 201 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub); 202 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 203 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 204 u32 tmp; 205 /* Use register 17 for GART */ 206 const unsigned eng = 17; 207 unsigned int i; 208 unsigned char hub_ip = 0; 209 210 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 211 GC_HWIP : MMHUB_HWIP; 212 213 spin_lock(&adev->gmc.invalidate_lock); 214 /* 215 * It may lose gpuvm invalidate acknowldege state across power-gating 216 * off cycle, add semaphore acquire before invalidation and semaphore 217 * release after invalidation to avoid entering power gated state 218 * to WA the Issue 219 */ 220 221 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 222 if (use_semaphore) { 223 for (i = 0; i < adev->usec_timeout; i++) { 224 /* a read return value of 1 means semaphore acuqire */ 225 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 226 hub->eng_distance * eng, hub_ip); 227 if (tmp & 0x1) 228 break; 229 udelay(1); 230 } 231 232 if (i >= adev->usec_timeout) 233 dev_err(adev->dev, 234 "Timeout waiting for sem acquire in VM flush!\n"); 235 } 236 237 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 238 239 /* Wait for ACK with a delay.*/ 240 for (i = 0; i < adev->usec_timeout; i++) { 241 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 242 hub->eng_distance * eng, hub_ip); 243 tmp &= 1 << vmid; 244 if (tmp) 245 break; 246 247 udelay(1); 248 } 249 250 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 251 if (use_semaphore) 252 /* 253 * add semaphore release after invalidation, 254 * write with 0 means semaphore release 255 */ 256 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 257 hub->eng_distance * eng, 0, hub_ip); 258 259 /* Issue additional private vm invalidation to MMHUB */ 260 if ((vmhub != AMDGPU_GFXHUB(0)) && 261 (hub->vm_l2_bank_select_reserved_cid2) && 262 !amdgpu_sriov_vf(adev)) { 263 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 264 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 265 inv_req |= (1 << 25); 266 /* Issue private invalidation */ 267 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 268 /* Read back to ensure invalidation is done*/ 269 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 270 } 271 272 spin_unlock(&adev->gmc.invalidate_lock); 273 274 if (i < adev->usec_timeout) 275 return; 276 277 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 278 } 279 280 /** 281 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback 282 * 283 * @adev: amdgpu_device pointer 284 * @vmid: vm instance to flush 285 * 286 * Flush the TLB for the requested page table. 287 */ 288 static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 289 uint32_t vmhub, uint32_t flush_type) 290 { 291 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 292 return; 293 294 /* flush hdp cache */ 295 adev->hdp.funcs->flush_hdp(adev, NULL); 296 297 /* This is necessary for SRIOV as well as for GFXOFF to function 298 * properly under bare metal 299 */ 300 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && 301 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 302 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 303 const unsigned eng = 17; 304 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 305 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 306 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 307 308 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 309 1 << vmid, GET_INST(GC, 0)); 310 return; 311 } 312 313 mutex_lock(&adev->mman.gtt_window_lock); 314 gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0); 315 mutex_unlock(&adev->mman.gtt_window_lock); 316 return; 317 } 318 319 /** 320 * gmc_v12_0_flush_gpu_tlb_pasid - tlb flush via pasid 321 * 322 * @adev: amdgpu_device pointer 323 * @pasid: pasid to be flush 324 * 325 * Flush the TLB for the requested pasid. 326 */ 327 static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 328 uint16_t pasid, uint32_t flush_type, 329 bool all_hub, uint32_t inst) 330 { 331 uint16_t queried; 332 int vmid, i; 333 334 for (vmid = 1; vmid < 16; vmid++) { 335 bool valid; 336 337 valid = gmc_v12_0_get_vmid_pasid_mapping_info(adev, vmid, 338 &queried); 339 if (!valid || queried != pasid) 340 continue; 341 342 if (all_hub) { 343 for_each_set_bit(i, adev->vmhubs_mask, 344 AMDGPU_MAX_VMHUBS) 345 gmc_v12_0_flush_gpu_tlb(adev, vmid, i, 346 flush_type); 347 } else { 348 gmc_v12_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 349 flush_type); 350 } 351 } 352 } 353 354 static uint64_t gmc_v12_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 355 unsigned vmid, uint64_t pd_addr) 356 { 357 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 358 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 359 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 360 unsigned eng = ring->vm_inv_eng; 361 362 /* 363 * It may lose gpuvm invalidate acknowldege state across power-gating 364 * off cycle, add semaphore acquire before invalidation and semaphore 365 * release after invalidation to avoid entering power gated state 366 * to WA the Issue 367 */ 368 369 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 370 if (use_semaphore) 371 /* a read return value of 1 means semaphore acuqire */ 372 amdgpu_ring_emit_reg_wait(ring, 373 hub->vm_inv_eng0_sem + 374 hub->eng_distance * eng, 0x1, 0x1); 375 376 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 377 (hub->ctx_addr_distance * vmid), 378 lower_32_bits(pd_addr)); 379 380 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 381 (hub->ctx_addr_distance * vmid), 382 upper_32_bits(pd_addr)); 383 384 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 385 hub->eng_distance * eng, 386 hub->vm_inv_eng0_ack + 387 hub->eng_distance * eng, 388 req, 1 << vmid); 389 390 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 391 if (use_semaphore) 392 /* 393 * add semaphore release after invalidation, 394 * write with 0 means semaphore release 395 */ 396 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 397 hub->eng_distance * eng, 0); 398 399 return pd_addr; 400 } 401 402 static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 403 unsigned pasid) 404 { 405 struct amdgpu_device *adev = ring->adev; 406 uint32_t reg; 407 408 /* MES fw manages IH_VMID_x_LUT updating */ 409 if (ring->is_mes_queue) 410 return; 411 412 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 413 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 414 else 415 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 416 417 amdgpu_ring_emit_wreg(ring, reg, pasid); 418 } 419 420 /* 421 * PTE format: 422 * 63 P 423 * 62:59 reserved 424 * 58 D 425 * 57 G 426 * 56 T 427 * 55:54 M 428 * 53:52 SW 429 * 51:48 reserved for future 430 * 47:12 4k physical page base address 431 * 11:7 fragment 432 * 6 write 433 * 5 read 434 * 4 exe 435 * 3 Z 436 * 2 snooped 437 * 1 system 438 * 0 valid 439 * 440 * PDE format: 441 * 63 P 442 * 62:58 block fragment size 443 * 57 reserved 444 * 56 A 445 * 55:54 M 446 * 53:52 reserved 447 * 51:48 reserved for future 448 * 47:6 physical base address of PD or PTE 449 * 5:3 reserved 450 * 2 C 451 * 1 system 452 * 0 valid 453 */ 454 455 static uint64_t gmc_v12_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 456 { 457 switch (flags) { 458 case AMDGPU_VM_MTYPE_DEFAULT: 459 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC); 460 case AMDGPU_VM_MTYPE_NC: 461 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC); 462 case AMDGPU_VM_MTYPE_WC: 463 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_WC); 464 case AMDGPU_VM_MTYPE_CC: 465 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_CC); 466 case AMDGPU_VM_MTYPE_UC: 467 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_UC); 468 default: 469 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC); 470 } 471 } 472 473 static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level, 474 uint64_t *addr, uint64_t *flags) 475 { 476 if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM)) 477 *addr = adev->vm_manager.vram_base_offset + *addr - 478 adev->gmc.vram_start; 479 BUG_ON(*addr & 0xFFFF00000000003FULL); 480 481 if (!adev->gmc.translate_further) 482 return; 483 484 if (level == AMDGPU_VM_PDB1) { 485 /* Set the block fragment size */ 486 if (!(*flags & AMDGPU_PDE_PTE_GFX12)) 487 *flags |= AMDGPU_PDE_BFS_GFX12(0x9); 488 489 } else if (level == AMDGPU_VM_PDB0) { 490 if (*flags & AMDGPU_PDE_PTE_GFX12) 491 *flags &= ~AMDGPU_PDE_PTE_GFX12; 492 } 493 } 494 495 static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, 496 struct amdgpu_bo_va_mapping *mapping, 497 uint64_t *flags) 498 { 499 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 500 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 501 bool coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; 502 bool is_system = bo->tbo.resource->mem_type == TTM_PL_SYSTEM; 503 504 505 *flags &= ~AMDGPU_PTE_EXECUTABLE; 506 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 507 508 *flags &= ~AMDGPU_PTE_MTYPE_GFX12_MASK; 509 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_GFX12_MASK); 510 511 if (mapping->flags & AMDGPU_PTE_PRT_GFX12) { 512 *flags |= AMDGPU_PTE_PRT_GFX12; 513 *flags |= AMDGPU_PTE_SNOOPED; 514 *flags |= AMDGPU_PTE_SYSTEM; 515 *flags &= ~AMDGPU_PTE_VALID; 516 } 517 518 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 519 AMDGPU_GEM_CREATE_UNCACHED)) 520 *flags = (*flags & ~AMDGPU_PTE_MTYPE_GFX12_MASK) | 521 AMDGPU_PTE_MTYPE_GFX12(MTYPE_UC); 522 523 /* WA for HW bug */ 524 if ((bo && is_system) || ((bo_adev != adev) && coherent)) 525 *flags |= AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC); 526 527 } 528 529 static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) 530 { 531 return 0; 532 } 533 534 static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { 535 .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, 536 .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, 537 .emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb, 538 .emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping, 539 .map_mtype = gmc_v12_0_map_mtype, 540 .get_vm_pde = gmc_v12_0_get_vm_pde, 541 .get_vm_pte = gmc_v12_0_get_vm_pte, 542 .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, 543 }; 544 545 static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev) 546 { 547 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; 548 } 549 550 static void gmc_v12_0_set_umc_funcs(struct amdgpu_device *adev) 551 { 552 } 553 554 555 static void gmc_v12_0_set_mmhub_funcs(struct amdgpu_device *adev) 556 { 557 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 558 case IP_VERSION(4, 1, 0): 559 adev->mmhub.funcs = &mmhub_v4_1_0_funcs; 560 break; 561 default: 562 break; 563 } 564 } 565 566 static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev) 567 { 568 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 569 case IP_VERSION(12, 0, 0): 570 case IP_VERSION(12, 0, 1): 571 adev->gfxhub.funcs = &gfxhub_v12_0_funcs; 572 break; 573 default: 574 break; 575 } 576 } 577 578 static int gmc_v12_0_early_init(void *handle) 579 { 580 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 581 582 gmc_v12_0_set_gfxhub_funcs(adev); 583 gmc_v12_0_set_mmhub_funcs(adev); 584 gmc_v12_0_set_gmc_funcs(adev); 585 gmc_v12_0_set_irq_funcs(adev); 586 gmc_v12_0_set_umc_funcs(adev); 587 588 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 589 adev->gmc.shared_aperture_end = 590 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 591 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 592 adev->gmc.private_aperture_end = 593 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 594 595 return 0; 596 } 597 598 static int gmc_v12_0_late_init(void *handle) 599 { 600 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 601 int r; 602 603 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 604 if (r) 605 return r; 606 607 r = amdgpu_gmc_ras_late_init(adev); 608 if (r) 609 return r; 610 611 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 612 } 613 614 static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, 615 struct amdgpu_gmc *mc) 616 { 617 u64 base = 0; 618 619 base = adev->mmhub.funcs->get_fb_location(adev); 620 621 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 622 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); 623 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 624 amdgpu_gmc_agp_location(adev, mc); 625 626 /* base offset of vram pages */ 627 if (amdgpu_sriov_vf(adev)) 628 adev->vm_manager.vram_base_offset = 0; 629 else 630 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 631 } 632 633 /** 634 * gmc_v12_0_mc_init - initialize the memory controller driver params 635 * 636 * @adev: amdgpu_device pointer 637 * 638 * Look up the amount of vram, vram width, and decide how to place 639 * vram and gart within the GPU's physical address space. 640 * Returns 0 for success. 641 */ 642 static int gmc_v12_0_mc_init(struct amdgpu_device *adev) 643 { 644 int r; 645 646 /* size in MB on si */ 647 adev->gmc.mc_vram_size = 648 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 649 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 650 651 if (!(adev->flags & AMD_IS_APU)) { 652 r = amdgpu_device_resize_fb_bar(adev); 653 if (r) 654 return r; 655 } 656 657 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 658 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 659 660 #ifdef CONFIG_X86_64 661 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 662 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 663 adev->gmc.aper_size = adev->gmc.real_vram_size; 664 } 665 #endif 666 /* In case the PCI BAR is larger than the actual amount of vram */ 667 adev->gmc.visible_vram_size = adev->gmc.aper_size; 668 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 669 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 670 671 /* set the gart size */ 672 if (amdgpu_gart_size == -1) { 673 adev->gmc.gart_size = 512ULL << 20; 674 } else 675 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 676 677 gmc_v12_0_vram_gtt_location(adev, &adev->gmc); 678 679 return 0; 680 } 681 682 static int gmc_v12_0_gart_init(struct amdgpu_device *adev) 683 { 684 int r; 685 686 if (adev->gart.bo) { 687 WARN(1, "PCIE GART already initialized\n"); 688 return 0; 689 } 690 691 /* Initialize common gart structure */ 692 r = amdgpu_gart_init(adev); 693 if (r) 694 return r; 695 696 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 697 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(MTYPE_UC) | 698 AMDGPU_PTE_EXECUTABLE | 699 AMDGPU_PTE_IS_PTE; 700 701 return amdgpu_gart_table_vram_alloc(adev); 702 } 703 704 static int gmc_v12_0_sw_init(void *handle) 705 { 706 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 707 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 708 709 adev->mmhub.funcs->init(adev); 710 711 adev->gfxhub.funcs->init(adev); 712 713 spin_lock_init(&adev->gmc.invalidate_lock); 714 715 r = amdgpu_atomfirmware_get_vram_info(adev, 716 &vram_width, &vram_type, &vram_vendor); 717 adev->gmc.vram_width = vram_width; 718 719 adev->gmc.vram_type = vram_type; 720 adev->gmc.vram_vendor = vram_vendor; 721 722 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 723 case IP_VERSION(12, 0, 0): 724 case IP_VERSION(12, 0, 1): 725 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 726 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 727 /* 728 * To fulfill 4-level page support, 729 * vm size is 256TB (48bit), maximum size, 730 * block size 512 (9bit) 731 */ 732 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 733 break; 734 default: 735 break; 736 } 737 738 /* This interrupt is VMC page fault.*/ 739 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 740 VMC_1_0__SRCID__VM_FAULT, 741 &adev->gmc.vm_fault); 742 743 if (r) 744 return r; 745 746 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 747 UTCL2_1_0__SRCID__FAULT, 748 &adev->gmc.vm_fault); 749 if (r) 750 return r; 751 752 if (!amdgpu_sriov_vf(adev)) { 753 /* interrupt sent to DF. */ 754 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 755 &adev->gmc.ecc_irq); 756 if (r) 757 return r; 758 } 759 760 /* 761 * Set the internal MC address mask This is the max address of the GPU's 762 * internal address space. 763 */ 764 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 765 766 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 767 if (r) { 768 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 769 return r; 770 } 771 772 adev->need_swiotlb = drm_need_swiotlb(44); 773 774 r = gmc_v12_0_mc_init(adev); 775 if (r) 776 return r; 777 778 amdgpu_gmc_get_vbios_allocations(adev); 779 780 /* Memory manager */ 781 r = amdgpu_bo_init(adev); 782 if (r) 783 return r; 784 785 r = gmc_v12_0_gart_init(adev); 786 if (r) 787 return r; 788 789 /* 790 * number of VMs 791 * VMID 0 is reserved for System 792 * amdgpu graphics/compute will use VMIDs 1-7 793 * amdkfd will use VMIDs 8-15 794 */ 795 adev->vm_manager.first_kfd_vmid = 8; 796 797 amdgpu_vm_manager_init(adev); 798 799 return 0; 800 } 801 802 /** 803 * gmc_v12_0_gart_fini - vm fini callback 804 * 805 * @adev: amdgpu_device pointer 806 * 807 * Tears down the driver GART/VM setup (CIK). 808 */ 809 static void gmc_v12_0_gart_fini(struct amdgpu_device *adev) 810 { 811 amdgpu_gart_table_vram_free(adev); 812 } 813 814 static int gmc_v12_0_sw_fini(void *handle) 815 { 816 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 817 818 amdgpu_vm_manager_fini(adev); 819 gmc_v12_0_gart_fini(adev); 820 amdgpu_gem_force_release(adev); 821 amdgpu_bo_fini(adev); 822 823 return 0; 824 } 825 826 static void gmc_v12_0_init_golden_registers(struct amdgpu_device *adev) 827 { 828 } 829 830 /** 831 * gmc_v12_0_gart_enable - gart enable 832 * 833 * @adev: amdgpu_device pointer 834 */ 835 static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) 836 { 837 int r; 838 bool value; 839 840 if (adev->gart.bo == NULL) { 841 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 842 return -EINVAL; 843 } 844 845 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 846 847 r = adev->mmhub.funcs->gart_enable(adev); 848 if (r) 849 return r; 850 851 /* Flush HDP after it is initialized */ 852 adev->hdp.funcs->flush_hdp(adev, NULL); 853 854 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 855 false : true; 856 857 adev->mmhub.funcs->set_fault_enable_default(adev, value); 858 gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 859 860 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 861 (unsigned)(adev->gmc.gart_size >> 20), 862 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 863 864 return 0; 865 } 866 867 static int gmc_v12_0_hw_init(void *handle) 868 { 869 int r; 870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 871 872 /* The sequence of these two function calls matters.*/ 873 gmc_v12_0_init_golden_registers(adev); 874 875 r = gmc_v12_0_gart_enable(adev); 876 if (r) 877 return r; 878 879 if (adev->umc.funcs && adev->umc.funcs->init_registers) 880 adev->umc.funcs->init_registers(adev); 881 882 return 0; 883 } 884 885 /** 886 * gmc_v12_0_gart_disable - gart disable 887 * 888 * @adev: amdgpu_device pointer 889 * 890 * This disables all VM page table. 891 */ 892 static void gmc_v12_0_gart_disable(struct amdgpu_device *adev) 893 { 894 adev->mmhub.funcs->gart_disable(adev); 895 } 896 897 static int gmc_v12_0_hw_fini(void *handle) 898 { 899 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 900 901 if (amdgpu_sriov_vf(adev)) { 902 /* full access mode, so don't touch any GMC register */ 903 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 904 return 0; 905 } 906 907 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 908 909 if (adev->gmc.ecc_irq.funcs && 910 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 911 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 912 913 gmc_v12_0_gart_disable(adev); 914 915 return 0; 916 } 917 918 static int gmc_v12_0_suspend(void *handle) 919 { 920 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 921 922 gmc_v12_0_hw_fini(adev); 923 924 return 0; 925 } 926 927 static int gmc_v12_0_resume(void *handle) 928 { 929 int r; 930 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 931 932 r = gmc_v12_0_hw_init(adev); 933 if (r) 934 return r; 935 936 amdgpu_vmid_reset_all(adev); 937 938 return 0; 939 } 940 941 static bool gmc_v12_0_is_idle(void *handle) 942 { 943 /* MC is always ready in GMC v11.*/ 944 return true; 945 } 946 947 static int gmc_v12_0_wait_for_idle(void *handle) 948 { 949 /* There is no need to wait for MC idle in GMC v11.*/ 950 return 0; 951 } 952 953 static int gmc_v12_0_soft_reset(void *handle) 954 { 955 return 0; 956 } 957 958 static int gmc_v12_0_set_clockgating_state(void *handle, 959 enum amd_clockgating_state state) 960 { 961 int r; 962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 963 964 r = adev->mmhub.funcs->set_clockgating(adev, state); 965 if (r) 966 return r; 967 968 return athub_v4_1_0_set_clockgating(adev, state); 969 } 970 971 static void gmc_v12_0_get_clockgating_state(void *handle, u64 *flags) 972 { 973 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 974 975 adev->mmhub.funcs->get_clockgating(adev, flags); 976 977 athub_v4_1_0_get_clockgating(adev, flags); 978 } 979 980 static int gmc_v12_0_set_powergating_state(void *handle, 981 enum amd_powergating_state state) 982 { 983 return 0; 984 } 985 986 const struct amd_ip_funcs gmc_v12_0_ip_funcs = { 987 .name = "gmc_v12_0", 988 .early_init = gmc_v12_0_early_init, 989 .sw_init = gmc_v12_0_sw_init, 990 .hw_init = gmc_v12_0_hw_init, 991 .late_init = gmc_v12_0_late_init, 992 .sw_fini = gmc_v12_0_sw_fini, 993 .hw_fini = gmc_v12_0_hw_fini, 994 .suspend = gmc_v12_0_suspend, 995 .resume = gmc_v12_0_resume, 996 .is_idle = gmc_v12_0_is_idle, 997 .wait_for_idle = gmc_v12_0_wait_for_idle, 998 .soft_reset = gmc_v12_0_soft_reset, 999 .set_clockgating_state = gmc_v12_0_set_clockgating_state, 1000 .set_powergating_state = gmc_v12_0_set_powergating_state, 1001 .get_clockgating_state = gmc_v12_0_get_clockgating_state, 1002 }; 1003 1004 const struct amdgpu_ip_block_version gmc_v12_0_ip_block = { 1005 .type = AMD_IP_BLOCK_TYPE_GMC, 1006 .major = 12, 1007 .minor = 0, 1008 .rev = 0, 1009 .funcs = &gmc_v12_0_ip_funcs, 1010 }; 1011