1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v12_0.h" 31 #include "gmc_v12_1.h" 32 #include "athub/athub_4_1_0_sh_mask.h" 33 #include "athub/athub_4_1_0_offset.h" 34 #include "oss/osssys_7_0_0_offset.h" 35 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 36 #include "soc24_enum.h" 37 #include "soc24.h" 38 #include "soc15d.h" 39 #include "soc15_common.h" 40 #include "nbif_v6_3_1.h" 41 #include "gfxhub_v12_0.h" 42 #include "gfxhub_v12_1.h" 43 #include "mmhub_v4_1_0.h" 44 #include "mmhub_v4_2_0.h" 45 #include "athub_v4_1_0.h" 46 #include "umc_v8_14.h" 47 48 static int gmc_v12_0_ecc_interrupt_state(struct amdgpu_device *adev, 49 struct amdgpu_irq_src *src, 50 unsigned type, 51 enum amdgpu_interrupt_state state) 52 { 53 return 0; 54 } 55 56 static int gmc_v12_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 57 struct amdgpu_irq_src *src, unsigned type, 58 enum amdgpu_interrupt_state state) 59 { 60 switch (state) { 61 case AMDGPU_IRQ_STATE_DISABLE: 62 /* MM HUB */ 63 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 64 /* GFX HUB */ 65 /* This works because this interrupt is only 66 * enabled at init/resume and disabled in 67 * fini/suspend, so the overall state doesn't 68 * change over the course of suspend/resume. 69 */ 70 if (!adev->in_s0ix) 71 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 72 break; 73 case AMDGPU_IRQ_STATE_ENABLE: 74 /* MM HUB */ 75 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 76 /* GFX HUB */ 77 /* This works because this interrupt is only 78 * enabled at init/resume and disabled in 79 * fini/suspend, so the overall state doesn't 80 * change over the course of suspend/resume. 81 */ 82 if (!adev->in_s0ix) 83 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 84 break; 85 default: 86 break; 87 } 88 89 return 0; 90 } 91 92 static int gmc_v12_0_process_interrupt(struct amdgpu_device *adev, 93 struct amdgpu_irq_src *source, 94 struct amdgpu_iv_entry *entry) 95 { 96 struct amdgpu_vmhub *hub; 97 bool retry_fault = !!(entry->src_data[1] & 98 AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY); 99 bool write_fault = !!(entry->src_data[1] & 100 AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE); 101 uint32_t status = 0; 102 u64 addr; 103 104 addr = (u64)entry->src_data[0] << 12; 105 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 106 107 if (entry->client_id == SOC21_IH_CLIENTID_VMC) 108 hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 109 else 110 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 111 112 if (retry_fault) { 113 /* Returning 1 here also prevents sending the IV to the KFD */ 114 115 /* Process it only if it's the first fault for this address */ 116 if (entry->ih != &adev->irq.ih_soft && 117 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 118 entry->timestamp)) 119 return 1; 120 121 /* Delegate it to a different ring if the hardware hasn't 122 * already done it. 123 */ 124 if (entry->ih == &adev->irq.ih) { 125 amdgpu_irq_delegate(adev, entry, 8); 126 return 1; 127 } 128 129 /* Try to handle the recoverable page faults by filling page 130 * tables 131 */ 132 if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, 133 entry->timestamp, write_fault)) 134 return 1; 135 } 136 137 if (!amdgpu_sriov_vf(adev)) { 138 /* 139 * Issue a dummy read to wait for the status register to 140 * be updated to avoid reading an incorrect value due to 141 * the new fast GRBM interface. 142 */ 143 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 144 RREG32(hub->vm_l2_pro_fault_status); 145 146 status = RREG32(hub->vm_l2_pro_fault_status); 147 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 148 149 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 150 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 151 } 152 153 if (printk_ratelimit()) { 154 struct amdgpu_task_info *task_info; 155 156 dev_err(adev->dev, 157 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 158 entry->vmid_src ? "mmhub" : "gfxhub", 159 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 160 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 161 if (task_info) { 162 amdgpu_vm_print_task_info(adev, task_info); 163 amdgpu_vm_put_task_info(task_info); 164 } 165 166 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 167 addr, entry->client_id); 168 169 /* Only print L2 fault status if the status register could be read and 170 * contains useful information 171 */ 172 if (status != 0) 173 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 174 } 175 176 return 0; 177 } 178 179 static const struct amdgpu_irq_src_funcs gmc_v12_0_irq_funcs = { 180 .set = gmc_v12_0_vm_fault_interrupt_state, 181 .process = gmc_v12_0_process_interrupt, 182 }; 183 184 static const struct amdgpu_irq_src_funcs gmc_v12_0_ecc_funcs = { 185 .set = gmc_v12_0_ecc_interrupt_state, 186 .process = amdgpu_umc_process_ecc_irq, 187 }; 188 189 static void gmc_v12_0_set_irq_funcs(struct amdgpu_device *adev) 190 { 191 adev->gmc.vm_fault.num_types = 1; 192 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; 193 194 if (!amdgpu_sriov_vf(adev)) { 195 adev->gmc.ecc_irq.num_types = 1; 196 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; 197 } 198 } 199 200 /** 201 * gmc_v12_0_use_invalidate_semaphore - judge whether to use semaphore 202 * 203 * @adev: amdgpu_device pointer 204 * @vmhub: vmhub type 205 * 206 */ 207 static bool gmc_v12_0_use_invalidate_semaphore(struct amdgpu_device *adev, 208 uint32_t vmhub) 209 { 210 return ((vmhub == AMDGPU_MMHUB0(0)) && 211 (!amdgpu_sriov_vf(adev))); 212 } 213 214 static bool gmc_v12_0_get_vmid_pasid_mapping_info( 215 struct amdgpu_device *adev, 216 uint8_t vmid, uint16_t *p_pasid) 217 { 218 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 219 220 return !!(*p_pasid); 221 } 222 223 /* 224 * GART 225 * VMID 0 is the physical GPU addresses as used by the kernel. 226 * VMIDs 1-15 are used for userspace clients and are handled 227 * by the amdgpu vm/hsa code. 228 */ 229 230 static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 231 unsigned int vmhub, uint32_t flush_type) 232 { 233 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub); 234 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 235 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 236 u32 tmp; 237 /* Use register 17 for GART */ 238 const unsigned eng = 17; 239 unsigned int i; 240 unsigned char hub_ip = 0; 241 242 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 243 GC_HWIP : MMHUB_HWIP; 244 245 spin_lock(&adev->gmc.invalidate_lock); 246 /* 247 * It may lose gpuvm invalidate acknowldege state across power-gating 248 * off cycle, add semaphore acquire before invalidation and semaphore 249 * release after invalidation to avoid entering power gated state 250 * to WA the Issue 251 */ 252 253 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 254 if (use_semaphore) { 255 for (i = 0; i < adev->usec_timeout; i++) { 256 /* a read return value of 1 means semaphore acuqire */ 257 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 258 hub->eng_distance * eng, hub_ip); 259 if (tmp & 0x1) 260 break; 261 udelay(1); 262 } 263 264 if (i >= adev->usec_timeout) 265 dev_err(adev->dev, 266 "Timeout waiting for sem acquire in VM flush!\n"); 267 } 268 269 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 270 271 /* Wait for ACK with a delay.*/ 272 for (i = 0; i < adev->usec_timeout; i++) { 273 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 274 hub->eng_distance * eng, hub_ip); 275 tmp &= 1 << vmid; 276 if (tmp) 277 break; 278 279 udelay(1); 280 } 281 282 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 283 if (use_semaphore) 284 /* 285 * add semaphore release after invalidation, 286 * write with 0 means semaphore release 287 */ 288 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 289 hub->eng_distance * eng, 0, hub_ip); 290 291 /* Issue additional private vm invalidation to MMHUB */ 292 if ((vmhub != AMDGPU_GFXHUB(0)) && 293 (hub->vm_l2_bank_select_reserved_cid2) && 294 !amdgpu_sriov_vf(adev)) { 295 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 296 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 297 inv_req |= (1 << 25); 298 /* Issue private invalidation */ 299 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 300 /* Read back to ensure invalidation is done*/ 301 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 302 } 303 304 spin_unlock(&adev->gmc.invalidate_lock); 305 306 if (i < adev->usec_timeout) 307 return; 308 309 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 310 } 311 312 /** 313 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback 314 * 315 * @adev: amdgpu_device pointer 316 * @vmid: vm instance to flush 317 * @vmhub: which hub to flush 318 * @flush_type: the flush type 319 * 320 * Flush the TLB for the requested page table. 321 */ 322 static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 323 uint32_t vmhub, uint32_t flush_type) 324 { 325 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 326 return; 327 328 /* flush hdp cache */ 329 amdgpu_device_flush_hdp(adev, NULL); 330 331 /* This is necessary for SRIOV as well as for GFXOFF to function 332 * properly under bare metal 333 */ 334 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) && 335 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 336 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 337 const unsigned eng = 17; 338 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 339 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 340 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 341 342 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 343 1 << vmid, GET_INST(GC, 0)); 344 return; 345 } 346 347 gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0); 348 return; 349 } 350 351 /** 352 * gmc_v12_0_flush_gpu_tlb_pasid - tlb flush via pasid 353 * 354 * @adev: amdgpu_device pointer 355 * @pasid: pasid to be flush 356 * @flush_type: the flush type 357 * @all_hub: flush all hubs 358 * @inst: is used to select which instance of KIQ to use for the invalidation 359 * 360 * Flush the TLB for the requested pasid. 361 */ 362 static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 363 uint16_t pasid, uint32_t flush_type, 364 bool all_hub, uint32_t inst) 365 { 366 uint16_t queried; 367 int vmid, i; 368 369 if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && 370 (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x84) { 371 struct mes_inv_tlbs_pasid_input input = {0}; 372 input.pasid = pasid; 373 input.flush_type = flush_type; 374 input.hub_id = AMDGPU_GFXHUB(0); 375 /* MES will invalidate all gc_hub for the device from master */ 376 adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); 377 if (all_hub) { 378 /* Only need to invalidate mm_hub now, gfx12 only support one mmhub */ 379 input.hub_id = AMDGPU_MMHUB0(0); 380 adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); 381 } 382 return; 383 } 384 385 for (vmid = 1; vmid < 16; vmid++) { 386 bool valid; 387 388 valid = gmc_v12_0_get_vmid_pasid_mapping_info(adev, vmid, 389 &queried); 390 if (!valid || queried != pasid) 391 continue; 392 393 if (all_hub) { 394 for_each_set_bit(i, adev->vmhubs_mask, 395 AMDGPU_MAX_VMHUBS) 396 gmc_v12_0_flush_gpu_tlb(adev, vmid, i, 397 flush_type); 398 } else { 399 gmc_v12_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 400 flush_type); 401 } 402 } 403 } 404 405 static uint64_t gmc_v12_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 406 unsigned vmid, uint64_t pd_addr) 407 { 408 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 409 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 410 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 411 unsigned eng = ring->vm_inv_eng; 412 413 /* 414 * It may lose gpuvm invalidate acknowldege state across power-gating 415 * off cycle, add semaphore acquire before invalidation and semaphore 416 * release after invalidation to avoid entering power gated state 417 * to WA the Issue 418 */ 419 420 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 421 if (use_semaphore) 422 /* a read return value of 1 means semaphore acuqire */ 423 amdgpu_ring_emit_reg_wait(ring, 424 hub->vm_inv_eng0_sem + 425 hub->eng_distance * eng, 0x1, 0x1); 426 427 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 428 (hub->ctx_addr_distance * vmid), 429 lower_32_bits(pd_addr)); 430 431 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 432 (hub->ctx_addr_distance * vmid), 433 upper_32_bits(pd_addr)); 434 435 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 436 hub->eng_distance * eng, 437 hub->vm_inv_eng0_ack + 438 hub->eng_distance * eng, 439 req, 1 << vmid); 440 441 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 442 if (use_semaphore) 443 /* 444 * add semaphore release after invalidation, 445 * write with 0 means semaphore release 446 */ 447 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 448 hub->eng_distance * eng, 0); 449 450 return pd_addr; 451 } 452 453 static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 454 unsigned pasid) 455 { 456 struct amdgpu_device *adev = ring->adev; 457 uint32_t reg; 458 459 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 460 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 461 else 462 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 463 464 amdgpu_ring_emit_wreg(ring, reg, pasid); 465 } 466 467 /* 468 * PTE format: 469 * 63 P 470 * 62:59 reserved 471 * 58 D 472 * 57 G 473 * 56 T 474 * 55:54 M 475 * 53:52 SW 476 * 51:48 reserved for future 477 * 47:12 4k physical page base address 478 * 11:7 fragment 479 * 6 write 480 * 5 read 481 * 4 exe 482 * 3 Z 483 * 2 snooped 484 * 1 system 485 * 0 valid 486 * 487 * PDE format: 488 * 63 P 489 * 62:58 block fragment size 490 * 57 reserved 491 * 56 A 492 * 55:54 M 493 * 53:52 reserved 494 * 51:48 reserved for future 495 * 47:6 physical base address of PD or PTE 496 * 5:3 reserved 497 * 2 C 498 * 1 system 499 * 0 valid 500 */ 501 502 static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level, 503 uint64_t *addr, uint64_t *flags) 504 { 505 if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM)) 506 *addr = adev->vm_manager.vram_base_offset + *addr - 507 adev->gmc.vram_start; 508 BUG_ON(*addr & 0xFFFF00000000003FULL); 509 510 if (!adev->gmc.translate_further) 511 return; 512 513 if (level == AMDGPU_VM_PDB1) { 514 /* Set the block fragment size */ 515 if (!(*flags & AMDGPU_PDE_PTE_GFX12)) 516 *flags |= AMDGPU_PDE_BFS_GFX12(0x9); 517 518 } else if (level == AMDGPU_VM_PDB0) { 519 if (*flags & AMDGPU_PDE_PTE_GFX12) 520 *flags &= ~AMDGPU_PDE_PTE_GFX12; 521 } 522 } 523 524 static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, 525 struct amdgpu_vm *vm, 526 struct amdgpu_bo *bo, 527 uint32_t vm_flags, 528 uint64_t *flags) 529 { 530 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 531 *flags |= AMDGPU_PTE_EXECUTABLE; 532 else 533 *flags &= ~AMDGPU_PTE_EXECUTABLE; 534 535 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 536 case AMDGPU_VM_MTYPE_DEFAULT: 537 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 538 break; 539 case AMDGPU_VM_MTYPE_NC: 540 default: 541 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 542 break; 543 case AMDGPU_VM_MTYPE_UC: 544 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 545 break; 546 } 547 548 if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) 549 *flags |= AMDGPU_PTE_NOALLOC; 550 else 551 *flags &= ~AMDGPU_PTE_NOALLOC; 552 553 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 554 *flags |= AMDGPU_PTE_PRT_GFX12; 555 *flags |= AMDGPU_PTE_SNOOPED; 556 *flags |= AMDGPU_PTE_SYSTEM; 557 *flags |= AMDGPU_PTE_IS_PTE; 558 *flags &= ~AMDGPU_PTE_VALID; 559 } 560 561 if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) 562 *flags |= AMDGPU_PTE_DCC; 563 564 if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED) 565 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 566 } 567 568 static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) 569 { 570 return 0; 571 } 572 573 static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev) 574 { 575 unsigned int max_tex_channel_caches, alignment; 576 577 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && 578 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) 579 return 0; 580 581 max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches; 582 if (is_power_of_2(max_tex_channel_caches)) 583 alignment = (unsigned int)(max_tex_channel_caches / SZ_4); 584 else 585 alignment = roundup_pow_of_two(max_tex_channel_caches); 586 587 return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K); 588 } 589 590 static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { 591 .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, 592 .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, 593 .emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb, 594 .emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping, 595 .get_vm_pde = gmc_v12_0_get_vm_pde, 596 .get_vm_pte = gmc_v12_0_get_vm_pte, 597 .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, 598 .get_dcc_alignment = gmc_v12_0_get_dcc_alignment, 599 }; 600 601 static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev) 602 { 603 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; 604 } 605 606 static void gmc_v12_0_set_umc_funcs(struct amdgpu_device *adev) 607 { 608 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 609 case IP_VERSION(8, 14, 0): 610 adev->umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM; 611 adev->umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev); 612 adev->umc.node_inst_num = 0; 613 adev->umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev); 614 adev->umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET; 615 adev->umc.ras = &umc_v8_14_ras; 616 break; 617 default: 618 break; 619 } 620 } 621 622 623 static void gmc_v12_0_set_mmhub_funcs(struct amdgpu_device *adev) 624 { 625 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 626 case IP_VERSION(4, 1, 0): 627 adev->mmhub.funcs = &mmhub_v4_1_0_funcs; 628 break; 629 case IP_VERSION(4, 2, 0): 630 adev->mmhub.funcs = &mmhub_v4_2_0_funcs; 631 break; 632 default: 633 break; 634 } 635 } 636 637 static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev) 638 { 639 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 640 case IP_VERSION(12, 0, 0): 641 case IP_VERSION(12, 0, 1): 642 adev->gfxhub.funcs = &gfxhub_v12_0_funcs; 643 break; 644 case IP_VERSION(12, 1, 0): 645 adev->gfxhub.funcs = &gfxhub_v12_1_funcs; 646 break; 647 default: 648 break; 649 } 650 } 651 652 static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) 653 { 654 struct amdgpu_device *adev = ip_block->adev; 655 656 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 657 case IP_VERSION(12, 1, 0): 658 gmc_v12_1_set_gmc_funcs(adev); 659 adev->gmc.init_pte_flags = AMDGPU_PTE_IS_PTE; 660 break; 661 default: 662 gmc_v12_0_set_gmc_funcs(adev); 663 break; 664 } 665 gmc_v12_0_set_gfxhub_funcs(adev); 666 gmc_v12_0_set_mmhub_funcs(adev); 667 gmc_v12_0_set_irq_funcs(adev); 668 gmc_v12_0_set_umc_funcs(adev); 669 670 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 671 adev->gmc.shared_aperture_end = 672 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 673 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 674 adev->gmc.private_aperture_end = 675 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 676 677 return 0; 678 } 679 680 static int gmc_v12_0_late_init(struct amdgpu_ip_block *ip_block) 681 { 682 struct amdgpu_device *adev = ip_block->adev; 683 int r; 684 685 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 686 if (r) 687 return r; 688 689 r = amdgpu_gmc_ras_late_init(adev); 690 if (r) 691 return r; 692 693 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 694 } 695 696 static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, 697 struct amdgpu_gmc *mc) 698 { 699 u64 base = 0; 700 701 base = adev->mmhub.funcs->get_fb_location(adev); 702 703 amdgpu_gmc_set_agp_default(adev, mc); 704 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 705 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); 706 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 707 amdgpu_gmc_agp_location(adev, mc); 708 709 /* base offset of vram pages */ 710 if (amdgpu_sriov_vf(adev)) 711 adev->vm_manager.vram_base_offset = 0; 712 else 713 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 714 } 715 716 /** 717 * gmc_v12_0_mc_init - initialize the memory controller driver params 718 * 719 * @adev: amdgpu_device pointer 720 * 721 * Look up the amount of vram, vram width, and decide how to place 722 * vram and gart within the GPU's physical address space. 723 * Returns 0 for success. 724 */ 725 static int gmc_v12_0_mc_init(struct amdgpu_device *adev) 726 { 727 int r; 728 729 /* size in MB on si */ 730 adev->gmc.mc_vram_size = 731 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 732 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 733 734 if (!(adev->flags & AMD_IS_APU)) { 735 r = amdgpu_device_resize_fb_bar(adev); 736 if (r) 737 return r; 738 } 739 740 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 741 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 742 743 #ifdef CONFIG_X86_64 744 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 745 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 746 adev->gmc.aper_size = adev->gmc.real_vram_size; 747 } 748 #endif 749 /* In case the PCI BAR is larger than the actual amount of vram */ 750 adev->gmc.visible_vram_size = adev->gmc.aper_size; 751 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 752 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 753 754 /* set the gart size */ 755 if (amdgpu_gart_size == -1) { 756 adev->gmc.gart_size = 512ULL << 20; 757 } else 758 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 759 760 gmc_v12_0_vram_gtt_location(adev, &adev->gmc); 761 762 return 0; 763 } 764 765 static int gmc_v12_0_gart_init(struct amdgpu_device *adev) 766 { 767 int r; 768 769 if (adev->gart.bo) { 770 WARN(1, "PCIE GART already initialized\n"); 771 return 0; 772 } 773 774 /* Initialize common gart structure */ 775 r = amdgpu_gart_init(adev); 776 if (r) 777 return r; 778 779 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 780 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) | 781 AMDGPU_PTE_EXECUTABLE | 782 AMDGPU_PTE_IS_PTE; 783 784 return amdgpu_gart_table_vram_alloc(adev); 785 } 786 787 static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 788 { 789 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 790 struct amdgpu_device *adev = ip_block->adev; 791 792 adev->mmhub.funcs->init(adev); 793 794 adev->gfxhub.funcs->init(adev); 795 796 spin_lock_init(&adev->gmc.invalidate_lock); 797 798 r = amdgpu_atomfirmware_get_vram_info(adev, 799 &vram_width, &vram_type, &vram_vendor); 800 adev->gmc.vram_width = vram_width; 801 802 adev->gmc.vram_type = vram_type; 803 adev->gmc.vram_vendor = vram_vendor; 804 805 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 806 case IP_VERSION(12, 0, 0): 807 case IP_VERSION(12, 0, 1): 808 case IP_VERSION(12, 1, 0): 809 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 810 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 811 /* 812 * To fulfill 4-level page support, 813 * vm size is 256TB (48bit), maximum size, 814 * block size 512 (9bit) 815 */ 816 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 817 break; 818 default: 819 break; 820 } 821 822 /* This interrupt is VMC page fault.*/ 823 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 824 VMC_1_0__SRCID__VM_FAULT, 825 &adev->gmc.vm_fault); 826 827 if (r) 828 return r; 829 830 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) 831 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_UTCL2, 832 UTCL2_1_0__SRCID__FAULT, 833 &adev->gmc.vm_fault); 834 else 835 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 836 UTCL2_1_0__SRCID__FAULT, 837 &adev->gmc.vm_fault); 838 if (r) 839 return r; 840 841 if (!amdgpu_sriov_vf(adev)) { 842 /* interrupt sent to DF. */ 843 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 844 &adev->gmc.ecc_irq); 845 if (r) 846 return r; 847 } 848 849 /* 850 * Set the internal MC address mask This is the max address of the GPU's 851 * internal address space. 852 */ 853 adev->gmc.mc_mask = AMDGPU_GMC_HOLE_MASK; 854 855 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 856 if (r) { 857 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 858 return r; 859 } 860 861 adev->need_swiotlb = drm_need_swiotlb(44); 862 863 r = gmc_v12_0_mc_init(adev); 864 if (r) 865 return r; 866 867 amdgpu_gmc_get_vbios_allocations(adev); 868 869 /* Memory manager */ 870 r = amdgpu_bo_init(adev); 871 if (r) 872 return r; 873 874 r = gmc_v12_0_gart_init(adev); 875 if (r) 876 return r; 877 878 /* 879 * number of VMs 880 * VMID 0 is reserved for System 881 * amdgpu graphics/compute will use VMIDs 1-7 882 * amdkfd will use VMIDs 8-15 883 */ 884 adev->vm_manager.first_kfd_vmid = 885 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) ? 886 3 : 8; 887 adev->vm_manager.first_kfd_vmid = 888 adev->gfx.disable_kq ? 1 : (adev->vm_manager.first_kfd_vmid); 889 890 amdgpu_vm_manager_init(adev); 891 892 r = amdgpu_gmc_ras_sw_init(adev); 893 if (r) 894 return r; 895 896 return 0; 897 } 898 899 /** 900 * gmc_v12_0_gart_fini - vm fini callback 901 * 902 * @adev: amdgpu_device pointer 903 * 904 * Tears down the driver GART/VM setup (CIK). 905 */ 906 static void gmc_v12_0_gart_fini(struct amdgpu_device *adev) 907 { 908 amdgpu_gart_table_vram_free(adev); 909 } 910 911 static int gmc_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 912 { 913 struct amdgpu_device *adev = ip_block->adev; 914 915 amdgpu_vm_manager_fini(adev); 916 gmc_v12_0_gart_fini(adev); 917 amdgpu_gem_force_release(adev); 918 amdgpu_bo_fini(adev); 919 920 return 0; 921 } 922 923 static void gmc_v12_0_init_golden_registers(struct amdgpu_device *adev) 924 { 925 } 926 927 /** 928 * gmc_v12_0_gart_enable - gart enable 929 * 930 * @adev: amdgpu_device pointer 931 */ 932 static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) 933 { 934 int r; 935 bool value; 936 937 if (adev->gart.bo == NULL) { 938 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 939 return -EINVAL; 940 } 941 942 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 943 944 r = adev->mmhub.funcs->gart_enable(adev); 945 if (r) 946 return r; 947 948 /* Flush HDP after it is initialized */ 949 amdgpu_device_flush_hdp(adev, NULL); 950 951 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 952 953 adev->mmhub.funcs->set_fault_enable_default(adev, value); 954 gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 955 956 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 957 (unsigned)(adev->gmc.gart_size >> 20), 958 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 959 960 return 0; 961 } 962 963 static int gmc_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 964 { 965 int r; 966 struct amdgpu_device *adev = ip_block->adev; 967 968 /* The sequence of these two function calls matters.*/ 969 gmc_v12_0_init_golden_registers(adev); 970 971 r = gmc_v12_0_gart_enable(adev); 972 if (r) 973 return r; 974 975 if (adev->umc.funcs && adev->umc.funcs->init_registers) 976 adev->umc.funcs->init_registers(adev); 977 978 return 0; 979 } 980 981 /** 982 * gmc_v12_0_gart_disable - gart disable 983 * 984 * @adev: amdgpu_device pointer 985 * 986 * This disables all VM page table. 987 */ 988 static void gmc_v12_0_gart_disable(struct amdgpu_device *adev) 989 { 990 adev->mmhub.funcs->gart_disable(adev); 991 } 992 993 static int gmc_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 994 { 995 struct amdgpu_device *adev = ip_block->adev; 996 997 if (amdgpu_sriov_vf(adev)) { 998 /* full access mode, so don't touch any GMC register */ 999 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1000 return 0; 1001 } 1002 1003 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1004 1005 if (adev->gmc.ecc_irq.funcs && 1006 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1007 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1008 1009 gmc_v12_0_gart_disable(adev); 1010 1011 return 0; 1012 } 1013 1014 static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block) 1015 { 1016 gmc_v12_0_hw_fini(ip_block); 1017 1018 return 0; 1019 } 1020 1021 static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block) 1022 { 1023 int r; 1024 1025 r = gmc_v12_0_hw_init(ip_block); 1026 if (r) 1027 return r; 1028 1029 amdgpu_vmid_reset_all(ip_block->adev); 1030 1031 return 0; 1032 } 1033 1034 static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 1035 { 1036 /* MC is always ready in GMC v11.*/ 1037 return true; 1038 } 1039 1040 static int gmc_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1041 { 1042 /* There is no need to wait for MC idle in GMC v11.*/ 1043 return 0; 1044 } 1045 1046 static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1047 enum amd_clockgating_state state) 1048 { 1049 int r; 1050 struct amdgpu_device *adev = ip_block->adev; 1051 1052 r = adev->mmhub.funcs->set_clockgating(adev, state); 1053 if (r) 1054 return r; 1055 1056 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 1, 0)) 1057 return athub_v4_1_0_set_clockgating(adev, state); 1058 else 1059 return 0; 1060 } 1061 1062 static void gmc_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1063 { 1064 struct amdgpu_device *adev = ip_block->adev; 1065 1066 adev->mmhub.funcs->get_clockgating(adev, flags); 1067 1068 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 1, 0)) 1069 athub_v4_1_0_get_clockgating(adev, flags); 1070 } 1071 1072 static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1073 enum amd_powergating_state state) 1074 { 1075 return 0; 1076 } 1077 1078 const struct amd_ip_funcs gmc_v12_0_ip_funcs = { 1079 .name = "gmc_v12_0", 1080 .early_init = gmc_v12_0_early_init, 1081 .sw_init = gmc_v12_0_sw_init, 1082 .hw_init = gmc_v12_0_hw_init, 1083 .late_init = gmc_v12_0_late_init, 1084 .sw_fini = gmc_v12_0_sw_fini, 1085 .hw_fini = gmc_v12_0_hw_fini, 1086 .suspend = gmc_v12_0_suspend, 1087 .resume = gmc_v12_0_resume, 1088 .is_idle = gmc_v12_0_is_idle, 1089 .wait_for_idle = gmc_v12_0_wait_for_idle, 1090 .set_clockgating_state = gmc_v12_0_set_clockgating_state, 1091 .set_powergating_state = gmc_v12_0_set_powergating_state, 1092 .get_clockgating_state = gmc_v12_0_get_clockgating_state, 1093 }; 1094 1095 const struct amdgpu_ip_block_version gmc_v12_0_ip_block = { 1096 .type = AMD_IP_BLOCK_TYPE_GMC, 1097 .major = 12, 1098 .minor = 0, 1099 .rev = 0, 1100 .funcs = &gmc_v12_0_ip_funcs, 1101 }; 1102