1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v12_0.h" 31 #include "athub/athub_4_1_0_sh_mask.h" 32 #include "athub/athub_4_1_0_offset.h" 33 #include "oss/osssys_7_0_0_offset.h" 34 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 35 #include "soc24_enum.h" 36 #include "soc24.h" 37 #include "soc15d.h" 38 #include "soc15_common.h" 39 #include "nbif_v6_3_1.h" 40 #include "gfxhub_v12_0.h" 41 #include "mmhub_v4_1_0.h" 42 #include "athub_v4_1_0.h" 43 #include "umc_v8_14.h" 44 45 static int gmc_v12_0_ecc_interrupt_state(struct amdgpu_device *adev, 46 struct amdgpu_irq_src *src, 47 unsigned type, 48 enum amdgpu_interrupt_state state) 49 { 50 return 0; 51 } 52 53 static int gmc_v12_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, unsigned type, 55 enum amdgpu_interrupt_state state) 56 { 57 switch (state) { 58 case AMDGPU_IRQ_STATE_DISABLE: 59 /* MM HUB */ 60 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 61 /* GFX HUB */ 62 /* This works because this interrupt is only 63 * enabled at init/resume and disabled in 64 * fini/suspend, so the overall state doesn't 65 * change over the course of suspend/resume. 66 */ 67 if (!adev->in_s0ix) 68 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 69 break; 70 case AMDGPU_IRQ_STATE_ENABLE: 71 /* MM HUB */ 72 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 73 /* GFX HUB */ 74 /* This works because this interrupt is only 75 * enabled at init/resume and disabled in 76 * fini/suspend, so the overall state doesn't 77 * change over the course of suspend/resume. 78 */ 79 if (!adev->in_s0ix) 80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 81 break; 82 default: 83 break; 84 } 85 86 return 0; 87 } 88 89 static int gmc_v12_0_process_interrupt(struct amdgpu_device *adev, 90 struct amdgpu_irq_src *source, 91 struct amdgpu_iv_entry *entry) 92 { 93 struct amdgpu_vmhub *hub; 94 uint32_t status = 0; 95 u64 addr; 96 97 addr = (u64)entry->src_data[0] << 12; 98 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 99 100 if (entry->client_id == SOC21_IH_CLIENTID_VMC) 101 hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 102 else 103 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 104 105 if (!amdgpu_sriov_vf(adev)) { 106 /* 107 * Issue a dummy read to wait for the status register to 108 * be updated to avoid reading an incorrect value due to 109 * the new fast GRBM interface. 110 */ 111 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 112 RREG32(hub->vm_l2_pro_fault_status); 113 114 status = RREG32(hub->vm_l2_pro_fault_status); 115 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 116 117 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 118 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 119 } 120 121 if (printk_ratelimit()) { 122 struct amdgpu_task_info *task_info; 123 124 dev_err(adev->dev, 125 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 126 entry->vmid_src ? "mmhub" : "gfxhub", 127 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 128 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 129 if (task_info) { 130 amdgpu_vm_print_task_info(adev, task_info); 131 amdgpu_vm_put_task_info(task_info); 132 } 133 134 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 135 addr, entry->client_id); 136 137 /* Only print L2 fault status if the status register could be read and 138 * contains useful information 139 */ 140 if (status != 0) 141 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 142 } 143 144 return 0; 145 } 146 147 static const struct amdgpu_irq_src_funcs gmc_v12_0_irq_funcs = { 148 .set = gmc_v12_0_vm_fault_interrupt_state, 149 .process = gmc_v12_0_process_interrupt, 150 }; 151 152 static const struct amdgpu_irq_src_funcs gmc_v12_0_ecc_funcs = { 153 .set = gmc_v12_0_ecc_interrupt_state, 154 .process = amdgpu_umc_process_ecc_irq, 155 }; 156 157 static void gmc_v12_0_set_irq_funcs(struct amdgpu_device *adev) 158 { 159 adev->gmc.vm_fault.num_types = 1; 160 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; 161 162 if (!amdgpu_sriov_vf(adev)) { 163 adev->gmc.ecc_irq.num_types = 1; 164 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; 165 } 166 } 167 168 /** 169 * gmc_v12_0_use_invalidate_semaphore - judge whether to use semaphore 170 * 171 * @adev: amdgpu_device pointer 172 * @vmhub: vmhub type 173 * 174 */ 175 static bool gmc_v12_0_use_invalidate_semaphore(struct amdgpu_device *adev, 176 uint32_t vmhub) 177 { 178 return ((vmhub == AMDGPU_MMHUB0(0)) && 179 (!amdgpu_sriov_vf(adev))); 180 } 181 182 static bool gmc_v12_0_get_vmid_pasid_mapping_info( 183 struct amdgpu_device *adev, 184 uint8_t vmid, uint16_t *p_pasid) 185 { 186 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 187 188 return !!(*p_pasid); 189 } 190 191 /* 192 * GART 193 * VMID 0 is the physical GPU addresses as used by the kernel. 194 * VMIDs 1-15 are used for userspace clients and are handled 195 * by the amdgpu vm/hsa code. 196 */ 197 198 static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 199 unsigned int vmhub, uint32_t flush_type) 200 { 201 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub); 202 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 203 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 204 u32 tmp; 205 /* Use register 17 for GART */ 206 const unsigned eng = 17; 207 unsigned int i; 208 unsigned char hub_ip = 0; 209 210 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 211 GC_HWIP : MMHUB_HWIP; 212 213 spin_lock(&adev->gmc.invalidate_lock); 214 /* 215 * It may lose gpuvm invalidate acknowldege state across power-gating 216 * off cycle, add semaphore acquire before invalidation and semaphore 217 * release after invalidation to avoid entering power gated state 218 * to WA the Issue 219 */ 220 221 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 222 if (use_semaphore) { 223 for (i = 0; i < adev->usec_timeout; i++) { 224 /* a read return value of 1 means semaphore acuqire */ 225 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 226 hub->eng_distance * eng, hub_ip); 227 if (tmp & 0x1) 228 break; 229 udelay(1); 230 } 231 232 if (i >= adev->usec_timeout) 233 dev_err(adev->dev, 234 "Timeout waiting for sem acquire in VM flush!\n"); 235 } 236 237 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 238 239 /* Wait for ACK with a delay.*/ 240 for (i = 0; i < adev->usec_timeout; i++) { 241 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 242 hub->eng_distance * eng, hub_ip); 243 tmp &= 1 << vmid; 244 if (tmp) 245 break; 246 247 udelay(1); 248 } 249 250 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 251 if (use_semaphore) 252 /* 253 * add semaphore release after invalidation, 254 * write with 0 means semaphore release 255 */ 256 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 257 hub->eng_distance * eng, 0, hub_ip); 258 259 /* Issue additional private vm invalidation to MMHUB */ 260 if ((vmhub != AMDGPU_GFXHUB(0)) && 261 (hub->vm_l2_bank_select_reserved_cid2) && 262 !amdgpu_sriov_vf(adev)) { 263 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 264 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 265 inv_req |= (1 << 25); 266 /* Issue private invalidation */ 267 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 268 /* Read back to ensure invalidation is done*/ 269 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 270 } 271 272 spin_unlock(&adev->gmc.invalidate_lock); 273 274 if (i < adev->usec_timeout) 275 return; 276 277 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 278 } 279 280 /** 281 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback 282 * 283 * @adev: amdgpu_device pointer 284 * @vmid: vm instance to flush 285 * @vmhub: which hub to flush 286 * @flush_type: the flush type 287 * 288 * Flush the TLB for the requested page table. 289 */ 290 static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 291 uint32_t vmhub, uint32_t flush_type) 292 { 293 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 294 return; 295 296 /* flush hdp cache */ 297 amdgpu_device_flush_hdp(adev, NULL); 298 299 /* This is necessary for SRIOV as well as for GFXOFF to function 300 * properly under bare metal 301 */ 302 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) && 303 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 304 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 305 const unsigned eng = 17; 306 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 307 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 308 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 309 310 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 311 1 << vmid, GET_INST(GC, 0)); 312 return; 313 } 314 315 mutex_lock(&adev->mman.gtt_window_lock); 316 gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0); 317 mutex_unlock(&adev->mman.gtt_window_lock); 318 return; 319 } 320 321 /** 322 * gmc_v12_0_flush_gpu_tlb_pasid - tlb flush via pasid 323 * 324 * @adev: amdgpu_device pointer 325 * @pasid: pasid to be flush 326 * @flush_type: the flush type 327 * @all_hub: flush all hubs 328 * @inst: is used to select which instance of KIQ to use for the invalidation 329 * 330 * Flush the TLB for the requested pasid. 331 */ 332 static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 333 uint16_t pasid, uint32_t flush_type, 334 bool all_hub, uint32_t inst) 335 { 336 uint16_t queried; 337 int vmid, i; 338 339 if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && 340 (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x81) { 341 struct mes_inv_tlbs_pasid_input input = {0}; 342 input.pasid = pasid; 343 input.flush_type = flush_type; 344 input.hub_id = AMDGPU_GFXHUB(0); 345 /* MES will invalidate all gc_hub for the device from master */ 346 adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); 347 if (all_hub) { 348 /* Only need to invalidate mm_hub now, gfx12 only support one mmhub */ 349 input.hub_id = AMDGPU_MMHUB0(0); 350 adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); 351 } 352 return; 353 } 354 355 for (vmid = 1; vmid < 16; vmid++) { 356 bool valid; 357 358 valid = gmc_v12_0_get_vmid_pasid_mapping_info(adev, vmid, 359 &queried); 360 if (!valid || queried != pasid) 361 continue; 362 363 if (all_hub) { 364 for_each_set_bit(i, adev->vmhubs_mask, 365 AMDGPU_MAX_VMHUBS) 366 gmc_v12_0_flush_gpu_tlb(adev, vmid, i, 367 flush_type); 368 } else { 369 gmc_v12_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 370 flush_type); 371 } 372 } 373 } 374 375 static uint64_t gmc_v12_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 376 unsigned vmid, uint64_t pd_addr) 377 { 378 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 379 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 380 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 381 unsigned eng = ring->vm_inv_eng; 382 383 /* 384 * It may lose gpuvm invalidate acknowldege state across power-gating 385 * off cycle, add semaphore acquire before invalidation and semaphore 386 * release after invalidation to avoid entering power gated state 387 * to WA the Issue 388 */ 389 390 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 391 if (use_semaphore) 392 /* a read return value of 1 means semaphore acuqire */ 393 amdgpu_ring_emit_reg_wait(ring, 394 hub->vm_inv_eng0_sem + 395 hub->eng_distance * eng, 0x1, 0x1); 396 397 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 398 (hub->ctx_addr_distance * vmid), 399 lower_32_bits(pd_addr)); 400 401 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 402 (hub->ctx_addr_distance * vmid), 403 upper_32_bits(pd_addr)); 404 405 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 406 hub->eng_distance * eng, 407 hub->vm_inv_eng0_ack + 408 hub->eng_distance * eng, 409 req, 1 << vmid); 410 411 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 412 if (use_semaphore) 413 /* 414 * add semaphore release after invalidation, 415 * write with 0 means semaphore release 416 */ 417 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 418 hub->eng_distance * eng, 0); 419 420 return pd_addr; 421 } 422 423 static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 424 unsigned pasid) 425 { 426 struct amdgpu_device *adev = ring->adev; 427 uint32_t reg; 428 429 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 430 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 431 else 432 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 433 434 amdgpu_ring_emit_wreg(ring, reg, pasid); 435 } 436 437 /* 438 * PTE format: 439 * 63 P 440 * 62:59 reserved 441 * 58 D 442 * 57 G 443 * 56 T 444 * 55:54 M 445 * 53:52 SW 446 * 51:48 reserved for future 447 * 47:12 4k physical page base address 448 * 11:7 fragment 449 * 6 write 450 * 5 read 451 * 4 exe 452 * 3 Z 453 * 2 snooped 454 * 1 system 455 * 0 valid 456 * 457 * PDE format: 458 * 63 P 459 * 62:58 block fragment size 460 * 57 reserved 461 * 56 A 462 * 55:54 M 463 * 53:52 reserved 464 * 51:48 reserved for future 465 * 47:6 physical base address of PD or PTE 466 * 5:3 reserved 467 * 2 C 468 * 1 system 469 * 0 valid 470 */ 471 472 static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level, 473 uint64_t *addr, uint64_t *flags) 474 { 475 if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM)) 476 *addr = adev->vm_manager.vram_base_offset + *addr - 477 adev->gmc.vram_start; 478 BUG_ON(*addr & 0xFFFF00000000003FULL); 479 480 if (!adev->gmc.translate_further) 481 return; 482 483 if (level == AMDGPU_VM_PDB1) { 484 /* Set the block fragment size */ 485 if (!(*flags & AMDGPU_PDE_PTE_GFX12)) 486 *flags |= AMDGPU_PDE_BFS_GFX12(0x9); 487 488 } else if (level == AMDGPU_VM_PDB0) { 489 if (*flags & AMDGPU_PDE_PTE_GFX12) 490 *flags &= ~AMDGPU_PDE_PTE_GFX12; 491 } 492 } 493 494 static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, 495 struct amdgpu_vm *vm, 496 struct amdgpu_bo *bo, 497 uint32_t vm_flags, 498 uint64_t *flags) 499 { 500 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 501 *flags |= AMDGPU_PTE_EXECUTABLE; 502 else 503 *flags &= ~AMDGPU_PTE_EXECUTABLE; 504 505 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 506 case AMDGPU_VM_MTYPE_DEFAULT: 507 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 508 break; 509 case AMDGPU_VM_MTYPE_NC: 510 default: 511 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 512 break; 513 case AMDGPU_VM_MTYPE_UC: 514 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 515 break; 516 } 517 518 if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) 519 *flags |= AMDGPU_PTE_NOALLOC; 520 else 521 *flags &= ~AMDGPU_PTE_NOALLOC; 522 523 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 524 *flags |= AMDGPU_PTE_SNOOPED; 525 *flags |= AMDGPU_PTE_SYSTEM; 526 *flags |= AMDGPU_PTE_IS_PTE; 527 *flags &= ~AMDGPU_PTE_VALID; 528 } 529 530 if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) 531 *flags |= AMDGPU_PTE_DCC; 532 533 if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED) 534 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 535 } 536 537 static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) 538 { 539 return 0; 540 } 541 542 static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev) 543 { 544 unsigned int max_tex_channel_caches, alignment; 545 546 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && 547 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) 548 return 0; 549 550 max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches; 551 if (is_power_of_2(max_tex_channel_caches)) 552 alignment = (unsigned int)(max_tex_channel_caches / SZ_4); 553 else 554 alignment = roundup_pow_of_two(max_tex_channel_caches); 555 556 return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K); 557 } 558 559 static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { 560 .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, 561 .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, 562 .emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb, 563 .emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping, 564 .get_vm_pde = gmc_v12_0_get_vm_pde, 565 .get_vm_pte = gmc_v12_0_get_vm_pte, 566 .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, 567 .get_dcc_alignment = gmc_v12_0_get_dcc_alignment, 568 }; 569 570 static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev) 571 { 572 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; 573 } 574 575 static void gmc_v12_0_set_umc_funcs(struct amdgpu_device *adev) 576 { 577 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 578 case IP_VERSION(8, 14, 0): 579 adev->umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM; 580 adev->umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev); 581 adev->umc.node_inst_num = 0; 582 adev->umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev); 583 adev->umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET; 584 adev->umc.ras = &umc_v8_14_ras; 585 break; 586 default: 587 break; 588 } 589 } 590 591 592 static void gmc_v12_0_set_mmhub_funcs(struct amdgpu_device *adev) 593 { 594 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 595 case IP_VERSION(4, 1, 0): 596 adev->mmhub.funcs = &mmhub_v4_1_0_funcs; 597 break; 598 default: 599 break; 600 } 601 } 602 603 static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev) 604 { 605 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 606 case IP_VERSION(12, 0, 0): 607 case IP_VERSION(12, 0, 1): 608 adev->gfxhub.funcs = &gfxhub_v12_0_funcs; 609 break; 610 default: 611 break; 612 } 613 } 614 615 static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) 616 { 617 struct amdgpu_device *adev = ip_block->adev; 618 619 gmc_v12_0_set_gfxhub_funcs(adev); 620 gmc_v12_0_set_mmhub_funcs(adev); 621 gmc_v12_0_set_gmc_funcs(adev); 622 gmc_v12_0_set_irq_funcs(adev); 623 gmc_v12_0_set_umc_funcs(adev); 624 625 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 626 adev->gmc.shared_aperture_end = 627 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 628 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 629 adev->gmc.private_aperture_end = 630 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 631 632 return 0; 633 } 634 635 static int gmc_v12_0_late_init(struct amdgpu_ip_block *ip_block) 636 { 637 struct amdgpu_device *adev = ip_block->adev; 638 int r; 639 640 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 641 if (r) 642 return r; 643 644 r = amdgpu_gmc_ras_late_init(adev); 645 if (r) 646 return r; 647 648 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 649 } 650 651 static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, 652 struct amdgpu_gmc *mc) 653 { 654 u64 base = 0; 655 656 base = adev->mmhub.funcs->get_fb_location(adev); 657 658 amdgpu_gmc_set_agp_default(adev, mc); 659 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 660 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); 661 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 662 amdgpu_gmc_agp_location(adev, mc); 663 664 /* base offset of vram pages */ 665 if (amdgpu_sriov_vf(adev)) 666 adev->vm_manager.vram_base_offset = 0; 667 else 668 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 669 } 670 671 /** 672 * gmc_v12_0_mc_init - initialize the memory controller driver params 673 * 674 * @adev: amdgpu_device pointer 675 * 676 * Look up the amount of vram, vram width, and decide how to place 677 * vram and gart within the GPU's physical address space. 678 * Returns 0 for success. 679 */ 680 static int gmc_v12_0_mc_init(struct amdgpu_device *adev) 681 { 682 int r; 683 684 /* size in MB on si */ 685 adev->gmc.mc_vram_size = 686 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 687 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 688 689 if (!(adev->flags & AMD_IS_APU)) { 690 r = amdgpu_device_resize_fb_bar(adev); 691 if (r) 692 return r; 693 } 694 695 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 696 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 697 698 #ifdef CONFIG_X86_64 699 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 700 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 701 adev->gmc.aper_size = adev->gmc.real_vram_size; 702 } 703 #endif 704 /* In case the PCI BAR is larger than the actual amount of vram */ 705 adev->gmc.visible_vram_size = adev->gmc.aper_size; 706 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 707 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 708 709 /* set the gart size */ 710 if (amdgpu_gart_size == -1) { 711 adev->gmc.gart_size = 512ULL << 20; 712 } else 713 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 714 715 gmc_v12_0_vram_gtt_location(adev, &adev->gmc); 716 717 return 0; 718 } 719 720 static int gmc_v12_0_gart_init(struct amdgpu_device *adev) 721 { 722 int r; 723 724 if (adev->gart.bo) { 725 WARN(1, "PCIE GART already initialized\n"); 726 return 0; 727 } 728 729 /* Initialize common gart structure */ 730 r = amdgpu_gart_init(adev); 731 if (r) 732 return r; 733 734 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 735 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) | 736 AMDGPU_PTE_EXECUTABLE | 737 AMDGPU_PTE_IS_PTE; 738 739 return amdgpu_gart_table_vram_alloc(adev); 740 } 741 742 static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 743 { 744 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 745 struct amdgpu_device *adev = ip_block->adev; 746 747 adev->mmhub.funcs->init(adev); 748 749 adev->gfxhub.funcs->init(adev); 750 751 spin_lock_init(&adev->gmc.invalidate_lock); 752 753 r = amdgpu_atomfirmware_get_vram_info(adev, 754 &vram_width, &vram_type, &vram_vendor); 755 adev->gmc.vram_width = vram_width; 756 757 adev->gmc.vram_type = vram_type; 758 adev->gmc.vram_vendor = vram_vendor; 759 760 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 761 case IP_VERSION(12, 0, 0): 762 case IP_VERSION(12, 0, 1): 763 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 764 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 765 /* 766 * To fulfill 4-level page support, 767 * vm size is 256TB (48bit), maximum size, 768 * block size 512 (9bit) 769 */ 770 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 771 break; 772 default: 773 break; 774 } 775 776 /* This interrupt is VMC page fault.*/ 777 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 778 VMC_1_0__SRCID__VM_FAULT, 779 &adev->gmc.vm_fault); 780 781 if (r) 782 return r; 783 784 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 785 UTCL2_1_0__SRCID__FAULT, 786 &adev->gmc.vm_fault); 787 if (r) 788 return r; 789 790 if (!amdgpu_sriov_vf(adev)) { 791 /* interrupt sent to DF. */ 792 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 793 &adev->gmc.ecc_irq); 794 if (r) 795 return r; 796 } 797 798 /* 799 * Set the internal MC address mask This is the max address of the GPU's 800 * internal address space. 801 */ 802 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 803 804 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 805 if (r) { 806 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 807 return r; 808 } 809 810 adev->need_swiotlb = drm_need_swiotlb(44); 811 812 r = gmc_v12_0_mc_init(adev); 813 if (r) 814 return r; 815 816 amdgpu_gmc_get_vbios_allocations(adev); 817 818 /* Memory manager */ 819 r = amdgpu_bo_init(adev); 820 if (r) 821 return r; 822 823 r = gmc_v12_0_gart_init(adev); 824 if (r) 825 return r; 826 827 /* 828 * number of VMs 829 * VMID 0 is reserved for System 830 * amdgpu graphics/compute will use VMIDs 1-7 831 * amdkfd will use VMIDs 8-15 832 */ 833 adev->vm_manager.first_kfd_vmid = adev->gfx.disable_kq ? 1 : 8; 834 835 amdgpu_vm_manager_init(adev); 836 837 r = amdgpu_gmc_ras_sw_init(adev); 838 if (r) 839 return r; 840 841 return 0; 842 } 843 844 /** 845 * gmc_v12_0_gart_fini - vm fini callback 846 * 847 * @adev: amdgpu_device pointer 848 * 849 * Tears down the driver GART/VM setup (CIK). 850 */ 851 static void gmc_v12_0_gart_fini(struct amdgpu_device *adev) 852 { 853 amdgpu_gart_table_vram_free(adev); 854 } 855 856 static int gmc_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 857 { 858 struct amdgpu_device *adev = ip_block->adev; 859 860 amdgpu_vm_manager_fini(adev); 861 gmc_v12_0_gart_fini(adev); 862 amdgpu_gem_force_release(adev); 863 amdgpu_bo_fini(adev); 864 865 return 0; 866 } 867 868 static void gmc_v12_0_init_golden_registers(struct amdgpu_device *adev) 869 { 870 } 871 872 /** 873 * gmc_v12_0_gart_enable - gart enable 874 * 875 * @adev: amdgpu_device pointer 876 */ 877 static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) 878 { 879 int r; 880 bool value; 881 882 if (adev->gart.bo == NULL) { 883 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 884 return -EINVAL; 885 } 886 887 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 888 889 r = adev->mmhub.funcs->gart_enable(adev); 890 if (r) 891 return r; 892 893 /* Flush HDP after it is initialized */ 894 amdgpu_device_flush_hdp(adev, NULL); 895 896 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 897 898 adev->mmhub.funcs->set_fault_enable_default(adev, value); 899 gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 900 901 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 902 (unsigned)(adev->gmc.gart_size >> 20), 903 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 904 905 return 0; 906 } 907 908 static int gmc_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 909 { 910 int r; 911 struct amdgpu_device *adev = ip_block->adev; 912 913 /* The sequence of these two function calls matters.*/ 914 gmc_v12_0_init_golden_registers(adev); 915 916 r = gmc_v12_0_gart_enable(adev); 917 if (r) 918 return r; 919 920 if (adev->umc.funcs && adev->umc.funcs->init_registers) 921 adev->umc.funcs->init_registers(adev); 922 923 return 0; 924 } 925 926 /** 927 * gmc_v12_0_gart_disable - gart disable 928 * 929 * @adev: amdgpu_device pointer 930 * 931 * This disables all VM page table. 932 */ 933 static void gmc_v12_0_gart_disable(struct amdgpu_device *adev) 934 { 935 adev->mmhub.funcs->gart_disable(adev); 936 } 937 938 static int gmc_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 939 { 940 struct amdgpu_device *adev = ip_block->adev; 941 942 if (amdgpu_sriov_vf(adev)) { 943 /* full access mode, so don't touch any GMC register */ 944 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 945 return 0; 946 } 947 948 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 949 950 if (adev->gmc.ecc_irq.funcs && 951 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 952 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 953 954 gmc_v12_0_gart_disable(adev); 955 956 return 0; 957 } 958 959 static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block) 960 { 961 gmc_v12_0_hw_fini(ip_block); 962 963 return 0; 964 } 965 966 static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block) 967 { 968 int r; 969 970 r = gmc_v12_0_hw_init(ip_block); 971 if (r) 972 return r; 973 974 amdgpu_vmid_reset_all(ip_block->adev); 975 976 return 0; 977 } 978 979 static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 980 { 981 /* MC is always ready in GMC v11.*/ 982 return true; 983 } 984 985 static int gmc_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 986 { 987 /* There is no need to wait for MC idle in GMC v11.*/ 988 return 0; 989 } 990 991 static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 992 enum amd_clockgating_state state) 993 { 994 int r; 995 struct amdgpu_device *adev = ip_block->adev; 996 997 r = adev->mmhub.funcs->set_clockgating(adev, state); 998 if (r) 999 return r; 1000 1001 return athub_v4_1_0_set_clockgating(adev, state); 1002 } 1003 1004 static void gmc_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1005 { 1006 struct amdgpu_device *adev = ip_block->adev; 1007 1008 adev->mmhub.funcs->get_clockgating(adev, flags); 1009 1010 athub_v4_1_0_get_clockgating(adev, flags); 1011 } 1012 1013 static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1014 enum amd_powergating_state state) 1015 { 1016 return 0; 1017 } 1018 1019 const struct amd_ip_funcs gmc_v12_0_ip_funcs = { 1020 .name = "gmc_v12_0", 1021 .early_init = gmc_v12_0_early_init, 1022 .sw_init = gmc_v12_0_sw_init, 1023 .hw_init = gmc_v12_0_hw_init, 1024 .late_init = gmc_v12_0_late_init, 1025 .sw_fini = gmc_v12_0_sw_fini, 1026 .hw_fini = gmc_v12_0_hw_fini, 1027 .suspend = gmc_v12_0_suspend, 1028 .resume = gmc_v12_0_resume, 1029 .is_idle = gmc_v12_0_is_idle, 1030 .wait_for_idle = gmc_v12_0_wait_for_idle, 1031 .set_clockgating_state = gmc_v12_0_set_clockgating_state, 1032 .set_powergating_state = gmc_v12_0_set_powergating_state, 1033 .get_clockgating_state = gmc_v12_0_get_clockgating_state, 1034 }; 1035 1036 const struct amdgpu_ip_block_version gmc_v12_0_ip_block = { 1037 .type = AMD_IP_BLOCK_TYPE_GMC, 1038 .major = 12, 1039 .minor = 0, 1040 .rev = 0, 1041 .funcs = &gmc_v12_0_ip_funcs, 1042 }; 1043