1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v12_0.h" 31 #include "athub/athub_4_1_0_sh_mask.h" 32 #include "athub/athub_4_1_0_offset.h" 33 #include "oss/osssys_7_0_0_offset.h" 34 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 35 #include "soc24_enum.h" 36 #include "soc24.h" 37 #include "soc15d.h" 38 #include "soc15_common.h" 39 #include "nbif_v6_3_1.h" 40 #include "gfxhub_v12_0.h" 41 #include "mmhub_v4_1_0.h" 42 #include "athub_v4_1_0.h" 43 #include "umc_v8_14.h" 44 45 static int gmc_v12_0_ecc_interrupt_state(struct amdgpu_device *adev, 46 struct amdgpu_irq_src *src, 47 unsigned type, 48 enum amdgpu_interrupt_state state) 49 { 50 return 0; 51 } 52 53 static int gmc_v12_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, unsigned type, 55 enum amdgpu_interrupt_state state) 56 { 57 switch (state) { 58 case AMDGPU_IRQ_STATE_DISABLE: 59 /* MM HUB */ 60 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 61 /* GFX HUB */ 62 /* This works because this interrupt is only 63 * enabled at init/resume and disabled in 64 * fini/suspend, so the overall state doesn't 65 * change over the course of suspend/resume. 66 */ 67 if (!adev->in_s0ix) 68 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 69 break; 70 case AMDGPU_IRQ_STATE_ENABLE: 71 /* MM HUB */ 72 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 73 /* GFX HUB */ 74 /* This works because this interrupt is only 75 * enabled at init/resume and disabled in 76 * fini/suspend, so the overall state doesn't 77 * change over the course of suspend/resume. 78 */ 79 if (!adev->in_s0ix) 80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 81 break; 82 default: 83 break; 84 } 85 86 return 0; 87 } 88 89 static int gmc_v12_0_process_interrupt(struct amdgpu_device *adev, 90 struct amdgpu_irq_src *source, 91 struct amdgpu_iv_entry *entry) 92 { 93 struct amdgpu_vmhub *hub; 94 uint32_t status = 0; 95 u64 addr; 96 97 addr = (u64)entry->src_data[0] << 12; 98 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 99 100 if (entry->client_id == SOC21_IH_CLIENTID_VMC) 101 hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 102 else 103 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 104 105 if (!amdgpu_sriov_vf(adev)) { 106 /* 107 * Issue a dummy read to wait for the status register to 108 * be updated to avoid reading an incorrect value due to 109 * the new fast GRBM interface. 110 */ 111 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 112 RREG32(hub->vm_l2_pro_fault_status); 113 114 status = RREG32(hub->vm_l2_pro_fault_status); 115 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 116 117 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 118 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 119 } 120 121 if (printk_ratelimit()) { 122 struct amdgpu_task_info *task_info; 123 124 dev_err(adev->dev, 125 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 126 entry->vmid_src ? "mmhub" : "gfxhub", 127 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 128 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 129 if (task_info) { 130 amdgpu_vm_print_task_info(adev, task_info); 131 amdgpu_vm_put_task_info(task_info); 132 } 133 134 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 135 addr, entry->client_id); 136 137 /* Only print L2 fault status if the status register could be read and 138 * contains useful information 139 */ 140 if (status != 0) 141 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 142 } 143 144 return 0; 145 } 146 147 static const struct amdgpu_irq_src_funcs gmc_v12_0_irq_funcs = { 148 .set = gmc_v12_0_vm_fault_interrupt_state, 149 .process = gmc_v12_0_process_interrupt, 150 }; 151 152 static const struct amdgpu_irq_src_funcs gmc_v12_0_ecc_funcs = { 153 .set = gmc_v12_0_ecc_interrupt_state, 154 .process = amdgpu_umc_process_ecc_irq, 155 }; 156 157 static void gmc_v12_0_set_irq_funcs(struct amdgpu_device *adev) 158 { 159 adev->gmc.vm_fault.num_types = 1; 160 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; 161 162 if (!amdgpu_sriov_vf(adev)) { 163 adev->gmc.ecc_irq.num_types = 1; 164 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; 165 } 166 } 167 168 /** 169 * gmc_v12_0_use_invalidate_semaphore - judge whether to use semaphore 170 * 171 * @adev: amdgpu_device pointer 172 * @vmhub: vmhub type 173 * 174 */ 175 static bool gmc_v12_0_use_invalidate_semaphore(struct amdgpu_device *adev, 176 uint32_t vmhub) 177 { 178 return ((vmhub == AMDGPU_MMHUB0(0)) && 179 (!amdgpu_sriov_vf(adev))); 180 } 181 182 static bool gmc_v12_0_get_vmid_pasid_mapping_info( 183 struct amdgpu_device *adev, 184 uint8_t vmid, uint16_t *p_pasid) 185 { 186 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 187 188 return !!(*p_pasid); 189 } 190 191 /* 192 * GART 193 * VMID 0 is the physical GPU addresses as used by the kernel. 194 * VMIDs 1-15 are used for userspace clients and are handled 195 * by the amdgpu vm/hsa code. 196 */ 197 198 static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 199 unsigned int vmhub, uint32_t flush_type) 200 { 201 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub); 202 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 203 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 204 u32 tmp; 205 /* Use register 17 for GART */ 206 const unsigned eng = 17; 207 unsigned int i; 208 unsigned char hub_ip = 0; 209 210 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 211 GC_HWIP : MMHUB_HWIP; 212 213 spin_lock(&adev->gmc.invalidate_lock); 214 /* 215 * It may lose gpuvm invalidate acknowldege state across power-gating 216 * off cycle, add semaphore acquire before invalidation and semaphore 217 * release after invalidation to avoid entering power gated state 218 * to WA the Issue 219 */ 220 221 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 222 if (use_semaphore) { 223 for (i = 0; i < adev->usec_timeout; i++) { 224 /* a read return value of 1 means semaphore acuqire */ 225 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 226 hub->eng_distance * eng, hub_ip); 227 if (tmp & 0x1) 228 break; 229 udelay(1); 230 } 231 232 if (i >= adev->usec_timeout) 233 dev_err(adev->dev, 234 "Timeout waiting for sem acquire in VM flush!\n"); 235 } 236 237 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 238 239 /* Wait for ACK with a delay.*/ 240 for (i = 0; i < adev->usec_timeout; i++) { 241 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 242 hub->eng_distance * eng, hub_ip); 243 tmp &= 1 << vmid; 244 if (tmp) 245 break; 246 247 udelay(1); 248 } 249 250 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 251 if (use_semaphore) 252 /* 253 * add semaphore release after invalidation, 254 * write with 0 means semaphore release 255 */ 256 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 257 hub->eng_distance * eng, 0, hub_ip); 258 259 /* Issue additional private vm invalidation to MMHUB */ 260 if ((vmhub != AMDGPU_GFXHUB(0)) && 261 (hub->vm_l2_bank_select_reserved_cid2) && 262 !amdgpu_sriov_vf(adev)) { 263 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 264 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 265 inv_req |= (1 << 25); 266 /* Issue private invalidation */ 267 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 268 /* Read back to ensure invalidation is done*/ 269 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 270 } 271 272 spin_unlock(&adev->gmc.invalidate_lock); 273 274 if (i < adev->usec_timeout) 275 return; 276 277 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 278 } 279 280 /** 281 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback 282 * 283 * @adev: amdgpu_device pointer 284 * @vmid: vm instance to flush 285 * @vmhub: which hub to flush 286 * @flush_type: the flush type 287 * 288 * Flush the TLB for the requested page table. 289 */ 290 static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 291 uint32_t vmhub, uint32_t flush_type) 292 { 293 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 294 return; 295 296 /* flush hdp cache */ 297 amdgpu_device_flush_hdp(adev, NULL); 298 299 /* This is necessary for SRIOV as well as for GFXOFF to function 300 * properly under bare metal 301 */ 302 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) && 303 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 304 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 305 const unsigned eng = 17; 306 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 307 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 308 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 309 310 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 311 1 << vmid, GET_INST(GC, 0)); 312 return; 313 } 314 315 gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0); 316 return; 317 } 318 319 /** 320 * gmc_v12_0_flush_gpu_tlb_pasid - tlb flush via pasid 321 * 322 * @adev: amdgpu_device pointer 323 * @pasid: pasid to be flush 324 * @flush_type: the flush type 325 * @all_hub: flush all hubs 326 * @inst: is used to select which instance of KIQ to use for the invalidation 327 * 328 * Flush the TLB for the requested pasid. 329 */ 330 static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 331 uint16_t pasid, uint32_t flush_type, 332 bool all_hub, uint32_t inst) 333 { 334 uint16_t queried; 335 int vmid, i; 336 337 if (adev->enable_uni_mes && adev->mes.ring[AMDGPU_MES_SCHED_PIPE].sched.ready && 338 (adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x84) { 339 struct mes_inv_tlbs_pasid_input input = {0}; 340 input.pasid = pasid; 341 input.flush_type = flush_type; 342 input.hub_id = AMDGPU_GFXHUB(0); 343 /* MES will invalidate all gc_hub for the device from master */ 344 adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); 345 if (all_hub) { 346 /* Only need to invalidate mm_hub now, gfx12 only support one mmhub */ 347 input.hub_id = AMDGPU_MMHUB0(0); 348 adev->mes.funcs->invalidate_tlbs_pasid(&adev->mes, &input); 349 } 350 return; 351 } 352 353 for (vmid = 1; vmid < 16; vmid++) { 354 bool valid; 355 356 valid = gmc_v12_0_get_vmid_pasid_mapping_info(adev, vmid, 357 &queried); 358 if (!valid || queried != pasid) 359 continue; 360 361 if (all_hub) { 362 for_each_set_bit(i, adev->vmhubs_mask, 363 AMDGPU_MAX_VMHUBS) 364 gmc_v12_0_flush_gpu_tlb(adev, vmid, i, 365 flush_type); 366 } else { 367 gmc_v12_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 368 flush_type); 369 } 370 } 371 } 372 373 static uint64_t gmc_v12_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 374 unsigned vmid, uint64_t pd_addr) 375 { 376 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 377 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 378 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 379 unsigned eng = ring->vm_inv_eng; 380 381 /* 382 * It may lose gpuvm invalidate acknowldege state across power-gating 383 * off cycle, add semaphore acquire before invalidation and semaphore 384 * release after invalidation to avoid entering power gated state 385 * to WA the Issue 386 */ 387 388 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 389 if (use_semaphore) 390 /* a read return value of 1 means semaphore acuqire */ 391 amdgpu_ring_emit_reg_wait(ring, 392 hub->vm_inv_eng0_sem + 393 hub->eng_distance * eng, 0x1, 0x1); 394 395 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 396 (hub->ctx_addr_distance * vmid), 397 lower_32_bits(pd_addr)); 398 399 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 400 (hub->ctx_addr_distance * vmid), 401 upper_32_bits(pd_addr)); 402 403 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 404 hub->eng_distance * eng, 405 hub->vm_inv_eng0_ack + 406 hub->eng_distance * eng, 407 req, 1 << vmid); 408 409 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 410 if (use_semaphore) 411 /* 412 * add semaphore release after invalidation, 413 * write with 0 means semaphore release 414 */ 415 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 416 hub->eng_distance * eng, 0); 417 418 return pd_addr; 419 } 420 421 static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 422 unsigned pasid) 423 { 424 struct amdgpu_device *adev = ring->adev; 425 uint32_t reg; 426 427 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 428 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 429 else 430 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 431 432 amdgpu_ring_emit_wreg(ring, reg, pasid); 433 } 434 435 /* 436 * PTE format: 437 * 63 P 438 * 62:59 reserved 439 * 58 D 440 * 57 G 441 * 56 T 442 * 55:54 M 443 * 53:52 SW 444 * 51:48 reserved for future 445 * 47:12 4k physical page base address 446 * 11:7 fragment 447 * 6 write 448 * 5 read 449 * 4 exe 450 * 3 Z 451 * 2 snooped 452 * 1 system 453 * 0 valid 454 * 455 * PDE format: 456 * 63 P 457 * 62:58 block fragment size 458 * 57 reserved 459 * 56 A 460 * 55:54 M 461 * 53:52 reserved 462 * 51:48 reserved for future 463 * 47:6 physical base address of PD or PTE 464 * 5:3 reserved 465 * 2 C 466 * 1 system 467 * 0 valid 468 */ 469 470 static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level, 471 uint64_t *addr, uint64_t *flags) 472 { 473 if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM)) 474 *addr = adev->vm_manager.vram_base_offset + *addr - 475 adev->gmc.vram_start; 476 BUG_ON(*addr & 0xFFFF00000000003FULL); 477 478 if (!adev->gmc.translate_further) 479 return; 480 481 if (level == AMDGPU_VM_PDB1) { 482 /* Set the block fragment size */ 483 if (!(*flags & AMDGPU_PDE_PTE_GFX12)) 484 *flags |= AMDGPU_PDE_BFS_GFX12(0x9); 485 486 } else if (level == AMDGPU_VM_PDB0) { 487 if (*flags & AMDGPU_PDE_PTE_GFX12) 488 *flags &= ~AMDGPU_PDE_PTE_GFX12; 489 } 490 } 491 492 static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, 493 struct amdgpu_vm *vm, 494 struct amdgpu_bo *bo, 495 uint32_t vm_flags, 496 uint64_t *flags) 497 { 498 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 499 *flags |= AMDGPU_PTE_EXECUTABLE; 500 else 501 *flags &= ~AMDGPU_PTE_EXECUTABLE; 502 503 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 504 case AMDGPU_VM_MTYPE_DEFAULT: 505 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 506 break; 507 case AMDGPU_VM_MTYPE_NC: 508 default: 509 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 510 break; 511 case AMDGPU_VM_MTYPE_UC: 512 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 513 break; 514 } 515 516 if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) 517 *flags |= AMDGPU_PTE_NOALLOC; 518 else 519 *flags &= ~AMDGPU_PTE_NOALLOC; 520 521 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 522 *flags |= AMDGPU_PTE_PRT_GFX12; 523 *flags |= AMDGPU_PTE_SNOOPED; 524 *flags |= AMDGPU_PTE_SYSTEM; 525 *flags |= AMDGPU_PTE_IS_PTE; 526 *flags &= ~AMDGPU_PTE_VALID; 527 } 528 529 if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) 530 *flags |= AMDGPU_PTE_DCC; 531 532 if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED) 533 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 534 } 535 536 static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) 537 { 538 return 0; 539 } 540 541 static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev) 542 { 543 unsigned int max_tex_channel_caches, alignment; 544 545 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && 546 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) 547 return 0; 548 549 max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches; 550 if (is_power_of_2(max_tex_channel_caches)) 551 alignment = (unsigned int)(max_tex_channel_caches / SZ_4); 552 else 553 alignment = roundup_pow_of_two(max_tex_channel_caches); 554 555 return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K); 556 } 557 558 static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { 559 .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, 560 .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, 561 .emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb, 562 .emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping, 563 .get_vm_pde = gmc_v12_0_get_vm_pde, 564 .get_vm_pte = gmc_v12_0_get_vm_pte, 565 .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, 566 .get_dcc_alignment = gmc_v12_0_get_dcc_alignment, 567 }; 568 569 static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev) 570 { 571 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; 572 } 573 574 static void gmc_v12_0_set_umc_funcs(struct amdgpu_device *adev) 575 { 576 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 577 case IP_VERSION(8, 14, 0): 578 adev->umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM; 579 adev->umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev); 580 adev->umc.node_inst_num = 0; 581 adev->umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev); 582 adev->umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET; 583 adev->umc.ras = &umc_v8_14_ras; 584 break; 585 default: 586 break; 587 } 588 } 589 590 591 static void gmc_v12_0_set_mmhub_funcs(struct amdgpu_device *adev) 592 { 593 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 594 case IP_VERSION(4, 1, 0): 595 adev->mmhub.funcs = &mmhub_v4_1_0_funcs; 596 break; 597 default: 598 break; 599 } 600 } 601 602 static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev) 603 { 604 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 605 case IP_VERSION(12, 0, 0): 606 case IP_VERSION(12, 0, 1): 607 adev->gfxhub.funcs = &gfxhub_v12_0_funcs; 608 break; 609 default: 610 break; 611 } 612 } 613 614 static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) 615 { 616 struct amdgpu_device *adev = ip_block->adev; 617 618 gmc_v12_0_set_gfxhub_funcs(adev); 619 gmc_v12_0_set_mmhub_funcs(adev); 620 gmc_v12_0_set_gmc_funcs(adev); 621 gmc_v12_0_set_irq_funcs(adev); 622 gmc_v12_0_set_umc_funcs(adev); 623 624 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 625 adev->gmc.shared_aperture_end = 626 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 627 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 628 adev->gmc.private_aperture_end = 629 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 630 631 return 0; 632 } 633 634 static int gmc_v12_0_late_init(struct amdgpu_ip_block *ip_block) 635 { 636 struct amdgpu_device *adev = ip_block->adev; 637 int r; 638 639 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 640 if (r) 641 return r; 642 643 r = amdgpu_gmc_ras_late_init(adev); 644 if (r) 645 return r; 646 647 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 648 } 649 650 static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, 651 struct amdgpu_gmc *mc) 652 { 653 u64 base = 0; 654 655 base = adev->mmhub.funcs->get_fb_location(adev); 656 657 amdgpu_gmc_set_agp_default(adev, mc); 658 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 659 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); 660 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 661 amdgpu_gmc_agp_location(adev, mc); 662 663 /* base offset of vram pages */ 664 if (amdgpu_sriov_vf(adev)) 665 adev->vm_manager.vram_base_offset = 0; 666 else 667 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 668 } 669 670 /** 671 * gmc_v12_0_mc_init - initialize the memory controller driver params 672 * 673 * @adev: amdgpu_device pointer 674 * 675 * Look up the amount of vram, vram width, and decide how to place 676 * vram and gart within the GPU's physical address space. 677 * Returns 0 for success. 678 */ 679 static int gmc_v12_0_mc_init(struct amdgpu_device *adev) 680 { 681 int r; 682 683 /* size in MB on si */ 684 adev->gmc.mc_vram_size = 685 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 686 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 687 688 if (!(adev->flags & AMD_IS_APU)) { 689 r = amdgpu_device_resize_fb_bar(adev); 690 if (r) 691 return r; 692 } 693 694 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 695 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 696 697 #ifdef CONFIG_X86_64 698 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 699 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 700 adev->gmc.aper_size = adev->gmc.real_vram_size; 701 } 702 #endif 703 /* In case the PCI BAR is larger than the actual amount of vram */ 704 adev->gmc.visible_vram_size = adev->gmc.aper_size; 705 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 706 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 707 708 /* set the gart size */ 709 if (amdgpu_gart_size == -1) { 710 adev->gmc.gart_size = 512ULL << 20; 711 } else 712 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 713 714 gmc_v12_0_vram_gtt_location(adev, &adev->gmc); 715 716 return 0; 717 } 718 719 static int gmc_v12_0_gart_init(struct amdgpu_device *adev) 720 { 721 int r; 722 723 if (adev->gart.bo) { 724 WARN(1, "PCIE GART already initialized\n"); 725 return 0; 726 } 727 728 /* Initialize common gart structure */ 729 r = amdgpu_gart_init(adev); 730 if (r) 731 return r; 732 733 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 734 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) | 735 AMDGPU_PTE_EXECUTABLE | 736 AMDGPU_PTE_IS_PTE; 737 738 return amdgpu_gart_table_vram_alloc(adev); 739 } 740 741 static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 742 { 743 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 744 struct amdgpu_device *adev = ip_block->adev; 745 746 adev->mmhub.funcs->init(adev); 747 748 adev->gfxhub.funcs->init(adev); 749 750 spin_lock_init(&adev->gmc.invalidate_lock); 751 752 r = amdgpu_atomfirmware_get_vram_info(adev, 753 &vram_width, &vram_type, &vram_vendor); 754 adev->gmc.vram_width = vram_width; 755 756 adev->gmc.vram_type = vram_type; 757 adev->gmc.vram_vendor = vram_vendor; 758 759 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 760 case IP_VERSION(12, 0, 0): 761 case IP_VERSION(12, 0, 1): 762 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 763 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 764 /* 765 * To fulfill 4-level page support, 766 * vm size is 256TB (48bit), maximum size, 767 * block size 512 (9bit) 768 */ 769 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 770 break; 771 default: 772 break; 773 } 774 775 /* This interrupt is VMC page fault.*/ 776 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 777 VMC_1_0__SRCID__VM_FAULT, 778 &adev->gmc.vm_fault); 779 780 if (r) 781 return r; 782 783 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 784 UTCL2_1_0__SRCID__FAULT, 785 &adev->gmc.vm_fault); 786 if (r) 787 return r; 788 789 if (!amdgpu_sriov_vf(adev)) { 790 /* interrupt sent to DF. */ 791 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 792 &adev->gmc.ecc_irq); 793 if (r) 794 return r; 795 } 796 797 /* 798 * Set the internal MC address mask This is the max address of the GPU's 799 * internal address space. 800 */ 801 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 802 803 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 804 if (r) { 805 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 806 return r; 807 } 808 809 adev->need_swiotlb = drm_need_swiotlb(44); 810 811 r = gmc_v12_0_mc_init(adev); 812 if (r) 813 return r; 814 815 amdgpu_gmc_get_vbios_allocations(adev); 816 817 /* Memory manager */ 818 r = amdgpu_bo_init(adev); 819 if (r) 820 return r; 821 822 r = gmc_v12_0_gart_init(adev); 823 if (r) 824 return r; 825 826 /* 827 * number of VMs 828 * VMID 0 is reserved for System 829 * amdgpu graphics/compute will use VMIDs 1-7 830 * amdkfd will use VMIDs 8-15 831 */ 832 adev->vm_manager.first_kfd_vmid = adev->gfx.disable_kq ? 1 : 8; 833 834 amdgpu_vm_manager_init(adev); 835 836 r = amdgpu_gmc_ras_sw_init(adev); 837 if (r) 838 return r; 839 840 return 0; 841 } 842 843 /** 844 * gmc_v12_0_gart_fini - vm fini callback 845 * 846 * @adev: amdgpu_device pointer 847 * 848 * Tears down the driver GART/VM setup (CIK). 849 */ 850 static void gmc_v12_0_gart_fini(struct amdgpu_device *adev) 851 { 852 amdgpu_gart_table_vram_free(adev); 853 } 854 855 static int gmc_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 856 { 857 struct amdgpu_device *adev = ip_block->adev; 858 859 amdgpu_vm_manager_fini(adev); 860 gmc_v12_0_gart_fini(adev); 861 amdgpu_gem_force_release(adev); 862 amdgpu_bo_fini(adev); 863 864 return 0; 865 } 866 867 static void gmc_v12_0_init_golden_registers(struct amdgpu_device *adev) 868 { 869 } 870 871 /** 872 * gmc_v12_0_gart_enable - gart enable 873 * 874 * @adev: amdgpu_device pointer 875 */ 876 static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) 877 { 878 int r; 879 bool value; 880 881 if (adev->gart.bo == NULL) { 882 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 883 return -EINVAL; 884 } 885 886 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 887 888 r = adev->mmhub.funcs->gart_enable(adev); 889 if (r) 890 return r; 891 892 /* Flush HDP after it is initialized */ 893 amdgpu_device_flush_hdp(adev, NULL); 894 895 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 896 897 adev->mmhub.funcs->set_fault_enable_default(adev, value); 898 gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 899 900 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 901 (unsigned)(adev->gmc.gart_size >> 20), 902 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 903 904 return 0; 905 } 906 907 static int gmc_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 908 { 909 int r; 910 struct amdgpu_device *adev = ip_block->adev; 911 912 /* The sequence of these two function calls matters.*/ 913 gmc_v12_0_init_golden_registers(adev); 914 915 r = gmc_v12_0_gart_enable(adev); 916 if (r) 917 return r; 918 919 if (adev->umc.funcs && adev->umc.funcs->init_registers) 920 adev->umc.funcs->init_registers(adev); 921 922 return 0; 923 } 924 925 /** 926 * gmc_v12_0_gart_disable - gart disable 927 * 928 * @adev: amdgpu_device pointer 929 * 930 * This disables all VM page table. 931 */ 932 static void gmc_v12_0_gart_disable(struct amdgpu_device *adev) 933 { 934 adev->mmhub.funcs->gart_disable(adev); 935 } 936 937 static int gmc_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 938 { 939 struct amdgpu_device *adev = ip_block->adev; 940 941 if (amdgpu_sriov_vf(adev)) { 942 /* full access mode, so don't touch any GMC register */ 943 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 944 return 0; 945 } 946 947 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 948 949 if (adev->gmc.ecc_irq.funcs && 950 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 951 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 952 953 gmc_v12_0_gart_disable(adev); 954 955 return 0; 956 } 957 958 static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block) 959 { 960 gmc_v12_0_hw_fini(ip_block); 961 962 return 0; 963 } 964 965 static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block) 966 { 967 int r; 968 969 r = gmc_v12_0_hw_init(ip_block); 970 if (r) 971 return r; 972 973 amdgpu_vmid_reset_all(ip_block->adev); 974 975 return 0; 976 } 977 978 static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 979 { 980 /* MC is always ready in GMC v11.*/ 981 return true; 982 } 983 984 static int gmc_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 985 { 986 /* There is no need to wait for MC idle in GMC v11.*/ 987 return 0; 988 } 989 990 static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 991 enum amd_clockgating_state state) 992 { 993 int r; 994 struct amdgpu_device *adev = ip_block->adev; 995 996 r = adev->mmhub.funcs->set_clockgating(adev, state); 997 if (r) 998 return r; 999 1000 return athub_v4_1_0_set_clockgating(adev, state); 1001 } 1002 1003 static void gmc_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1004 { 1005 struct amdgpu_device *adev = ip_block->adev; 1006 1007 adev->mmhub.funcs->get_clockgating(adev, flags); 1008 1009 athub_v4_1_0_get_clockgating(adev, flags); 1010 } 1011 1012 static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1013 enum amd_powergating_state state) 1014 { 1015 return 0; 1016 } 1017 1018 const struct amd_ip_funcs gmc_v12_0_ip_funcs = { 1019 .name = "gmc_v12_0", 1020 .early_init = gmc_v12_0_early_init, 1021 .sw_init = gmc_v12_0_sw_init, 1022 .hw_init = gmc_v12_0_hw_init, 1023 .late_init = gmc_v12_0_late_init, 1024 .sw_fini = gmc_v12_0_sw_fini, 1025 .hw_fini = gmc_v12_0_hw_fini, 1026 .suspend = gmc_v12_0_suspend, 1027 .resume = gmc_v12_0_resume, 1028 .is_idle = gmc_v12_0_is_idle, 1029 .wait_for_idle = gmc_v12_0_wait_for_idle, 1030 .set_clockgating_state = gmc_v12_0_set_clockgating_state, 1031 .set_powergating_state = gmc_v12_0_set_powergating_state, 1032 .get_clockgating_state = gmc_v12_0_get_clockgating_state, 1033 }; 1034 1035 const struct amdgpu_ip_block_version gmc_v12_0_ip_block = { 1036 .type = AMD_IP_BLOCK_TYPE_GMC, 1037 .major = 12, 1038 .minor = 0, 1039 .rev = 0, 1040 .funcs = &gmc_v12_0_ip_funcs, 1041 }; 1042