1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v12_0.h" 31 #include "athub/athub_4_1_0_sh_mask.h" 32 #include "athub/athub_4_1_0_offset.h" 33 #include "oss/osssys_7_0_0_offset.h" 34 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 35 #include "soc24_enum.h" 36 #include "soc24.h" 37 #include "soc15d.h" 38 #include "soc15_common.h" 39 #include "nbif_v6_3_1.h" 40 #include "gfxhub_v12_0.h" 41 #include "mmhub_v4_1_0.h" 42 #include "athub_v4_1_0.h" 43 #include "umc_v8_14.h" 44 45 static int gmc_v12_0_ecc_interrupt_state(struct amdgpu_device *adev, 46 struct amdgpu_irq_src *src, 47 unsigned type, 48 enum amdgpu_interrupt_state state) 49 { 50 return 0; 51 } 52 53 static int gmc_v12_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, unsigned type, 55 enum amdgpu_interrupt_state state) 56 { 57 switch (state) { 58 case AMDGPU_IRQ_STATE_DISABLE: 59 /* MM HUB */ 60 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 61 /* GFX HUB */ 62 /* This works because this interrupt is only 63 * enabled at init/resume and disabled in 64 * fini/suspend, so the overall state doesn't 65 * change over the course of suspend/resume. 66 */ 67 if (!adev->in_s0ix) 68 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 69 break; 70 case AMDGPU_IRQ_STATE_ENABLE: 71 /* MM HUB */ 72 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 73 /* GFX HUB */ 74 /* This works because this interrupt is only 75 * enabled at init/resume and disabled in 76 * fini/suspend, so the overall state doesn't 77 * change over the course of suspend/resume. 78 */ 79 if (!adev->in_s0ix) 80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 81 break; 82 default: 83 break; 84 } 85 86 return 0; 87 } 88 89 static int gmc_v12_0_process_interrupt(struct amdgpu_device *adev, 90 struct amdgpu_irq_src *source, 91 struct amdgpu_iv_entry *entry) 92 { 93 struct amdgpu_vmhub *hub; 94 uint32_t status = 0; 95 u64 addr; 96 97 addr = (u64)entry->src_data[0] << 12; 98 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 99 100 if (entry->client_id == SOC21_IH_CLIENTID_VMC) 101 hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 102 else 103 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 104 105 if (!amdgpu_sriov_vf(adev)) { 106 /* 107 * Issue a dummy read to wait for the status register to 108 * be updated to avoid reading an incorrect value due to 109 * the new fast GRBM interface. 110 */ 111 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 112 RREG32(hub->vm_l2_pro_fault_status); 113 114 status = RREG32(hub->vm_l2_pro_fault_status); 115 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 116 117 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 118 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 119 } 120 121 if (printk_ratelimit()) { 122 struct amdgpu_task_info *task_info; 123 124 dev_err(adev->dev, 125 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 126 entry->vmid_src ? "mmhub" : "gfxhub", 127 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 128 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 129 if (task_info) { 130 amdgpu_vm_print_task_info(adev, task_info); 131 amdgpu_vm_put_task_info(task_info); 132 } 133 134 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 135 addr, entry->client_id); 136 137 /* Only print L2 fault status if the status register could be read and 138 * contains useful information 139 */ 140 if (status != 0) 141 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 142 } 143 144 return 0; 145 } 146 147 static const struct amdgpu_irq_src_funcs gmc_v12_0_irq_funcs = { 148 .set = gmc_v12_0_vm_fault_interrupt_state, 149 .process = gmc_v12_0_process_interrupt, 150 }; 151 152 static const struct amdgpu_irq_src_funcs gmc_v12_0_ecc_funcs = { 153 .set = gmc_v12_0_ecc_interrupt_state, 154 .process = amdgpu_umc_process_ecc_irq, 155 }; 156 157 static void gmc_v12_0_set_irq_funcs(struct amdgpu_device *adev) 158 { 159 adev->gmc.vm_fault.num_types = 1; 160 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; 161 162 if (!amdgpu_sriov_vf(adev)) { 163 adev->gmc.ecc_irq.num_types = 1; 164 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; 165 } 166 } 167 168 /** 169 * gmc_v12_0_use_invalidate_semaphore - judge whether to use semaphore 170 * 171 * @adev: amdgpu_device pointer 172 * @vmhub: vmhub type 173 * 174 */ 175 static bool gmc_v12_0_use_invalidate_semaphore(struct amdgpu_device *adev, 176 uint32_t vmhub) 177 { 178 return ((vmhub == AMDGPU_MMHUB0(0)) && 179 (!amdgpu_sriov_vf(adev))); 180 } 181 182 static bool gmc_v12_0_get_vmid_pasid_mapping_info( 183 struct amdgpu_device *adev, 184 uint8_t vmid, uint16_t *p_pasid) 185 { 186 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 187 188 return !!(*p_pasid); 189 } 190 191 /* 192 * GART 193 * VMID 0 is the physical GPU addresses as used by the kernel. 194 * VMIDs 1-15 are used for userspace clients and are handled 195 * by the amdgpu vm/hsa code. 196 */ 197 198 static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 199 unsigned int vmhub, uint32_t flush_type) 200 { 201 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub); 202 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 203 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 204 u32 tmp; 205 /* Use register 17 for GART */ 206 const unsigned eng = 17; 207 unsigned int i; 208 unsigned char hub_ip = 0; 209 210 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 211 GC_HWIP : MMHUB_HWIP; 212 213 spin_lock(&adev->gmc.invalidate_lock); 214 /* 215 * It may lose gpuvm invalidate acknowldege state across power-gating 216 * off cycle, add semaphore acquire before invalidation and semaphore 217 * release after invalidation to avoid entering power gated state 218 * to WA the Issue 219 */ 220 221 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 222 if (use_semaphore) { 223 for (i = 0; i < adev->usec_timeout; i++) { 224 /* a read return value of 1 means semaphore acuqire */ 225 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 226 hub->eng_distance * eng, hub_ip); 227 if (tmp & 0x1) 228 break; 229 udelay(1); 230 } 231 232 if (i >= adev->usec_timeout) 233 dev_err(adev->dev, 234 "Timeout waiting for sem acquire in VM flush!\n"); 235 } 236 237 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 238 239 /* Wait for ACK with a delay.*/ 240 for (i = 0; i < adev->usec_timeout; i++) { 241 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 242 hub->eng_distance * eng, hub_ip); 243 tmp &= 1 << vmid; 244 if (tmp) 245 break; 246 247 udelay(1); 248 } 249 250 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 251 if (use_semaphore) 252 /* 253 * add semaphore release after invalidation, 254 * write with 0 means semaphore release 255 */ 256 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 257 hub->eng_distance * eng, 0, hub_ip); 258 259 /* Issue additional private vm invalidation to MMHUB */ 260 if ((vmhub != AMDGPU_GFXHUB(0)) && 261 (hub->vm_l2_bank_select_reserved_cid2) && 262 !amdgpu_sriov_vf(adev)) { 263 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 264 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 265 inv_req |= (1 << 25); 266 /* Issue private invalidation */ 267 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 268 /* Read back to ensure invalidation is done*/ 269 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 270 } 271 272 spin_unlock(&adev->gmc.invalidate_lock); 273 274 if (i < adev->usec_timeout) 275 return; 276 277 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 278 } 279 280 /** 281 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback 282 * 283 * @adev: amdgpu_device pointer 284 * @vmid: vm instance to flush 285 * @vmhub: which hub to flush 286 * @flush_type: the flush type 287 * 288 * Flush the TLB for the requested page table. 289 */ 290 static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 291 uint32_t vmhub, uint32_t flush_type) 292 { 293 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 294 return; 295 296 /* flush hdp cache */ 297 amdgpu_device_flush_hdp(adev, NULL); 298 299 /* This is necessary for SRIOV as well as for GFXOFF to function 300 * properly under bare metal 301 */ 302 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) && 303 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 304 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 305 const unsigned eng = 17; 306 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 307 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 308 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 309 310 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 311 1 << vmid, GET_INST(GC, 0)); 312 return; 313 } 314 315 mutex_lock(&adev->mman.gtt_window_lock); 316 gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0); 317 mutex_unlock(&adev->mman.gtt_window_lock); 318 return; 319 } 320 321 /** 322 * gmc_v12_0_flush_gpu_tlb_pasid - tlb flush via pasid 323 * 324 * @adev: amdgpu_device pointer 325 * @pasid: pasid to be flush 326 * @flush_type: the flush type 327 * @all_hub: flush all hubs 328 * @inst: is used to select which instance of KIQ to use for the invalidation 329 * 330 * Flush the TLB for the requested pasid. 331 */ 332 static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 333 uint16_t pasid, uint32_t flush_type, 334 bool all_hub, uint32_t inst) 335 { 336 uint16_t queried; 337 int vmid, i; 338 339 for (vmid = 1; vmid < 16; vmid++) { 340 bool valid; 341 342 valid = gmc_v12_0_get_vmid_pasid_mapping_info(adev, vmid, 343 &queried); 344 if (!valid || queried != pasid) 345 continue; 346 347 if (all_hub) { 348 for_each_set_bit(i, adev->vmhubs_mask, 349 AMDGPU_MAX_VMHUBS) 350 gmc_v12_0_flush_gpu_tlb(adev, vmid, i, 351 flush_type); 352 } else { 353 gmc_v12_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 354 flush_type); 355 } 356 } 357 } 358 359 static uint64_t gmc_v12_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 360 unsigned vmid, uint64_t pd_addr) 361 { 362 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 363 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 364 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 365 unsigned eng = ring->vm_inv_eng; 366 367 /* 368 * It may lose gpuvm invalidate acknowldege state across power-gating 369 * off cycle, add semaphore acquire before invalidation and semaphore 370 * release after invalidation to avoid entering power gated state 371 * to WA the Issue 372 */ 373 374 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 375 if (use_semaphore) 376 /* a read return value of 1 means semaphore acuqire */ 377 amdgpu_ring_emit_reg_wait(ring, 378 hub->vm_inv_eng0_sem + 379 hub->eng_distance * eng, 0x1, 0x1); 380 381 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 382 (hub->ctx_addr_distance * vmid), 383 lower_32_bits(pd_addr)); 384 385 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 386 (hub->ctx_addr_distance * vmid), 387 upper_32_bits(pd_addr)); 388 389 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 390 hub->eng_distance * eng, 391 hub->vm_inv_eng0_ack + 392 hub->eng_distance * eng, 393 req, 1 << vmid); 394 395 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 396 if (use_semaphore) 397 /* 398 * add semaphore release after invalidation, 399 * write with 0 means semaphore release 400 */ 401 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 402 hub->eng_distance * eng, 0); 403 404 return pd_addr; 405 } 406 407 static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 408 unsigned pasid) 409 { 410 struct amdgpu_device *adev = ring->adev; 411 uint32_t reg; 412 413 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 414 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 415 else 416 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 417 418 amdgpu_ring_emit_wreg(ring, reg, pasid); 419 } 420 421 /* 422 * PTE format: 423 * 63 P 424 * 62:59 reserved 425 * 58 D 426 * 57 G 427 * 56 T 428 * 55:54 M 429 * 53:52 SW 430 * 51:48 reserved for future 431 * 47:12 4k physical page base address 432 * 11:7 fragment 433 * 6 write 434 * 5 read 435 * 4 exe 436 * 3 Z 437 * 2 snooped 438 * 1 system 439 * 0 valid 440 * 441 * PDE format: 442 * 63 P 443 * 62:58 block fragment size 444 * 57 reserved 445 * 56 A 446 * 55:54 M 447 * 53:52 reserved 448 * 51:48 reserved for future 449 * 47:6 physical base address of PD or PTE 450 * 5:3 reserved 451 * 2 C 452 * 1 system 453 * 0 valid 454 */ 455 456 static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level, 457 uint64_t *addr, uint64_t *flags) 458 { 459 if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM)) 460 *addr = adev->vm_manager.vram_base_offset + *addr - 461 adev->gmc.vram_start; 462 BUG_ON(*addr & 0xFFFF00000000003FULL); 463 464 if (!adev->gmc.translate_further) 465 return; 466 467 if (level == AMDGPU_VM_PDB1) { 468 /* Set the block fragment size */ 469 if (!(*flags & AMDGPU_PDE_PTE_GFX12)) 470 *flags |= AMDGPU_PDE_BFS_GFX12(0x9); 471 472 } else if (level == AMDGPU_VM_PDB0) { 473 if (*flags & AMDGPU_PDE_PTE_GFX12) 474 *flags &= ~AMDGPU_PDE_PTE_GFX12; 475 } 476 } 477 478 static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, 479 struct amdgpu_vm *vm, 480 struct amdgpu_bo *bo, 481 uint32_t vm_flags, 482 uint64_t *flags) 483 { 484 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 485 *flags |= AMDGPU_PTE_EXECUTABLE; 486 else 487 *flags &= ~AMDGPU_PTE_EXECUTABLE; 488 489 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 490 case AMDGPU_VM_MTYPE_DEFAULT: 491 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 492 break; 493 case AMDGPU_VM_MTYPE_NC: 494 default: 495 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); 496 break; 497 case AMDGPU_VM_MTYPE_UC: 498 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 499 break; 500 } 501 502 if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) 503 *flags |= AMDGPU_PTE_NOALLOC; 504 else 505 *flags &= ~AMDGPU_PTE_NOALLOC; 506 507 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 508 *flags |= AMDGPU_PTE_SNOOPED; 509 *flags |= AMDGPU_PTE_SYSTEM; 510 *flags |= AMDGPU_PTE_IS_PTE; 511 *flags &= ~AMDGPU_PTE_VALID; 512 } 513 514 if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) 515 *flags |= AMDGPU_PTE_DCC; 516 517 if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED) 518 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 519 } 520 521 static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) 522 { 523 return 0; 524 } 525 526 static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev) 527 { 528 unsigned int max_tex_channel_caches, alignment; 529 530 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && 531 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) 532 return 0; 533 534 max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches; 535 if (is_power_of_2(max_tex_channel_caches)) 536 alignment = (unsigned int)(max_tex_channel_caches / SZ_4); 537 else 538 alignment = roundup_pow_of_two(max_tex_channel_caches); 539 540 return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K); 541 } 542 543 static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { 544 .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, 545 .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, 546 .emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb, 547 .emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping, 548 .get_vm_pde = gmc_v12_0_get_vm_pde, 549 .get_vm_pte = gmc_v12_0_get_vm_pte, 550 .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, 551 .get_dcc_alignment = gmc_v12_0_get_dcc_alignment, 552 }; 553 554 static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev) 555 { 556 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; 557 } 558 559 static void gmc_v12_0_set_umc_funcs(struct amdgpu_device *adev) 560 { 561 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 562 case IP_VERSION(8, 14, 0): 563 adev->umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM; 564 adev->umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev); 565 adev->umc.node_inst_num = 0; 566 adev->umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev); 567 adev->umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET; 568 adev->umc.ras = &umc_v8_14_ras; 569 break; 570 default: 571 break; 572 } 573 } 574 575 576 static void gmc_v12_0_set_mmhub_funcs(struct amdgpu_device *adev) 577 { 578 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 579 case IP_VERSION(4, 1, 0): 580 adev->mmhub.funcs = &mmhub_v4_1_0_funcs; 581 break; 582 default: 583 break; 584 } 585 } 586 587 static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev) 588 { 589 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 590 case IP_VERSION(12, 0, 0): 591 case IP_VERSION(12, 0, 1): 592 adev->gfxhub.funcs = &gfxhub_v12_0_funcs; 593 break; 594 default: 595 break; 596 } 597 } 598 599 static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) 600 { 601 struct amdgpu_device *adev = ip_block->adev; 602 603 gmc_v12_0_set_gfxhub_funcs(adev); 604 gmc_v12_0_set_mmhub_funcs(adev); 605 gmc_v12_0_set_gmc_funcs(adev); 606 gmc_v12_0_set_irq_funcs(adev); 607 gmc_v12_0_set_umc_funcs(adev); 608 609 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 610 adev->gmc.shared_aperture_end = 611 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 612 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 613 adev->gmc.private_aperture_end = 614 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 615 616 return 0; 617 } 618 619 static int gmc_v12_0_late_init(struct amdgpu_ip_block *ip_block) 620 { 621 struct amdgpu_device *adev = ip_block->adev; 622 int r; 623 624 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 625 if (r) 626 return r; 627 628 r = amdgpu_gmc_ras_late_init(adev); 629 if (r) 630 return r; 631 632 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 633 } 634 635 static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, 636 struct amdgpu_gmc *mc) 637 { 638 u64 base = 0; 639 640 base = adev->mmhub.funcs->get_fb_location(adev); 641 642 amdgpu_gmc_set_agp_default(adev, mc); 643 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 644 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); 645 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 646 amdgpu_gmc_agp_location(adev, mc); 647 648 /* base offset of vram pages */ 649 if (amdgpu_sriov_vf(adev)) 650 adev->vm_manager.vram_base_offset = 0; 651 else 652 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 653 } 654 655 /** 656 * gmc_v12_0_mc_init - initialize the memory controller driver params 657 * 658 * @adev: amdgpu_device pointer 659 * 660 * Look up the amount of vram, vram width, and decide how to place 661 * vram and gart within the GPU's physical address space. 662 * Returns 0 for success. 663 */ 664 static int gmc_v12_0_mc_init(struct amdgpu_device *adev) 665 { 666 int r; 667 668 /* size in MB on si */ 669 adev->gmc.mc_vram_size = 670 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 671 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 672 673 if (!(adev->flags & AMD_IS_APU)) { 674 r = amdgpu_device_resize_fb_bar(adev); 675 if (r) 676 return r; 677 } 678 679 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 680 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 681 682 #ifdef CONFIG_X86_64 683 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 684 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 685 adev->gmc.aper_size = adev->gmc.real_vram_size; 686 } 687 #endif 688 /* In case the PCI BAR is larger than the actual amount of vram */ 689 adev->gmc.visible_vram_size = adev->gmc.aper_size; 690 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 691 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 692 693 /* set the gart size */ 694 if (amdgpu_gart_size == -1) { 695 adev->gmc.gart_size = 512ULL << 20; 696 } else 697 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 698 699 gmc_v12_0_vram_gtt_location(adev, &adev->gmc); 700 701 return 0; 702 } 703 704 static int gmc_v12_0_gart_init(struct amdgpu_device *adev) 705 { 706 int r; 707 708 if (adev->gart.bo) { 709 WARN(1, "PCIE GART already initialized\n"); 710 return 0; 711 } 712 713 /* Initialize common gart structure */ 714 r = amdgpu_gart_init(adev); 715 if (r) 716 return r; 717 718 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 719 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) | 720 AMDGPU_PTE_EXECUTABLE | 721 AMDGPU_PTE_IS_PTE; 722 723 return amdgpu_gart_table_vram_alloc(adev); 724 } 725 726 static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 727 { 728 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 729 struct amdgpu_device *adev = ip_block->adev; 730 731 adev->mmhub.funcs->init(adev); 732 733 adev->gfxhub.funcs->init(adev); 734 735 spin_lock_init(&adev->gmc.invalidate_lock); 736 737 r = amdgpu_atomfirmware_get_vram_info(adev, 738 &vram_width, &vram_type, &vram_vendor); 739 adev->gmc.vram_width = vram_width; 740 741 adev->gmc.vram_type = vram_type; 742 adev->gmc.vram_vendor = vram_vendor; 743 744 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 745 case IP_VERSION(12, 0, 0): 746 case IP_VERSION(12, 0, 1): 747 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 748 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 749 /* 750 * To fulfill 4-level page support, 751 * vm size is 256TB (48bit), maximum size, 752 * block size 512 (9bit) 753 */ 754 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 755 break; 756 default: 757 break; 758 } 759 760 /* This interrupt is VMC page fault.*/ 761 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 762 VMC_1_0__SRCID__VM_FAULT, 763 &adev->gmc.vm_fault); 764 765 if (r) 766 return r; 767 768 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 769 UTCL2_1_0__SRCID__FAULT, 770 &adev->gmc.vm_fault); 771 if (r) 772 return r; 773 774 if (!amdgpu_sriov_vf(adev)) { 775 /* interrupt sent to DF. */ 776 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 777 &adev->gmc.ecc_irq); 778 if (r) 779 return r; 780 } 781 782 /* 783 * Set the internal MC address mask This is the max address of the GPU's 784 * internal address space. 785 */ 786 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 787 788 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 789 if (r) { 790 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 791 return r; 792 } 793 794 adev->need_swiotlb = drm_need_swiotlb(44); 795 796 r = gmc_v12_0_mc_init(adev); 797 if (r) 798 return r; 799 800 amdgpu_gmc_get_vbios_allocations(adev); 801 802 /* Memory manager */ 803 r = amdgpu_bo_init(adev); 804 if (r) 805 return r; 806 807 r = gmc_v12_0_gart_init(adev); 808 if (r) 809 return r; 810 811 /* 812 * number of VMs 813 * VMID 0 is reserved for System 814 * amdgpu graphics/compute will use VMIDs 1-7 815 * amdkfd will use VMIDs 8-15 816 */ 817 adev->vm_manager.first_kfd_vmid = adev->gfx.disable_kq ? 1 : 8; 818 819 amdgpu_vm_manager_init(adev); 820 821 r = amdgpu_gmc_ras_sw_init(adev); 822 if (r) 823 return r; 824 825 return 0; 826 } 827 828 /** 829 * gmc_v12_0_gart_fini - vm fini callback 830 * 831 * @adev: amdgpu_device pointer 832 * 833 * Tears down the driver GART/VM setup (CIK). 834 */ 835 static void gmc_v12_0_gart_fini(struct amdgpu_device *adev) 836 { 837 amdgpu_gart_table_vram_free(adev); 838 } 839 840 static int gmc_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 841 { 842 struct amdgpu_device *adev = ip_block->adev; 843 844 amdgpu_vm_manager_fini(adev); 845 gmc_v12_0_gart_fini(adev); 846 amdgpu_gem_force_release(adev); 847 amdgpu_bo_fini(adev); 848 849 return 0; 850 } 851 852 static void gmc_v12_0_init_golden_registers(struct amdgpu_device *adev) 853 { 854 } 855 856 /** 857 * gmc_v12_0_gart_enable - gart enable 858 * 859 * @adev: amdgpu_device pointer 860 */ 861 static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) 862 { 863 int r; 864 bool value; 865 866 if (adev->gart.bo == NULL) { 867 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 868 return -EINVAL; 869 } 870 871 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 872 873 r = adev->mmhub.funcs->gart_enable(adev); 874 if (r) 875 return r; 876 877 /* Flush HDP after it is initialized */ 878 amdgpu_device_flush_hdp(adev, NULL); 879 880 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 881 false : true; 882 883 adev->mmhub.funcs->set_fault_enable_default(adev, value); 884 gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 885 886 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 887 (unsigned)(adev->gmc.gart_size >> 20), 888 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 889 890 return 0; 891 } 892 893 static int gmc_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 894 { 895 int r; 896 struct amdgpu_device *adev = ip_block->adev; 897 898 /* The sequence of these two function calls matters.*/ 899 gmc_v12_0_init_golden_registers(adev); 900 901 r = gmc_v12_0_gart_enable(adev); 902 if (r) 903 return r; 904 905 if (adev->umc.funcs && adev->umc.funcs->init_registers) 906 adev->umc.funcs->init_registers(adev); 907 908 return 0; 909 } 910 911 /** 912 * gmc_v12_0_gart_disable - gart disable 913 * 914 * @adev: amdgpu_device pointer 915 * 916 * This disables all VM page table. 917 */ 918 static void gmc_v12_0_gart_disable(struct amdgpu_device *adev) 919 { 920 adev->mmhub.funcs->gart_disable(adev); 921 } 922 923 static int gmc_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 924 { 925 struct amdgpu_device *adev = ip_block->adev; 926 927 if (amdgpu_sriov_vf(adev)) { 928 /* full access mode, so don't touch any GMC register */ 929 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 930 return 0; 931 } 932 933 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 934 935 if (adev->gmc.ecc_irq.funcs && 936 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 937 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 938 939 gmc_v12_0_gart_disable(adev); 940 941 return 0; 942 } 943 944 static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block) 945 { 946 gmc_v12_0_hw_fini(ip_block); 947 948 return 0; 949 } 950 951 static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block) 952 { 953 int r; 954 955 r = gmc_v12_0_hw_init(ip_block); 956 if (r) 957 return r; 958 959 amdgpu_vmid_reset_all(ip_block->adev); 960 961 return 0; 962 } 963 964 static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 965 { 966 /* MC is always ready in GMC v11.*/ 967 return true; 968 } 969 970 static int gmc_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 971 { 972 /* There is no need to wait for MC idle in GMC v11.*/ 973 return 0; 974 } 975 976 static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 977 enum amd_clockgating_state state) 978 { 979 int r; 980 struct amdgpu_device *adev = ip_block->adev; 981 982 r = adev->mmhub.funcs->set_clockgating(adev, state); 983 if (r) 984 return r; 985 986 return athub_v4_1_0_set_clockgating(adev, state); 987 } 988 989 static void gmc_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 990 { 991 struct amdgpu_device *adev = ip_block->adev; 992 993 adev->mmhub.funcs->get_clockgating(adev, flags); 994 995 athub_v4_1_0_get_clockgating(adev, flags); 996 } 997 998 static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 999 enum amd_powergating_state state) 1000 { 1001 return 0; 1002 } 1003 1004 const struct amd_ip_funcs gmc_v12_0_ip_funcs = { 1005 .name = "gmc_v12_0", 1006 .early_init = gmc_v12_0_early_init, 1007 .sw_init = gmc_v12_0_sw_init, 1008 .hw_init = gmc_v12_0_hw_init, 1009 .late_init = gmc_v12_0_late_init, 1010 .sw_fini = gmc_v12_0_sw_fini, 1011 .hw_fini = gmc_v12_0_hw_fini, 1012 .suspend = gmc_v12_0_suspend, 1013 .resume = gmc_v12_0_resume, 1014 .is_idle = gmc_v12_0_is_idle, 1015 .wait_for_idle = gmc_v12_0_wait_for_idle, 1016 .set_clockgating_state = gmc_v12_0_set_clockgating_state, 1017 .set_powergating_state = gmc_v12_0_set_powergating_state, 1018 .get_clockgating_state = gmc_v12_0_get_clockgating_state, 1019 }; 1020 1021 const struct amdgpu_ip_block_version gmc_v12_0_ip_block = { 1022 .type = AMD_IP_BLOCK_TYPE_GMC, 1023 .major = 12, 1024 .minor = 0, 1025 .rev = 0, 1026 .funcs = &gmc_v12_0_ip_funcs, 1027 }; 1028