1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v12_0.h" 31 #include "athub/athub_4_1_0_sh_mask.h" 32 #include "athub/athub_4_1_0_offset.h" 33 #include "oss/osssys_7_0_0_offset.h" 34 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 35 #include "soc24_enum.h" 36 #include "soc24.h" 37 #include "soc15d.h" 38 #include "soc15_common.h" 39 #include "nbif_v6_3_1.h" 40 #include "gfxhub_v12_0.h" 41 #include "mmhub_v4_1_0.h" 42 #include "athub_v4_1_0.h" 43 44 45 static int gmc_v12_0_ecc_interrupt_state(struct amdgpu_device *adev, 46 struct amdgpu_irq_src *src, 47 unsigned type, 48 enum amdgpu_interrupt_state state) 49 { 50 return 0; 51 } 52 53 static int gmc_v12_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, unsigned type, 55 enum amdgpu_interrupt_state state) 56 { 57 switch (state) { 58 case AMDGPU_IRQ_STATE_DISABLE: 59 /* MM HUB */ 60 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 61 /* GFX HUB */ 62 /* This works because this interrupt is only 63 * enabled at init/resume and disabled in 64 * fini/suspend, so the overall state doesn't 65 * change over the course of suspend/resume. 66 */ 67 if (!adev->in_s0ix) 68 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 69 break; 70 case AMDGPU_IRQ_STATE_ENABLE: 71 /* MM HUB */ 72 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 73 /* GFX HUB */ 74 /* This works because this interrupt is only 75 * enabled at init/resume and disabled in 76 * fini/suspend, so the overall state doesn't 77 * change over the course of suspend/resume. 78 */ 79 if (!adev->in_s0ix) 80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 81 break; 82 default: 83 break; 84 } 85 86 return 0; 87 } 88 89 static int gmc_v12_0_process_interrupt(struct amdgpu_device *adev, 90 struct amdgpu_irq_src *source, 91 struct amdgpu_iv_entry *entry) 92 { 93 struct amdgpu_vmhub *hub; 94 uint32_t status = 0; 95 u64 addr; 96 97 addr = (u64)entry->src_data[0] << 12; 98 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 99 100 if (entry->client_id == SOC21_IH_CLIENTID_VMC) 101 hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 102 else 103 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 104 105 if (!amdgpu_sriov_vf(adev)) { 106 /* 107 * Issue a dummy read to wait for the status register to 108 * be updated to avoid reading an incorrect value due to 109 * the new fast GRBM interface. 110 */ 111 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 112 RREG32(hub->vm_l2_pro_fault_status); 113 114 status = RREG32(hub->vm_l2_pro_fault_status); 115 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 116 117 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 118 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 119 } 120 121 if (printk_ratelimit()) { 122 struct amdgpu_task_info *task_info; 123 124 dev_err(adev->dev, 125 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 126 entry->vmid_src ? "mmhub" : "gfxhub", 127 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 128 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 129 if (task_info) { 130 dev_err(adev->dev, 131 " in process %s pid %d thread %s pid %d)\n", 132 task_info->process_name, task_info->tgid, 133 task_info->task_name, task_info->pid); 134 amdgpu_vm_put_task_info(task_info); 135 } 136 137 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 138 addr, entry->client_id); 139 140 if (!amdgpu_sriov_vf(adev)) 141 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 142 } 143 144 return 0; 145 } 146 147 static const struct amdgpu_irq_src_funcs gmc_v12_0_irq_funcs = { 148 .set = gmc_v12_0_vm_fault_interrupt_state, 149 .process = gmc_v12_0_process_interrupt, 150 }; 151 152 static const struct amdgpu_irq_src_funcs gmc_v12_0_ecc_funcs = { 153 .set = gmc_v12_0_ecc_interrupt_state, 154 .process = amdgpu_umc_process_ecc_irq, 155 }; 156 157 static void gmc_v12_0_set_irq_funcs(struct amdgpu_device *adev) 158 { 159 adev->gmc.vm_fault.num_types = 1; 160 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; 161 162 if (!amdgpu_sriov_vf(adev)) { 163 adev->gmc.ecc_irq.num_types = 1; 164 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; 165 } 166 } 167 168 /** 169 * gmc_v12_0_use_invalidate_semaphore - judge whether to use semaphore 170 * 171 * @adev: amdgpu_device pointer 172 * @vmhub: vmhub type 173 * 174 */ 175 static bool gmc_v12_0_use_invalidate_semaphore(struct amdgpu_device *adev, 176 uint32_t vmhub) 177 { 178 return ((vmhub == AMDGPU_MMHUB0(0)) && 179 (!amdgpu_sriov_vf(adev))); 180 } 181 182 static bool gmc_v12_0_get_vmid_pasid_mapping_info( 183 struct amdgpu_device *adev, 184 uint8_t vmid, uint16_t *p_pasid) 185 { 186 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 187 188 return !!(*p_pasid); 189 } 190 191 /* 192 * GART 193 * VMID 0 is the physical GPU addresses as used by the kernel. 194 * VMIDs 1-15 are used for userspace clients and are handled 195 * by the amdgpu vm/hsa code. 196 */ 197 198 static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 199 unsigned int vmhub, uint32_t flush_type) 200 { 201 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub); 202 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 203 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 204 u32 tmp; 205 /* Use register 17 for GART */ 206 const unsigned eng = 17; 207 unsigned int i; 208 unsigned char hub_ip = 0; 209 210 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 211 GC_HWIP : MMHUB_HWIP; 212 213 spin_lock(&adev->gmc.invalidate_lock); 214 /* 215 * It may lose gpuvm invalidate acknowldege state across power-gating 216 * off cycle, add semaphore acquire before invalidation and semaphore 217 * release after invalidation to avoid entering power gated state 218 * to WA the Issue 219 */ 220 221 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 222 if (use_semaphore) { 223 for (i = 0; i < adev->usec_timeout; i++) { 224 /* a read return value of 1 means semaphore acuqire */ 225 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 226 hub->eng_distance * eng, hub_ip); 227 if (tmp & 0x1) 228 break; 229 udelay(1); 230 } 231 232 if (i >= adev->usec_timeout) 233 dev_err(adev->dev, 234 "Timeout waiting for sem acquire in VM flush!\n"); 235 } 236 237 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 238 239 /* Wait for ACK with a delay.*/ 240 for (i = 0; i < adev->usec_timeout; i++) { 241 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 242 hub->eng_distance * eng, hub_ip); 243 tmp &= 1 << vmid; 244 if (tmp) 245 break; 246 247 udelay(1); 248 } 249 250 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 251 if (use_semaphore) 252 /* 253 * add semaphore release after invalidation, 254 * write with 0 means semaphore release 255 */ 256 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 257 hub->eng_distance * eng, 0, hub_ip); 258 259 /* Issue additional private vm invalidation to MMHUB */ 260 if ((vmhub != AMDGPU_GFXHUB(0)) && 261 (hub->vm_l2_bank_select_reserved_cid2) && 262 !amdgpu_sriov_vf(adev)) { 263 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 264 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 265 inv_req |= (1 << 25); 266 /* Issue private invalidation */ 267 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 268 /* Read back to ensure invalidation is done*/ 269 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 270 } 271 272 spin_unlock(&adev->gmc.invalidate_lock); 273 274 if (i < adev->usec_timeout) 275 return; 276 277 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 278 } 279 280 /** 281 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback 282 * 283 * @adev: amdgpu_device pointer 284 * @vmid: vm instance to flush 285 * @vmhub: which hub to flush 286 * @flush_type: the flush type 287 * 288 * Flush the TLB for the requested page table. 289 */ 290 static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 291 uint32_t vmhub, uint32_t flush_type) 292 { 293 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 294 return; 295 296 /* flush hdp cache */ 297 adev->hdp.funcs->flush_hdp(adev, NULL); 298 299 /* This is necessary for SRIOV as well as for GFXOFF to function 300 * properly under bare metal 301 */ 302 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && 303 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 304 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 305 const unsigned eng = 17; 306 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 307 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 308 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 309 310 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 311 1 << vmid, GET_INST(GC, 0)); 312 return; 313 } 314 315 mutex_lock(&adev->mman.gtt_window_lock); 316 gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0); 317 mutex_unlock(&adev->mman.gtt_window_lock); 318 return; 319 } 320 321 /** 322 * gmc_v12_0_flush_gpu_tlb_pasid - tlb flush via pasid 323 * 324 * @adev: amdgpu_device pointer 325 * @pasid: pasid to be flush 326 * @flush_type: the flush type 327 * @all_hub: flush all hubs 328 * @inst: is used to select which instance of KIQ to use for the invalidation 329 * 330 * Flush the TLB for the requested pasid. 331 */ 332 static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 333 uint16_t pasid, uint32_t flush_type, 334 bool all_hub, uint32_t inst) 335 { 336 uint16_t queried; 337 int vmid, i; 338 339 for (vmid = 1; vmid < 16; vmid++) { 340 bool valid; 341 342 valid = gmc_v12_0_get_vmid_pasid_mapping_info(adev, vmid, 343 &queried); 344 if (!valid || queried != pasid) 345 continue; 346 347 if (all_hub) { 348 for_each_set_bit(i, adev->vmhubs_mask, 349 AMDGPU_MAX_VMHUBS) 350 gmc_v12_0_flush_gpu_tlb(adev, vmid, i, 351 flush_type); 352 } else { 353 gmc_v12_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 354 flush_type); 355 } 356 } 357 } 358 359 static uint64_t gmc_v12_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 360 unsigned vmid, uint64_t pd_addr) 361 { 362 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 363 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 364 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 365 unsigned eng = ring->vm_inv_eng; 366 367 /* 368 * It may lose gpuvm invalidate acknowldege state across power-gating 369 * off cycle, add semaphore acquire before invalidation and semaphore 370 * release after invalidation to avoid entering power gated state 371 * to WA the Issue 372 */ 373 374 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 375 if (use_semaphore) 376 /* a read return value of 1 means semaphore acuqire */ 377 amdgpu_ring_emit_reg_wait(ring, 378 hub->vm_inv_eng0_sem + 379 hub->eng_distance * eng, 0x1, 0x1); 380 381 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 382 (hub->ctx_addr_distance * vmid), 383 lower_32_bits(pd_addr)); 384 385 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 386 (hub->ctx_addr_distance * vmid), 387 upper_32_bits(pd_addr)); 388 389 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 390 hub->eng_distance * eng, 391 hub->vm_inv_eng0_ack + 392 hub->eng_distance * eng, 393 req, 1 << vmid); 394 395 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 396 if (use_semaphore) 397 /* 398 * add semaphore release after invalidation, 399 * write with 0 means semaphore release 400 */ 401 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 402 hub->eng_distance * eng, 0); 403 404 return pd_addr; 405 } 406 407 static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 408 unsigned pasid) 409 { 410 struct amdgpu_device *adev = ring->adev; 411 uint32_t reg; 412 413 /* MES fw manages IH_VMID_x_LUT updating */ 414 if (ring->is_mes_queue) 415 return; 416 417 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 418 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 419 else 420 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 421 422 amdgpu_ring_emit_wreg(ring, reg, pasid); 423 } 424 425 /* 426 * PTE format: 427 * 63 P 428 * 62:59 reserved 429 * 58 D 430 * 57 G 431 * 56 T 432 * 55:54 M 433 * 53:52 SW 434 * 51:48 reserved for future 435 * 47:12 4k physical page base address 436 * 11:7 fragment 437 * 6 write 438 * 5 read 439 * 4 exe 440 * 3 Z 441 * 2 snooped 442 * 1 system 443 * 0 valid 444 * 445 * PDE format: 446 * 63 P 447 * 62:58 block fragment size 448 * 57 reserved 449 * 56 A 450 * 55:54 M 451 * 53:52 reserved 452 * 51:48 reserved for future 453 * 47:6 physical base address of PD or PTE 454 * 5:3 reserved 455 * 2 C 456 * 1 system 457 * 0 valid 458 */ 459 460 static uint64_t gmc_v12_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 461 { 462 switch (flags) { 463 case AMDGPU_VM_MTYPE_DEFAULT: 464 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC); 465 case AMDGPU_VM_MTYPE_NC: 466 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC); 467 case AMDGPU_VM_MTYPE_WC: 468 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_WC); 469 case AMDGPU_VM_MTYPE_CC: 470 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_CC); 471 case AMDGPU_VM_MTYPE_UC: 472 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_UC); 473 default: 474 return AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC); 475 } 476 } 477 478 static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level, 479 uint64_t *addr, uint64_t *flags) 480 { 481 if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM)) 482 *addr = adev->vm_manager.vram_base_offset + *addr - 483 adev->gmc.vram_start; 484 BUG_ON(*addr & 0xFFFF00000000003FULL); 485 486 if (!adev->gmc.translate_further) 487 return; 488 489 if (level == AMDGPU_VM_PDB1) { 490 /* Set the block fragment size */ 491 if (!(*flags & AMDGPU_PDE_PTE_GFX12)) 492 *flags |= AMDGPU_PDE_BFS_GFX12(0x9); 493 494 } else if (level == AMDGPU_VM_PDB0) { 495 if (*flags & AMDGPU_PDE_PTE_GFX12) 496 *flags &= ~AMDGPU_PDE_PTE_GFX12; 497 } 498 } 499 500 static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, 501 struct amdgpu_bo_va_mapping *mapping, 502 uint64_t *flags) 503 { 504 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 505 struct amdgpu_device *bo_adev; 506 bool coherent, is_system; 507 508 509 *flags &= ~AMDGPU_PTE_EXECUTABLE; 510 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 511 512 *flags &= ~AMDGPU_PTE_MTYPE_GFX12_MASK; 513 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_GFX12_MASK); 514 515 if (mapping->flags & AMDGPU_PTE_PRT_GFX12) { 516 *flags |= AMDGPU_PTE_PRT_GFX12; 517 *flags |= AMDGPU_PTE_SNOOPED; 518 *flags |= AMDGPU_PTE_SYSTEM; 519 *flags &= ~AMDGPU_PTE_VALID; 520 } 521 522 if (!bo) 523 return; 524 525 if (bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 526 AMDGPU_GEM_CREATE_UNCACHED)) 527 *flags = (*flags & ~AMDGPU_PTE_MTYPE_GFX12_MASK) | 528 AMDGPU_PTE_MTYPE_GFX12(MTYPE_UC); 529 530 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); 531 coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; 532 is_system = (bo->tbo.resource->mem_type == TTM_PL_TT) || 533 (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT); 534 535 /* WA for HW bug */ 536 if (is_system || ((bo_adev != adev) && coherent)) 537 *flags |= AMDGPU_PTE_MTYPE_GFX12(MTYPE_NC); 538 539 } 540 541 static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) 542 { 543 return 0; 544 } 545 546 static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { 547 .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, 548 .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, 549 .emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb, 550 .emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping, 551 .map_mtype = gmc_v12_0_map_mtype, 552 .get_vm_pde = gmc_v12_0_get_vm_pde, 553 .get_vm_pte = gmc_v12_0_get_vm_pte, 554 .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, 555 }; 556 557 static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev) 558 { 559 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; 560 } 561 562 static void gmc_v12_0_set_umc_funcs(struct amdgpu_device *adev) 563 { 564 } 565 566 567 static void gmc_v12_0_set_mmhub_funcs(struct amdgpu_device *adev) 568 { 569 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 570 case IP_VERSION(4, 1, 0): 571 adev->mmhub.funcs = &mmhub_v4_1_0_funcs; 572 break; 573 default: 574 break; 575 } 576 } 577 578 static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev) 579 { 580 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 581 case IP_VERSION(12, 0, 0): 582 case IP_VERSION(12, 0, 1): 583 adev->gfxhub.funcs = &gfxhub_v12_0_funcs; 584 break; 585 default: 586 break; 587 } 588 } 589 590 static int gmc_v12_0_early_init(void *handle) 591 { 592 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 593 594 gmc_v12_0_set_gfxhub_funcs(adev); 595 gmc_v12_0_set_mmhub_funcs(adev); 596 gmc_v12_0_set_gmc_funcs(adev); 597 gmc_v12_0_set_irq_funcs(adev); 598 gmc_v12_0_set_umc_funcs(adev); 599 600 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 601 adev->gmc.shared_aperture_end = 602 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 603 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 604 adev->gmc.private_aperture_end = 605 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 606 607 return 0; 608 } 609 610 static int gmc_v12_0_late_init(void *handle) 611 { 612 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 613 int r; 614 615 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 616 if (r) 617 return r; 618 619 r = amdgpu_gmc_ras_late_init(adev); 620 if (r) 621 return r; 622 623 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 624 } 625 626 static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, 627 struct amdgpu_gmc *mc) 628 { 629 u64 base = 0; 630 631 base = adev->mmhub.funcs->get_fb_location(adev); 632 633 amdgpu_gmc_set_agp_default(adev, mc); 634 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 635 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); 636 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 637 amdgpu_gmc_agp_location(adev, mc); 638 639 /* base offset of vram pages */ 640 if (amdgpu_sriov_vf(adev)) 641 adev->vm_manager.vram_base_offset = 0; 642 else 643 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 644 } 645 646 /** 647 * gmc_v12_0_mc_init - initialize the memory controller driver params 648 * 649 * @adev: amdgpu_device pointer 650 * 651 * Look up the amount of vram, vram width, and decide how to place 652 * vram and gart within the GPU's physical address space. 653 * Returns 0 for success. 654 */ 655 static int gmc_v12_0_mc_init(struct amdgpu_device *adev) 656 { 657 int r; 658 659 /* size in MB on si */ 660 adev->gmc.mc_vram_size = 661 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 662 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 663 664 if (!(adev->flags & AMD_IS_APU)) { 665 r = amdgpu_device_resize_fb_bar(adev); 666 if (r) 667 return r; 668 } 669 670 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 671 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 672 673 #ifdef CONFIG_X86_64 674 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 675 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 676 adev->gmc.aper_size = adev->gmc.real_vram_size; 677 } 678 #endif 679 /* In case the PCI BAR is larger than the actual amount of vram */ 680 adev->gmc.visible_vram_size = adev->gmc.aper_size; 681 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 682 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 683 684 /* set the gart size */ 685 if (amdgpu_gart_size == -1) { 686 adev->gmc.gart_size = 512ULL << 20; 687 } else 688 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 689 690 gmc_v12_0_vram_gtt_location(adev, &adev->gmc); 691 692 return 0; 693 } 694 695 static int gmc_v12_0_gart_init(struct amdgpu_device *adev) 696 { 697 int r; 698 699 if (adev->gart.bo) { 700 WARN(1, "PCIE GART already initialized\n"); 701 return 0; 702 } 703 704 /* Initialize common gart structure */ 705 r = amdgpu_gart_init(adev); 706 if (r) 707 return r; 708 709 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 710 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(MTYPE_UC) | 711 AMDGPU_PTE_EXECUTABLE | 712 AMDGPU_PTE_IS_PTE; 713 714 return amdgpu_gart_table_vram_alloc(adev); 715 } 716 717 static int gmc_v12_0_sw_init(void *handle) 718 { 719 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 720 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 721 722 adev->mmhub.funcs->init(adev); 723 724 adev->gfxhub.funcs->init(adev); 725 726 spin_lock_init(&adev->gmc.invalidate_lock); 727 728 r = amdgpu_atomfirmware_get_vram_info(adev, 729 &vram_width, &vram_type, &vram_vendor); 730 adev->gmc.vram_width = vram_width; 731 732 adev->gmc.vram_type = vram_type; 733 adev->gmc.vram_vendor = vram_vendor; 734 735 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 736 case IP_VERSION(12, 0, 0): 737 case IP_VERSION(12, 0, 1): 738 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 739 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 740 /* 741 * To fulfill 4-level page support, 742 * vm size is 256TB (48bit), maximum size, 743 * block size 512 (9bit) 744 */ 745 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 746 break; 747 default: 748 break; 749 } 750 751 /* This interrupt is VMC page fault.*/ 752 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 753 VMC_1_0__SRCID__VM_FAULT, 754 &adev->gmc.vm_fault); 755 756 if (r) 757 return r; 758 759 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 760 UTCL2_1_0__SRCID__FAULT, 761 &adev->gmc.vm_fault); 762 if (r) 763 return r; 764 765 if (!amdgpu_sriov_vf(adev)) { 766 /* interrupt sent to DF. */ 767 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 768 &adev->gmc.ecc_irq); 769 if (r) 770 return r; 771 } 772 773 /* 774 * Set the internal MC address mask This is the max address of the GPU's 775 * internal address space. 776 */ 777 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 778 779 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 780 if (r) { 781 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 782 return r; 783 } 784 785 adev->need_swiotlb = drm_need_swiotlb(44); 786 787 r = gmc_v12_0_mc_init(adev); 788 if (r) 789 return r; 790 791 amdgpu_gmc_get_vbios_allocations(adev); 792 793 /* Memory manager */ 794 r = amdgpu_bo_init(adev); 795 if (r) 796 return r; 797 798 r = gmc_v12_0_gart_init(adev); 799 if (r) 800 return r; 801 802 /* 803 * number of VMs 804 * VMID 0 is reserved for System 805 * amdgpu graphics/compute will use VMIDs 1-7 806 * amdkfd will use VMIDs 8-15 807 */ 808 adev->vm_manager.first_kfd_vmid = 8; 809 810 amdgpu_vm_manager_init(adev); 811 812 return 0; 813 } 814 815 /** 816 * gmc_v12_0_gart_fini - vm fini callback 817 * 818 * @adev: amdgpu_device pointer 819 * 820 * Tears down the driver GART/VM setup (CIK). 821 */ 822 static void gmc_v12_0_gart_fini(struct amdgpu_device *adev) 823 { 824 amdgpu_gart_table_vram_free(adev); 825 } 826 827 static int gmc_v12_0_sw_fini(void *handle) 828 { 829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 830 831 amdgpu_vm_manager_fini(adev); 832 gmc_v12_0_gart_fini(adev); 833 amdgpu_gem_force_release(adev); 834 amdgpu_bo_fini(adev); 835 836 return 0; 837 } 838 839 static void gmc_v12_0_init_golden_registers(struct amdgpu_device *adev) 840 { 841 } 842 843 /** 844 * gmc_v12_0_gart_enable - gart enable 845 * 846 * @adev: amdgpu_device pointer 847 */ 848 static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) 849 { 850 int r; 851 bool value; 852 853 if (adev->gart.bo == NULL) { 854 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 855 return -EINVAL; 856 } 857 858 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 859 860 r = adev->mmhub.funcs->gart_enable(adev); 861 if (r) 862 return r; 863 864 /* Flush HDP after it is initialized */ 865 adev->hdp.funcs->flush_hdp(adev, NULL); 866 867 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 868 false : true; 869 870 adev->mmhub.funcs->set_fault_enable_default(adev, value); 871 gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 872 873 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 874 (unsigned)(adev->gmc.gart_size >> 20), 875 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 876 877 return 0; 878 } 879 880 static int gmc_v12_0_hw_init(void *handle) 881 { 882 int r; 883 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 884 885 /* The sequence of these two function calls matters.*/ 886 gmc_v12_0_init_golden_registers(adev); 887 888 r = gmc_v12_0_gart_enable(adev); 889 if (r) 890 return r; 891 892 if (adev->umc.funcs && adev->umc.funcs->init_registers) 893 adev->umc.funcs->init_registers(adev); 894 895 return 0; 896 } 897 898 /** 899 * gmc_v12_0_gart_disable - gart disable 900 * 901 * @adev: amdgpu_device pointer 902 * 903 * This disables all VM page table. 904 */ 905 static void gmc_v12_0_gart_disable(struct amdgpu_device *adev) 906 { 907 adev->mmhub.funcs->gart_disable(adev); 908 } 909 910 static int gmc_v12_0_hw_fini(void *handle) 911 { 912 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 913 914 if (amdgpu_sriov_vf(adev)) { 915 /* full access mode, so don't touch any GMC register */ 916 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 917 return 0; 918 } 919 920 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 921 922 if (adev->gmc.ecc_irq.funcs && 923 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 924 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 925 926 gmc_v12_0_gart_disable(adev); 927 928 return 0; 929 } 930 931 static int gmc_v12_0_suspend(void *handle) 932 { 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 gmc_v12_0_hw_fini(adev); 936 937 return 0; 938 } 939 940 static int gmc_v12_0_resume(void *handle) 941 { 942 int r; 943 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 944 945 r = gmc_v12_0_hw_init(adev); 946 if (r) 947 return r; 948 949 amdgpu_vmid_reset_all(adev); 950 951 return 0; 952 } 953 954 static bool gmc_v12_0_is_idle(void *handle) 955 { 956 /* MC is always ready in GMC v11.*/ 957 return true; 958 } 959 960 static int gmc_v12_0_wait_for_idle(void *handle) 961 { 962 /* There is no need to wait for MC idle in GMC v11.*/ 963 return 0; 964 } 965 966 static int gmc_v12_0_soft_reset(void *handle) 967 { 968 return 0; 969 } 970 971 static int gmc_v12_0_set_clockgating_state(void *handle, 972 enum amd_clockgating_state state) 973 { 974 int r; 975 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 976 977 r = adev->mmhub.funcs->set_clockgating(adev, state); 978 if (r) 979 return r; 980 981 return athub_v4_1_0_set_clockgating(adev, state); 982 } 983 984 static void gmc_v12_0_get_clockgating_state(void *handle, u64 *flags) 985 { 986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 987 988 adev->mmhub.funcs->get_clockgating(adev, flags); 989 990 athub_v4_1_0_get_clockgating(adev, flags); 991 } 992 993 static int gmc_v12_0_set_powergating_state(void *handle, 994 enum amd_powergating_state state) 995 { 996 return 0; 997 } 998 999 const struct amd_ip_funcs gmc_v12_0_ip_funcs = { 1000 .name = "gmc_v12_0", 1001 .early_init = gmc_v12_0_early_init, 1002 .sw_init = gmc_v12_0_sw_init, 1003 .hw_init = gmc_v12_0_hw_init, 1004 .late_init = gmc_v12_0_late_init, 1005 .sw_fini = gmc_v12_0_sw_fini, 1006 .hw_fini = gmc_v12_0_hw_fini, 1007 .suspend = gmc_v12_0_suspend, 1008 .resume = gmc_v12_0_resume, 1009 .is_idle = gmc_v12_0_is_idle, 1010 .wait_for_idle = gmc_v12_0_wait_for_idle, 1011 .soft_reset = gmc_v12_0_soft_reset, 1012 .set_clockgating_state = gmc_v12_0_set_clockgating_state, 1013 .set_powergating_state = gmc_v12_0_set_powergating_state, 1014 .get_clockgating_state = gmc_v12_0_get_clockgating_state, 1015 }; 1016 1017 const struct amdgpu_ip_block_version gmc_v12_0_ip_block = { 1018 .type = AMD_IP_BLOCK_TYPE_GMC, 1019 .major = 12, 1020 .minor = 0, 1021 .rev = 0, 1022 .funcs = &gmc_v12_0_ip_funcs, 1023 }; 1024