1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v12_0.h" 31 #include "athub/athub_4_1_0_sh_mask.h" 32 #include "athub/athub_4_1_0_offset.h" 33 #include "oss/osssys_7_0_0_offset.h" 34 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 35 #include "soc24_enum.h" 36 #include "soc24.h" 37 #include "soc15d.h" 38 #include "soc15_common.h" 39 #include "nbif_v6_3_1.h" 40 #include "gfxhub_v12_0.h" 41 #include "mmhub_v4_1_0.h" 42 #include "athub_v4_1_0.h" 43 #include "umc_v8_14.h" 44 45 static int gmc_v12_0_ecc_interrupt_state(struct amdgpu_device *adev, 46 struct amdgpu_irq_src *src, 47 unsigned type, 48 enum amdgpu_interrupt_state state) 49 { 50 return 0; 51 } 52 53 static int gmc_v12_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, unsigned type, 55 enum amdgpu_interrupt_state state) 56 { 57 switch (state) { 58 case AMDGPU_IRQ_STATE_DISABLE: 59 /* MM HUB */ 60 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 61 /* GFX HUB */ 62 /* This works because this interrupt is only 63 * enabled at init/resume and disabled in 64 * fini/suspend, so the overall state doesn't 65 * change over the course of suspend/resume. 66 */ 67 if (!adev->in_s0ix) 68 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 69 break; 70 case AMDGPU_IRQ_STATE_ENABLE: 71 /* MM HUB */ 72 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 73 /* GFX HUB */ 74 /* This works because this interrupt is only 75 * enabled at init/resume and disabled in 76 * fini/suspend, so the overall state doesn't 77 * change over the course of suspend/resume. 78 */ 79 if (!adev->in_s0ix) 80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 81 break; 82 default: 83 break; 84 } 85 86 return 0; 87 } 88 89 static int gmc_v12_0_process_interrupt(struct amdgpu_device *adev, 90 struct amdgpu_irq_src *source, 91 struct amdgpu_iv_entry *entry) 92 { 93 struct amdgpu_vmhub *hub; 94 uint32_t status = 0; 95 u64 addr; 96 97 addr = (u64)entry->src_data[0] << 12; 98 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 99 100 if (entry->client_id == SOC21_IH_CLIENTID_VMC) 101 hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 102 else 103 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 104 105 if (!amdgpu_sriov_vf(adev)) { 106 /* 107 * Issue a dummy read to wait for the status register to 108 * be updated to avoid reading an incorrect value due to 109 * the new fast GRBM interface. 110 */ 111 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 112 RREG32(hub->vm_l2_pro_fault_status); 113 114 status = RREG32(hub->vm_l2_pro_fault_status); 115 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 116 117 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 118 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 119 } 120 121 if (printk_ratelimit()) { 122 struct amdgpu_task_info *task_info; 123 124 dev_err(adev->dev, 125 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 126 entry->vmid_src ? "mmhub" : "gfxhub", 127 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 128 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 129 if (task_info) { 130 amdgpu_vm_print_task_info(adev, task_info); 131 amdgpu_vm_put_task_info(task_info); 132 } 133 134 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 135 addr, entry->client_id); 136 137 /* Only print L2 fault status if the status register could be read and 138 * contains useful information 139 */ 140 if (status != 0) 141 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 142 } 143 144 return 0; 145 } 146 147 static const struct amdgpu_irq_src_funcs gmc_v12_0_irq_funcs = { 148 .set = gmc_v12_0_vm_fault_interrupt_state, 149 .process = gmc_v12_0_process_interrupt, 150 }; 151 152 static const struct amdgpu_irq_src_funcs gmc_v12_0_ecc_funcs = { 153 .set = gmc_v12_0_ecc_interrupt_state, 154 .process = amdgpu_umc_process_ecc_irq, 155 }; 156 157 static void gmc_v12_0_set_irq_funcs(struct amdgpu_device *adev) 158 { 159 adev->gmc.vm_fault.num_types = 1; 160 adev->gmc.vm_fault.funcs = &gmc_v12_0_irq_funcs; 161 162 if (!amdgpu_sriov_vf(adev)) { 163 adev->gmc.ecc_irq.num_types = 1; 164 adev->gmc.ecc_irq.funcs = &gmc_v12_0_ecc_funcs; 165 } 166 } 167 168 /** 169 * gmc_v12_0_use_invalidate_semaphore - judge whether to use semaphore 170 * 171 * @adev: amdgpu_device pointer 172 * @vmhub: vmhub type 173 * 174 */ 175 static bool gmc_v12_0_use_invalidate_semaphore(struct amdgpu_device *adev, 176 uint32_t vmhub) 177 { 178 return ((vmhub == AMDGPU_MMHUB0(0)) && 179 (!amdgpu_sriov_vf(adev))); 180 } 181 182 static bool gmc_v12_0_get_vmid_pasid_mapping_info( 183 struct amdgpu_device *adev, 184 uint8_t vmid, uint16_t *p_pasid) 185 { 186 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 187 188 return !!(*p_pasid); 189 } 190 191 /* 192 * GART 193 * VMID 0 is the physical GPU addresses as used by the kernel. 194 * VMIDs 1-15 are used for userspace clients and are handled 195 * by the amdgpu vm/hsa code. 196 */ 197 198 static void gmc_v12_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 199 unsigned int vmhub, uint32_t flush_type) 200 { 201 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(adev, vmhub); 202 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 203 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 204 u32 tmp; 205 /* Use register 17 for GART */ 206 const unsigned eng = 17; 207 unsigned int i; 208 unsigned char hub_ip = 0; 209 210 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 211 GC_HWIP : MMHUB_HWIP; 212 213 spin_lock(&adev->gmc.invalidate_lock); 214 /* 215 * It may lose gpuvm invalidate acknowldege state across power-gating 216 * off cycle, add semaphore acquire before invalidation and semaphore 217 * release after invalidation to avoid entering power gated state 218 * to WA the Issue 219 */ 220 221 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 222 if (use_semaphore) { 223 for (i = 0; i < adev->usec_timeout; i++) { 224 /* a read return value of 1 means semaphore acuqire */ 225 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 226 hub->eng_distance * eng, hub_ip); 227 if (tmp & 0x1) 228 break; 229 udelay(1); 230 } 231 232 if (i >= adev->usec_timeout) 233 dev_err(adev->dev, 234 "Timeout waiting for sem acquire in VM flush!\n"); 235 } 236 237 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 238 239 /* Wait for ACK with a delay.*/ 240 for (i = 0; i < adev->usec_timeout; i++) { 241 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 242 hub->eng_distance * eng, hub_ip); 243 tmp &= 1 << vmid; 244 if (tmp) 245 break; 246 247 udelay(1); 248 } 249 250 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 251 if (use_semaphore) 252 /* 253 * add semaphore release after invalidation, 254 * write with 0 means semaphore release 255 */ 256 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 257 hub->eng_distance * eng, 0, hub_ip); 258 259 /* Issue additional private vm invalidation to MMHUB */ 260 if ((vmhub != AMDGPU_GFXHUB(0)) && 261 (hub->vm_l2_bank_select_reserved_cid2) && 262 !amdgpu_sriov_vf(adev)) { 263 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 264 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 265 inv_req |= (1 << 25); 266 /* Issue private invalidation */ 267 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 268 /* Read back to ensure invalidation is done*/ 269 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 270 } 271 272 spin_unlock(&adev->gmc.invalidate_lock); 273 274 if (i < adev->usec_timeout) 275 return; 276 277 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 278 } 279 280 /** 281 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback 282 * 283 * @adev: amdgpu_device pointer 284 * @vmid: vm instance to flush 285 * @vmhub: which hub to flush 286 * @flush_type: the flush type 287 * 288 * Flush the TLB for the requested page table. 289 */ 290 static void gmc_v12_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 291 uint32_t vmhub, uint32_t flush_type) 292 { 293 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 294 return; 295 296 /* flush hdp cache */ 297 amdgpu_device_flush_hdp(adev, NULL); 298 299 /* This is necessary for SRIOV as well as for GFXOFF to function 300 * properly under bare metal 301 */ 302 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) && 303 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 304 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 305 const unsigned eng = 17; 306 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 307 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 308 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 309 310 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 311 1 << vmid, GET_INST(GC, 0)); 312 return; 313 } 314 315 mutex_lock(&adev->mman.gtt_window_lock); 316 gmc_v12_0_flush_vm_hub(adev, vmid, vmhub, 0); 317 mutex_unlock(&adev->mman.gtt_window_lock); 318 return; 319 } 320 321 /** 322 * gmc_v12_0_flush_gpu_tlb_pasid - tlb flush via pasid 323 * 324 * @adev: amdgpu_device pointer 325 * @pasid: pasid to be flush 326 * @flush_type: the flush type 327 * @all_hub: flush all hubs 328 * @inst: is used to select which instance of KIQ to use for the invalidation 329 * 330 * Flush the TLB for the requested pasid. 331 */ 332 static void gmc_v12_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 333 uint16_t pasid, uint32_t flush_type, 334 bool all_hub, uint32_t inst) 335 { 336 uint16_t queried; 337 int vmid, i; 338 339 for (vmid = 1; vmid < 16; vmid++) { 340 bool valid; 341 342 valid = gmc_v12_0_get_vmid_pasid_mapping_info(adev, vmid, 343 &queried); 344 if (!valid || queried != pasid) 345 continue; 346 347 if (all_hub) { 348 for_each_set_bit(i, adev->vmhubs_mask, 349 AMDGPU_MAX_VMHUBS) 350 gmc_v12_0_flush_gpu_tlb(adev, vmid, i, 351 flush_type); 352 } else { 353 gmc_v12_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 354 flush_type); 355 } 356 } 357 } 358 359 static uint64_t gmc_v12_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 360 unsigned vmid, uint64_t pd_addr) 361 { 362 bool use_semaphore = gmc_v12_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 363 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 364 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 365 unsigned eng = ring->vm_inv_eng; 366 367 /* 368 * It may lose gpuvm invalidate acknowldege state across power-gating 369 * off cycle, add semaphore acquire before invalidation and semaphore 370 * release after invalidation to avoid entering power gated state 371 * to WA the Issue 372 */ 373 374 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 375 if (use_semaphore) 376 /* a read return value of 1 means semaphore acuqire */ 377 amdgpu_ring_emit_reg_wait(ring, 378 hub->vm_inv_eng0_sem + 379 hub->eng_distance * eng, 0x1, 0x1); 380 381 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 382 (hub->ctx_addr_distance * vmid), 383 lower_32_bits(pd_addr)); 384 385 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 386 (hub->ctx_addr_distance * vmid), 387 upper_32_bits(pd_addr)); 388 389 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 390 hub->eng_distance * eng, 391 hub->vm_inv_eng0_ack + 392 hub->eng_distance * eng, 393 req, 1 << vmid); 394 395 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 396 if (use_semaphore) 397 /* 398 * add semaphore release after invalidation, 399 * write with 0 means semaphore release 400 */ 401 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 402 hub->eng_distance * eng, 0); 403 404 return pd_addr; 405 } 406 407 static void gmc_v12_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 408 unsigned pasid) 409 { 410 struct amdgpu_device *adev = ring->adev; 411 uint32_t reg; 412 413 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 414 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 415 else 416 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 417 418 amdgpu_ring_emit_wreg(ring, reg, pasid); 419 } 420 421 /* 422 * PTE format: 423 * 63 P 424 * 62:59 reserved 425 * 58 D 426 * 57 G 427 * 56 T 428 * 55:54 M 429 * 53:52 SW 430 * 51:48 reserved for future 431 * 47:12 4k physical page base address 432 * 11:7 fragment 433 * 6 write 434 * 5 read 435 * 4 exe 436 * 3 Z 437 * 2 snooped 438 * 1 system 439 * 0 valid 440 * 441 * PDE format: 442 * 63 P 443 * 62:58 block fragment size 444 * 57 reserved 445 * 56 A 446 * 55:54 M 447 * 53:52 reserved 448 * 51:48 reserved for future 449 * 47:6 physical base address of PD or PTE 450 * 5:3 reserved 451 * 2 C 452 * 1 system 453 * 0 valid 454 */ 455 456 static uint64_t gmc_v12_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 457 { 458 switch (flags) { 459 case AMDGPU_VM_MTYPE_DEFAULT: 460 return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_NC); 461 case AMDGPU_VM_MTYPE_NC: 462 return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_NC); 463 case AMDGPU_VM_MTYPE_UC: 464 return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC); 465 default: 466 return AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_NC); 467 } 468 } 469 470 static void gmc_v12_0_get_vm_pde(struct amdgpu_device *adev, int level, 471 uint64_t *addr, uint64_t *flags) 472 { 473 if (!(*flags & AMDGPU_PDE_PTE_GFX12) && !(*flags & AMDGPU_PTE_SYSTEM)) 474 *addr = adev->vm_manager.vram_base_offset + *addr - 475 adev->gmc.vram_start; 476 BUG_ON(*addr & 0xFFFF00000000003FULL); 477 478 if (!adev->gmc.translate_further) 479 return; 480 481 if (level == AMDGPU_VM_PDB1) { 482 /* Set the block fragment size */ 483 if (!(*flags & AMDGPU_PDE_PTE_GFX12)) 484 *flags |= AMDGPU_PDE_BFS_GFX12(0x9); 485 486 } else if (level == AMDGPU_VM_PDB0) { 487 if (*flags & AMDGPU_PDE_PTE_GFX12) 488 *flags &= ~AMDGPU_PDE_PTE_GFX12; 489 } 490 } 491 492 static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, 493 struct amdgpu_bo_va_mapping *mapping, 494 uint64_t *flags) 495 { 496 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 497 498 *flags &= ~AMDGPU_PTE_EXECUTABLE; 499 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 500 501 *flags &= ~AMDGPU_PTE_MTYPE_GFX12_MASK; 502 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_GFX12_MASK); 503 504 if (mapping->flags & AMDGPU_PTE_PRT_GFX12) { 505 *flags |= AMDGPU_PTE_PRT_GFX12; 506 *flags |= AMDGPU_PTE_SNOOPED; 507 *flags |= AMDGPU_PTE_SYSTEM; 508 *flags |= AMDGPU_PTE_IS_PTE; 509 *flags &= ~AMDGPU_PTE_VALID; 510 } 511 512 if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) 513 *flags |= AMDGPU_PTE_DCC; 514 515 if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED) 516 *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); 517 } 518 519 static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) 520 { 521 return 0; 522 } 523 524 static unsigned int gmc_v12_0_get_dcc_alignment(struct amdgpu_device *adev) 525 { 526 unsigned int max_tex_channel_caches, alignment; 527 528 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 0) && 529 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(12, 0, 1)) 530 return 0; 531 532 max_tex_channel_caches = adev->gfx.config.max_texture_channel_caches; 533 if (is_power_of_2(max_tex_channel_caches)) 534 alignment = (unsigned int)(max_tex_channel_caches / SZ_4); 535 else 536 alignment = roundup_pow_of_two(max_tex_channel_caches); 537 538 return (unsigned int)(alignment * max_tex_channel_caches * SZ_1K); 539 } 540 541 static const struct amdgpu_gmc_funcs gmc_v12_0_gmc_funcs = { 542 .flush_gpu_tlb = gmc_v12_0_flush_gpu_tlb, 543 .flush_gpu_tlb_pasid = gmc_v12_0_flush_gpu_tlb_pasid, 544 .emit_flush_gpu_tlb = gmc_v12_0_emit_flush_gpu_tlb, 545 .emit_pasid_mapping = gmc_v12_0_emit_pasid_mapping, 546 .map_mtype = gmc_v12_0_map_mtype, 547 .get_vm_pde = gmc_v12_0_get_vm_pde, 548 .get_vm_pte = gmc_v12_0_get_vm_pte, 549 .get_vbios_fb_size = gmc_v12_0_get_vbios_fb_size, 550 .get_dcc_alignment = gmc_v12_0_get_dcc_alignment, 551 }; 552 553 static void gmc_v12_0_set_gmc_funcs(struct amdgpu_device *adev) 554 { 555 adev->gmc.gmc_funcs = &gmc_v12_0_gmc_funcs; 556 } 557 558 static void gmc_v12_0_set_umc_funcs(struct amdgpu_device *adev) 559 { 560 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 561 case IP_VERSION(8, 14, 0): 562 adev->umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM; 563 adev->umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev); 564 adev->umc.node_inst_num = 0; 565 adev->umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev); 566 adev->umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET; 567 adev->umc.ras = &umc_v8_14_ras; 568 break; 569 default: 570 break; 571 } 572 } 573 574 575 static void gmc_v12_0_set_mmhub_funcs(struct amdgpu_device *adev) 576 { 577 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 578 case IP_VERSION(4, 1, 0): 579 adev->mmhub.funcs = &mmhub_v4_1_0_funcs; 580 break; 581 default: 582 break; 583 } 584 } 585 586 static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev) 587 { 588 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 589 case IP_VERSION(12, 0, 0): 590 case IP_VERSION(12, 0, 1): 591 adev->gfxhub.funcs = &gfxhub_v12_0_funcs; 592 break; 593 default: 594 break; 595 } 596 } 597 598 static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) 599 { 600 struct amdgpu_device *adev = ip_block->adev; 601 602 gmc_v12_0_set_gfxhub_funcs(adev); 603 gmc_v12_0_set_mmhub_funcs(adev); 604 gmc_v12_0_set_gmc_funcs(adev); 605 gmc_v12_0_set_irq_funcs(adev); 606 gmc_v12_0_set_umc_funcs(adev); 607 608 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 609 adev->gmc.shared_aperture_end = 610 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 611 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 612 adev->gmc.private_aperture_end = 613 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 614 615 return 0; 616 } 617 618 static int gmc_v12_0_late_init(struct amdgpu_ip_block *ip_block) 619 { 620 struct amdgpu_device *adev = ip_block->adev; 621 int r; 622 623 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 624 if (r) 625 return r; 626 627 r = amdgpu_gmc_ras_late_init(adev); 628 if (r) 629 return r; 630 631 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 632 } 633 634 static void gmc_v12_0_vram_gtt_location(struct amdgpu_device *adev, 635 struct amdgpu_gmc *mc) 636 { 637 u64 base = 0; 638 639 base = adev->mmhub.funcs->get_fb_location(adev); 640 641 amdgpu_gmc_set_agp_default(adev, mc); 642 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 643 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_LOW); 644 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 645 amdgpu_gmc_agp_location(adev, mc); 646 647 /* base offset of vram pages */ 648 if (amdgpu_sriov_vf(adev)) 649 adev->vm_manager.vram_base_offset = 0; 650 else 651 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 652 } 653 654 /** 655 * gmc_v12_0_mc_init - initialize the memory controller driver params 656 * 657 * @adev: amdgpu_device pointer 658 * 659 * Look up the amount of vram, vram width, and decide how to place 660 * vram and gart within the GPU's physical address space. 661 * Returns 0 for success. 662 */ 663 static int gmc_v12_0_mc_init(struct amdgpu_device *adev) 664 { 665 int r; 666 667 /* size in MB on si */ 668 adev->gmc.mc_vram_size = 669 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 670 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 671 672 if (!(adev->flags & AMD_IS_APU)) { 673 r = amdgpu_device_resize_fb_bar(adev); 674 if (r) 675 return r; 676 } 677 678 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 679 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 680 681 #ifdef CONFIG_X86_64 682 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 683 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 684 adev->gmc.aper_size = adev->gmc.real_vram_size; 685 } 686 #endif 687 /* In case the PCI BAR is larger than the actual amount of vram */ 688 adev->gmc.visible_vram_size = adev->gmc.aper_size; 689 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 690 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 691 692 /* set the gart size */ 693 if (amdgpu_gart_size == -1) { 694 adev->gmc.gart_size = 512ULL << 20; 695 } else 696 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 697 698 gmc_v12_0_vram_gtt_location(adev, &adev->gmc); 699 700 return 0; 701 } 702 703 static int gmc_v12_0_gart_init(struct amdgpu_device *adev) 704 { 705 int r; 706 707 if (adev->gart.bo) { 708 WARN(1, "PCIE GART already initialized\n"); 709 return 0; 710 } 711 712 /* Initialize common gart structure */ 713 r = amdgpu_gart_init(adev); 714 if (r) 715 return r; 716 717 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 718 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) | 719 AMDGPU_PTE_EXECUTABLE | 720 AMDGPU_PTE_IS_PTE; 721 722 return amdgpu_gart_table_vram_alloc(adev); 723 } 724 725 static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) 726 { 727 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 728 struct amdgpu_device *adev = ip_block->adev; 729 730 adev->mmhub.funcs->init(adev); 731 732 adev->gfxhub.funcs->init(adev); 733 734 spin_lock_init(&adev->gmc.invalidate_lock); 735 736 r = amdgpu_atomfirmware_get_vram_info(adev, 737 &vram_width, &vram_type, &vram_vendor); 738 adev->gmc.vram_width = vram_width; 739 740 adev->gmc.vram_type = vram_type; 741 adev->gmc.vram_vendor = vram_vendor; 742 743 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 744 case IP_VERSION(12, 0, 0): 745 case IP_VERSION(12, 0, 1): 746 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 747 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 748 /* 749 * To fulfill 4-level page support, 750 * vm size is 256TB (48bit), maximum size, 751 * block size 512 (9bit) 752 */ 753 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 754 break; 755 default: 756 break; 757 } 758 759 /* This interrupt is VMC page fault.*/ 760 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 761 VMC_1_0__SRCID__VM_FAULT, 762 &adev->gmc.vm_fault); 763 764 if (r) 765 return r; 766 767 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 768 UTCL2_1_0__SRCID__FAULT, 769 &adev->gmc.vm_fault); 770 if (r) 771 return r; 772 773 if (!amdgpu_sriov_vf(adev)) { 774 /* interrupt sent to DF. */ 775 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 776 &adev->gmc.ecc_irq); 777 if (r) 778 return r; 779 } 780 781 /* 782 * Set the internal MC address mask This is the max address of the GPU's 783 * internal address space. 784 */ 785 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 786 787 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 788 if (r) { 789 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 790 return r; 791 } 792 793 adev->need_swiotlb = drm_need_swiotlb(44); 794 795 r = gmc_v12_0_mc_init(adev); 796 if (r) 797 return r; 798 799 amdgpu_gmc_get_vbios_allocations(adev); 800 801 /* Memory manager */ 802 r = amdgpu_bo_init(adev); 803 if (r) 804 return r; 805 806 r = gmc_v12_0_gart_init(adev); 807 if (r) 808 return r; 809 810 /* 811 * number of VMs 812 * VMID 0 is reserved for System 813 * amdgpu graphics/compute will use VMIDs 1-7 814 * amdkfd will use VMIDs 8-15 815 */ 816 adev->vm_manager.first_kfd_vmid = adev->gfx.disable_kq ? 1 : 8; 817 818 amdgpu_vm_manager_init(adev); 819 820 r = amdgpu_gmc_ras_sw_init(adev); 821 if (r) 822 return r; 823 824 return 0; 825 } 826 827 /** 828 * gmc_v12_0_gart_fini - vm fini callback 829 * 830 * @adev: amdgpu_device pointer 831 * 832 * Tears down the driver GART/VM setup (CIK). 833 */ 834 static void gmc_v12_0_gart_fini(struct amdgpu_device *adev) 835 { 836 amdgpu_gart_table_vram_free(adev); 837 } 838 839 static int gmc_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) 840 { 841 struct amdgpu_device *adev = ip_block->adev; 842 843 amdgpu_vm_manager_fini(adev); 844 gmc_v12_0_gart_fini(adev); 845 amdgpu_gem_force_release(adev); 846 amdgpu_bo_fini(adev); 847 848 return 0; 849 } 850 851 static void gmc_v12_0_init_golden_registers(struct amdgpu_device *adev) 852 { 853 } 854 855 /** 856 * gmc_v12_0_gart_enable - gart enable 857 * 858 * @adev: amdgpu_device pointer 859 */ 860 static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) 861 { 862 int r; 863 bool value; 864 865 if (adev->gart.bo == NULL) { 866 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 867 return -EINVAL; 868 } 869 870 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 871 872 r = adev->mmhub.funcs->gart_enable(adev); 873 if (r) 874 return r; 875 876 /* Flush HDP after it is initialized */ 877 amdgpu_device_flush_hdp(adev, NULL); 878 879 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 880 false : true; 881 882 adev->mmhub.funcs->set_fault_enable_default(adev, value); 883 gmc_v12_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 884 885 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", 886 (unsigned)(adev->gmc.gart_size >> 20), 887 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 888 889 return 0; 890 } 891 892 static int gmc_v12_0_hw_init(struct amdgpu_ip_block *ip_block) 893 { 894 int r; 895 struct amdgpu_device *adev = ip_block->adev; 896 897 /* The sequence of these two function calls matters.*/ 898 gmc_v12_0_init_golden_registers(adev); 899 900 r = gmc_v12_0_gart_enable(adev); 901 if (r) 902 return r; 903 904 if (adev->umc.funcs && adev->umc.funcs->init_registers) 905 adev->umc.funcs->init_registers(adev); 906 907 return 0; 908 } 909 910 /** 911 * gmc_v12_0_gart_disable - gart disable 912 * 913 * @adev: amdgpu_device pointer 914 * 915 * This disables all VM page table. 916 */ 917 static void gmc_v12_0_gart_disable(struct amdgpu_device *adev) 918 { 919 adev->mmhub.funcs->gart_disable(adev); 920 } 921 922 static int gmc_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) 923 { 924 struct amdgpu_device *adev = ip_block->adev; 925 926 if (amdgpu_sriov_vf(adev)) { 927 /* full access mode, so don't touch any GMC register */ 928 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 929 return 0; 930 } 931 932 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 933 934 if (adev->gmc.ecc_irq.funcs && 935 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 936 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 937 938 gmc_v12_0_gart_disable(adev); 939 940 return 0; 941 } 942 943 static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block) 944 { 945 gmc_v12_0_hw_fini(ip_block); 946 947 return 0; 948 } 949 950 static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block) 951 { 952 int r; 953 954 r = gmc_v12_0_hw_init(ip_block); 955 if (r) 956 return r; 957 958 amdgpu_vmid_reset_all(ip_block->adev); 959 960 return 0; 961 } 962 963 static bool gmc_v12_0_is_idle(struct amdgpu_ip_block *ip_block) 964 { 965 /* MC is always ready in GMC v11.*/ 966 return true; 967 } 968 969 static int gmc_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 970 { 971 /* There is no need to wait for MC idle in GMC v11.*/ 972 return 0; 973 } 974 975 static int gmc_v12_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 976 enum amd_clockgating_state state) 977 { 978 int r; 979 struct amdgpu_device *adev = ip_block->adev; 980 981 r = adev->mmhub.funcs->set_clockgating(adev, state); 982 if (r) 983 return r; 984 985 return athub_v4_1_0_set_clockgating(adev, state); 986 } 987 988 static void gmc_v12_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 989 { 990 struct amdgpu_device *adev = ip_block->adev; 991 992 adev->mmhub.funcs->get_clockgating(adev, flags); 993 994 athub_v4_1_0_get_clockgating(adev, flags); 995 } 996 997 static int gmc_v12_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 998 enum amd_powergating_state state) 999 { 1000 return 0; 1001 } 1002 1003 const struct amd_ip_funcs gmc_v12_0_ip_funcs = { 1004 .name = "gmc_v12_0", 1005 .early_init = gmc_v12_0_early_init, 1006 .sw_init = gmc_v12_0_sw_init, 1007 .hw_init = gmc_v12_0_hw_init, 1008 .late_init = gmc_v12_0_late_init, 1009 .sw_fini = gmc_v12_0_sw_fini, 1010 .hw_fini = gmc_v12_0_hw_fini, 1011 .suspend = gmc_v12_0_suspend, 1012 .resume = gmc_v12_0_resume, 1013 .is_idle = gmc_v12_0_is_idle, 1014 .wait_for_idle = gmc_v12_0_wait_for_idle, 1015 .set_clockgating_state = gmc_v12_0_set_clockgating_state, 1016 .set_powergating_state = gmc_v12_0_set_powergating_state, 1017 .get_clockgating_state = gmc_v12_0_get_clockgating_state, 1018 }; 1019 1020 const struct amdgpu_ip_block_version gmc_v12_0_ip_block = { 1021 .type = AMD_IP_BLOCK_TYPE_GMC, 1022 .major = 12, 1023 .minor = 0, 1024 .rev = 0, 1025 .funcs = &gmc_v12_0_ip_funcs, 1026 }; 1027