1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v11_0.h" 31 #include "umc_v8_10.h" 32 #include "athub/athub_3_0_0_sh_mask.h" 33 #include "athub/athub_3_0_0_offset.h" 34 #include "dcn/dcn_3_2_0_offset.h" 35 #include "dcn/dcn_3_2_0_sh_mask.h" 36 #include "oss/osssys_6_0_0_offset.h" 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 38 #include "navi10_enum.h" 39 #include "soc15.h" 40 #include "soc15d.h" 41 #include "soc15_common.h" 42 #include "nbio_v4_3.h" 43 #include "gfxhub_v3_0.h" 44 #include "gfxhub_v3_0_3.h" 45 #include "gfxhub_v11_5_0.h" 46 #include "mmhub_v3_0.h" 47 #include "mmhub_v3_0_1.h" 48 #include "mmhub_v3_0_2.h" 49 #include "mmhub_v3_3.h" 50 #include "athub_v3_0.h" 51 52 53 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, 55 unsigned int type, 56 enum amdgpu_interrupt_state state) 57 { 58 return 0; 59 } 60 61 static int 62 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 63 struct amdgpu_irq_src *src, unsigned int type, 64 enum amdgpu_interrupt_state state) 65 { 66 switch (state) { 67 case AMDGPU_IRQ_STATE_DISABLE: 68 /* MM HUB */ 69 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 70 /* GFX HUB */ 71 /* This works because this interrupt is only 72 * enabled at init/resume and disabled in 73 * fini/suspend, so the overall state doesn't 74 * change over the course of suspend/resume. 75 */ 76 if (!adev->in_s0ix) 77 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 78 break; 79 case AMDGPU_IRQ_STATE_ENABLE: 80 /* MM HUB */ 81 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 82 /* GFX HUB */ 83 /* This works because this interrupt is only 84 * enabled at init/resume and disabled in 85 * fini/suspend, so the overall state doesn't 86 * change over the course of suspend/resume. 87 */ 88 if (!adev->in_s0ix) 89 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 90 break; 91 default: 92 break; 93 } 94 95 return 0; 96 } 97 98 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 99 struct amdgpu_irq_src *source, 100 struct amdgpu_iv_entry *entry) 101 { 102 uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ? 103 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 104 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 105 uint32_t status = 0; 106 u64 addr; 107 108 addr = (u64)entry->src_data[0] << 12; 109 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 110 111 if (!amdgpu_sriov_vf(adev)) { 112 /* 113 * Issue a dummy read to wait for the status register to 114 * be updated to avoid reading an incorrect value due to 115 * the new fast GRBM interface. 116 */ 117 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 118 RREG32(hub->vm_l2_pro_fault_status); 119 120 status = RREG32(hub->vm_l2_pro_fault_status); 121 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 122 } 123 124 if (printk_ratelimit()) { 125 struct amdgpu_task_info task_info; 126 127 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 128 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 129 130 dev_err(adev->dev, 131 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 132 entry->vmid_src ? "mmhub" : "gfxhub", 133 entry->src_id, entry->ring_id, entry->vmid, 134 entry->pasid, task_info.process_name, task_info.tgid, 135 task_info.task_name, task_info.pid); 136 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 137 addr, entry->client_id); 138 if (!amdgpu_sriov_vf(adev)) 139 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 140 } 141 142 return 0; 143 } 144 145 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 146 .set = gmc_v11_0_vm_fault_interrupt_state, 147 .process = gmc_v11_0_process_interrupt, 148 }; 149 150 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 151 .set = gmc_v11_0_ecc_interrupt_state, 152 .process = amdgpu_umc_process_ecc_irq, 153 }; 154 155 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 156 { 157 adev->gmc.vm_fault.num_types = 1; 158 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 159 160 if (!amdgpu_sriov_vf(adev)) { 161 adev->gmc.ecc_irq.num_types = 1; 162 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 163 } 164 } 165 166 /** 167 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 168 * 169 * @adev: amdgpu_device pointer 170 * @vmhub: vmhub type 171 * 172 */ 173 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 174 uint32_t vmhub) 175 { 176 return ((vmhub == AMDGPU_MMHUB0(0)) && 177 (!amdgpu_sriov_vf(adev))); 178 } 179 180 static bool gmc_v11_0_get_vmid_pasid_mapping_info( 181 struct amdgpu_device *adev, 182 uint8_t vmid, uint16_t *p_pasid) 183 { 184 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 185 186 return !!(*p_pasid); 187 } 188 189 /* 190 * GART 191 * VMID 0 is the physical GPU addresses as used by the kernel. 192 * VMIDs 1-15 are used for userspace clients and are handled 193 * by the amdgpu vm/hsa code. 194 */ 195 196 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 197 unsigned int vmhub, uint32_t flush_type) 198 { 199 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 200 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 201 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 202 u32 tmp; 203 /* Use register 17 for GART */ 204 const unsigned int eng = 17; 205 unsigned int i; 206 unsigned char hub_ip = 0; 207 208 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 209 GC_HWIP : MMHUB_HWIP; 210 211 spin_lock(&adev->gmc.invalidate_lock); 212 /* 213 * It may lose gpuvm invalidate acknowldege state across power-gating 214 * off cycle, add semaphore acquire before invalidation and semaphore 215 * release after invalidation to avoid entering power gated state 216 * to WA the Issue 217 */ 218 219 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 220 if (use_semaphore) { 221 for (i = 0; i < adev->usec_timeout; i++) { 222 /* a read return value of 1 means semaphore acuqire */ 223 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 224 hub->eng_distance * eng, hub_ip); 225 if (tmp & 0x1) 226 break; 227 udelay(1); 228 } 229 230 if (i >= adev->usec_timeout) 231 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 232 } 233 234 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req, hub_ip); 235 236 /* Wait for ACK with a delay.*/ 237 for (i = 0; i < adev->usec_timeout; i++) { 238 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 239 hub->eng_distance * eng, hub_ip); 240 tmp &= 1 << vmid; 241 if (tmp) 242 break; 243 244 udelay(1); 245 } 246 247 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 248 if (use_semaphore) 249 /* 250 * add semaphore release after invalidation, 251 * write with 0 means semaphore release 252 */ 253 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 254 hub->eng_distance * eng, 0, hub_ip); 255 256 /* Issue additional private vm invalidation to MMHUB */ 257 if ((vmhub != AMDGPU_GFXHUB(0)) && 258 (hub->vm_l2_bank_select_reserved_cid2) && 259 !amdgpu_sriov_vf(adev)) { 260 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 261 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 262 inv_req |= (1 << 25); 263 /* Issue private invalidation */ 264 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 265 /* Read back to ensure invalidation is done*/ 266 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 267 } 268 269 spin_unlock(&adev->gmc.invalidate_lock); 270 271 if (i < adev->usec_timeout) 272 return; 273 274 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 275 } 276 277 /** 278 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 279 * 280 * @adev: amdgpu_device pointer 281 * @vmid: vm instance to flush 282 * @vmhub: which hub to flush 283 * @flush_type: the flush type 284 * 285 * Flush the TLB for the requested page table. 286 */ 287 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 288 uint32_t vmhub, uint32_t flush_type) 289 { 290 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 291 return; 292 293 /* flush hdp cache */ 294 adev->hdp.funcs->flush_hdp(adev, NULL); 295 296 /* For SRIOV run time, driver shouldn't access the register through MMIO 297 * Directly use kiq to do the vm invalidation instead 298 */ 299 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && 300 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 301 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 302 const unsigned int eng = 17; 303 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 304 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 305 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 306 307 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 308 1 << vmid); 309 return; 310 } 311 312 mutex_lock(&adev->mman.gtt_window_lock); 313 gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); 314 mutex_unlock(&adev->mman.gtt_window_lock); 315 } 316 317 /** 318 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 319 * 320 * @adev: amdgpu_device pointer 321 * @pasid: pasid to be flush 322 * @flush_type: the flush type 323 * @all_hub: flush all hubs 324 * @inst: is used to select which instance of KIQ to use for the invalidation 325 * 326 * Flush the TLB for the requested pasid. 327 */ 328 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 329 uint16_t pasid, uint32_t flush_type, 330 bool all_hub, uint32_t inst) 331 { 332 int vmid, i; 333 signed long r; 334 uint32_t seq; 335 uint16_t queried_pasid; 336 bool ret; 337 struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring; 338 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 339 340 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 341 spin_lock(&adev->gfx.kiq[0].ring_lock); 342 /* 2 dwords flush + 8 dwords fence */ 343 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 344 kiq->pmf->kiq_invalidate_tlbs(ring, 345 pasid, flush_type, all_hub); 346 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 347 if (r) { 348 amdgpu_ring_undo(ring); 349 spin_unlock(&adev->gfx.kiq[0].ring_lock); 350 return -ETIME; 351 } 352 353 amdgpu_ring_commit(ring); 354 spin_unlock(&adev->gfx.kiq[0].ring_lock); 355 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 356 if (r < 1) { 357 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 358 return -ETIME; 359 } 360 361 return 0; 362 } 363 364 for (vmid = 1; vmid < 16; vmid++) { 365 366 ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 367 &queried_pasid); 368 if (ret && queried_pasid == pasid) { 369 if (all_hub) { 370 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 371 gmc_v11_0_flush_gpu_tlb(adev, vmid, 372 i, flush_type); 373 } else { 374 gmc_v11_0_flush_gpu_tlb(adev, vmid, 375 AMDGPU_GFXHUB(0), flush_type); 376 } 377 } 378 } 379 380 return 0; 381 } 382 383 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 384 unsigned int vmid, uint64_t pd_addr) 385 { 386 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 387 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 388 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 389 unsigned int eng = ring->vm_inv_eng; 390 391 /* 392 * It may lose gpuvm invalidate acknowldege state across power-gating 393 * off cycle, add semaphore acquire before invalidation and semaphore 394 * release after invalidation to avoid entering power gated state 395 * to WA the Issue 396 */ 397 398 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 399 if (use_semaphore) 400 /* a read return value of 1 means semaphore acuqire */ 401 amdgpu_ring_emit_reg_wait(ring, 402 hub->vm_inv_eng0_sem + 403 hub->eng_distance * eng, 0x1, 0x1); 404 405 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 406 (hub->ctx_addr_distance * vmid), 407 lower_32_bits(pd_addr)); 408 409 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 410 (hub->ctx_addr_distance * vmid), 411 upper_32_bits(pd_addr)); 412 413 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 414 hub->eng_distance * eng, 415 hub->vm_inv_eng0_ack + 416 hub->eng_distance * eng, 417 req, 1 << vmid); 418 419 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 420 if (use_semaphore) 421 /* 422 * add semaphore release after invalidation, 423 * write with 0 means semaphore release 424 */ 425 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 426 hub->eng_distance * eng, 0); 427 428 return pd_addr; 429 } 430 431 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 432 unsigned int pasid) 433 { 434 struct amdgpu_device *adev = ring->adev; 435 uint32_t reg; 436 437 /* MES fw manages IH_VMID_x_LUT updating */ 438 if (ring->is_mes_queue) 439 return; 440 441 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 442 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 443 else 444 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 445 446 amdgpu_ring_emit_wreg(ring, reg, pasid); 447 } 448 449 /* 450 * PTE format: 451 * 63:59 reserved 452 * 58:57 reserved 453 * 56 F 454 * 55 L 455 * 54 reserved 456 * 53:52 SW 457 * 51 T 458 * 50:48 mtype 459 * 47:12 4k physical page base address 460 * 11:7 fragment 461 * 6 write 462 * 5 read 463 * 4 exe 464 * 3 Z 465 * 2 snooped 466 * 1 system 467 * 0 valid 468 * 469 * PDE format: 470 * 63:59 block fragment size 471 * 58:55 reserved 472 * 54 P 473 * 53:48 reserved 474 * 47:6 physical base address of PD or PTE 475 * 5:3 reserved 476 * 2 C 477 * 1 system 478 * 0 valid 479 */ 480 481 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 482 { 483 switch (flags) { 484 case AMDGPU_VM_MTYPE_DEFAULT: 485 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 486 case AMDGPU_VM_MTYPE_NC: 487 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 488 case AMDGPU_VM_MTYPE_WC: 489 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 490 case AMDGPU_VM_MTYPE_CC: 491 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 492 case AMDGPU_VM_MTYPE_UC: 493 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 494 default: 495 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 496 } 497 } 498 499 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 500 uint64_t *addr, uint64_t *flags) 501 { 502 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 503 *addr = adev->vm_manager.vram_base_offset + *addr - 504 adev->gmc.vram_start; 505 BUG_ON(*addr & 0xFFFF00000000003FULL); 506 507 if (!adev->gmc.translate_further) 508 return; 509 510 if (level == AMDGPU_VM_PDB1) { 511 /* Set the block fragment size */ 512 if (!(*flags & AMDGPU_PDE_PTE)) 513 *flags |= AMDGPU_PDE_BFS(0x9); 514 515 } else if (level == AMDGPU_VM_PDB0) { 516 if (*flags & AMDGPU_PDE_PTE) 517 *flags &= ~AMDGPU_PDE_PTE; 518 else 519 *flags |= AMDGPU_PTE_TF; 520 } 521 } 522 523 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 524 struct amdgpu_bo_va_mapping *mapping, 525 uint64_t *flags) 526 { 527 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 528 529 *flags &= ~AMDGPU_PTE_EXECUTABLE; 530 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 531 532 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 533 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 534 535 *flags &= ~AMDGPU_PTE_NOALLOC; 536 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 537 538 if (mapping->flags & AMDGPU_PTE_PRT) { 539 *flags |= AMDGPU_PTE_PRT; 540 *flags |= AMDGPU_PTE_SNOOPED; 541 *flags |= AMDGPU_PTE_LOG; 542 *flags |= AMDGPU_PTE_SYSTEM; 543 *flags &= ~AMDGPU_PTE_VALID; 544 } 545 546 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 547 AMDGPU_GEM_CREATE_UNCACHED)) 548 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 549 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 550 } 551 552 static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 553 { 554 u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL); 555 unsigned int size; 556 557 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 558 size = AMDGPU_VBIOS_VGA_ALLOCATION; 559 } else { 560 u32 viewport; 561 u32 pitch; 562 563 viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 564 pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH); 565 size = (REG_GET_FIELD(viewport, 566 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 567 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 568 4); 569 } 570 571 return size; 572 } 573 574 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 575 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 576 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 577 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 578 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 579 .map_mtype = gmc_v11_0_map_mtype, 580 .get_vm_pde = gmc_v11_0_get_vm_pde, 581 .get_vm_pte = gmc_v11_0_get_vm_pte, 582 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 583 }; 584 585 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 586 { 587 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 588 } 589 590 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 591 { 592 switch (adev->ip_versions[UMC_HWIP][0]) { 593 case IP_VERSION(8, 10, 0): 594 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; 595 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; 596 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 597 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; 598 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; 599 if (adev->umc.node_inst_num == 4) 600 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; 601 else 602 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; 603 adev->umc.ras = &umc_v8_10_ras; 604 break; 605 case IP_VERSION(8, 11, 0): 606 break; 607 default: 608 break; 609 } 610 } 611 612 613 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 614 { 615 switch (adev->ip_versions[MMHUB_HWIP][0]) { 616 case IP_VERSION(3, 0, 1): 617 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; 618 break; 619 case IP_VERSION(3, 0, 2): 620 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 621 break; 622 case IP_VERSION(3, 3, 0): 623 adev->mmhub.funcs = &mmhub_v3_3_funcs; 624 break; 625 default: 626 adev->mmhub.funcs = &mmhub_v3_0_funcs; 627 break; 628 } 629 } 630 631 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 632 { 633 switch (adev->ip_versions[GC_HWIP][0]) { 634 case IP_VERSION(11, 0, 3): 635 adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs; 636 break; 637 case IP_VERSION(11, 5, 0): 638 adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs; 639 break; 640 default: 641 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 642 break; 643 } 644 } 645 646 static int gmc_v11_0_early_init(void *handle) 647 { 648 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 649 650 gmc_v11_0_set_gfxhub_funcs(adev); 651 gmc_v11_0_set_mmhub_funcs(adev); 652 gmc_v11_0_set_gmc_funcs(adev); 653 gmc_v11_0_set_irq_funcs(adev); 654 gmc_v11_0_set_umc_funcs(adev); 655 656 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 657 adev->gmc.shared_aperture_end = 658 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 659 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 660 adev->gmc.private_aperture_end = 661 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 662 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 663 664 return 0; 665 } 666 667 static int gmc_v11_0_late_init(void *handle) 668 { 669 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 670 int r; 671 672 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 673 if (r) 674 return r; 675 676 r = amdgpu_gmc_ras_late_init(adev); 677 if (r) 678 return r; 679 680 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 681 } 682 683 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 684 struct amdgpu_gmc *mc) 685 { 686 u64 base = 0; 687 688 base = adev->mmhub.funcs->get_fb_location(adev); 689 690 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 691 amdgpu_gmc_gart_location(adev, mc); 692 amdgpu_gmc_agp_location(adev, mc); 693 694 /* base offset of vram pages */ 695 if (amdgpu_sriov_vf(adev)) 696 adev->vm_manager.vram_base_offset = 0; 697 else 698 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 699 } 700 701 /** 702 * gmc_v11_0_mc_init - initialize the memory controller driver params 703 * 704 * @adev: amdgpu_device pointer 705 * 706 * Look up the amount of vram, vram width, and decide how to place 707 * vram and gart within the GPU's physical address space. 708 * Returns 0 for success. 709 */ 710 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 711 { 712 int r; 713 714 /* size in MB on si */ 715 adev->gmc.mc_vram_size = 716 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 717 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 718 719 if (!(adev->flags & AMD_IS_APU)) { 720 r = amdgpu_device_resize_fb_bar(adev); 721 if (r) 722 return r; 723 } 724 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 725 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 726 727 #ifdef CONFIG_X86_64 728 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 729 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 730 adev->gmc.aper_size = adev->gmc.real_vram_size; 731 } 732 #endif 733 /* In case the PCI BAR is larger than the actual amount of vram */ 734 adev->gmc.visible_vram_size = adev->gmc.aper_size; 735 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 736 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 737 738 /* set the gart size */ 739 if (amdgpu_gart_size == -1) 740 adev->gmc.gart_size = 512ULL << 20; 741 else 742 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 743 744 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 745 746 return 0; 747 } 748 749 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 750 { 751 int r; 752 753 if (adev->gart.bo) { 754 WARN(1, "PCIE GART already initialized\n"); 755 return 0; 756 } 757 758 /* Initialize common gart structure */ 759 r = amdgpu_gart_init(adev); 760 if (r) 761 return r; 762 763 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 764 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 765 AMDGPU_PTE_EXECUTABLE; 766 767 return amdgpu_gart_table_vram_alloc(adev); 768 } 769 770 static int gmc_v11_0_sw_init(void *handle) 771 { 772 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 773 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 774 775 adev->mmhub.funcs->init(adev); 776 777 spin_lock_init(&adev->gmc.invalidate_lock); 778 779 r = amdgpu_atomfirmware_get_vram_info(adev, 780 &vram_width, &vram_type, &vram_vendor); 781 adev->gmc.vram_width = vram_width; 782 783 adev->gmc.vram_type = vram_type; 784 adev->gmc.vram_vendor = vram_vendor; 785 786 switch (adev->ip_versions[GC_HWIP][0]) { 787 case IP_VERSION(11, 0, 0): 788 case IP_VERSION(11, 0, 1): 789 case IP_VERSION(11, 0, 2): 790 case IP_VERSION(11, 0, 3): 791 case IP_VERSION(11, 0, 4): 792 case IP_VERSION(11, 5, 0): 793 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 794 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 795 /* 796 * To fulfill 4-level page support, 797 * vm size is 256TB (48bit), maximum size, 798 * block size 512 (9bit) 799 */ 800 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 801 break; 802 default: 803 break; 804 } 805 806 /* This interrupt is VMC page fault.*/ 807 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 808 VMC_1_0__SRCID__VM_FAULT, 809 &adev->gmc.vm_fault); 810 811 if (r) 812 return r; 813 814 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 815 UTCL2_1_0__SRCID__FAULT, 816 &adev->gmc.vm_fault); 817 if (r) 818 return r; 819 820 if (!amdgpu_sriov_vf(adev)) { 821 /* interrupt sent to DF. */ 822 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 823 &adev->gmc.ecc_irq); 824 if (r) 825 return r; 826 } 827 828 /* 829 * Set the internal MC address mask This is the max address of the GPU's 830 * internal address space. 831 */ 832 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 833 834 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 835 if (r) { 836 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 837 return r; 838 } 839 840 adev->need_swiotlb = drm_need_swiotlb(44); 841 842 r = gmc_v11_0_mc_init(adev); 843 if (r) 844 return r; 845 846 amdgpu_gmc_get_vbios_allocations(adev); 847 848 /* Memory manager */ 849 r = amdgpu_bo_init(adev); 850 if (r) 851 return r; 852 853 r = gmc_v11_0_gart_init(adev); 854 if (r) 855 return r; 856 857 /* 858 * number of VMs 859 * VMID 0 is reserved for System 860 * amdgpu graphics/compute will use VMIDs 1-7 861 * amdkfd will use VMIDs 8-15 862 */ 863 adev->vm_manager.first_kfd_vmid = 8; 864 865 amdgpu_vm_manager_init(adev); 866 867 r = amdgpu_gmc_ras_sw_init(adev); 868 if (r) 869 return r; 870 871 return 0; 872 } 873 874 /** 875 * gmc_v11_0_gart_fini - vm fini callback 876 * 877 * @adev: amdgpu_device pointer 878 * 879 * Tears down the driver GART/VM setup (CIK). 880 */ 881 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 882 { 883 amdgpu_gart_table_vram_free(adev); 884 } 885 886 static int gmc_v11_0_sw_fini(void *handle) 887 { 888 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 889 890 amdgpu_vm_manager_fini(adev); 891 gmc_v11_0_gart_fini(adev); 892 amdgpu_gem_force_release(adev); 893 amdgpu_bo_fini(adev); 894 895 return 0; 896 } 897 898 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 899 { 900 if (amdgpu_sriov_vf(adev)) { 901 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 902 903 WREG32(hub->vm_contexts_disable, 0); 904 return; 905 } 906 } 907 908 /** 909 * gmc_v11_0_gart_enable - gart enable 910 * 911 * @adev: amdgpu_device pointer 912 */ 913 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 914 { 915 int r; 916 bool value; 917 918 if (adev->gart.bo == NULL) { 919 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 920 return -EINVAL; 921 } 922 923 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 924 925 r = adev->mmhub.funcs->gart_enable(adev); 926 if (r) 927 return r; 928 929 /* Flush HDP after it is initialized */ 930 adev->hdp.funcs->flush_hdp(adev, NULL); 931 932 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 933 false : true; 934 935 adev->mmhub.funcs->set_fault_enable_default(adev, value); 936 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 937 938 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 939 (unsigned int)(adev->gmc.gart_size >> 20), 940 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 941 942 return 0; 943 } 944 945 static int gmc_v11_0_hw_init(void *handle) 946 { 947 int r; 948 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 949 950 /* The sequence of these two function calls matters.*/ 951 gmc_v11_0_init_golden_registers(adev); 952 953 r = gmc_v11_0_gart_enable(adev); 954 if (r) 955 return r; 956 957 if (adev->umc.funcs && adev->umc.funcs->init_registers) 958 adev->umc.funcs->init_registers(adev); 959 960 return 0; 961 } 962 963 /** 964 * gmc_v11_0_gart_disable - gart disable 965 * 966 * @adev: amdgpu_device pointer 967 * 968 * This disables all VM page table. 969 */ 970 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 971 { 972 adev->mmhub.funcs->gart_disable(adev); 973 } 974 975 static int gmc_v11_0_hw_fini(void *handle) 976 { 977 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 978 979 if (amdgpu_sriov_vf(adev)) { 980 /* full access mode, so don't touch any GMC register */ 981 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 982 return 0; 983 } 984 985 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 986 gmc_v11_0_gart_disable(adev); 987 988 return 0; 989 } 990 991 static int gmc_v11_0_suspend(void *handle) 992 { 993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 994 995 gmc_v11_0_hw_fini(adev); 996 997 return 0; 998 } 999 1000 static int gmc_v11_0_resume(void *handle) 1001 { 1002 int r; 1003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1004 1005 r = gmc_v11_0_hw_init(adev); 1006 if (r) 1007 return r; 1008 1009 amdgpu_vmid_reset_all(adev); 1010 1011 return 0; 1012 } 1013 1014 static bool gmc_v11_0_is_idle(void *handle) 1015 { 1016 /* MC is always ready in GMC v11.*/ 1017 return true; 1018 } 1019 1020 static int gmc_v11_0_wait_for_idle(void *handle) 1021 { 1022 /* There is no need to wait for MC idle in GMC v11.*/ 1023 return 0; 1024 } 1025 1026 static int gmc_v11_0_soft_reset(void *handle) 1027 { 1028 return 0; 1029 } 1030 1031 static int gmc_v11_0_set_clockgating_state(void *handle, 1032 enum amd_clockgating_state state) 1033 { 1034 int r; 1035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1036 1037 r = adev->mmhub.funcs->set_clockgating(adev, state); 1038 if (r) 1039 return r; 1040 1041 return athub_v3_0_set_clockgating(adev, state); 1042 } 1043 1044 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 1045 { 1046 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1047 1048 adev->mmhub.funcs->get_clockgating(adev, flags); 1049 1050 athub_v3_0_get_clockgating(adev, flags); 1051 } 1052 1053 static int gmc_v11_0_set_powergating_state(void *handle, 1054 enum amd_powergating_state state) 1055 { 1056 return 0; 1057 } 1058 1059 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 1060 .name = "gmc_v11_0", 1061 .early_init = gmc_v11_0_early_init, 1062 .sw_init = gmc_v11_0_sw_init, 1063 .hw_init = gmc_v11_0_hw_init, 1064 .late_init = gmc_v11_0_late_init, 1065 .sw_fini = gmc_v11_0_sw_fini, 1066 .hw_fini = gmc_v11_0_hw_fini, 1067 .suspend = gmc_v11_0_suspend, 1068 .resume = gmc_v11_0_resume, 1069 .is_idle = gmc_v11_0_is_idle, 1070 .wait_for_idle = gmc_v11_0_wait_for_idle, 1071 .soft_reset = gmc_v11_0_soft_reset, 1072 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 1073 .set_powergating_state = gmc_v11_0_set_powergating_state, 1074 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 1075 }; 1076 1077 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 1078 .type = AMD_IP_BLOCK_TYPE_GMC, 1079 .major = 11, 1080 .minor = 0, 1081 .rev = 0, 1082 .funcs = &gmc_v11_0_ip_funcs, 1083 }; 1084