1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v11_0.h" 31 #include "umc_v8_10.h" 32 #include "athub/athub_3_0_0_sh_mask.h" 33 #include "athub/athub_3_0_0_offset.h" 34 #include "dcn/dcn_3_2_0_offset.h" 35 #include "dcn/dcn_3_2_0_sh_mask.h" 36 #include "oss/osssys_6_0_0_offset.h" 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 38 #include "navi10_enum.h" 39 #include "soc15.h" 40 #include "soc15d.h" 41 #include "soc15_common.h" 42 #include "nbio_v4_3.h" 43 #include "gfxhub_v3_0.h" 44 #include "gfxhub_v3_0_3.h" 45 #include "gfxhub_v11_5_0.h" 46 #include "mmhub_v3_0.h" 47 #include "mmhub_v3_0_1.h" 48 #include "mmhub_v3_0_2.h" 49 #include "mmhub_v3_3.h" 50 #include "athub_v3_0.h" 51 52 53 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, 55 unsigned int type, 56 enum amdgpu_interrupt_state state) 57 { 58 return 0; 59 } 60 61 static int 62 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 63 struct amdgpu_irq_src *src, unsigned int type, 64 enum amdgpu_interrupt_state state) 65 { 66 switch (state) { 67 case AMDGPU_IRQ_STATE_DISABLE: 68 /* MM HUB */ 69 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 70 /* GFX HUB */ 71 /* This works because this interrupt is only 72 * enabled at init/resume and disabled in 73 * fini/suspend, so the overall state doesn't 74 * change over the course of suspend/resume. 75 */ 76 if (!adev->in_s0ix && (adev->in_runpm || adev->in_suspend || 77 amdgpu_in_reset(adev))) 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 83 /* GFX HUB */ 84 /* This works because this interrupt is only 85 * enabled at init/resume and disabled in 86 * fini/suspend, so the overall state doesn't 87 * change over the course of suspend/resume. 88 */ 89 if (!adev->in_s0ix) 90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 91 break; 92 default: 93 break; 94 } 95 96 return 0; 97 } 98 99 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 100 struct amdgpu_irq_src *source, 101 struct amdgpu_iv_entry *entry) 102 { 103 uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ? 104 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 105 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 106 bool retry_fault = !!(entry->src_data[1] & 107 AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY); 108 bool write_fault = !!(entry->src_data[1] & 109 AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE); 110 uint32_t status = 0; 111 u64 addr; 112 113 addr = (u64)entry->src_data[0] << 12; 114 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 115 116 if (retry_fault) { 117 int ret = amdgpu_gmc_handle_retry_fault(adev, entry, addr, 0, 0, 118 write_fault); 119 /* Returning 1 here also prevents sending the IV to the KFD */ 120 if (ret == 1) 121 return 1; 122 } 123 124 if (!amdgpu_sriov_vf(adev)) { 125 /* 126 * Issue a dummy read to wait for the status register to 127 * be updated to avoid reading an incorrect value due to 128 * the new fast GRBM interface. 129 */ 130 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 131 RREG32(hub->vm_l2_pro_fault_status); 132 133 status = RREG32(hub->vm_l2_pro_fault_status); 134 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 135 136 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 137 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 138 } 139 140 if (printk_ratelimit()) { 141 struct amdgpu_task_info *task_info; 142 143 dev_err(adev->dev, 144 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 145 entry->vmid_src ? "mmhub" : "gfxhub", 146 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 147 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 148 if (task_info) { 149 amdgpu_vm_print_task_info(adev, task_info); 150 amdgpu_vm_put_task_info(task_info); 151 } 152 153 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 154 addr, entry->client_id); 155 156 /* Only print L2 fault status if the status register could be read and 157 * contains useful information 158 */ 159 if (status != 0) 160 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 161 } 162 163 return 0; 164 } 165 166 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 167 .set = gmc_v11_0_vm_fault_interrupt_state, 168 .process = gmc_v11_0_process_interrupt, 169 }; 170 171 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 172 .set = gmc_v11_0_ecc_interrupt_state, 173 .process = amdgpu_umc_process_ecc_irq, 174 }; 175 176 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 177 { 178 adev->gmc.vm_fault.num_types = 1; 179 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 180 181 if (!amdgpu_sriov_vf(adev)) { 182 adev->gmc.ecc_irq.num_types = 1; 183 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 184 } 185 } 186 187 /** 188 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 189 * 190 * @adev: amdgpu_device pointer 191 * @vmhub: vmhub type 192 * 193 */ 194 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 195 uint32_t vmhub) 196 { 197 return ((vmhub == AMDGPU_MMHUB0(0)) && 198 (!amdgpu_sriov_vf(adev))); 199 } 200 201 static bool gmc_v11_0_get_vmid_pasid_mapping_info( 202 struct amdgpu_device *adev, 203 uint8_t vmid, uint16_t *p_pasid) 204 { 205 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 206 207 return !!(*p_pasid); 208 } 209 210 /** 211 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 212 * 213 * @adev: amdgpu_device pointer 214 * @vmid: vm instance to flush 215 * @vmhub: which hub to flush 216 * @flush_type: the flush type 217 * 218 * Flush the TLB for the requested page table. 219 */ 220 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 221 uint32_t vmhub, uint32_t flush_type) 222 { 223 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 224 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 225 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 226 /* Use register 17 for GART */ 227 const unsigned int eng = 17; 228 unsigned char hub_ip; 229 u32 sem, req, ack; 230 unsigned int i; 231 u32 tmp; 232 233 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 234 return; 235 236 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 237 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 238 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 239 240 /* flush hdp cache */ 241 amdgpu_device_flush_hdp(adev, NULL); 242 243 /* This is necessary for SRIOV as well as for GFXOFF to function 244 * properly under bare metal 245 */ 246 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring[0].sched.ready) && 247 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 248 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 249 1 << vmid, GET_INST(GC, 0)); 250 return; 251 } 252 253 /* This path is needed before KIQ/MES/GFXOFF are set up */ 254 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; 255 256 spin_lock(&adev->gmc.invalidate_lock); 257 /* 258 * It may lose gpuvm invalidate acknowldege state across power-gating 259 * off cycle, add semaphore acquire before invalidation and semaphore 260 * release after invalidation to avoid entering power gated state 261 * to WA the Issue 262 */ 263 264 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 265 if (use_semaphore) { 266 for (i = 0; i < adev->usec_timeout; i++) { 267 /* a read return value of 1 means semaphore acuqire */ 268 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); 269 if (tmp & 0x1) 270 break; 271 udelay(1); 272 } 273 274 if (i >= adev->usec_timeout) 275 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 276 } 277 278 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); 279 280 /* Wait for ACK with a delay.*/ 281 for (i = 0; i < adev->usec_timeout; i++) { 282 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); 283 tmp &= 1 << vmid; 284 if (tmp) 285 break; 286 287 udelay(1); 288 } 289 290 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 291 if (use_semaphore) 292 WREG32_RLC_NO_KIQ(sem, 0, hub_ip); 293 294 /* Issue additional private vm invalidation to MMHUB */ 295 if ((vmhub != AMDGPU_GFXHUB(0)) && 296 (hub->vm_l2_bank_select_reserved_cid2) && 297 !amdgpu_sriov_vf(adev)) { 298 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 299 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 300 inv_req |= (1 << 25); 301 /* Issue private invalidation */ 302 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 303 /* Read back to ensure invalidation is done*/ 304 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 305 } 306 307 spin_unlock(&adev->gmc.invalidate_lock); 308 309 if (i >= adev->usec_timeout) 310 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 311 } 312 313 /** 314 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 315 * 316 * @adev: amdgpu_device pointer 317 * @pasid: pasid to be flush 318 * @flush_type: the flush type 319 * @all_hub: flush all hubs 320 * @inst: is used to select which instance of KIQ to use for the invalidation 321 * 322 * Flush the TLB for the requested pasid. 323 */ 324 static void gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 325 uint16_t pasid, uint32_t flush_type, 326 bool all_hub, uint32_t inst) 327 { 328 uint16_t queried; 329 int vmid, i; 330 331 for (vmid = 1; vmid < 16; vmid++) { 332 bool valid; 333 334 valid = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 335 &queried); 336 if (!valid || queried != pasid) 337 continue; 338 339 if (all_hub) { 340 for_each_set_bit(i, adev->vmhubs_mask, 341 AMDGPU_MAX_VMHUBS) 342 gmc_v11_0_flush_gpu_tlb(adev, vmid, i, 343 flush_type); 344 } else { 345 gmc_v11_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 346 flush_type); 347 } 348 } 349 } 350 351 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 352 unsigned int vmid, uint64_t pd_addr) 353 { 354 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 355 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 356 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 357 unsigned int eng = ring->vm_inv_eng; 358 359 /* 360 * It may lose gpuvm invalidate acknowldege state across power-gating 361 * off cycle, add semaphore acquire before invalidation and semaphore 362 * release after invalidation to avoid entering power gated state 363 * to WA the Issue 364 */ 365 366 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 367 if (use_semaphore) 368 /* a read return value of 1 means semaphore acuqire */ 369 amdgpu_ring_emit_reg_wait(ring, 370 hub->vm_inv_eng0_sem + 371 hub->eng_distance * eng, 0x1, 0x1); 372 373 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 374 (hub->ctx_addr_distance * vmid), 375 lower_32_bits(pd_addr)); 376 377 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 378 (hub->ctx_addr_distance * vmid), 379 upper_32_bits(pd_addr)); 380 381 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 382 hub->eng_distance * eng, 383 hub->vm_inv_eng0_ack + 384 hub->eng_distance * eng, 385 req, 1 << vmid); 386 387 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 388 if (use_semaphore) 389 /* 390 * add semaphore release after invalidation, 391 * write with 0 means semaphore release 392 */ 393 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 394 hub->eng_distance * eng, 0); 395 396 return pd_addr; 397 } 398 399 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 400 unsigned int pasid) 401 { 402 struct amdgpu_device *adev = ring->adev; 403 uint32_t reg; 404 405 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 406 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 407 else 408 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 409 410 amdgpu_ring_emit_wreg(ring, reg, pasid); 411 } 412 413 /* 414 * PTE format: 415 * 63:59 reserved 416 * 58:57 reserved 417 * 56 F 418 * 55 L 419 * 54 reserved 420 * 53:52 SW 421 * 51 T 422 * 50:48 mtype 423 * 47:12 4k physical page base address 424 * 11:7 fragment 425 * 6 write 426 * 5 read 427 * 4 exe 428 * 3 Z 429 * 2 snooped 430 * 1 system 431 * 0 valid 432 * 433 * PDE format: 434 * 63:59 block fragment size 435 * 58:55 reserved 436 * 54 P 437 * 53:48 reserved 438 * 47:6 physical base address of PD or PTE 439 * 5:3 reserved 440 * 2 C 441 * 1 system 442 * 0 valid 443 */ 444 445 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 446 uint64_t *addr, uint64_t *flags) 447 { 448 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 449 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 450 BUG_ON(*addr & 0xFFFF00000000003FULL); 451 452 if (!adev->gmc.translate_further) 453 return; 454 455 if (level == AMDGPU_VM_PDB1) { 456 /* Set the block fragment size */ 457 if (!(*flags & AMDGPU_PDE_PTE)) 458 *flags |= AMDGPU_PDE_BFS(0x9); 459 460 } else if (level == AMDGPU_VM_PDB0) { 461 if (*flags & AMDGPU_PDE_PTE) 462 *flags &= ~AMDGPU_PDE_PTE; 463 else 464 *flags |= AMDGPU_PTE_TF; 465 } 466 } 467 468 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 469 struct amdgpu_vm *vm, 470 struct amdgpu_bo *bo, 471 uint32_t vm_flags, 472 uint64_t *flags) 473 { 474 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 475 *flags |= AMDGPU_PTE_EXECUTABLE; 476 else 477 *flags &= ~AMDGPU_PTE_EXECUTABLE; 478 479 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 480 case AMDGPU_VM_MTYPE_DEFAULT: 481 case AMDGPU_VM_MTYPE_NC: 482 default: 483 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC); 484 break; 485 case AMDGPU_VM_MTYPE_WC: 486 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC); 487 break; 488 case AMDGPU_VM_MTYPE_CC: 489 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC); 490 break; 491 case AMDGPU_VM_MTYPE_UC: 492 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); 493 break; 494 } 495 496 if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) 497 *flags |= AMDGPU_PTE_NOALLOC; 498 else 499 *flags &= ~AMDGPU_PTE_NOALLOC; 500 501 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 502 *flags |= AMDGPU_PTE_PRT; 503 *flags |= AMDGPU_PTE_SNOOPED; 504 *flags |= AMDGPU_PTE_LOG; 505 *flags |= AMDGPU_PTE_SYSTEM; 506 *flags &= ~AMDGPU_PTE_VALID; 507 } 508 509 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 510 AMDGPU_GEM_CREATE_EXT_COHERENT | 511 AMDGPU_GEM_CREATE_UNCACHED)) 512 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); 513 } 514 515 static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 516 { 517 u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL); 518 unsigned int size; 519 520 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 521 size = AMDGPU_VBIOS_VGA_ALLOCATION; 522 } else { 523 u32 viewport; 524 u32 pitch; 525 526 viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 527 pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH); 528 size = (REG_GET_FIELD(viewport, 529 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 530 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 531 4); 532 } 533 534 return size; 535 } 536 537 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 538 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 539 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 540 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 541 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 542 .get_vm_pde = gmc_v11_0_get_vm_pde, 543 .get_vm_pte = gmc_v11_0_get_vm_pte, 544 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 545 }; 546 547 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 548 { 549 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 550 } 551 552 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 553 { 554 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 555 case IP_VERSION(8, 10, 0): 556 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; 557 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; 558 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 559 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; 560 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; 561 if (adev->umc.node_inst_num == 4) 562 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; 563 else 564 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; 565 adev->umc.ras = &umc_v8_10_ras; 566 break; 567 case IP_VERSION(8, 11, 0): 568 break; 569 default: 570 break; 571 } 572 } 573 574 575 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 576 { 577 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 578 case IP_VERSION(3, 0, 1): 579 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; 580 break; 581 case IP_VERSION(3, 0, 2): 582 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 583 break; 584 case IP_VERSION(3, 3, 0): 585 case IP_VERSION(3, 3, 1): 586 case IP_VERSION(3, 3, 2): 587 case IP_VERSION(3, 4, 0): 588 adev->mmhub.funcs = &mmhub_v3_3_funcs; 589 break; 590 default: 591 adev->mmhub.funcs = &mmhub_v3_0_funcs; 592 break; 593 } 594 } 595 596 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 597 { 598 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 599 case IP_VERSION(11, 0, 3): 600 adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs; 601 break; 602 case IP_VERSION(11, 5, 0): 603 case IP_VERSION(11, 5, 1): 604 case IP_VERSION(11, 5, 2): 605 case IP_VERSION(11, 5, 3): 606 case IP_VERSION(11, 5, 4): 607 adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs; 608 break; 609 default: 610 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 611 break; 612 } 613 } 614 615 static int gmc_v11_0_early_init(struct amdgpu_ip_block *ip_block) 616 { 617 struct amdgpu_device *adev = ip_block->adev; 618 619 gmc_v11_0_set_gfxhub_funcs(adev); 620 gmc_v11_0_set_mmhub_funcs(adev); 621 gmc_v11_0_set_gmc_funcs(adev); 622 gmc_v11_0_set_irq_funcs(adev); 623 gmc_v11_0_set_umc_funcs(adev); 624 625 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 626 adev->gmc.shared_aperture_end = 627 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 628 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 629 adev->gmc.private_aperture_end = 630 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 631 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 632 633 return 0; 634 } 635 636 static int gmc_v11_0_late_init(struct amdgpu_ip_block *ip_block) 637 { 638 struct amdgpu_device *adev = ip_block->adev; 639 int r; 640 641 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 642 if (r) 643 return r; 644 645 r = amdgpu_gmc_ras_late_init(adev); 646 if (r) 647 return r; 648 649 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 650 } 651 652 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 653 struct amdgpu_gmc *mc) 654 { 655 u64 base = 0; 656 657 base = adev->mmhub.funcs->get_fb_location(adev); 658 659 amdgpu_gmc_set_agp_default(adev, mc); 660 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 661 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH); 662 if (!amdgpu_sriov_vf(adev) && 663 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) && 664 (amdgpu_agp == 1)) 665 amdgpu_gmc_agp_location(adev, mc); 666 667 /* base offset of vram pages */ 668 if (amdgpu_sriov_vf(adev)) 669 adev->vm_manager.vram_base_offset = 0; 670 else 671 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 672 } 673 674 /** 675 * gmc_v11_0_mc_init - initialize the memory controller driver params 676 * 677 * @adev: amdgpu_device pointer 678 * 679 * Look up the amount of vram, vram width, and decide how to place 680 * vram and gart within the GPU's physical address space. 681 * Returns 0 for success. 682 */ 683 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 684 { 685 int r; 686 687 /* size in MB on si */ 688 adev->gmc.mc_vram_size = 689 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 690 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 691 692 if (!(adev->flags & AMD_IS_APU)) { 693 r = amdgpu_device_resize_fb_bar(adev); 694 if (r) 695 return r; 696 } 697 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 698 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 699 700 #ifdef CONFIG_X86_64 701 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 702 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 703 adev->gmc.aper_size = adev->gmc.real_vram_size; 704 } 705 #endif 706 /* In case the PCI BAR is larger than the actual amount of vram */ 707 adev->gmc.visible_vram_size = adev->gmc.aper_size; 708 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 709 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 710 711 /* set the gart size */ 712 amdgpu_gmc_set_gart_size(adev, SZ_512M); 713 714 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 715 716 return 0; 717 } 718 719 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 720 { 721 int r; 722 723 if (adev->gart.bo) { 724 WARN(1, "PCIE GART already initialized\n"); 725 return 0; 726 } 727 728 /* Initialize common gart structure */ 729 r = amdgpu_gart_init(adev); 730 if (r) 731 return r; 732 733 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 734 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | 735 AMDGPU_PTE_EXECUTABLE; 736 737 return amdgpu_gart_table_vram_alloc(adev); 738 } 739 740 static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 741 { 742 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 743 struct amdgpu_device *adev = ip_block->adev; 744 745 adev->mmhub.funcs->init(adev); 746 747 adev->gfxhub.funcs->init(adev); 748 749 spin_lock_init(&adev->gmc.invalidate_lock); 750 751 r = amdgpu_gmc_get_vram_info(adev, 752 &vram_width, &vram_type, &vram_vendor); 753 adev->gmc.vram_width = vram_width; 754 755 adev->gmc.vram_type = vram_type; 756 adev->gmc.vram_vendor = vram_vendor; 757 758 /* The mall_size is already calculated as mall_size_per_umc * num_umc. 759 * However, for gfx1151, which features a 2-to-1 UMC mapping, 760 * the result must be multiplied by 2 to determine the actual mall size. 761 */ 762 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 763 case IP_VERSION(11, 5, 1): 764 adev->gmc.mall_size *= 2; 765 break; 766 default: 767 break; 768 } 769 770 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 771 case IP_VERSION(11, 0, 0): 772 case IP_VERSION(11, 0, 1): 773 case IP_VERSION(11, 0, 2): 774 case IP_VERSION(11, 0, 3): 775 case IP_VERSION(11, 0, 4): 776 case IP_VERSION(11, 5, 0): 777 case IP_VERSION(11, 5, 1): 778 case IP_VERSION(11, 5, 2): 779 case IP_VERSION(11, 5, 3): 780 case IP_VERSION(11, 5, 4): 781 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 782 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 783 /* 784 * To fulfill 4-level page support, 785 * vm size is 256TB (48bit), maximum size, 786 * block size 512 (9bit) 787 */ 788 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 789 break; 790 default: 791 break; 792 } 793 794 /* This interrupt is VMC page fault.*/ 795 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 796 VMC_1_0__SRCID__VM_FAULT, 797 &adev->gmc.vm_fault); 798 799 if (r) 800 return r; 801 802 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 803 UTCL2_1_0__SRCID__FAULT, 804 &adev->gmc.vm_fault); 805 if (r) 806 return r; 807 808 if (!amdgpu_sriov_vf(adev)) { 809 /* interrupt sent to DF. */ 810 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 811 &adev->gmc.ecc_irq); 812 if (r) 813 return r; 814 } 815 816 /* 817 * Set the internal MC address mask This is the max address of the GPU's 818 * internal address space. 819 */ 820 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 821 822 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 823 if (r) { 824 drm_warn(adev_to_drm(adev), "No suitable DMA available.\n"); 825 return r; 826 } 827 828 adev->need_swiotlb = drm_need_swiotlb(44); 829 830 r = gmc_v11_0_mc_init(adev); 831 if (r) 832 return r; 833 834 /* Memory manager */ 835 r = amdgpu_bo_init(adev); 836 if (r) 837 return r; 838 839 r = gmc_v11_0_gart_init(adev); 840 if (r) 841 return r; 842 843 /* 844 * number of VMs 845 * VMID 0 is reserved for System 846 * amdgpu graphics/compute will use VMIDs 1-7 847 * amdkfd will use VMIDs 8-15 848 */ 849 adev->vm_manager.first_kfd_vmid = adev->gfx.disable_kq ? 1 : 8; 850 851 amdgpu_vm_manager_init(adev); 852 853 r = amdgpu_gmc_ras_sw_init(adev); 854 if (r) 855 return r; 856 857 return 0; 858 } 859 860 /** 861 * gmc_v11_0_gart_fini - vm fini callback 862 * 863 * @adev: amdgpu_device pointer 864 * 865 * Tears down the driver GART/VM setup (CIK). 866 */ 867 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 868 { 869 amdgpu_gart_table_vram_free(adev); 870 } 871 872 static int gmc_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) 873 { 874 struct amdgpu_device *adev = ip_block->adev; 875 876 amdgpu_vm_manager_fini(adev); 877 gmc_v11_0_gart_fini(adev); 878 amdgpu_gem_force_release(adev); 879 amdgpu_bo_fini(adev); 880 881 return 0; 882 } 883 884 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 885 { 886 if (amdgpu_sriov_vf(adev)) { 887 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 888 889 WREG32(hub->vm_contexts_disable, 0); 890 return; 891 } 892 } 893 894 /** 895 * gmc_v11_0_gart_enable - gart enable 896 * 897 * @adev: amdgpu_device pointer 898 */ 899 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 900 { 901 int r; 902 bool value; 903 904 if (adev->gart.bo == NULL) { 905 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 906 return -EINVAL; 907 } 908 909 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 910 911 r = adev->mmhub.funcs->gart_enable(adev); 912 if (r) 913 return r; 914 915 /* Flush HDP after it is initialized */ 916 amdgpu_device_flush_hdp(adev, NULL); 917 918 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 919 920 adev->mmhub.funcs->set_fault_enable_default(adev, value); 921 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 922 923 drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", 924 (unsigned int)(adev->gmc.gart_size >> 20), 925 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 926 927 return 0; 928 } 929 930 static int gmc_v11_0_hw_init(struct amdgpu_ip_block *ip_block) 931 { 932 struct amdgpu_device *adev = ip_block->adev; 933 int r; 934 935 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; 936 937 /* The sequence of these two function calls matters.*/ 938 gmc_v11_0_init_golden_registers(adev); 939 940 r = gmc_v11_0_gart_enable(adev); 941 if (r) 942 return r; 943 944 if (adev->umc.funcs && adev->umc.funcs->init_registers) 945 adev->umc.funcs->init_registers(adev); 946 947 return 0; 948 } 949 950 /** 951 * gmc_v11_0_gart_disable - gart disable 952 * 953 * @adev: amdgpu_device pointer 954 * 955 * This disables all VM page table. 956 */ 957 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 958 { 959 adev->mmhub.funcs->gart_disable(adev); 960 } 961 962 static int gmc_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) 963 { 964 struct amdgpu_device *adev = ip_block->adev; 965 966 if (amdgpu_sriov_vf(adev)) { 967 /* full access mode, so don't touch any GMC register */ 968 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 969 return 0; 970 } 971 972 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 973 974 if (adev->gmc.ecc_irq.funcs && 975 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 976 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 977 978 gmc_v11_0_gart_disable(adev); 979 980 return 0; 981 } 982 983 static int gmc_v11_0_suspend(struct amdgpu_ip_block *ip_block) 984 { 985 gmc_v11_0_hw_fini(ip_block); 986 987 return 0; 988 } 989 990 static int gmc_v11_0_resume(struct amdgpu_ip_block *ip_block) 991 { 992 int r; 993 994 r = gmc_v11_0_hw_init(ip_block); 995 if (r) 996 return r; 997 998 amdgpu_vmid_reset_all(ip_block->adev); 999 1000 return 0; 1001 } 1002 1003 static bool gmc_v11_0_is_idle(struct amdgpu_ip_block *ip_block) 1004 { 1005 /* MC is always ready in GMC v11.*/ 1006 return true; 1007 } 1008 1009 static int gmc_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1010 { 1011 /* There is no need to wait for MC idle in GMC v11.*/ 1012 return 0; 1013 } 1014 1015 static int gmc_v11_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1016 enum amd_clockgating_state state) 1017 { 1018 int r; 1019 struct amdgpu_device *adev = ip_block->adev; 1020 1021 r = adev->mmhub.funcs->set_clockgating(adev, state); 1022 if (r) 1023 return r; 1024 1025 return athub_v3_0_set_clockgating(adev, state); 1026 } 1027 1028 static void gmc_v11_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1029 { 1030 struct amdgpu_device *adev = ip_block->adev; 1031 1032 adev->mmhub.funcs->get_clockgating(adev, flags); 1033 1034 athub_v3_0_get_clockgating(adev, flags); 1035 } 1036 1037 static int gmc_v11_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1038 enum amd_powergating_state state) 1039 { 1040 return 0; 1041 } 1042 1043 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 1044 .name = "gmc_v11_0", 1045 .early_init = gmc_v11_0_early_init, 1046 .sw_init = gmc_v11_0_sw_init, 1047 .hw_init = gmc_v11_0_hw_init, 1048 .late_init = gmc_v11_0_late_init, 1049 .sw_fini = gmc_v11_0_sw_fini, 1050 .hw_fini = gmc_v11_0_hw_fini, 1051 .suspend = gmc_v11_0_suspend, 1052 .resume = gmc_v11_0_resume, 1053 .is_idle = gmc_v11_0_is_idle, 1054 .wait_for_idle = gmc_v11_0_wait_for_idle, 1055 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 1056 .set_powergating_state = gmc_v11_0_set_powergating_state, 1057 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 1058 }; 1059 1060 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 1061 .type = AMD_IP_BLOCK_TYPE_GMC, 1062 .major = 11, 1063 .minor = 0, 1064 .rev = 0, 1065 .funcs = &gmc_v11_0_ip_funcs, 1066 }; 1067