1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v11_0.h" 28 #include "umc_v8_7.h" 29 #include "athub/athub_3_0_0_sh_mask.h" 30 #include "athub/athub_3_0_0_offset.h" 31 #include "oss/osssys_6_0_0_offset.h" 32 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 33 #include "navi10_enum.h" 34 #include "soc15.h" 35 #include "soc15d.h" 36 #include "soc15_common.h" 37 #include "nbio_v4_3.h" 38 #include "gfxhub_v3_0.h" 39 #include "mmhub_v3_0.h" 40 #include "mmhub_v3_0_2.h" 41 #include "athub_v3_0.h" 42 43 44 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 45 struct amdgpu_irq_src *src, 46 unsigned type, 47 enum amdgpu_interrupt_state state) 48 { 49 return 0; 50 } 51 52 static int 53 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, unsigned type, 55 enum amdgpu_interrupt_state state) 56 { 57 switch (state) { 58 case AMDGPU_IRQ_STATE_DISABLE: 59 /* MM HUB */ 60 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 61 /* GFX HUB */ 62 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 63 break; 64 case AMDGPU_IRQ_STATE_ENABLE: 65 /* MM HUB */ 66 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 67 /* GFX HUB */ 68 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 69 break; 70 default: 71 break; 72 } 73 74 return 0; 75 } 76 77 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 78 struct amdgpu_irq_src *source, 79 struct amdgpu_iv_entry *entry) 80 { 81 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 82 uint32_t status = 0; 83 u64 addr; 84 85 addr = (u64)entry->src_data[0] << 12; 86 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 87 88 if (!amdgpu_sriov_vf(adev)) { 89 /* 90 * Issue a dummy read to wait for the status register to 91 * be updated to avoid reading an incorrect value due to 92 * the new fast GRBM interface. 93 */ 94 if (entry->vmid_src == AMDGPU_GFXHUB_0) 95 RREG32(hub->vm_l2_pro_fault_status); 96 97 status = RREG32(hub->vm_l2_pro_fault_status); 98 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 99 } 100 101 if (printk_ratelimit()) { 102 struct amdgpu_task_info task_info; 103 104 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 105 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 106 107 dev_err(adev->dev, 108 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 109 "for process %s pid %d thread %s pid %d)\n", 110 entry->vmid_src ? "mmhub" : "gfxhub", 111 entry->src_id, entry->ring_id, entry->vmid, 112 entry->pasid, task_info.process_name, task_info.tgid, 113 task_info.task_name, task_info.pid); 114 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 115 addr, entry->client_id); 116 if (!amdgpu_sriov_vf(adev)) 117 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 118 } 119 120 return 0; 121 } 122 123 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 124 .set = gmc_v11_0_vm_fault_interrupt_state, 125 .process = gmc_v11_0_process_interrupt, 126 }; 127 128 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 129 .set = gmc_v11_0_ecc_interrupt_state, 130 .process = amdgpu_umc_process_ecc_irq, 131 }; 132 133 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 134 { 135 adev->gmc.vm_fault.num_types = 1; 136 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 137 138 if (!amdgpu_sriov_vf(adev)) { 139 adev->gmc.ecc_irq.num_types = 1; 140 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 141 } 142 } 143 144 /** 145 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 146 * 147 * @adev: amdgpu_device pointer 148 * @vmhub: vmhub type 149 * 150 */ 151 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 152 uint32_t vmhub) 153 { 154 return ((vmhub == AMDGPU_MMHUB_0) && 155 (!amdgpu_sriov_vf(adev))); 156 } 157 158 static bool gmc_v11_0_get_atc_vmid_pasid_mapping_info( 159 struct amdgpu_device *adev, 160 uint8_t vmid, uint16_t *p_pasid) 161 { 162 #if 0 // TODO: 163 uint32_t value; 164 165 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 166 + vmid); 167 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 168 169 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 170 #else 171 return 0; 172 #endif 173 } 174 175 /* 176 * GART 177 * VMID 0 is the physical GPU addresses as used by the kernel. 178 * VMIDs 1-15 are used for userspace clients and are handled 179 * by the amdgpu vm/hsa code. 180 */ 181 182 static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 183 unsigned int vmhub, uint32_t flush_type) 184 { 185 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 186 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 187 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 188 u32 tmp; 189 /* Use register 17 for GART */ 190 const unsigned eng = 17; 191 unsigned int i; 192 193 spin_lock(&adev->gmc.invalidate_lock); 194 /* 195 * It may lose gpuvm invalidate acknowldege state across power-gating 196 * off cycle, add semaphore acquire before invalidation and semaphore 197 * release after invalidation to avoid entering power gated state 198 * to WA the Issue 199 */ 200 201 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 202 if (use_semaphore) { 203 for (i = 0; i < adev->usec_timeout; i++) { 204 /* a read return value of 1 means semaphore acuqire */ 205 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 206 hub->eng_distance * eng); 207 if (tmp & 0x1) 208 break; 209 udelay(1); 210 } 211 212 if (i >= adev->usec_timeout) 213 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 214 } 215 216 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 217 218 /* Wait for ACK with a delay.*/ 219 for (i = 0; i < adev->usec_timeout; i++) { 220 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 221 hub->eng_distance * eng); 222 tmp &= 1 << vmid; 223 if (tmp) 224 break; 225 226 udelay(1); 227 } 228 229 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 230 if (use_semaphore) 231 /* 232 * add semaphore release after invalidation, 233 * write with 0 means semaphore release 234 */ 235 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 236 hub->eng_distance * eng, 0); 237 238 /* Issue additional private vm invalidation to MMHUB */ 239 if ((vmhub != AMDGPU_GFXHUB_0) && 240 (hub->vm_l2_bank_select_reserved_cid2)) { 241 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 242 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 243 inv_req |= (1 << 25); 244 /* Issue private invalidation */ 245 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 246 /* Read back to ensure invalidation is done*/ 247 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 248 } 249 250 spin_unlock(&adev->gmc.invalidate_lock); 251 252 if (i < adev->usec_timeout) 253 return; 254 255 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 256 } 257 258 /** 259 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 260 * 261 * @adev: amdgpu_device pointer 262 * @vmid: vm instance to flush 263 * 264 * Flush the TLB for the requested page table. 265 */ 266 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 267 uint32_t vmhub, uint32_t flush_type) 268 { 269 if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron) 270 return; 271 272 /* flush hdp cache */ 273 adev->hdp.funcs->flush_hdp(adev, NULL); 274 275 /* For SRIOV run time, driver shouldn't access the register through MMIO 276 * Directly use kiq to do the vm invalidation instead 277 */ 278 if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes && 279 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 280 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 281 const unsigned eng = 17; 282 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 283 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 284 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 285 286 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 287 1 << vmid); 288 return; 289 } 290 291 mutex_lock(&adev->mman.gtt_window_lock); 292 gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0); 293 mutex_unlock(&adev->mman.gtt_window_lock); 294 return; 295 } 296 297 /** 298 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 299 * 300 * @adev: amdgpu_device pointer 301 * @pasid: pasid to be flush 302 * 303 * Flush the TLB for the requested pasid. 304 */ 305 static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 306 uint16_t pasid, uint32_t flush_type, 307 bool all_hub) 308 { 309 int vmid, i; 310 signed long r; 311 uint32_t seq; 312 uint16_t queried_pasid; 313 bool ret; 314 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 315 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 316 317 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 318 spin_lock(&adev->gfx.kiq.ring_lock); 319 /* 2 dwords flush + 8 dwords fence */ 320 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 321 kiq->pmf->kiq_invalidate_tlbs(ring, 322 pasid, flush_type, all_hub); 323 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 324 if (r) { 325 amdgpu_ring_undo(ring); 326 spin_unlock(&adev->gfx.kiq.ring_lock); 327 return -ETIME; 328 } 329 330 amdgpu_ring_commit(ring); 331 spin_unlock(&adev->gfx.kiq.ring_lock); 332 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 333 if (r < 1) { 334 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 335 return -ETIME; 336 } 337 338 return 0; 339 } 340 341 for (vmid = 1; vmid < 16; vmid++) { 342 343 ret = gmc_v11_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 344 &queried_pasid); 345 if (ret && queried_pasid == pasid) { 346 if (all_hub) { 347 for (i = 0; i < adev->num_vmhubs; i++) 348 gmc_v11_0_flush_gpu_tlb(adev, vmid, 349 i, flush_type); 350 } else { 351 gmc_v11_0_flush_gpu_tlb(adev, vmid, 352 AMDGPU_GFXHUB_0, flush_type); 353 } 354 break; 355 } 356 } 357 358 return 0; 359 } 360 361 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 362 unsigned vmid, uint64_t pd_addr) 363 { 364 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 365 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 366 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 367 unsigned eng = ring->vm_inv_eng; 368 369 /* 370 * It may lose gpuvm invalidate acknowldege state across power-gating 371 * off cycle, add semaphore acquire before invalidation and semaphore 372 * release after invalidation to avoid entering power gated state 373 * to WA the Issue 374 */ 375 376 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 377 if (use_semaphore) 378 /* a read return value of 1 means semaphore acuqire */ 379 amdgpu_ring_emit_reg_wait(ring, 380 hub->vm_inv_eng0_sem + 381 hub->eng_distance * eng, 0x1, 0x1); 382 383 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 384 (hub->ctx_addr_distance * vmid), 385 lower_32_bits(pd_addr)); 386 387 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 388 (hub->ctx_addr_distance * vmid), 389 upper_32_bits(pd_addr)); 390 391 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 392 hub->eng_distance * eng, 393 hub->vm_inv_eng0_ack + 394 hub->eng_distance * eng, 395 req, 1 << vmid); 396 397 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 398 if (use_semaphore) 399 /* 400 * add semaphore release after invalidation, 401 * write with 0 means semaphore release 402 */ 403 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 404 hub->eng_distance * eng, 0); 405 406 return pd_addr; 407 } 408 409 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 410 unsigned pasid) 411 { 412 struct amdgpu_device *adev = ring->adev; 413 uint32_t reg; 414 415 /* MES fw manages IH_VMID_x_LUT updating */ 416 if (ring->is_mes_queue) 417 return; 418 419 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 420 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 421 else 422 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 423 424 amdgpu_ring_emit_wreg(ring, reg, pasid); 425 } 426 427 /* 428 * PTE format: 429 * 63:59 reserved 430 * 58:57 reserved 431 * 56 F 432 * 55 L 433 * 54 reserved 434 * 53:52 SW 435 * 51 T 436 * 50:48 mtype 437 * 47:12 4k physical page base address 438 * 11:7 fragment 439 * 6 write 440 * 5 read 441 * 4 exe 442 * 3 Z 443 * 2 snooped 444 * 1 system 445 * 0 valid 446 * 447 * PDE format: 448 * 63:59 block fragment size 449 * 58:55 reserved 450 * 54 P 451 * 53:48 reserved 452 * 47:6 physical base address of PD or PTE 453 * 5:3 reserved 454 * 2 C 455 * 1 system 456 * 0 valid 457 */ 458 459 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 460 { 461 switch (flags) { 462 case AMDGPU_VM_MTYPE_DEFAULT: 463 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 464 case AMDGPU_VM_MTYPE_NC: 465 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 466 case AMDGPU_VM_MTYPE_WC: 467 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 468 case AMDGPU_VM_MTYPE_CC: 469 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 470 case AMDGPU_VM_MTYPE_UC: 471 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 472 default: 473 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 474 } 475 } 476 477 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 478 uint64_t *addr, uint64_t *flags) 479 { 480 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 481 *addr = adev->vm_manager.vram_base_offset + *addr - 482 adev->gmc.vram_start; 483 BUG_ON(*addr & 0xFFFF00000000003FULL); 484 485 if (!adev->gmc.translate_further) 486 return; 487 488 if (level == AMDGPU_VM_PDB1) { 489 /* Set the block fragment size */ 490 if (!(*flags & AMDGPU_PDE_PTE)) 491 *flags |= AMDGPU_PDE_BFS(0x9); 492 493 } else if (level == AMDGPU_VM_PDB0) { 494 if (*flags & AMDGPU_PDE_PTE) 495 *flags &= ~AMDGPU_PDE_PTE; 496 else 497 *flags |= AMDGPU_PTE_TF; 498 } 499 } 500 501 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 502 struct amdgpu_bo_va_mapping *mapping, 503 uint64_t *flags) 504 { 505 *flags &= ~AMDGPU_PTE_EXECUTABLE; 506 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 507 508 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 509 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 510 511 if (mapping->flags & AMDGPU_PTE_PRT) { 512 *flags |= AMDGPU_PTE_PRT; 513 *flags |= AMDGPU_PTE_SNOOPED; 514 *flags |= AMDGPU_PTE_LOG; 515 *flags |= AMDGPU_PTE_SYSTEM; 516 *flags &= ~AMDGPU_PTE_VALID; 517 } 518 } 519 520 static unsigned gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 521 { 522 return 0; 523 } 524 525 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 526 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 527 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 528 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 529 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 530 .map_mtype = gmc_v11_0_map_mtype, 531 .get_vm_pde = gmc_v11_0_get_vm_pde, 532 .get_vm_pte = gmc_v11_0_get_vm_pte, 533 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 534 }; 535 536 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 537 { 538 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 539 } 540 541 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 542 { 543 switch (adev->ip_versions[UMC_HWIP][0]) { 544 case IP_VERSION(8, 10, 0): 545 case IP_VERSION(8, 11, 0): 546 break; 547 default: 548 break; 549 } 550 } 551 552 553 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 554 { 555 switch (adev->ip_versions[MMHUB_HWIP][0]) { 556 case IP_VERSION(3, 0, 2): 557 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 558 break; 559 default: 560 adev->mmhub.funcs = &mmhub_v3_0_funcs; 561 break; 562 } 563 } 564 565 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 566 { 567 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 568 } 569 570 static int gmc_v11_0_early_init(void *handle) 571 { 572 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 573 574 gmc_v11_0_set_gfxhub_funcs(adev); 575 gmc_v11_0_set_mmhub_funcs(adev); 576 gmc_v11_0_set_gmc_funcs(adev); 577 gmc_v11_0_set_irq_funcs(adev); 578 gmc_v11_0_set_umc_funcs(adev); 579 580 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 581 adev->gmc.shared_aperture_end = 582 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 583 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 584 adev->gmc.private_aperture_end = 585 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 586 587 return 0; 588 } 589 590 static int gmc_v11_0_late_init(void *handle) 591 { 592 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 593 int r; 594 595 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 596 if (r) 597 return r; 598 599 r = amdgpu_gmc_ras_late_init(adev); 600 if (r) 601 return r; 602 603 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 604 } 605 606 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 607 struct amdgpu_gmc *mc) 608 { 609 u64 base = 0; 610 611 base = adev->mmhub.funcs->get_fb_location(adev); 612 613 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 614 amdgpu_gmc_gart_location(adev, mc); 615 616 /* base offset of vram pages */ 617 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 618 } 619 620 /** 621 * gmc_v11_0_mc_init - initialize the memory controller driver params 622 * 623 * @adev: amdgpu_device pointer 624 * 625 * Look up the amount of vram, vram width, and decide how to place 626 * vram and gart within the GPU's physical address space. 627 * Returns 0 for success. 628 */ 629 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 630 { 631 int r; 632 633 /* size in MB on si */ 634 adev->gmc.mc_vram_size = 635 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 636 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 637 638 if (!(adev->flags & AMD_IS_APU)) { 639 r = amdgpu_device_resize_fb_bar(adev); 640 if (r) 641 return r; 642 } 643 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 644 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 645 646 /* In case the PCI BAR is larger than the actual amount of vram */ 647 adev->gmc.visible_vram_size = adev->gmc.aper_size; 648 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 649 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 650 651 /* set the gart size */ 652 if (amdgpu_gart_size == -1) { 653 adev->gmc.gart_size = 512ULL << 20; 654 } else 655 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 656 657 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 658 659 return 0; 660 } 661 662 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 663 { 664 int r; 665 666 if (adev->gart.bo) { 667 WARN(1, "PCIE GART already initialized\n"); 668 return 0; 669 } 670 671 /* Initialize common gart structure */ 672 r = amdgpu_gart_init(adev); 673 if (r) 674 return r; 675 676 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 677 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 678 AMDGPU_PTE_EXECUTABLE; 679 680 return amdgpu_gart_table_vram_alloc(adev); 681 } 682 683 static int gmc_v11_0_sw_init(void *handle) 684 { 685 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 686 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 687 688 adev->mmhub.funcs->init(adev); 689 690 spin_lock_init(&adev->gmc.invalidate_lock); 691 692 r = amdgpu_atomfirmware_get_vram_info(adev, 693 &vram_width, &vram_type, &vram_vendor); 694 adev->gmc.vram_width = vram_width; 695 696 adev->gmc.vram_type = vram_type; 697 adev->gmc.vram_vendor = vram_vendor; 698 699 switch (adev->ip_versions[GC_HWIP][0]) { 700 case IP_VERSION(11, 0, 0): 701 case IP_VERSION(11, 0, 1): 702 case IP_VERSION(11, 0, 2): 703 adev->num_vmhubs = 2; 704 /* 705 * To fulfill 4-level page support, 706 * vm size is 256TB (48bit), maximum size, 707 * block size 512 (9bit) 708 */ 709 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 710 break; 711 default: 712 break; 713 } 714 715 /* This interrupt is VMC page fault.*/ 716 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 717 VMC_1_0__SRCID__VM_FAULT, 718 &adev->gmc.vm_fault); 719 720 if (r) 721 return r; 722 723 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 724 UTCL2_1_0__SRCID__FAULT, 725 &adev->gmc.vm_fault); 726 if (r) 727 return r; 728 729 if (!amdgpu_sriov_vf(adev)) { 730 /* interrupt sent to DF. */ 731 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 732 &adev->gmc.ecc_irq); 733 if (r) 734 return r; 735 } 736 737 /* 738 * Set the internal MC address mask This is the max address of the GPU's 739 * internal address space. 740 */ 741 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 742 743 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 744 if (r) { 745 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 746 return r; 747 } 748 749 r = gmc_v11_0_mc_init(adev); 750 if (r) 751 return r; 752 753 amdgpu_gmc_get_vbios_allocations(adev); 754 755 /* Memory manager */ 756 r = amdgpu_bo_init(adev); 757 if (r) 758 return r; 759 760 r = gmc_v11_0_gart_init(adev); 761 if (r) 762 return r; 763 764 /* 765 * number of VMs 766 * VMID 0 is reserved for System 767 * amdgpu graphics/compute will use VMIDs 1-7 768 * amdkfd will use VMIDs 8-15 769 */ 770 adev->vm_manager.first_kfd_vmid = 8; 771 772 amdgpu_vm_manager_init(adev); 773 774 return 0; 775 } 776 777 /** 778 * gmc_v11_0_gart_fini - vm fini callback 779 * 780 * @adev: amdgpu_device pointer 781 * 782 * Tears down the driver GART/VM setup (CIK). 783 */ 784 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 785 { 786 amdgpu_gart_table_vram_free(adev); 787 } 788 789 static int gmc_v11_0_sw_fini(void *handle) 790 { 791 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 792 793 amdgpu_vm_manager_fini(adev); 794 gmc_v11_0_gart_fini(adev); 795 amdgpu_gem_force_release(adev); 796 amdgpu_bo_fini(adev); 797 798 return 0; 799 } 800 801 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 802 { 803 } 804 805 /** 806 * gmc_v11_0_gart_enable - gart enable 807 * 808 * @adev: amdgpu_device pointer 809 */ 810 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 811 { 812 int r; 813 bool value; 814 815 if (adev->gart.bo == NULL) { 816 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 817 return -EINVAL; 818 } 819 820 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 821 822 r = adev->mmhub.funcs->gart_enable(adev); 823 if (r) 824 return r; 825 826 /* Flush HDP after it is initialized */ 827 adev->hdp.funcs->flush_hdp(adev, NULL); 828 829 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 830 false : true; 831 832 adev->mmhub.funcs->set_fault_enable_default(adev, value); 833 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 834 835 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 836 (unsigned)(adev->gmc.gart_size >> 20), 837 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 838 839 return 0; 840 } 841 842 static int gmc_v11_0_hw_init(void *handle) 843 { 844 int r; 845 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 846 847 /* The sequence of these two function calls matters.*/ 848 gmc_v11_0_init_golden_registers(adev); 849 850 r = gmc_v11_0_gart_enable(adev); 851 if (r) 852 return r; 853 854 if (adev->umc.funcs && adev->umc.funcs->init_registers) 855 adev->umc.funcs->init_registers(adev); 856 857 return 0; 858 } 859 860 /** 861 * gmc_v11_0_gart_disable - gart disable 862 * 863 * @adev: amdgpu_device pointer 864 * 865 * This disables all VM page table. 866 */ 867 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 868 { 869 adev->mmhub.funcs->gart_disable(adev); 870 } 871 872 static int gmc_v11_0_hw_fini(void *handle) 873 { 874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 875 876 if (amdgpu_sriov_vf(adev)) { 877 /* full access mode, so don't touch any GMC register */ 878 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 879 return 0; 880 } 881 882 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 883 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 884 gmc_v11_0_gart_disable(adev); 885 886 return 0; 887 } 888 889 static int gmc_v11_0_suspend(void *handle) 890 { 891 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 892 893 gmc_v11_0_hw_fini(adev); 894 895 return 0; 896 } 897 898 static int gmc_v11_0_resume(void *handle) 899 { 900 int r; 901 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 902 903 r = gmc_v11_0_hw_init(adev); 904 if (r) 905 return r; 906 907 amdgpu_vmid_reset_all(adev); 908 909 return 0; 910 } 911 912 static bool gmc_v11_0_is_idle(void *handle) 913 { 914 /* MC is always ready in GMC v11.*/ 915 return true; 916 } 917 918 static int gmc_v11_0_wait_for_idle(void *handle) 919 { 920 /* There is no need to wait for MC idle in GMC v11.*/ 921 return 0; 922 } 923 924 static int gmc_v11_0_soft_reset(void *handle) 925 { 926 return 0; 927 } 928 929 static int gmc_v11_0_set_clockgating_state(void *handle, 930 enum amd_clockgating_state state) 931 { 932 int r; 933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 934 935 r = adev->mmhub.funcs->set_clockgating(adev, state); 936 if (r) 937 return r; 938 939 return athub_v3_0_set_clockgating(adev, state); 940 } 941 942 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 943 { 944 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 945 946 adev->mmhub.funcs->get_clockgating(adev, flags); 947 948 athub_v3_0_get_clockgating(adev, flags); 949 } 950 951 static int gmc_v11_0_set_powergating_state(void *handle, 952 enum amd_powergating_state state) 953 { 954 return 0; 955 } 956 957 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 958 .name = "gmc_v11_0", 959 .early_init = gmc_v11_0_early_init, 960 .sw_init = gmc_v11_0_sw_init, 961 .hw_init = gmc_v11_0_hw_init, 962 .late_init = gmc_v11_0_late_init, 963 .sw_fini = gmc_v11_0_sw_fini, 964 .hw_fini = gmc_v11_0_hw_fini, 965 .suspend = gmc_v11_0_suspend, 966 .resume = gmc_v11_0_resume, 967 .is_idle = gmc_v11_0_is_idle, 968 .wait_for_idle = gmc_v11_0_wait_for_idle, 969 .soft_reset = gmc_v11_0_soft_reset, 970 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 971 .set_powergating_state = gmc_v11_0_set_powergating_state, 972 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 973 }; 974 975 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 976 .type = AMD_IP_BLOCK_TYPE_GMC, 977 .major = 11, 978 .minor = 0, 979 .rev = 0, 980 .funcs = &gmc_v11_0_ip_funcs, 981 }; 982