1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v11_0.h" 31 #include "umc_v8_10.h" 32 #include "athub/athub_3_0_0_sh_mask.h" 33 #include "athub/athub_3_0_0_offset.h" 34 #include "dcn/dcn_3_2_0_offset.h" 35 #include "dcn/dcn_3_2_0_sh_mask.h" 36 #include "oss/osssys_6_0_0_offset.h" 37 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 38 #include "navi10_enum.h" 39 #include "soc15.h" 40 #include "soc15d.h" 41 #include "soc15_common.h" 42 #include "nbio_v4_3.h" 43 #include "gfxhub_v3_0.h" 44 #include "gfxhub_v3_0_3.h" 45 #include "gfxhub_v11_5_0.h" 46 #include "mmhub_v3_0.h" 47 #include "mmhub_v3_0_1.h" 48 #include "mmhub_v3_0_2.h" 49 #include "mmhub_v3_3.h" 50 #include "athub_v3_0.h" 51 52 53 static int gmc_v11_0_ecc_interrupt_state(struct amdgpu_device *adev, 54 struct amdgpu_irq_src *src, 55 unsigned int type, 56 enum amdgpu_interrupt_state state) 57 { 58 return 0; 59 } 60 61 static int 62 gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 63 struct amdgpu_irq_src *src, unsigned int type, 64 enum amdgpu_interrupt_state state) 65 { 66 switch (state) { 67 case AMDGPU_IRQ_STATE_DISABLE: 68 /* MM HUB */ 69 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 70 /* GFX HUB */ 71 /* This works because this interrupt is only 72 * enabled at init/resume and disabled in 73 * fini/suspend, so the overall state doesn't 74 * change over the course of suspend/resume. 75 */ 76 if (!adev->in_s0ix && (adev->in_runpm || adev->in_suspend || 77 amdgpu_in_reset(adev))) 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 83 /* GFX HUB */ 84 /* This works because this interrupt is only 85 * enabled at init/resume and disabled in 86 * fini/suspend, so the overall state doesn't 87 * change over the course of suspend/resume. 88 */ 89 if (!adev->in_s0ix) 90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 91 break; 92 default: 93 break; 94 } 95 96 return 0; 97 } 98 99 static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, 100 struct amdgpu_irq_src *source, 101 struct amdgpu_iv_entry *entry) 102 { 103 uint32_t vmhub_index = entry->client_id == SOC21_IH_CLIENTID_VMC ? 104 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 105 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 106 uint32_t status = 0; 107 u64 addr; 108 109 addr = (u64)entry->src_data[0] << 12; 110 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 111 112 if (!amdgpu_sriov_vf(adev)) { 113 /* 114 * Issue a dummy read to wait for the status register to 115 * be updated to avoid reading an incorrect value due to 116 * the new fast GRBM interface. 117 */ 118 if (entry->vmid_src == AMDGPU_GFXHUB(0)) 119 RREG32(hub->vm_l2_pro_fault_status); 120 121 status = RREG32(hub->vm_l2_pro_fault_status); 122 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 123 124 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 125 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 126 } 127 128 if (printk_ratelimit()) { 129 struct amdgpu_task_info task_info; 130 131 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 132 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 133 134 dev_err(adev->dev, 135 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 136 entry->vmid_src ? "mmhub" : "gfxhub", 137 entry->src_id, entry->ring_id, entry->vmid, 138 entry->pasid, task_info.process_name, task_info.tgid, 139 task_info.task_name, task_info.pid); 140 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n", 141 addr, entry->client_id); 142 if (!amdgpu_sriov_vf(adev)) 143 hub->vmhub_funcs->print_l2_protection_fault_status(adev, status); 144 } 145 146 return 0; 147 } 148 149 static const struct amdgpu_irq_src_funcs gmc_v11_0_irq_funcs = { 150 .set = gmc_v11_0_vm_fault_interrupt_state, 151 .process = gmc_v11_0_process_interrupt, 152 }; 153 154 static const struct amdgpu_irq_src_funcs gmc_v11_0_ecc_funcs = { 155 .set = gmc_v11_0_ecc_interrupt_state, 156 .process = amdgpu_umc_process_ecc_irq, 157 }; 158 159 static void gmc_v11_0_set_irq_funcs(struct amdgpu_device *adev) 160 { 161 adev->gmc.vm_fault.num_types = 1; 162 adev->gmc.vm_fault.funcs = &gmc_v11_0_irq_funcs; 163 164 if (!amdgpu_sriov_vf(adev)) { 165 adev->gmc.ecc_irq.num_types = 1; 166 adev->gmc.ecc_irq.funcs = &gmc_v11_0_ecc_funcs; 167 } 168 } 169 170 /** 171 * gmc_v11_0_use_invalidate_semaphore - judge whether to use semaphore 172 * 173 * @adev: amdgpu_device pointer 174 * @vmhub: vmhub type 175 * 176 */ 177 static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, 178 uint32_t vmhub) 179 { 180 return ((vmhub == AMDGPU_MMHUB0(0)) && 181 (!amdgpu_sriov_vf(adev))); 182 } 183 184 static bool gmc_v11_0_get_vmid_pasid_mapping_info( 185 struct amdgpu_device *adev, 186 uint8_t vmid, uint16_t *p_pasid) 187 { 188 *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; 189 190 return !!(*p_pasid); 191 } 192 193 /** 194 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback 195 * 196 * @adev: amdgpu_device pointer 197 * @vmid: vm instance to flush 198 * @vmhub: which hub to flush 199 * @flush_type: the flush type 200 * 201 * Flush the TLB for the requested page table. 202 */ 203 static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 204 uint32_t vmhub, uint32_t flush_type) 205 { 206 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(adev, vmhub); 207 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 208 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 209 /* Use register 17 for GART */ 210 const unsigned int eng = 17; 211 unsigned char hub_ip; 212 u32 sem, req, ack; 213 unsigned int i; 214 u32 tmp; 215 216 if ((vmhub == AMDGPU_GFXHUB(0)) && !adev->gfx.is_poweron) 217 return; 218 219 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 220 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 221 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 222 223 /* flush hdp cache */ 224 adev->hdp.funcs->flush_hdp(adev, NULL); 225 226 /* This is necessary for SRIOV as well as for GFXOFF to function 227 * properly under bare metal 228 */ 229 if ((adev->gfx.kiq[0].ring.sched.ready || adev->mes.ring.sched.ready) && 230 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 231 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 232 1 << vmid, GET_INST(GC, 0)); 233 return; 234 } 235 236 /* This path is needed before KIQ/MES/GFXOFF are set up */ 237 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; 238 239 spin_lock(&adev->gmc.invalidate_lock); 240 /* 241 * It may lose gpuvm invalidate acknowldege state across power-gating 242 * off cycle, add semaphore acquire before invalidation and semaphore 243 * release after invalidation to avoid entering power gated state 244 * to WA the Issue 245 */ 246 247 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 248 if (use_semaphore) { 249 for (i = 0; i < adev->usec_timeout; i++) { 250 /* a read return value of 1 means semaphore acuqire */ 251 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); 252 if (tmp & 0x1) 253 break; 254 udelay(1); 255 } 256 257 if (i >= adev->usec_timeout) 258 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 259 } 260 261 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); 262 263 /* Wait for ACK with a delay.*/ 264 for (i = 0; i < adev->usec_timeout; i++) { 265 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); 266 tmp &= 1 << vmid; 267 if (tmp) 268 break; 269 270 udelay(1); 271 } 272 273 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 274 if (use_semaphore) 275 WREG32_RLC_NO_KIQ(sem, 0, hub_ip); 276 277 /* Issue additional private vm invalidation to MMHUB */ 278 if ((vmhub != AMDGPU_GFXHUB(0)) && 279 (hub->vm_l2_bank_select_reserved_cid2) && 280 !amdgpu_sriov_vf(adev)) { 281 inv_req = RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 282 /* bit 25: RSERVED_CACHE_PRIVATE_INVALIDATION */ 283 inv_req |= (1 << 25); 284 /* Issue private invalidation */ 285 WREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2, inv_req); 286 /* Read back to ensure invalidation is done*/ 287 RREG32_NO_KIQ(hub->vm_l2_bank_select_reserved_cid2); 288 } 289 290 spin_unlock(&adev->gmc.invalidate_lock); 291 292 if (i >= adev->usec_timeout) 293 dev_err(adev->dev, "Timeout waiting for VM flush ACK!\n"); 294 } 295 296 /** 297 * gmc_v11_0_flush_gpu_tlb_pasid - tlb flush via pasid 298 * 299 * @adev: amdgpu_device pointer 300 * @pasid: pasid to be flush 301 * @flush_type: the flush type 302 * @all_hub: flush all hubs 303 * @inst: is used to select which instance of KIQ to use for the invalidation 304 * 305 * Flush the TLB for the requested pasid. 306 */ 307 static void gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 308 uint16_t pasid, uint32_t flush_type, 309 bool all_hub, uint32_t inst) 310 { 311 uint16_t queried; 312 int vmid, i; 313 314 for (vmid = 1; vmid < 16; vmid++) { 315 bool valid; 316 317 valid = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, 318 &queried); 319 if (!valid || queried != pasid) 320 continue; 321 322 if (all_hub) { 323 for_each_set_bit(i, adev->vmhubs_mask, 324 AMDGPU_MAX_VMHUBS) 325 gmc_v11_0_flush_gpu_tlb(adev, vmid, i, 326 flush_type); 327 } else { 328 gmc_v11_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 329 flush_type); 330 } 331 } 332 } 333 334 static uint64_t gmc_v11_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 335 unsigned int vmid, uint64_t pd_addr) 336 { 337 bool use_semaphore = gmc_v11_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 338 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 339 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 340 unsigned int eng = ring->vm_inv_eng; 341 342 /* 343 * It may lose gpuvm invalidate acknowldege state across power-gating 344 * off cycle, add semaphore acquire before invalidation and semaphore 345 * release after invalidation to avoid entering power gated state 346 * to WA the Issue 347 */ 348 349 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 350 if (use_semaphore) 351 /* a read return value of 1 means semaphore acuqire */ 352 amdgpu_ring_emit_reg_wait(ring, 353 hub->vm_inv_eng0_sem + 354 hub->eng_distance * eng, 0x1, 0x1); 355 356 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 357 (hub->ctx_addr_distance * vmid), 358 lower_32_bits(pd_addr)); 359 360 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 361 (hub->ctx_addr_distance * vmid), 362 upper_32_bits(pd_addr)); 363 364 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 365 hub->eng_distance * eng, 366 hub->vm_inv_eng0_ack + 367 hub->eng_distance * eng, 368 req, 1 << vmid); 369 370 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 371 if (use_semaphore) 372 /* 373 * add semaphore release after invalidation, 374 * write with 0 means semaphore release 375 */ 376 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 377 hub->eng_distance * eng, 0); 378 379 return pd_addr; 380 } 381 382 static void gmc_v11_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 383 unsigned int pasid) 384 { 385 struct amdgpu_device *adev = ring->adev; 386 uint32_t reg; 387 388 /* MES fw manages IH_VMID_x_LUT updating */ 389 if (ring->is_mes_queue) 390 return; 391 392 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 393 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid; 394 else 395 reg = SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid; 396 397 amdgpu_ring_emit_wreg(ring, reg, pasid); 398 } 399 400 /* 401 * PTE format: 402 * 63:59 reserved 403 * 58:57 reserved 404 * 56 F 405 * 55 L 406 * 54 reserved 407 * 53:52 SW 408 * 51 T 409 * 50:48 mtype 410 * 47:12 4k physical page base address 411 * 11:7 fragment 412 * 6 write 413 * 5 read 414 * 4 exe 415 * 3 Z 416 * 2 snooped 417 * 1 system 418 * 0 valid 419 * 420 * PDE format: 421 * 63:59 block fragment size 422 * 58:55 reserved 423 * 54 P 424 * 53:48 reserved 425 * 47:6 physical base address of PD or PTE 426 * 5:3 reserved 427 * 2 C 428 * 1 system 429 * 0 valid 430 */ 431 432 static uint64_t gmc_v11_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 433 { 434 switch (flags) { 435 case AMDGPU_VM_MTYPE_DEFAULT: 436 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 437 case AMDGPU_VM_MTYPE_NC: 438 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 439 case AMDGPU_VM_MTYPE_WC: 440 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 441 case AMDGPU_VM_MTYPE_CC: 442 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 443 case AMDGPU_VM_MTYPE_UC: 444 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 445 default: 446 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 447 } 448 } 449 450 static void gmc_v11_0_get_vm_pde(struct amdgpu_device *adev, int level, 451 uint64_t *addr, uint64_t *flags) 452 { 453 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 454 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 455 BUG_ON(*addr & 0xFFFF00000000003FULL); 456 457 if (!adev->gmc.translate_further) 458 return; 459 460 if (level == AMDGPU_VM_PDB1) { 461 /* Set the block fragment size */ 462 if (!(*flags & AMDGPU_PDE_PTE)) 463 *flags |= AMDGPU_PDE_BFS(0x9); 464 465 } else if (level == AMDGPU_VM_PDB0) { 466 if (*flags & AMDGPU_PDE_PTE) 467 *flags &= ~AMDGPU_PDE_PTE; 468 else 469 *flags |= AMDGPU_PTE_TF; 470 } 471 } 472 473 static void gmc_v11_0_get_vm_pte(struct amdgpu_device *adev, 474 struct amdgpu_bo_va_mapping *mapping, 475 uint64_t *flags) 476 { 477 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 478 479 *flags &= ~AMDGPU_PTE_EXECUTABLE; 480 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 481 482 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 483 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 484 485 *flags &= ~AMDGPU_PTE_NOALLOC; 486 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 487 488 if (mapping->flags & AMDGPU_PTE_PRT) { 489 *flags |= AMDGPU_PTE_PRT; 490 *flags |= AMDGPU_PTE_SNOOPED; 491 *flags |= AMDGPU_PTE_LOG; 492 *flags |= AMDGPU_PTE_SYSTEM; 493 *flags &= ~AMDGPU_PTE_VALID; 494 } 495 496 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 497 AMDGPU_GEM_CREATE_EXT_COHERENT | 498 AMDGPU_GEM_CREATE_UNCACHED)) 499 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 500 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 501 } 502 503 static unsigned int gmc_v11_0_get_vbios_fb_size(struct amdgpu_device *adev) 504 { 505 u32 d1vga_control = RREG32_SOC15(DCE, 0, regD1VGA_CONTROL); 506 unsigned int size; 507 508 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 509 size = AMDGPU_VBIOS_VGA_ALLOCATION; 510 } else { 511 u32 viewport; 512 u32 pitch; 513 514 viewport = RREG32_SOC15(DCE, 0, regHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 515 pitch = RREG32_SOC15(DCE, 0, regHUBPREQ0_DCSURF_SURFACE_PITCH); 516 size = (REG_GET_FIELD(viewport, 517 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 518 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 519 4); 520 } 521 522 return size; 523 } 524 525 static const struct amdgpu_gmc_funcs gmc_v11_0_gmc_funcs = { 526 .flush_gpu_tlb = gmc_v11_0_flush_gpu_tlb, 527 .flush_gpu_tlb_pasid = gmc_v11_0_flush_gpu_tlb_pasid, 528 .emit_flush_gpu_tlb = gmc_v11_0_emit_flush_gpu_tlb, 529 .emit_pasid_mapping = gmc_v11_0_emit_pasid_mapping, 530 .map_mtype = gmc_v11_0_map_mtype, 531 .get_vm_pde = gmc_v11_0_get_vm_pde, 532 .get_vm_pte = gmc_v11_0_get_vm_pte, 533 .get_vbios_fb_size = gmc_v11_0_get_vbios_fb_size, 534 }; 535 536 static void gmc_v11_0_set_gmc_funcs(struct amdgpu_device *adev) 537 { 538 adev->gmc.gmc_funcs = &gmc_v11_0_gmc_funcs; 539 } 540 541 static void gmc_v11_0_set_umc_funcs(struct amdgpu_device *adev) 542 { 543 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 544 case IP_VERSION(8, 10, 0): 545 adev->umc.channel_inst_num = UMC_V8_10_CHANNEL_INSTANCE_NUM; 546 adev->umc.umc_inst_num = UMC_V8_10_UMC_INSTANCE_NUM; 547 adev->umc.max_ras_err_cnt_per_query = UMC_V8_10_TOTAL_CHANNEL_NUM(adev); 548 adev->umc.channel_offs = UMC_V8_10_PER_CHANNEL_OFFSET; 549 adev->umc.retire_unit = UMC_V8_10_NA_COL_2BITS_POWER_OF_2_NUM; 550 if (adev->umc.node_inst_num == 4) 551 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl_ext0[0][0][0]; 552 else 553 adev->umc.channel_idx_tbl = &umc_v8_10_channel_idx_tbl[0][0][0]; 554 adev->umc.ras = &umc_v8_10_ras; 555 break; 556 case IP_VERSION(8, 11, 0): 557 break; 558 default: 559 break; 560 } 561 } 562 563 564 static void gmc_v11_0_set_mmhub_funcs(struct amdgpu_device *adev) 565 { 566 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 567 case IP_VERSION(3, 0, 1): 568 adev->mmhub.funcs = &mmhub_v3_0_1_funcs; 569 break; 570 case IP_VERSION(3, 0, 2): 571 adev->mmhub.funcs = &mmhub_v3_0_2_funcs; 572 break; 573 case IP_VERSION(3, 3, 0): 574 case IP_VERSION(3, 3, 1): 575 adev->mmhub.funcs = &mmhub_v3_3_funcs; 576 break; 577 default: 578 adev->mmhub.funcs = &mmhub_v3_0_funcs; 579 break; 580 } 581 } 582 583 static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) 584 { 585 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 586 case IP_VERSION(11, 0, 3): 587 adev->gfxhub.funcs = &gfxhub_v3_0_3_funcs; 588 break; 589 case IP_VERSION(11, 5, 0): 590 adev->gfxhub.funcs = &gfxhub_v11_5_0_funcs; 591 break; 592 default: 593 adev->gfxhub.funcs = &gfxhub_v3_0_funcs; 594 break; 595 } 596 } 597 598 static int gmc_v11_0_early_init(void *handle) 599 { 600 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 601 602 gmc_v11_0_set_gfxhub_funcs(adev); 603 gmc_v11_0_set_mmhub_funcs(adev); 604 gmc_v11_0_set_gmc_funcs(adev); 605 gmc_v11_0_set_irq_funcs(adev); 606 gmc_v11_0_set_umc_funcs(adev); 607 608 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 609 adev->gmc.shared_aperture_end = 610 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 611 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 612 adev->gmc.private_aperture_end = 613 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 614 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 615 616 return 0; 617 } 618 619 static int gmc_v11_0_late_init(void *handle) 620 { 621 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 622 int r; 623 624 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 625 if (r) 626 return r; 627 628 r = amdgpu_gmc_ras_late_init(adev); 629 if (r) 630 return r; 631 632 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 633 } 634 635 static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, 636 struct amdgpu_gmc *mc) 637 { 638 u64 base = 0; 639 640 base = adev->mmhub.funcs->get_fb_location(adev); 641 642 amdgpu_gmc_set_agp_default(adev, mc); 643 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 644 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH); 645 if (!amdgpu_sriov_vf(adev) && 646 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 5, 0)) && 647 (amdgpu_agp == 1)) 648 amdgpu_gmc_agp_location(adev, mc); 649 650 /* base offset of vram pages */ 651 if (amdgpu_sriov_vf(adev)) 652 adev->vm_manager.vram_base_offset = 0; 653 else 654 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); 655 } 656 657 /** 658 * gmc_v11_0_mc_init - initialize the memory controller driver params 659 * 660 * @adev: amdgpu_device pointer 661 * 662 * Look up the amount of vram, vram width, and decide how to place 663 * vram and gart within the GPU's physical address space. 664 * Returns 0 for success. 665 */ 666 static int gmc_v11_0_mc_init(struct amdgpu_device *adev) 667 { 668 int r; 669 670 /* size in MB on si */ 671 adev->gmc.mc_vram_size = 672 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 673 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 674 675 if (!(adev->flags & AMD_IS_APU)) { 676 r = amdgpu_device_resize_fb_bar(adev); 677 if (r) 678 return r; 679 } 680 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 681 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 682 683 #ifdef CONFIG_X86_64 684 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 685 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); 686 adev->gmc.aper_size = adev->gmc.real_vram_size; 687 } 688 #endif 689 /* In case the PCI BAR is larger than the actual amount of vram */ 690 adev->gmc.visible_vram_size = adev->gmc.aper_size; 691 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 692 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 693 694 /* set the gart size */ 695 if (amdgpu_gart_size == -1) 696 adev->gmc.gart_size = 512ULL << 20; 697 else 698 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 699 700 gmc_v11_0_vram_gtt_location(adev, &adev->gmc); 701 702 return 0; 703 } 704 705 static int gmc_v11_0_gart_init(struct amdgpu_device *adev) 706 { 707 int r; 708 709 if (adev->gart.bo) { 710 WARN(1, "PCIE GART already initialized\n"); 711 return 0; 712 } 713 714 /* Initialize common gart structure */ 715 r = amdgpu_gart_init(adev); 716 if (r) 717 return r; 718 719 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 720 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 721 AMDGPU_PTE_EXECUTABLE; 722 723 return amdgpu_gart_table_vram_alloc(adev); 724 } 725 726 static int gmc_v11_0_sw_init(void *handle) 727 { 728 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 729 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 730 731 adev->mmhub.funcs->init(adev); 732 733 adev->gfxhub.funcs->init(adev); 734 735 spin_lock_init(&adev->gmc.invalidate_lock); 736 737 r = amdgpu_atomfirmware_get_vram_info(adev, 738 &vram_width, &vram_type, &vram_vendor); 739 adev->gmc.vram_width = vram_width; 740 741 adev->gmc.vram_type = vram_type; 742 adev->gmc.vram_vendor = vram_vendor; 743 744 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 745 case IP_VERSION(11, 0, 0): 746 case IP_VERSION(11, 0, 1): 747 case IP_VERSION(11, 0, 2): 748 case IP_VERSION(11, 0, 3): 749 case IP_VERSION(11, 0, 4): 750 case IP_VERSION(11, 5, 0): 751 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 752 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 753 /* 754 * To fulfill 4-level page support, 755 * vm size is 256TB (48bit), maximum size, 756 * block size 512 (9bit) 757 */ 758 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 759 break; 760 default: 761 break; 762 } 763 764 /* This interrupt is VMC page fault.*/ 765 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_VMC, 766 VMC_1_0__SRCID__VM_FAULT, 767 &adev->gmc.vm_fault); 768 769 if (r) 770 return r; 771 772 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX, 773 UTCL2_1_0__SRCID__FAULT, 774 &adev->gmc.vm_fault); 775 if (r) 776 return r; 777 778 if (!amdgpu_sriov_vf(adev)) { 779 /* interrupt sent to DF. */ 780 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_DF, 0, 781 &adev->gmc.ecc_irq); 782 if (r) 783 return r; 784 } 785 786 /* 787 * Set the internal MC address mask This is the max address of the GPU's 788 * internal address space. 789 */ 790 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 791 792 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 793 if (r) { 794 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 795 return r; 796 } 797 798 adev->need_swiotlb = drm_need_swiotlb(44); 799 800 r = gmc_v11_0_mc_init(adev); 801 if (r) 802 return r; 803 804 amdgpu_gmc_get_vbios_allocations(adev); 805 806 /* Memory manager */ 807 r = amdgpu_bo_init(adev); 808 if (r) 809 return r; 810 811 r = gmc_v11_0_gart_init(adev); 812 if (r) 813 return r; 814 815 /* 816 * number of VMs 817 * VMID 0 is reserved for System 818 * amdgpu graphics/compute will use VMIDs 1-7 819 * amdkfd will use VMIDs 8-15 820 */ 821 adev->vm_manager.first_kfd_vmid = 8; 822 823 amdgpu_vm_manager_init(adev); 824 825 r = amdgpu_gmc_ras_sw_init(adev); 826 if (r) 827 return r; 828 829 return 0; 830 } 831 832 /** 833 * gmc_v11_0_gart_fini - vm fini callback 834 * 835 * @adev: amdgpu_device pointer 836 * 837 * Tears down the driver GART/VM setup (CIK). 838 */ 839 static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) 840 { 841 amdgpu_gart_table_vram_free(adev); 842 } 843 844 static int gmc_v11_0_sw_fini(void *handle) 845 { 846 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 847 848 amdgpu_vm_manager_fini(adev); 849 gmc_v11_0_gart_fini(adev); 850 amdgpu_gem_force_release(adev); 851 amdgpu_bo_fini(adev); 852 853 return 0; 854 } 855 856 static void gmc_v11_0_init_golden_registers(struct amdgpu_device *adev) 857 { 858 if (amdgpu_sriov_vf(adev)) { 859 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; 860 861 WREG32(hub->vm_contexts_disable, 0); 862 return; 863 } 864 } 865 866 /** 867 * gmc_v11_0_gart_enable - gart enable 868 * 869 * @adev: amdgpu_device pointer 870 */ 871 static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) 872 { 873 int r; 874 bool value; 875 876 if (adev->gart.bo == NULL) { 877 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 878 return -EINVAL; 879 } 880 881 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 882 883 r = adev->mmhub.funcs->gart_enable(adev); 884 if (r) 885 return r; 886 887 /* Flush HDP after it is initialized */ 888 adev->hdp.funcs->flush_hdp(adev, NULL); 889 890 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 891 false : true; 892 893 adev->mmhub.funcs->set_fault_enable_default(adev, value); 894 gmc_v11_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 895 896 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 897 (unsigned int)(adev->gmc.gart_size >> 20), 898 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 899 900 return 0; 901 } 902 903 static int gmc_v11_0_hw_init(void *handle) 904 { 905 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 906 int r; 907 908 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; 909 910 /* The sequence of these two function calls matters.*/ 911 gmc_v11_0_init_golden_registers(adev); 912 913 r = gmc_v11_0_gart_enable(adev); 914 if (r) 915 return r; 916 917 if (adev->umc.funcs && adev->umc.funcs->init_registers) 918 adev->umc.funcs->init_registers(adev); 919 920 return 0; 921 } 922 923 /** 924 * gmc_v11_0_gart_disable - gart disable 925 * 926 * @adev: amdgpu_device pointer 927 * 928 * This disables all VM page table. 929 */ 930 static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) 931 { 932 adev->mmhub.funcs->gart_disable(adev); 933 } 934 935 static int gmc_v11_0_hw_fini(void *handle) 936 { 937 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 938 939 if (amdgpu_sriov_vf(adev)) { 940 /* full access mode, so don't touch any GMC register */ 941 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 942 return 0; 943 } 944 945 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 946 947 if (adev->gmc.ecc_irq.funcs && 948 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 949 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 950 951 gmc_v11_0_gart_disable(adev); 952 953 return 0; 954 } 955 956 static int gmc_v11_0_suspend(void *handle) 957 { 958 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 959 960 gmc_v11_0_hw_fini(adev); 961 962 return 0; 963 } 964 965 static int gmc_v11_0_resume(void *handle) 966 { 967 int r; 968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 969 970 r = gmc_v11_0_hw_init(adev); 971 if (r) 972 return r; 973 974 amdgpu_vmid_reset_all(adev); 975 976 return 0; 977 } 978 979 static bool gmc_v11_0_is_idle(void *handle) 980 { 981 /* MC is always ready in GMC v11.*/ 982 return true; 983 } 984 985 static int gmc_v11_0_wait_for_idle(void *handle) 986 { 987 /* There is no need to wait for MC idle in GMC v11.*/ 988 return 0; 989 } 990 991 static int gmc_v11_0_soft_reset(void *handle) 992 { 993 return 0; 994 } 995 996 static int gmc_v11_0_set_clockgating_state(void *handle, 997 enum amd_clockgating_state state) 998 { 999 int r; 1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1001 1002 r = adev->mmhub.funcs->set_clockgating(adev, state); 1003 if (r) 1004 return r; 1005 1006 return athub_v3_0_set_clockgating(adev, state); 1007 } 1008 1009 static void gmc_v11_0_get_clockgating_state(void *handle, u64 *flags) 1010 { 1011 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1012 1013 adev->mmhub.funcs->get_clockgating(adev, flags); 1014 1015 athub_v3_0_get_clockgating(adev, flags); 1016 } 1017 1018 static int gmc_v11_0_set_powergating_state(void *handle, 1019 enum amd_powergating_state state) 1020 { 1021 return 0; 1022 } 1023 1024 const struct amd_ip_funcs gmc_v11_0_ip_funcs = { 1025 .name = "gmc_v11_0", 1026 .early_init = gmc_v11_0_early_init, 1027 .sw_init = gmc_v11_0_sw_init, 1028 .hw_init = gmc_v11_0_hw_init, 1029 .late_init = gmc_v11_0_late_init, 1030 .sw_fini = gmc_v11_0_sw_fini, 1031 .hw_fini = gmc_v11_0_hw_fini, 1032 .suspend = gmc_v11_0_suspend, 1033 .resume = gmc_v11_0_resume, 1034 .is_idle = gmc_v11_0_is_idle, 1035 .wait_for_idle = gmc_v11_0_wait_for_idle, 1036 .soft_reset = gmc_v11_0_soft_reset, 1037 .set_clockgating_state = gmc_v11_0_set_clockgating_state, 1038 .set_powergating_state = gmc_v11_0_set_powergating_state, 1039 .get_clockgating_state = gmc_v11_0_get_clockgating_state, 1040 }; 1041 1042 const struct amdgpu_ip_block_version gmc_v11_0_ip_block = { 1043 .type = AMD_IP_BLOCK_TYPE_GMC, 1044 .major = 11, 1045 .minor = 0, 1046 .rev = 0, 1047 .funcs = &gmc_v11_0_ip_funcs, 1048 }; 1049