1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 #include "amdgpu.h" 26 #include "amdgpu_atomfirmware.h" 27 #include "gmc_v10_0.h" 28 #include "umc_v8_7.h" 29 30 #include "athub/athub_2_0_0_sh_mask.h" 31 #include "athub/athub_2_0_0_offset.h" 32 #include "dcn/dcn_2_0_0_offset.h" 33 #include "dcn/dcn_2_0_0_sh_mask.h" 34 #include "oss/osssys_5_0_0_offset.h" 35 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 36 #include "navi10_enum.h" 37 38 #include "soc15.h" 39 #include "soc15d.h" 40 #include "soc15_common.h" 41 42 #include "nbio_v2_3.h" 43 44 #include "gfxhub_v2_0.h" 45 #include "gfxhub_v2_1.h" 46 #include "mmhub_v2_0.h" 47 #include "mmhub_v2_3.h" 48 #include "athub_v2_0.h" 49 #include "athub_v2_1.h" 50 51 #if 0 52 static const struct soc15_reg_golden golden_settings_navi10_hdp[] = 53 { 54 /* TODO add golden setting for hdp */ 55 }; 56 #endif 57 58 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 59 struct amdgpu_irq_src *src, 60 unsigned type, 61 enum amdgpu_interrupt_state state) 62 { 63 return 0; 64 } 65 66 static int 67 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 68 struct amdgpu_irq_src *src, unsigned type, 69 enum amdgpu_interrupt_state state) 70 { 71 switch (state) { 72 case AMDGPU_IRQ_STATE_DISABLE: 73 /* MM HUB */ 74 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false); 75 /* GFX HUB */ 76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false); 77 break; 78 case AMDGPU_IRQ_STATE_ENABLE: 79 /* MM HUB */ 80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true); 81 /* GFX HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true); 83 break; 84 default: 85 break; 86 } 87 88 return 0; 89 } 90 91 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 92 struct amdgpu_irq_src *source, 93 struct amdgpu_iv_entry *entry) 94 { 95 bool retry_fault = !!(entry->src_data[1] & 0x80); 96 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src]; 97 struct amdgpu_task_info task_info; 98 uint32_t status = 0; 99 u64 addr; 100 101 addr = (u64)entry->src_data[0] << 12; 102 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 103 104 if (retry_fault) { 105 /* Returning 1 here also prevents sending the IV to the KFD */ 106 107 /* Process it onyl if it's the first fault for this address */ 108 if (entry->ih != &adev->irq.ih_soft && 109 amdgpu_gmc_filter_faults(adev, addr, entry->pasid, 110 entry->timestamp)) 111 return 1; 112 113 /* Delegate it to a different ring if the hardware hasn't 114 * already done it. 115 */ 116 if (entry->ih == &adev->irq.ih) { 117 amdgpu_irq_delegate(adev, entry, 8); 118 return 1; 119 } 120 121 /* Try to handle the recoverable page faults by filling page 122 * tables 123 */ 124 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr)) 125 return 1; 126 } 127 128 if (!amdgpu_sriov_vf(adev)) { 129 /* 130 * Issue a dummy read to wait for the status register to 131 * be updated to avoid reading an incorrect value due to 132 * the new fast GRBM interface. 133 */ 134 if ((entry->vmid_src == AMDGPU_GFXHUB_0) && 135 (adev->asic_type < CHIP_SIENNA_CICHLID)) 136 RREG32(hub->vm_l2_pro_fault_status); 137 138 status = RREG32(hub->vm_l2_pro_fault_status); 139 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 140 } 141 142 if (!printk_ratelimit()) 143 return 0; 144 145 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 146 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 147 148 dev_err(adev->dev, 149 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, " 150 "for process %s pid %d thread %s pid %d)\n", 151 entry->vmid_src ? "mmhub" : "gfxhub", 152 entry->src_id, entry->ring_id, entry->vmid, 153 entry->pasid, task_info.process_name, task_info.tgid, 154 task_info.task_name, task_info.pid); 155 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 156 addr, entry->client_id, 157 soc15_ih_clientid_name[entry->client_id]); 158 159 if (!amdgpu_sriov_vf(adev)) 160 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 161 status); 162 163 return 0; 164 } 165 166 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 167 .set = gmc_v10_0_vm_fault_interrupt_state, 168 .process = gmc_v10_0_process_interrupt, 169 }; 170 171 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 172 .set = gmc_v10_0_ecc_interrupt_state, 173 .process = amdgpu_umc_process_ecc_irq, 174 }; 175 176 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 177 { 178 adev->gmc.vm_fault.num_types = 1; 179 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 180 181 if (!amdgpu_sriov_vf(adev)) { 182 adev->gmc.ecc_irq.num_types = 1; 183 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 184 } 185 } 186 187 /** 188 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 189 * 190 * @adev: amdgpu_device pointer 191 * @vmhub: vmhub type 192 * 193 */ 194 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 195 uint32_t vmhub) 196 { 197 return ((vmhub == AMDGPU_MMHUB_0 || 198 vmhub == AMDGPU_MMHUB_1) && 199 (!amdgpu_sriov_vf(adev))); 200 } 201 202 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 203 struct amdgpu_device *adev, 204 uint8_t vmid, uint16_t *p_pasid) 205 { 206 uint32_t value; 207 208 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 209 + vmid); 210 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 211 212 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 213 } 214 215 /* 216 * GART 217 * VMID 0 is the physical GPU addresses as used by the kernel. 218 * VMIDs 1-15 are used for userspace clients and are handled 219 * by the amdgpu vm/hsa code. 220 */ 221 222 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 223 unsigned int vmhub, uint32_t flush_type) 224 { 225 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 226 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 227 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 228 u32 tmp; 229 /* Use register 17 for GART */ 230 const unsigned eng = 17; 231 unsigned int i; 232 233 spin_lock(&adev->gmc.invalidate_lock); 234 /* 235 * It may lose gpuvm invalidate acknowldege state across power-gating 236 * off cycle, add semaphore acquire before invalidation and semaphore 237 * release after invalidation to avoid entering power gated state 238 * to WA the Issue 239 */ 240 241 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 242 if (use_semaphore) { 243 for (i = 0; i < adev->usec_timeout; i++) { 244 /* a read return value of 1 means semaphore acuqire */ 245 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + 246 hub->eng_distance * eng); 247 if (tmp & 0x1) 248 break; 249 udelay(1); 250 } 251 252 if (i >= adev->usec_timeout) 253 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 254 } 255 256 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req); 257 258 /* 259 * Issue a dummy read to wait for the ACK register to be cleared 260 * to avoid a false ACK due to the new fast GRBM interface. 261 */ 262 if ((vmhub == AMDGPU_GFXHUB_0) && 263 (adev->asic_type < CHIP_SIENNA_CICHLID)) 264 RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng); 265 266 /* Wait for ACK with a delay.*/ 267 for (i = 0; i < adev->usec_timeout; i++) { 268 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + 269 hub->eng_distance * eng); 270 tmp &= 1 << vmid; 271 if (tmp) 272 break; 273 274 udelay(1); 275 } 276 277 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 278 if (use_semaphore) 279 /* 280 * add semaphore release after invalidation, 281 * write with 0 means semaphore release 282 */ 283 WREG32_NO_KIQ(hub->vm_inv_eng0_sem + 284 hub->eng_distance * eng, 0); 285 286 spin_unlock(&adev->gmc.invalidate_lock); 287 288 if (i < adev->usec_timeout) 289 return; 290 291 DRM_ERROR("Timeout waiting for VM flush ACK!\n"); 292 } 293 294 /** 295 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 296 * 297 * @adev: amdgpu_device pointer 298 * @vmid: vm instance to flush 299 * @vmhub: vmhub type 300 * @flush_type: the flush type 301 * 302 * Flush the TLB for the requested page table. 303 */ 304 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 305 uint32_t vmhub, uint32_t flush_type) 306 { 307 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 308 struct dma_fence *fence; 309 struct amdgpu_job *job; 310 311 int r; 312 313 /* flush hdp cache */ 314 adev->hdp.funcs->flush_hdp(adev, NULL); 315 316 /* For SRIOV run time, driver shouldn't access the register through MMIO 317 * Directly use kiq to do the vm invalidation instead 318 */ 319 if (adev->gfx.kiq.ring.sched.ready && 320 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 321 down_read_trylock(&adev->reset_sem)) { 322 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 323 const unsigned eng = 17; 324 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 325 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 326 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 327 328 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 329 1 << vmid); 330 331 up_read(&adev->reset_sem); 332 return; 333 } 334 335 mutex_lock(&adev->mman.gtt_window_lock); 336 337 if (vmhub == AMDGPU_MMHUB_0) { 338 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); 339 mutex_unlock(&adev->mman.gtt_window_lock); 340 return; 341 } 342 343 BUG_ON(vmhub != AMDGPU_GFXHUB_0); 344 345 if (!adev->mman.buffer_funcs_enabled || 346 !adev->ib_pool_ready || 347 amdgpu_in_reset(adev) || 348 ring->sched.ready == false) { 349 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); 350 mutex_unlock(&adev->mman.gtt_window_lock); 351 return; 352 } 353 354 /* The SDMA on Navi has a bug which can theoretically result in memory 355 * corruption if an invalidation happens at the same time as an VA 356 * translation. Avoid this by doing the invalidation from the SDMA 357 * itself. 358 */ 359 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 360 &job); 361 if (r) 362 goto error_alloc; 363 364 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 365 job->vm_needs_flush = true; 366 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 367 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 368 r = amdgpu_job_submit(job, &adev->mman.entity, 369 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 370 if (r) 371 goto error_submit; 372 373 mutex_unlock(&adev->mman.gtt_window_lock); 374 375 dma_fence_wait(fence, false); 376 dma_fence_put(fence); 377 378 return; 379 380 error_submit: 381 amdgpu_job_free(job); 382 383 error_alloc: 384 mutex_unlock(&adev->mman.gtt_window_lock); 385 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 386 } 387 388 /** 389 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 390 * 391 * @adev: amdgpu_device pointer 392 * @pasid: pasid to be flush 393 * @flush_type: the flush type 394 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 395 * 396 * Flush the TLB for the requested pasid. 397 */ 398 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 399 uint16_t pasid, uint32_t flush_type, 400 bool all_hub) 401 { 402 int vmid, i; 403 signed long r; 404 uint32_t seq; 405 uint16_t queried_pasid; 406 bool ret; 407 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 408 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 409 410 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 411 spin_lock(&adev->gfx.kiq.ring_lock); 412 /* 2 dwords flush + 8 dwords fence */ 413 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 414 kiq->pmf->kiq_invalidate_tlbs(ring, 415 pasid, flush_type, all_hub); 416 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 417 if (r) { 418 amdgpu_ring_undo(ring); 419 spin_unlock(&adev->gfx.kiq.ring_lock); 420 return -ETIME; 421 } 422 423 amdgpu_ring_commit(ring); 424 spin_unlock(&adev->gfx.kiq.ring_lock); 425 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 426 if (r < 1) { 427 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 428 return -ETIME; 429 } 430 431 return 0; 432 } 433 434 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 435 436 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 437 &queried_pasid); 438 if (ret && queried_pasid == pasid) { 439 if (all_hub) { 440 for (i = 0; i < adev->num_vmhubs; i++) 441 gmc_v10_0_flush_gpu_tlb(adev, vmid, 442 i, flush_type); 443 } else { 444 gmc_v10_0_flush_gpu_tlb(adev, vmid, 445 AMDGPU_GFXHUB_0, flush_type); 446 } 447 break; 448 } 449 } 450 451 return 0; 452 } 453 454 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 455 unsigned vmid, uint64_t pd_addr) 456 { 457 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub); 458 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 459 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 460 unsigned eng = ring->vm_inv_eng; 461 462 /* 463 * It may lose gpuvm invalidate acknowldege state across power-gating 464 * off cycle, add semaphore acquire before invalidation and semaphore 465 * release after invalidation to avoid entering power gated state 466 * to WA the Issue 467 */ 468 469 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 470 if (use_semaphore) 471 /* a read return value of 1 means semaphore acuqire */ 472 amdgpu_ring_emit_reg_wait(ring, 473 hub->vm_inv_eng0_sem + 474 hub->eng_distance * eng, 0x1, 0x1); 475 476 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 477 (hub->ctx_addr_distance * vmid), 478 lower_32_bits(pd_addr)); 479 480 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 481 (hub->ctx_addr_distance * vmid), 482 upper_32_bits(pd_addr)); 483 484 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 485 hub->eng_distance * eng, 486 hub->vm_inv_eng0_ack + 487 hub->eng_distance * eng, 488 req, 1 << vmid); 489 490 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 491 if (use_semaphore) 492 /* 493 * add semaphore release after invalidation, 494 * write with 0 means semaphore release 495 */ 496 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 497 hub->eng_distance * eng, 0); 498 499 return pd_addr; 500 } 501 502 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, 503 unsigned pasid) 504 { 505 struct amdgpu_device *adev = ring->adev; 506 uint32_t reg; 507 508 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) 509 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 510 else 511 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 512 513 amdgpu_ring_emit_wreg(ring, reg, pasid); 514 } 515 516 /* 517 * PTE format on NAVI 10: 518 * 63:59 reserved 519 * 58 reserved and for sienna_cichlid is used for MALL noalloc 520 * 57 reserved 521 * 56 F 522 * 55 L 523 * 54 reserved 524 * 53:52 SW 525 * 51 T 526 * 50:48 mtype 527 * 47:12 4k physical page base address 528 * 11:7 fragment 529 * 6 write 530 * 5 read 531 * 4 exe 532 * 3 Z 533 * 2 snooped 534 * 1 system 535 * 0 valid 536 * 537 * PDE format on NAVI 10: 538 * 63:59 block fragment size 539 * 58:55 reserved 540 * 54 P 541 * 53:48 reserved 542 * 47:6 physical base address of PD or PTE 543 * 5:3 reserved 544 * 2 C 545 * 1 system 546 * 0 valid 547 */ 548 549 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 550 { 551 switch (flags) { 552 case AMDGPU_VM_MTYPE_DEFAULT: 553 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 554 case AMDGPU_VM_MTYPE_NC: 555 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 556 case AMDGPU_VM_MTYPE_WC: 557 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 558 case AMDGPU_VM_MTYPE_CC: 559 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 560 case AMDGPU_VM_MTYPE_UC: 561 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 562 default: 563 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 564 } 565 } 566 567 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 568 uint64_t *addr, uint64_t *flags) 569 { 570 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 571 *addr = adev->vm_manager.vram_base_offset + *addr - 572 adev->gmc.vram_start; 573 BUG_ON(*addr & 0xFFFF00000000003FULL); 574 575 if (!adev->gmc.translate_further) 576 return; 577 578 if (level == AMDGPU_VM_PDB1) { 579 /* Set the block fragment size */ 580 if (!(*flags & AMDGPU_PDE_PTE)) 581 *flags |= AMDGPU_PDE_BFS(0x9); 582 583 } else if (level == AMDGPU_VM_PDB0) { 584 if (*flags & AMDGPU_PDE_PTE) 585 *flags &= ~AMDGPU_PDE_PTE; 586 else 587 *flags |= AMDGPU_PTE_TF; 588 } 589 } 590 591 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 592 struct amdgpu_bo_va_mapping *mapping, 593 uint64_t *flags) 594 { 595 *flags &= ~AMDGPU_PTE_EXECUTABLE; 596 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 597 598 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 599 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 600 601 if (mapping->flags & AMDGPU_PTE_PRT) { 602 *flags |= AMDGPU_PTE_PRT; 603 *flags |= AMDGPU_PTE_SNOOPED; 604 *flags |= AMDGPU_PTE_LOG; 605 *flags |= AMDGPU_PTE_SYSTEM; 606 *flags &= ~AMDGPU_PTE_VALID; 607 } 608 } 609 610 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 611 { 612 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 613 unsigned size; 614 615 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 616 size = AMDGPU_VBIOS_VGA_ALLOCATION; 617 } else { 618 u32 viewport; 619 u32 pitch; 620 621 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 622 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 623 size = (REG_GET_FIELD(viewport, 624 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 625 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 626 4); 627 } 628 629 return size; 630 } 631 632 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 633 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 634 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 635 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 636 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 637 .map_mtype = gmc_v10_0_map_mtype, 638 .get_vm_pde = gmc_v10_0_get_vm_pde, 639 .get_vm_pte = gmc_v10_0_get_vm_pte, 640 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 641 }; 642 643 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 644 { 645 if (adev->gmc.gmc_funcs == NULL) 646 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 647 } 648 649 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 650 { 651 switch (adev->asic_type) { 652 case CHIP_SIENNA_CICHLID: 653 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 654 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 655 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 656 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 657 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 658 adev->umc.ras_funcs = &umc_v8_7_ras_funcs; 659 break; 660 default: 661 break; 662 } 663 } 664 665 666 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 667 { 668 switch (adev->asic_type) { 669 case CHIP_VANGOGH: 670 adev->mmhub.funcs = &mmhub_v2_3_funcs; 671 break; 672 default: 673 adev->mmhub.funcs = &mmhub_v2_0_funcs; 674 break; 675 } 676 } 677 678 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 679 { 680 switch (adev->asic_type) { 681 case CHIP_SIENNA_CICHLID: 682 case CHIP_NAVY_FLOUNDER: 683 case CHIP_VANGOGH: 684 case CHIP_DIMGREY_CAVEFISH: 685 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 686 break; 687 default: 688 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 689 break; 690 } 691 } 692 693 694 static int gmc_v10_0_early_init(void *handle) 695 { 696 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 697 698 gmc_v10_0_set_mmhub_funcs(adev); 699 gmc_v10_0_set_gfxhub_funcs(adev); 700 gmc_v10_0_set_gmc_funcs(adev); 701 gmc_v10_0_set_irq_funcs(adev); 702 gmc_v10_0_set_umc_funcs(adev); 703 704 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 705 adev->gmc.shared_aperture_end = 706 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 707 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 708 adev->gmc.private_aperture_end = 709 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 710 711 return 0; 712 } 713 714 static int gmc_v10_0_late_init(void *handle) 715 { 716 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 717 int r; 718 719 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 720 if (r) 721 return r; 722 723 r = amdgpu_gmc_ras_late_init(adev); 724 if (r) 725 return r; 726 727 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 728 } 729 730 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 731 struct amdgpu_gmc *mc) 732 { 733 u64 base = 0; 734 735 base = adev->gfxhub.funcs->get_fb_location(adev); 736 737 /* add the xgmi offset of the physical node */ 738 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 739 740 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 741 amdgpu_gmc_gart_location(adev, mc); 742 amdgpu_gmc_agp_location(adev, mc); 743 744 /* base offset of vram pages */ 745 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 746 747 /* add the xgmi offset of the physical node */ 748 adev->vm_manager.vram_base_offset += 749 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 750 } 751 752 /** 753 * gmc_v10_0_mc_init - initialize the memory controller driver params 754 * 755 * @adev: amdgpu_device pointer 756 * 757 * Look up the amount of vram, vram width, and decide how to place 758 * vram and gart within the GPU's physical address space. 759 * Returns 0 for success. 760 */ 761 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 762 { 763 int r; 764 765 /* size in MB on si */ 766 adev->gmc.mc_vram_size = 767 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 768 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 769 770 if (!(adev->flags & AMD_IS_APU)) { 771 r = amdgpu_device_resize_fb_bar(adev); 772 if (r) 773 return r; 774 } 775 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 776 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 777 778 #ifdef CONFIG_X86_64 779 if (adev->flags & AMD_IS_APU) { 780 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 781 adev->gmc.aper_size = adev->gmc.real_vram_size; 782 } 783 #endif 784 785 /* In case the PCI BAR is larger than the actual amount of vram */ 786 adev->gmc.visible_vram_size = adev->gmc.aper_size; 787 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) 788 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; 789 790 /* set the gart size */ 791 if (amdgpu_gart_size == -1) { 792 switch (adev->asic_type) { 793 case CHIP_NAVI10: 794 case CHIP_NAVI14: 795 case CHIP_NAVI12: 796 case CHIP_SIENNA_CICHLID: 797 case CHIP_NAVY_FLOUNDER: 798 case CHIP_VANGOGH: 799 case CHIP_DIMGREY_CAVEFISH: 800 default: 801 adev->gmc.gart_size = 512ULL << 20; 802 break; 803 } 804 } else 805 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 806 807 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 808 809 return 0; 810 } 811 812 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 813 { 814 int r; 815 816 if (adev->gart.bo) { 817 WARN(1, "NAVI10 PCIE GART already initialized\n"); 818 return 0; 819 } 820 821 /* Initialize common gart structure */ 822 r = amdgpu_gart_init(adev); 823 if (r) 824 return r; 825 826 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 827 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 828 AMDGPU_PTE_EXECUTABLE; 829 830 return amdgpu_gart_table_vram_alloc(adev); 831 } 832 833 static int gmc_v10_0_sw_init(void *handle) 834 { 835 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 836 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 837 838 adev->gfxhub.funcs->init(adev); 839 840 adev->mmhub.funcs->init(adev); 841 842 spin_lock_init(&adev->gmc.invalidate_lock); 843 844 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 845 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 846 adev->gmc.vram_width = 64; 847 } else if (amdgpu_emu_mode == 1) { 848 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 849 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 850 } else { 851 r = amdgpu_atomfirmware_get_vram_info(adev, 852 &vram_width, &vram_type, &vram_vendor); 853 adev->gmc.vram_width = vram_width; 854 855 adev->gmc.vram_type = vram_type; 856 adev->gmc.vram_vendor = vram_vendor; 857 } 858 859 switch (adev->asic_type) { 860 case CHIP_NAVI10: 861 case CHIP_NAVI14: 862 case CHIP_NAVI12: 863 case CHIP_SIENNA_CICHLID: 864 case CHIP_NAVY_FLOUNDER: 865 case CHIP_VANGOGH: 866 case CHIP_DIMGREY_CAVEFISH: 867 adev->num_vmhubs = 2; 868 /* 869 * To fulfill 4-level page support, 870 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 871 * block size 512 (9bit) 872 */ 873 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 874 break; 875 default: 876 break; 877 } 878 879 /* This interrupt is VMC page fault.*/ 880 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 881 VMC_1_0__SRCID__VM_FAULT, 882 &adev->gmc.vm_fault); 883 884 if (r) 885 return r; 886 887 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 888 UTCL2_1_0__SRCID__FAULT, 889 &adev->gmc.vm_fault); 890 if (r) 891 return r; 892 893 if (!amdgpu_sriov_vf(adev)) { 894 /* interrupt sent to DF. */ 895 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 896 &adev->gmc.ecc_irq); 897 if (r) 898 return r; 899 } 900 901 /* 902 * Set the internal MC address mask This is the max address of the GPU's 903 * internal address space. 904 */ 905 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 906 907 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 908 if (r) { 909 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n"); 910 return r; 911 } 912 913 if (adev->gmc.xgmi.supported) { 914 r = adev->gfxhub.funcs->get_xgmi_info(adev); 915 if (r) 916 return r; 917 } 918 919 r = gmc_v10_0_mc_init(adev); 920 if (r) 921 return r; 922 923 amdgpu_gmc_get_vbios_allocations(adev); 924 925 /* Memory manager */ 926 r = amdgpu_bo_init(adev); 927 if (r) 928 return r; 929 930 r = gmc_v10_0_gart_init(adev); 931 if (r) 932 return r; 933 934 /* 935 * number of VMs 936 * VMID 0 is reserved for System 937 * amdgpu graphics/compute will use VMIDs 1-7 938 * amdkfd will use VMIDs 8-15 939 */ 940 adev->vm_manager.first_kfd_vmid = 8; 941 942 amdgpu_vm_manager_init(adev); 943 944 return 0; 945 } 946 947 /** 948 * gmc_v8_0_gart_fini - vm fini callback 949 * 950 * @adev: amdgpu_device pointer 951 * 952 * Tears down the driver GART/VM setup (CIK). 953 */ 954 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 955 { 956 amdgpu_gart_table_vram_free(adev); 957 amdgpu_gart_fini(adev); 958 } 959 960 static int gmc_v10_0_sw_fini(void *handle) 961 { 962 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 963 964 amdgpu_vm_manager_fini(adev); 965 gmc_v10_0_gart_fini(adev); 966 amdgpu_gem_force_release(adev); 967 amdgpu_bo_fini(adev); 968 969 return 0; 970 } 971 972 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 973 { 974 switch (adev->asic_type) { 975 case CHIP_NAVI10: 976 case CHIP_NAVI14: 977 case CHIP_NAVI12: 978 case CHIP_SIENNA_CICHLID: 979 case CHIP_NAVY_FLOUNDER: 980 case CHIP_VANGOGH: 981 case CHIP_DIMGREY_CAVEFISH: 982 break; 983 default: 984 break; 985 } 986 } 987 988 /** 989 * gmc_v10_0_gart_enable - gart enable 990 * 991 * @adev: amdgpu_device pointer 992 */ 993 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 994 { 995 int r; 996 bool value; 997 998 if (adev->gart.bo == NULL) { 999 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1000 return -EINVAL; 1001 } 1002 1003 r = amdgpu_gart_table_vram_pin(adev); 1004 if (r) 1005 return r; 1006 1007 r = adev->gfxhub.funcs->gart_enable(adev); 1008 if (r) 1009 return r; 1010 1011 r = adev->mmhub.funcs->gart_enable(adev); 1012 if (r) 1013 return r; 1014 1015 adev->hdp.funcs->init_registers(adev); 1016 1017 /* Flush HDP after it is initialized */ 1018 adev->hdp.funcs->flush_hdp(adev, NULL); 1019 1020 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 1021 false : true; 1022 1023 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1024 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1025 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0); 1026 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0); 1027 1028 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1029 (unsigned)(adev->gmc.gart_size >> 20), 1030 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1031 1032 adev->gart.ready = true; 1033 1034 return 0; 1035 } 1036 1037 static int gmc_v10_0_hw_init(void *handle) 1038 { 1039 int r; 1040 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1041 1042 /* The sequence of these two function calls matters.*/ 1043 gmc_v10_0_init_golden_registers(adev); 1044 1045 r = gmc_v10_0_gart_enable(adev); 1046 if (r) 1047 return r; 1048 1049 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1050 adev->umc.funcs->init_registers(adev); 1051 1052 return 0; 1053 } 1054 1055 /** 1056 * gmc_v10_0_gart_disable - gart disable 1057 * 1058 * @adev: amdgpu_device pointer 1059 * 1060 * This disables all VM page table. 1061 */ 1062 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1063 { 1064 adev->gfxhub.funcs->gart_disable(adev); 1065 adev->mmhub.funcs->gart_disable(adev); 1066 amdgpu_gart_table_vram_unpin(adev); 1067 } 1068 1069 static int gmc_v10_0_hw_fini(void *handle) 1070 { 1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1072 1073 if (amdgpu_sriov_vf(adev)) { 1074 /* full access mode, so don't touch any GMC register */ 1075 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1076 return 0; 1077 } 1078 1079 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1080 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1081 gmc_v10_0_gart_disable(adev); 1082 1083 return 0; 1084 } 1085 1086 static int gmc_v10_0_suspend(void *handle) 1087 { 1088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1089 1090 gmc_v10_0_hw_fini(adev); 1091 1092 return 0; 1093 } 1094 1095 static int gmc_v10_0_resume(void *handle) 1096 { 1097 int r; 1098 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1099 1100 r = gmc_v10_0_hw_init(adev); 1101 if (r) 1102 return r; 1103 1104 amdgpu_vmid_reset_all(adev); 1105 1106 return 0; 1107 } 1108 1109 static bool gmc_v10_0_is_idle(void *handle) 1110 { 1111 /* MC is always ready in GMC v10.*/ 1112 return true; 1113 } 1114 1115 static int gmc_v10_0_wait_for_idle(void *handle) 1116 { 1117 /* There is no need to wait for MC idle in GMC v10.*/ 1118 return 0; 1119 } 1120 1121 static int gmc_v10_0_soft_reset(void *handle) 1122 { 1123 return 0; 1124 } 1125 1126 static int gmc_v10_0_set_clockgating_state(void *handle, 1127 enum amd_clockgating_state state) 1128 { 1129 int r; 1130 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1131 1132 r = adev->mmhub.funcs->set_clockgating(adev, state); 1133 if (r) 1134 return r; 1135 1136 if (adev->asic_type >= CHIP_SIENNA_CICHLID && 1137 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) 1138 return athub_v2_1_set_clockgating(adev, state); 1139 else 1140 return athub_v2_0_set_clockgating(adev, state); 1141 } 1142 1143 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags) 1144 { 1145 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1146 1147 adev->mmhub.funcs->get_clockgating(adev, flags); 1148 1149 if (adev->asic_type >= CHIP_SIENNA_CICHLID && 1150 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) 1151 athub_v2_1_get_clockgating(adev, flags); 1152 else 1153 athub_v2_0_get_clockgating(adev, flags); 1154 } 1155 1156 static int gmc_v10_0_set_powergating_state(void *handle, 1157 enum amd_powergating_state state) 1158 { 1159 return 0; 1160 } 1161 1162 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1163 .name = "gmc_v10_0", 1164 .early_init = gmc_v10_0_early_init, 1165 .late_init = gmc_v10_0_late_init, 1166 .sw_init = gmc_v10_0_sw_init, 1167 .sw_fini = gmc_v10_0_sw_fini, 1168 .hw_init = gmc_v10_0_hw_init, 1169 .hw_fini = gmc_v10_0_hw_fini, 1170 .suspend = gmc_v10_0_suspend, 1171 .resume = gmc_v10_0_resume, 1172 .is_idle = gmc_v10_0_is_idle, 1173 .wait_for_idle = gmc_v10_0_wait_for_idle, 1174 .soft_reset = gmc_v10_0_soft_reset, 1175 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1176 .set_powergating_state = gmc_v10_0_set_powergating_state, 1177 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1178 }; 1179 1180 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = 1181 { 1182 .type = AMD_IP_BLOCK_TYPE_GMC, 1183 .major = 10, 1184 .minor = 0, 1185 .rev = 0, 1186 .funcs = &gmc_v10_0_ip_funcs, 1187 }; 1188