1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 55 struct amdgpu_irq_src *src, 56 unsigned int type, 57 enum amdgpu_interrupt_state state) 58 { 59 return 0; 60 } 61 62 static int 63 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 64 struct amdgpu_irq_src *src, unsigned int type, 65 enum amdgpu_interrupt_state state) 66 { 67 switch (state) { 68 case AMDGPU_IRQ_STATE_DISABLE: 69 /* MM HUB */ 70 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 71 /* GFX HUB */ 72 /* This works because this interrupt is only 73 * enabled at init/resume and disabled in 74 * fini/suspend, so the overall state doesn't 75 * change over the course of suspend/resume. 76 */ 77 if (!adev->in_s0ix) 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 83 /* GFX HUB */ 84 /* This works because this interrupt is only 85 * enabled at init/resume and disabled in 86 * fini/suspend, so the overall state doesn't 87 * change over the course of suspend/resume. 88 */ 89 if (!adev->in_s0ix) 90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 91 break; 92 default: 93 break; 94 } 95 96 return 0; 97 } 98 99 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 100 struct amdgpu_irq_src *source, 101 struct amdgpu_iv_entry *entry) 102 { 103 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? 104 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 105 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 106 bool retry_fault = !!(entry->src_data[1] & 107 AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY); 108 bool write_fault = !!(entry->src_data[1] & 109 AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE); 110 struct amdgpu_task_info *task_info; 111 uint32_t status = 0; 112 u64 addr; 113 114 addr = (u64)entry->src_data[0] << 12; 115 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 116 117 if (retry_fault) { 118 int ret = amdgpu_gmc_handle_retry_fault(adev, entry, addr, 0, 0, 119 write_fault); 120 /* Returning 1 here also prevents sending the IV to the KFD */ 121 if (ret == 1) 122 return 1; 123 } 124 125 if (!amdgpu_sriov_vf(adev)) { 126 /* 127 * Issue a dummy read to wait for the status register to 128 * be updated to avoid reading an incorrect value due to 129 * the new fast GRBM interface. 130 */ 131 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 132 (amdgpu_ip_version(adev, GC_HWIP, 0) < 133 IP_VERSION(10, 3, 0))) 134 RREG32(hub->vm_l2_pro_fault_status); 135 136 status = RREG32(hub->vm_l2_pro_fault_status); 137 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 138 139 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 140 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 141 } 142 143 if (!printk_ratelimit()) 144 return 0; 145 146 dev_err(adev->dev, 147 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 148 entry->vmid_src ? "mmhub" : "gfxhub", 149 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 150 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 151 if (task_info) { 152 amdgpu_vm_print_task_info(adev, task_info); 153 amdgpu_vm_put_task_info(task_info); 154 } 155 156 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 157 addr, entry->client_id, 158 soc15_ih_clientid_name[entry->client_id]); 159 160 /* Only print L2 fault status if the status register could be read and 161 * contains useful information 162 */ 163 if (status != 0) 164 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 165 status); 166 167 return 0; 168 } 169 170 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 171 .set = gmc_v10_0_vm_fault_interrupt_state, 172 .process = gmc_v10_0_process_interrupt, 173 }; 174 175 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 176 .set = gmc_v10_0_ecc_interrupt_state, 177 .process = amdgpu_umc_process_ecc_irq, 178 }; 179 180 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 181 { 182 adev->gmc.vm_fault.num_types = 1; 183 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 184 185 if (!amdgpu_sriov_vf(adev)) { 186 adev->gmc.ecc_irq.num_types = 1; 187 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 188 } 189 } 190 191 /** 192 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 193 * 194 * @adev: amdgpu_device pointer 195 * @vmhub: vmhub type 196 * 197 */ 198 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 199 uint32_t vmhub) 200 { 201 return ((vmhub == AMDGPU_MMHUB0(0)) && 202 (!amdgpu_sriov_vf(adev))); 203 } 204 205 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 206 struct amdgpu_device *adev, 207 uint8_t vmid, uint16_t *p_pasid) 208 { 209 uint32_t value; 210 211 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 212 + vmid); 213 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 214 215 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 216 } 217 218 /* 219 * GART 220 * VMID 0 is the physical GPU addresses as used by the kernel. 221 * VMIDs 1-15 are used for userspace clients and are handled 222 * by the amdgpu vm/hsa code. 223 */ 224 225 /** 226 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 227 * 228 * @adev: amdgpu_device pointer 229 * @vmid: vm instance to flush 230 * @vmhub: vmhub type 231 * @flush_type: the flush type 232 * 233 * Flush the TLB for the requested page table. 234 */ 235 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 236 uint32_t vmhub, uint32_t flush_type) 237 { 238 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 239 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 240 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 241 /* Use register 17 for GART */ 242 const unsigned int eng = 17; 243 unsigned char hub_ip = 0; 244 u32 sem, req, ack; 245 unsigned int i; 246 u32 tmp; 247 248 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 249 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 250 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 251 252 /* flush hdp cache */ 253 amdgpu_device_flush_hdp(adev, NULL); 254 255 /* This is necessary for SRIOV as well as for GFXOFF to function 256 * properly under bare metal 257 */ 258 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && 259 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 260 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 261 1 << vmid, GET_INST(GC, 0)); 262 return; 263 } 264 265 /* This path is needed before KIQ/MES/GFXOFF are set up */ 266 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; 267 268 spin_lock(&adev->gmc.invalidate_lock); 269 /* 270 * It may lose gpuvm invalidate acknowldege state across power-gating 271 * off cycle, add semaphore acquire before invalidation and semaphore 272 * release after invalidation to avoid entering power gated state 273 * to WA the Issue 274 */ 275 276 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 277 if (use_semaphore) { 278 for (i = 0; i < adev->usec_timeout; i++) { 279 /* a read return value of 1 means semaphore acuqire */ 280 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); 281 if (tmp & 0x1) 282 break; 283 udelay(1); 284 } 285 286 if (i >= adev->usec_timeout) 287 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 288 } 289 290 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); 291 292 /* 293 * Issue a dummy read to wait for the ACK register to be cleared 294 * to avoid a false ACK due to the new fast GRBM interface. 295 */ 296 if ((vmhub == AMDGPU_GFXHUB(0)) && 297 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) 298 RREG32_RLC_NO_KIQ(req, hub_ip); 299 300 /* Wait for ACK with a delay.*/ 301 for (i = 0; i < adev->usec_timeout; i++) { 302 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); 303 tmp &= 1 << vmid; 304 if (tmp) 305 break; 306 307 udelay(1); 308 } 309 310 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 311 if (use_semaphore) 312 WREG32_RLC_NO_KIQ(sem, 0, hub_ip); 313 314 spin_unlock(&adev->gmc.invalidate_lock); 315 316 if (i >= adev->usec_timeout) 317 dev_err(adev->dev, "Timeout waiting for VM flush hub: %d!\n", 318 vmhub); 319 } 320 321 /** 322 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 323 * 324 * @adev: amdgpu_device pointer 325 * @pasid: pasid to be flush 326 * @flush_type: the flush type 327 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 328 * @inst: is used to select which instance of KIQ to use for the invalidation 329 * 330 * Flush the TLB for the requested pasid. 331 */ 332 static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 333 uint16_t pasid, uint32_t flush_type, 334 bool all_hub, uint32_t inst) 335 { 336 uint16_t queried; 337 int vmid, i; 338 339 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 340 bool valid; 341 342 valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 343 &queried); 344 if (!valid || queried != pasid) 345 continue; 346 347 if (all_hub) { 348 for_each_set_bit(i, adev->vmhubs_mask, 349 AMDGPU_MAX_VMHUBS) 350 gmc_v10_0_flush_gpu_tlb(adev, vmid, i, 351 flush_type); 352 } else { 353 gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 354 flush_type); 355 } 356 } 357 } 358 359 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 360 unsigned int vmid, uint64_t pd_addr) 361 { 362 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 363 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 364 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 365 unsigned int eng = ring->vm_inv_eng; 366 367 /* 368 * It may lose gpuvm invalidate acknowldege state across power-gating 369 * off cycle, add semaphore acquire before invalidation and semaphore 370 * release after invalidation to avoid entering power gated state 371 * to WA the Issue 372 */ 373 374 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 375 if (use_semaphore) 376 /* a read return value of 1 means semaphore acuqire */ 377 amdgpu_ring_emit_reg_wait(ring, 378 hub->vm_inv_eng0_sem + 379 hub->eng_distance * eng, 0x1, 0x1); 380 381 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 382 (hub->ctx_addr_distance * vmid), 383 lower_32_bits(pd_addr)); 384 385 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 386 (hub->ctx_addr_distance * vmid), 387 upper_32_bits(pd_addr)); 388 389 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 390 hub->eng_distance * eng, 391 hub->vm_inv_eng0_ack + 392 hub->eng_distance * eng, 393 req, 1 << vmid); 394 395 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 396 if (use_semaphore) 397 /* 398 * add semaphore release after invalidation, 399 * write with 0 means semaphore release 400 */ 401 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 402 hub->eng_distance * eng, 0); 403 404 return pd_addr; 405 } 406 407 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 408 unsigned int pasid) 409 { 410 struct amdgpu_device *adev = ring->adev; 411 uint32_t reg; 412 413 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 414 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 415 else 416 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 417 418 amdgpu_ring_emit_wreg(ring, reg, pasid); 419 } 420 421 /* 422 * PTE format on NAVI 10: 423 * 63:59 reserved 424 * 58 reserved and for sienna_cichlid is used for MALL noalloc 425 * 57 reserved 426 * 56 F 427 * 55 L 428 * 54 reserved 429 * 53:52 SW 430 * 51 T 431 * 50:48 mtype 432 * 47:12 4k physical page base address 433 * 11:7 fragment 434 * 6 write 435 * 5 read 436 * 4 exe 437 * 3 Z 438 * 2 snooped 439 * 1 system 440 * 0 valid 441 * 442 * PDE format on NAVI 10: 443 * 63:59 block fragment size 444 * 58:55 reserved 445 * 54 P 446 * 53:48 reserved 447 * 47:6 physical base address of PD or PTE 448 * 5:3 reserved 449 * 2 C 450 * 1 system 451 * 0 valid 452 */ 453 454 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 455 uint64_t *addr, uint64_t *flags) 456 { 457 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 458 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 459 BUG_ON(*addr & 0xFFFF00000000003FULL); 460 461 if (!adev->gmc.translate_further) 462 return; 463 464 if (level == AMDGPU_VM_PDB1) { 465 /* Set the block fragment size */ 466 if (!(*flags & AMDGPU_PDE_PTE)) 467 *flags |= AMDGPU_PDE_BFS(0x9); 468 469 } else if (level == AMDGPU_VM_PDB0) { 470 if (*flags & AMDGPU_PDE_PTE) 471 *flags &= ~AMDGPU_PDE_PTE; 472 else 473 *flags |= AMDGPU_PTE_TF; 474 } 475 } 476 477 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 478 struct amdgpu_vm *vm, 479 struct amdgpu_bo *bo, 480 uint32_t vm_flags, 481 uint64_t *flags) 482 { 483 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 484 *flags |= AMDGPU_PTE_EXECUTABLE; 485 else 486 *flags &= ~AMDGPU_PTE_EXECUTABLE; 487 488 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 489 case AMDGPU_VM_MTYPE_DEFAULT: 490 case AMDGPU_VM_MTYPE_NC: 491 default: 492 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC); 493 break; 494 case AMDGPU_VM_MTYPE_WC: 495 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC); 496 break; 497 case AMDGPU_VM_MTYPE_CC: 498 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC); 499 break; 500 case AMDGPU_VM_MTYPE_UC: 501 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); 502 break; 503 } 504 505 if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) 506 *flags |= AMDGPU_PTE_NOALLOC; 507 else 508 *flags &= ~AMDGPU_PTE_NOALLOC; 509 510 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 511 *flags |= AMDGPU_PTE_PRT; 512 *flags |= AMDGPU_PTE_SNOOPED; 513 *flags |= AMDGPU_PTE_LOG; 514 *flags |= AMDGPU_PTE_SYSTEM; 515 *flags &= ~AMDGPU_PTE_VALID; 516 } 517 518 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 519 AMDGPU_GEM_CREATE_EXT_COHERENT | 520 AMDGPU_GEM_CREATE_UNCACHED)) 521 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); 522 } 523 524 static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 525 { 526 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 527 unsigned int size; 528 529 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 530 size = AMDGPU_VBIOS_VGA_ALLOCATION; 531 } else { 532 u32 viewport; 533 u32 pitch; 534 535 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 536 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 537 size = (REG_GET_FIELD(viewport, 538 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 539 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 540 4); 541 } 542 543 return size; 544 } 545 546 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 547 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 548 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 549 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 550 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 551 .get_vm_pde = gmc_v10_0_get_vm_pde, 552 .get_vm_pte = gmc_v10_0_get_vm_pte, 553 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 554 }; 555 556 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 557 { 558 if (adev->gmc.gmc_funcs == NULL) 559 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 560 } 561 562 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 563 { 564 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 565 case IP_VERSION(8, 7, 0): 566 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 567 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 568 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 569 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 570 adev->umc.retire_unit = 1; 571 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 572 adev->umc.ras = &umc_v8_7_ras; 573 break; 574 default: 575 break; 576 } 577 } 578 579 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 580 { 581 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 582 case IP_VERSION(2, 3, 0): 583 case IP_VERSION(2, 4, 0): 584 case IP_VERSION(2, 4, 1): 585 adev->mmhub.funcs = &mmhub_v2_3_funcs; 586 break; 587 default: 588 adev->mmhub.funcs = &mmhub_v2_0_funcs; 589 break; 590 } 591 } 592 593 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 594 { 595 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 596 case IP_VERSION(10, 3, 0): 597 case IP_VERSION(10, 3, 2): 598 case IP_VERSION(10, 3, 1): 599 case IP_VERSION(10, 3, 4): 600 case IP_VERSION(10, 3, 5): 601 case IP_VERSION(10, 3, 6): 602 case IP_VERSION(10, 3, 3): 603 case IP_VERSION(10, 3, 7): 604 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 605 break; 606 default: 607 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 608 break; 609 } 610 } 611 612 613 static int gmc_v10_0_early_init(struct amdgpu_ip_block *ip_block) 614 { 615 struct amdgpu_device *adev = ip_block->adev; 616 617 gmc_v10_0_set_mmhub_funcs(adev); 618 gmc_v10_0_set_gfxhub_funcs(adev); 619 gmc_v10_0_set_gmc_funcs(adev); 620 gmc_v10_0_set_irq_funcs(adev); 621 gmc_v10_0_set_umc_funcs(adev); 622 623 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 624 adev->gmc.shared_aperture_end = 625 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 626 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 627 adev->gmc.private_aperture_end = 628 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 629 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 630 631 return 0; 632 } 633 634 static int gmc_v10_0_late_init(struct amdgpu_ip_block *ip_block) 635 { 636 struct amdgpu_device *adev = ip_block->adev; 637 int r; 638 639 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 640 if (r) 641 return r; 642 643 r = amdgpu_gmc_ras_late_init(adev); 644 if (r) 645 return r; 646 647 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 648 } 649 650 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 651 struct amdgpu_gmc *mc) 652 { 653 u64 base = 0; 654 655 base = adev->gfxhub.funcs->get_fb_location(adev); 656 657 /* add the xgmi offset of the physical node */ 658 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 659 660 amdgpu_gmc_set_agp_default(adev, mc); 661 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 662 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 663 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 664 amdgpu_gmc_agp_location(adev, mc); 665 666 /* base offset of vram pages */ 667 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 668 669 /* add the xgmi offset of the physical node */ 670 adev->vm_manager.vram_base_offset += 671 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 672 } 673 674 /** 675 * gmc_v10_0_mc_init - initialize the memory controller driver params 676 * 677 * @adev: amdgpu_device pointer 678 * 679 * Look up the amount of vram, vram width, and decide how to place 680 * vram and gart within the GPU's physical address space. 681 * Returns 0 for success. 682 */ 683 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 684 { 685 int r; 686 687 /* size in MB on si */ 688 adev->gmc.mc_vram_size = 689 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 690 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 691 692 if (!(adev->flags & AMD_IS_APU)) { 693 r = amdgpu_device_resize_fb_bar(adev); 694 if (r) 695 return r; 696 } 697 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 698 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 699 700 #ifdef CONFIG_X86_64 701 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 702 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 703 adev->gmc.aper_size = adev->gmc.real_vram_size; 704 } 705 #endif 706 707 adev->gmc.visible_vram_size = adev->gmc.aper_size; 708 709 /* set the gart size */ 710 if (amdgpu_gart_size == -1) { 711 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 712 default: 713 adev->gmc.gart_size = 512ULL << 20; 714 break; 715 case IP_VERSION(10, 3, 1): /* DCE SG support */ 716 case IP_VERSION(10, 3, 3): /* DCE SG support */ 717 case IP_VERSION(10, 3, 6): /* DCE SG support */ 718 case IP_VERSION(10, 3, 7): /* DCE SG support */ 719 adev->gmc.gart_size = 1024ULL << 20; 720 break; 721 } 722 } else { 723 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 724 } 725 726 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 727 728 return 0; 729 } 730 731 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 732 { 733 int r; 734 735 if (adev->gart.bo) { 736 WARN(1, "NAVI10 PCIE GART already initialized\n"); 737 return 0; 738 } 739 740 /* Initialize common gart structure */ 741 r = amdgpu_gart_init(adev); 742 if (r) 743 return r; 744 745 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 746 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | 747 AMDGPU_PTE_EXECUTABLE; 748 749 return amdgpu_gart_table_vram_alloc(adev); 750 } 751 752 static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 753 { 754 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 755 struct amdgpu_device *adev = ip_block->adev; 756 757 adev->gfxhub.funcs->init(adev); 758 759 adev->mmhub.funcs->init(adev); 760 761 spin_lock_init(&adev->gmc.invalidate_lock); 762 763 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 764 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 765 adev->gmc.vram_width = 64; 766 } else if (amdgpu_emu_mode == 1) { 767 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 768 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 769 } else { 770 r = amdgpu_atomfirmware_get_vram_info(adev, 771 &vram_width, &vram_type, &vram_vendor); 772 adev->gmc.vram_width = vram_width; 773 774 adev->gmc.vram_type = vram_type; 775 adev->gmc.vram_vendor = vram_vendor; 776 } 777 778 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 779 case IP_VERSION(10, 3, 0): 780 adev->gmc.mall_size = 128 * 1024 * 1024; 781 break; 782 case IP_VERSION(10, 3, 2): 783 adev->gmc.mall_size = 96 * 1024 * 1024; 784 break; 785 case IP_VERSION(10, 3, 4): 786 adev->gmc.mall_size = 32 * 1024 * 1024; 787 break; 788 case IP_VERSION(10, 3, 5): 789 adev->gmc.mall_size = 16 * 1024 * 1024; 790 break; 791 default: 792 adev->gmc.mall_size = 0; 793 break; 794 } 795 796 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 797 case IP_VERSION(10, 1, 10): 798 case IP_VERSION(10, 1, 1): 799 case IP_VERSION(10, 1, 2): 800 case IP_VERSION(10, 1, 3): 801 case IP_VERSION(10, 1, 4): 802 case IP_VERSION(10, 3, 0): 803 case IP_VERSION(10, 3, 2): 804 case IP_VERSION(10, 3, 1): 805 case IP_VERSION(10, 3, 4): 806 case IP_VERSION(10, 3, 5): 807 case IP_VERSION(10, 3, 6): 808 case IP_VERSION(10, 3, 3): 809 case IP_VERSION(10, 3, 7): 810 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 811 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 812 /* 813 * To fulfill 4-level page support, 814 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 815 * block size 512 (9bit) 816 */ 817 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 818 break; 819 default: 820 break; 821 } 822 823 /* This interrupt is VMC page fault.*/ 824 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 825 VMC_1_0__SRCID__VM_FAULT, 826 &adev->gmc.vm_fault); 827 828 if (r) 829 return r; 830 831 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 832 UTCL2_1_0__SRCID__FAULT, 833 &adev->gmc.vm_fault); 834 if (r) 835 return r; 836 837 if (!amdgpu_sriov_vf(adev)) { 838 /* interrupt sent to DF. */ 839 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 840 &adev->gmc.ecc_irq); 841 if (r) 842 return r; 843 } 844 845 /* 846 * Set the internal MC address mask This is the max address of the GPU's 847 * internal address space. 848 */ 849 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 850 851 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 852 if (r) { 853 drm_warn(adev_to_drm(adev), "No suitable DMA available.\n"); 854 return r; 855 } 856 857 adev->need_swiotlb = drm_need_swiotlb(44); 858 859 r = gmc_v10_0_mc_init(adev); 860 if (r) 861 return r; 862 863 amdgpu_gmc_get_vbios_allocations(adev); 864 865 /* Memory manager */ 866 r = amdgpu_bo_init(adev); 867 if (r) 868 return r; 869 870 r = gmc_v10_0_gart_init(adev); 871 if (r) 872 return r; 873 874 /* 875 * number of VMs 876 * VMID 0 is reserved for System 877 * amdgpu graphics/compute will use VMIDs 1-7 878 * amdkfd will use VMIDs 8-15 879 */ 880 adev->vm_manager.first_kfd_vmid = 8; 881 882 amdgpu_vm_manager_init(adev); 883 884 r = amdgpu_gmc_ras_sw_init(adev); 885 if (r) 886 return r; 887 888 return 0; 889 } 890 891 /** 892 * gmc_v10_0_gart_fini - vm fini callback 893 * 894 * @adev: amdgpu_device pointer 895 * 896 * Tears down the driver GART/VM setup (CIK). 897 */ 898 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 899 { 900 amdgpu_gart_table_vram_free(adev); 901 } 902 903 static int gmc_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 904 { 905 struct amdgpu_device *adev = ip_block->adev; 906 907 amdgpu_vm_manager_fini(adev); 908 gmc_v10_0_gart_fini(adev); 909 amdgpu_gem_force_release(adev); 910 amdgpu_bo_fini(adev); 911 912 return 0; 913 } 914 915 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 916 { 917 } 918 919 /** 920 * gmc_v10_0_gart_enable - gart enable 921 * 922 * @adev: amdgpu_device pointer 923 */ 924 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 925 { 926 int r; 927 bool value; 928 929 if (adev->gart.bo == NULL) { 930 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 931 return -EINVAL; 932 } 933 934 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 935 936 if (!adev->in_s0ix) { 937 r = adev->gfxhub.funcs->gart_enable(adev); 938 if (r) 939 return r; 940 } 941 942 r = adev->mmhub.funcs->gart_enable(adev); 943 if (r) 944 return r; 945 946 adev->hdp.funcs->init_registers(adev); 947 948 /* Flush HDP after it is initialized */ 949 amdgpu_device_flush_hdp(adev, NULL); 950 951 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 952 953 if (!adev->in_s0ix) 954 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 955 adev->mmhub.funcs->set_fault_enable_default(adev, value); 956 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 957 if (!adev->in_s0ix) 958 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 959 960 drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled (table at 0x%016llX).\n", 961 (unsigned int)(adev->gmc.gart_size >> 20), 962 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 963 964 return 0; 965 } 966 967 static int gmc_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 968 { 969 struct amdgpu_device *adev = ip_block->adev; 970 int r; 971 972 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; 973 974 /* The sequence of these two function calls matters.*/ 975 gmc_v10_0_init_golden_registers(adev); 976 977 /* 978 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 979 * register setup within GMC, or else system hang when harvesting SA. 980 */ 981 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 982 adev->gfxhub.funcs->utcl2_harvest(adev); 983 984 r = gmc_v10_0_gart_enable(adev); 985 if (r) 986 return r; 987 988 if (amdgpu_emu_mode == 1) { 989 r = amdgpu_gmc_vram_checking(adev); 990 if (r) 991 return r; 992 } 993 994 if (adev->umc.funcs && adev->umc.funcs->init_registers) 995 adev->umc.funcs->init_registers(adev); 996 997 return 0; 998 } 999 1000 /** 1001 * gmc_v10_0_gart_disable - gart disable 1002 * 1003 * @adev: amdgpu_device pointer 1004 * 1005 * This disables all VM page table. 1006 */ 1007 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1008 { 1009 if (!adev->in_s0ix) 1010 adev->gfxhub.funcs->gart_disable(adev); 1011 adev->mmhub.funcs->gart_disable(adev); 1012 } 1013 1014 static int gmc_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 1015 { 1016 struct amdgpu_device *adev = ip_block->adev; 1017 1018 gmc_v10_0_gart_disable(adev); 1019 1020 if (amdgpu_sriov_vf(adev)) { 1021 /* full access mode, so don't touch any GMC register */ 1022 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1023 return 0; 1024 } 1025 1026 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1027 1028 if (adev->gmc.ecc_irq.funcs && 1029 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1030 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1031 1032 return 0; 1033 } 1034 1035 static int gmc_v10_0_suspend(struct amdgpu_ip_block *ip_block) 1036 { 1037 gmc_v10_0_hw_fini(ip_block); 1038 1039 return 0; 1040 } 1041 1042 static int gmc_v10_0_resume(struct amdgpu_ip_block *ip_block) 1043 { 1044 int r; 1045 1046 r = gmc_v10_0_hw_init(ip_block); 1047 if (r) 1048 return r; 1049 1050 amdgpu_vmid_reset_all(ip_block->adev); 1051 1052 return 0; 1053 } 1054 1055 static bool gmc_v10_0_is_idle(struct amdgpu_ip_block *ip_block) 1056 { 1057 /* MC is always ready in GMC v10.*/ 1058 return true; 1059 } 1060 1061 static int gmc_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1062 { 1063 /* There is no need to wait for MC idle in GMC v10.*/ 1064 return 0; 1065 } 1066 1067 static int gmc_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1068 enum amd_clockgating_state state) 1069 { 1070 int r; 1071 struct amdgpu_device *adev = ip_block->adev; 1072 1073 /* 1074 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1075 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1076 * seen any issue on the DF 3.0.2 series platform. 1077 */ 1078 if (adev->in_s0ix && 1079 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) { 1080 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1081 return 0; 1082 } 1083 1084 r = adev->mmhub.funcs->set_clockgating(adev, state); 1085 if (r) 1086 return r; 1087 1088 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1089 return athub_v2_1_set_clockgating(adev, state); 1090 else 1091 return athub_v2_0_set_clockgating(adev, state); 1092 } 1093 1094 static void gmc_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1095 { 1096 struct amdgpu_device *adev = ip_block->adev; 1097 1098 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || 1099 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) 1100 return; 1101 1102 adev->mmhub.funcs->get_clockgating(adev, flags); 1103 1104 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1105 athub_v2_1_get_clockgating(adev, flags); 1106 else 1107 athub_v2_0_get_clockgating(adev, flags); 1108 } 1109 1110 static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1111 enum amd_powergating_state state) 1112 { 1113 return 0; 1114 } 1115 1116 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1117 .name = "gmc_v10_0", 1118 .early_init = gmc_v10_0_early_init, 1119 .late_init = gmc_v10_0_late_init, 1120 .sw_init = gmc_v10_0_sw_init, 1121 .sw_fini = gmc_v10_0_sw_fini, 1122 .hw_init = gmc_v10_0_hw_init, 1123 .hw_fini = gmc_v10_0_hw_fini, 1124 .suspend = gmc_v10_0_suspend, 1125 .resume = gmc_v10_0_resume, 1126 .is_idle = gmc_v10_0_is_idle, 1127 .wait_for_idle = gmc_v10_0_wait_for_idle, 1128 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1129 .set_powergating_state = gmc_v10_0_set_powergating_state, 1130 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1131 }; 1132 1133 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = { 1134 .type = AMD_IP_BLOCK_TYPE_GMC, 1135 .major = 10, 1136 .minor = 0, 1137 .rev = 0, 1138 .funcs = &gmc_v10_0_ip_funcs, 1139 }; 1140