1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 55 struct amdgpu_irq_src *src, 56 unsigned int type, 57 enum amdgpu_interrupt_state state) 58 { 59 return 0; 60 } 61 62 static int 63 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 64 struct amdgpu_irq_src *src, unsigned int type, 65 enum amdgpu_interrupt_state state) 66 { 67 switch (state) { 68 case AMDGPU_IRQ_STATE_DISABLE: 69 /* MM HUB */ 70 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 71 /* GFX HUB */ 72 /* This works because this interrupt is only 73 * enabled at init/resume and disabled in 74 * fini/suspend, so the overall state doesn't 75 * change over the course of suspend/resume. 76 */ 77 if (!adev->in_s0ix) 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 83 /* GFX HUB */ 84 /* This works because this interrupt is only 85 * enabled at init/resume and disabled in 86 * fini/suspend, so the overall state doesn't 87 * change over the course of suspend/resume. 88 */ 89 if (!adev->in_s0ix) 90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 91 break; 92 default: 93 break; 94 } 95 96 return 0; 97 } 98 99 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 100 struct amdgpu_irq_src *source, 101 struct amdgpu_iv_entry *entry) 102 { 103 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? 104 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 105 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 106 bool retry_fault = !!(entry->src_data[1] & 0x80); 107 bool write_fault = !!(entry->src_data[1] & 0x20); 108 struct amdgpu_task_info *task_info; 109 uint32_t status = 0; 110 u64 addr; 111 112 addr = (u64)entry->src_data[0] << 12; 113 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 114 115 if (retry_fault) { 116 /* Returning 1 here also prevents sending the IV to the KFD */ 117 118 /* Process it onyl if it's the first fault for this address */ 119 if (entry->ih != &adev->irq.ih_soft && 120 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 121 entry->timestamp)) 122 return 1; 123 124 /* Delegate it to a different ring if the hardware hasn't 125 * already done it. 126 */ 127 if (entry->ih == &adev->irq.ih) { 128 amdgpu_irq_delegate(adev, entry, 8); 129 return 1; 130 } 131 132 /* Try to handle the recoverable page faults by filling page 133 * tables 134 */ 135 if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, 136 entry->timestamp, write_fault)) 137 return 1; 138 } 139 140 if (!amdgpu_sriov_vf(adev)) { 141 /* 142 * Issue a dummy read to wait for the status register to 143 * be updated to avoid reading an incorrect value due to 144 * the new fast GRBM interface. 145 */ 146 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 147 (amdgpu_ip_version(adev, GC_HWIP, 0) < 148 IP_VERSION(10, 3, 0))) 149 RREG32(hub->vm_l2_pro_fault_status); 150 151 status = RREG32(hub->vm_l2_pro_fault_status); 152 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 153 154 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 155 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 156 } 157 158 if (!printk_ratelimit()) 159 return 0; 160 161 dev_err(adev->dev, 162 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 163 entry->vmid_src ? "mmhub" : "gfxhub", 164 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 165 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 166 if (task_info) { 167 dev_err(adev->dev, 168 " in process %s pid %d thread %s pid %d\n", 169 task_info->process_name, task_info->tgid, 170 task_info->task_name, task_info->pid); 171 amdgpu_vm_put_task_info(task_info); 172 } 173 174 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 175 addr, entry->client_id, 176 soc15_ih_clientid_name[entry->client_id]); 177 178 /* Only print L2 fault status if the status register could be read and 179 * contains useful information 180 */ 181 if (status != 0) 182 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 183 status); 184 185 return 0; 186 } 187 188 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 189 .set = gmc_v10_0_vm_fault_interrupt_state, 190 .process = gmc_v10_0_process_interrupt, 191 }; 192 193 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 194 .set = gmc_v10_0_ecc_interrupt_state, 195 .process = amdgpu_umc_process_ecc_irq, 196 }; 197 198 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 199 { 200 adev->gmc.vm_fault.num_types = 1; 201 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 202 203 if (!amdgpu_sriov_vf(adev)) { 204 adev->gmc.ecc_irq.num_types = 1; 205 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 206 } 207 } 208 209 /** 210 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 211 * 212 * @adev: amdgpu_device pointer 213 * @vmhub: vmhub type 214 * 215 */ 216 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 217 uint32_t vmhub) 218 { 219 return ((vmhub == AMDGPU_MMHUB0(0)) && 220 (!amdgpu_sriov_vf(adev))); 221 } 222 223 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 224 struct amdgpu_device *adev, 225 uint8_t vmid, uint16_t *p_pasid) 226 { 227 uint32_t value; 228 229 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 230 + vmid); 231 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 232 233 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 234 } 235 236 /* 237 * GART 238 * VMID 0 is the physical GPU addresses as used by the kernel. 239 * VMIDs 1-15 are used for userspace clients and are handled 240 * by the amdgpu vm/hsa code. 241 */ 242 243 /** 244 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 245 * 246 * @adev: amdgpu_device pointer 247 * @vmid: vm instance to flush 248 * @vmhub: vmhub type 249 * @flush_type: the flush type 250 * 251 * Flush the TLB for the requested page table. 252 */ 253 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 254 uint32_t vmhub, uint32_t flush_type) 255 { 256 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 257 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 258 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 259 /* Use register 17 for GART */ 260 const unsigned int eng = 17; 261 unsigned char hub_ip = 0; 262 u32 sem, req, ack; 263 unsigned int i; 264 u32 tmp; 265 266 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 267 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 268 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 269 270 /* flush hdp cache */ 271 adev->hdp.funcs->flush_hdp(adev, NULL); 272 273 /* This is necessary for SRIOV as well as for GFXOFF to function 274 * properly under bare metal 275 */ 276 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && 277 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 278 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 279 1 << vmid, GET_INST(GC, 0)); 280 return; 281 } 282 283 /* This path is needed before KIQ/MES/GFXOFF are set up */ 284 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; 285 286 spin_lock(&adev->gmc.invalidate_lock); 287 /* 288 * It may lose gpuvm invalidate acknowldege state across power-gating 289 * off cycle, add semaphore acquire before invalidation and semaphore 290 * release after invalidation to avoid entering power gated state 291 * to WA the Issue 292 */ 293 294 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 295 if (use_semaphore) { 296 for (i = 0; i < adev->usec_timeout; i++) { 297 /* a read return value of 1 means semaphore acuqire */ 298 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); 299 if (tmp & 0x1) 300 break; 301 udelay(1); 302 } 303 304 if (i >= adev->usec_timeout) 305 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 306 } 307 308 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); 309 310 /* 311 * Issue a dummy read to wait for the ACK register to be cleared 312 * to avoid a false ACK due to the new fast GRBM interface. 313 */ 314 if ((vmhub == AMDGPU_GFXHUB(0)) && 315 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) 316 RREG32_RLC_NO_KIQ(req, hub_ip); 317 318 /* Wait for ACK with a delay.*/ 319 for (i = 0; i < adev->usec_timeout; i++) { 320 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); 321 tmp &= 1 << vmid; 322 if (tmp) 323 break; 324 325 udelay(1); 326 } 327 328 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 329 if (use_semaphore) 330 WREG32_RLC_NO_KIQ(sem, 0, hub_ip); 331 332 spin_unlock(&adev->gmc.invalidate_lock); 333 334 if (i >= adev->usec_timeout) 335 dev_err(adev->dev, "Timeout waiting for VM flush hub: %d!\n", 336 vmhub); 337 } 338 339 /** 340 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 341 * 342 * @adev: amdgpu_device pointer 343 * @pasid: pasid to be flush 344 * @flush_type: the flush type 345 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 346 * @inst: is used to select which instance of KIQ to use for the invalidation 347 * 348 * Flush the TLB for the requested pasid. 349 */ 350 static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 351 uint16_t pasid, uint32_t flush_type, 352 bool all_hub, uint32_t inst) 353 { 354 uint16_t queried; 355 int vmid, i; 356 357 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 358 bool valid; 359 360 valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 361 &queried); 362 if (!valid || queried != pasid) 363 continue; 364 365 if (all_hub) { 366 for_each_set_bit(i, adev->vmhubs_mask, 367 AMDGPU_MAX_VMHUBS) 368 gmc_v10_0_flush_gpu_tlb(adev, vmid, i, 369 flush_type); 370 } else { 371 gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 372 flush_type); 373 } 374 } 375 } 376 377 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 378 unsigned int vmid, uint64_t pd_addr) 379 { 380 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 381 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 382 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 383 unsigned int eng = ring->vm_inv_eng; 384 385 /* 386 * It may lose gpuvm invalidate acknowldege state across power-gating 387 * off cycle, add semaphore acquire before invalidation and semaphore 388 * release after invalidation to avoid entering power gated state 389 * to WA the Issue 390 */ 391 392 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 393 if (use_semaphore) 394 /* a read return value of 1 means semaphore acuqire */ 395 amdgpu_ring_emit_reg_wait(ring, 396 hub->vm_inv_eng0_sem + 397 hub->eng_distance * eng, 0x1, 0x1); 398 399 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 400 (hub->ctx_addr_distance * vmid), 401 lower_32_bits(pd_addr)); 402 403 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 404 (hub->ctx_addr_distance * vmid), 405 upper_32_bits(pd_addr)); 406 407 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 408 hub->eng_distance * eng, 409 hub->vm_inv_eng0_ack + 410 hub->eng_distance * eng, 411 req, 1 << vmid); 412 413 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 414 if (use_semaphore) 415 /* 416 * add semaphore release after invalidation, 417 * write with 0 means semaphore release 418 */ 419 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 420 hub->eng_distance * eng, 0); 421 422 return pd_addr; 423 } 424 425 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 426 unsigned int pasid) 427 { 428 struct amdgpu_device *adev = ring->adev; 429 uint32_t reg; 430 431 /* MES fw manages IH_VMID_x_LUT updating */ 432 if (ring->is_mes_queue) 433 return; 434 435 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 436 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 437 else 438 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 439 440 amdgpu_ring_emit_wreg(ring, reg, pasid); 441 } 442 443 /* 444 * PTE format on NAVI 10: 445 * 63:59 reserved 446 * 58 reserved and for sienna_cichlid is used for MALL noalloc 447 * 57 reserved 448 * 56 F 449 * 55 L 450 * 54 reserved 451 * 53:52 SW 452 * 51 T 453 * 50:48 mtype 454 * 47:12 4k physical page base address 455 * 11:7 fragment 456 * 6 write 457 * 5 read 458 * 4 exe 459 * 3 Z 460 * 2 snooped 461 * 1 system 462 * 0 valid 463 * 464 * PDE format on NAVI 10: 465 * 63:59 block fragment size 466 * 58:55 reserved 467 * 54 P 468 * 53:48 reserved 469 * 47:6 physical base address of PD or PTE 470 * 5:3 reserved 471 * 2 C 472 * 1 system 473 * 0 valid 474 */ 475 476 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 477 { 478 switch (flags) { 479 case AMDGPU_VM_MTYPE_DEFAULT: 480 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); 481 case AMDGPU_VM_MTYPE_NC: 482 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); 483 case AMDGPU_VM_MTYPE_WC: 484 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_WC); 485 case AMDGPU_VM_MTYPE_CC: 486 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_CC); 487 case AMDGPU_VM_MTYPE_UC: 488 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC); 489 default: 490 return AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_NC); 491 } 492 } 493 494 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 495 uint64_t *addr, uint64_t *flags) 496 { 497 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 498 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 499 BUG_ON(*addr & 0xFFFF00000000003FULL); 500 501 if (!adev->gmc.translate_further) 502 return; 503 504 if (level == AMDGPU_VM_PDB1) { 505 /* Set the block fragment size */ 506 if (!(*flags & AMDGPU_PDE_PTE)) 507 *flags |= AMDGPU_PDE_BFS(0x9); 508 509 } else if (level == AMDGPU_VM_PDB0) { 510 if (*flags & AMDGPU_PDE_PTE) 511 *flags &= ~AMDGPU_PDE_PTE; 512 else 513 *flags |= AMDGPU_PTE_TF; 514 } 515 } 516 517 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 518 struct amdgpu_bo_va_mapping *mapping, 519 uint64_t *flags) 520 { 521 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 522 523 *flags &= ~AMDGPU_PTE_EXECUTABLE; 524 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 525 526 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 527 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 528 529 *flags &= ~AMDGPU_PTE_NOALLOC; 530 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 531 532 if (mapping->flags & AMDGPU_PTE_PRT) { 533 *flags |= AMDGPU_PTE_PRT; 534 *flags |= AMDGPU_PTE_SNOOPED; 535 *flags |= AMDGPU_PTE_LOG; 536 *flags |= AMDGPU_PTE_SYSTEM; 537 *flags &= ~AMDGPU_PTE_VALID; 538 } 539 540 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 541 AMDGPU_GEM_CREATE_EXT_COHERENT | 542 AMDGPU_GEM_CREATE_UNCACHED)) 543 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); 544 } 545 546 static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 547 { 548 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 549 unsigned int size; 550 551 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 552 size = AMDGPU_VBIOS_VGA_ALLOCATION; 553 } else { 554 u32 viewport; 555 u32 pitch; 556 557 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 558 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 559 size = (REG_GET_FIELD(viewport, 560 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 561 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 562 4); 563 } 564 565 return size; 566 } 567 568 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 569 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 570 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 571 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 572 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 573 .map_mtype = gmc_v10_0_map_mtype, 574 .get_vm_pde = gmc_v10_0_get_vm_pde, 575 .get_vm_pte = gmc_v10_0_get_vm_pte, 576 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 577 }; 578 579 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 580 { 581 if (adev->gmc.gmc_funcs == NULL) 582 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 583 } 584 585 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 586 { 587 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 588 case IP_VERSION(8, 7, 0): 589 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 590 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 591 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 592 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 593 adev->umc.retire_unit = 1; 594 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 595 adev->umc.ras = &umc_v8_7_ras; 596 break; 597 default: 598 break; 599 } 600 } 601 602 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 603 { 604 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 605 case IP_VERSION(2, 3, 0): 606 case IP_VERSION(2, 4, 0): 607 case IP_VERSION(2, 4, 1): 608 adev->mmhub.funcs = &mmhub_v2_3_funcs; 609 break; 610 default: 611 adev->mmhub.funcs = &mmhub_v2_0_funcs; 612 break; 613 } 614 } 615 616 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 617 { 618 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 619 case IP_VERSION(10, 3, 0): 620 case IP_VERSION(10, 3, 2): 621 case IP_VERSION(10, 3, 1): 622 case IP_VERSION(10, 3, 4): 623 case IP_VERSION(10, 3, 5): 624 case IP_VERSION(10, 3, 6): 625 case IP_VERSION(10, 3, 3): 626 case IP_VERSION(10, 3, 7): 627 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 628 break; 629 default: 630 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 631 break; 632 } 633 } 634 635 636 static int gmc_v10_0_early_init(struct amdgpu_ip_block *ip_block) 637 { 638 struct amdgpu_device *adev = ip_block->adev; 639 640 gmc_v10_0_set_mmhub_funcs(adev); 641 gmc_v10_0_set_gfxhub_funcs(adev); 642 gmc_v10_0_set_gmc_funcs(adev); 643 gmc_v10_0_set_irq_funcs(adev); 644 gmc_v10_0_set_umc_funcs(adev); 645 646 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 647 adev->gmc.shared_aperture_end = 648 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 649 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 650 adev->gmc.private_aperture_end = 651 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 652 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 653 654 return 0; 655 } 656 657 static int gmc_v10_0_late_init(struct amdgpu_ip_block *ip_block) 658 { 659 struct amdgpu_device *adev = ip_block->adev; 660 int r; 661 662 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 663 if (r) 664 return r; 665 666 r = amdgpu_gmc_ras_late_init(adev); 667 if (r) 668 return r; 669 670 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 671 } 672 673 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 674 struct amdgpu_gmc *mc) 675 { 676 u64 base = 0; 677 678 base = adev->gfxhub.funcs->get_fb_location(adev); 679 680 /* add the xgmi offset of the physical node */ 681 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 682 683 amdgpu_gmc_set_agp_default(adev, mc); 684 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 685 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 686 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 687 amdgpu_gmc_agp_location(adev, mc); 688 689 /* base offset of vram pages */ 690 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 691 692 /* add the xgmi offset of the physical node */ 693 adev->vm_manager.vram_base_offset += 694 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 695 } 696 697 /** 698 * gmc_v10_0_mc_init - initialize the memory controller driver params 699 * 700 * @adev: amdgpu_device pointer 701 * 702 * Look up the amount of vram, vram width, and decide how to place 703 * vram and gart within the GPU's physical address space. 704 * Returns 0 for success. 705 */ 706 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 707 { 708 int r; 709 710 /* size in MB on si */ 711 adev->gmc.mc_vram_size = 712 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 713 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 714 715 if (!(adev->flags & AMD_IS_APU)) { 716 r = amdgpu_device_resize_fb_bar(adev); 717 if (r) 718 return r; 719 } 720 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 721 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 722 723 #ifdef CONFIG_X86_64 724 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 725 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 726 adev->gmc.aper_size = adev->gmc.real_vram_size; 727 } 728 #endif 729 730 adev->gmc.visible_vram_size = adev->gmc.aper_size; 731 732 /* set the gart size */ 733 if (amdgpu_gart_size == -1) { 734 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 735 default: 736 adev->gmc.gart_size = 512ULL << 20; 737 break; 738 case IP_VERSION(10, 3, 1): /* DCE SG support */ 739 case IP_VERSION(10, 3, 3): /* DCE SG support */ 740 case IP_VERSION(10, 3, 6): /* DCE SG support */ 741 case IP_VERSION(10, 3, 7): /* DCE SG support */ 742 adev->gmc.gart_size = 1024ULL << 20; 743 break; 744 } 745 } else { 746 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 747 } 748 749 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 750 751 return 0; 752 } 753 754 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 755 { 756 int r; 757 758 if (adev->gart.bo) { 759 WARN(1, "NAVI10 PCIE GART already initialized\n"); 760 return 0; 761 } 762 763 /* Initialize common gart structure */ 764 r = amdgpu_gart_init(adev); 765 if (r) 766 return r; 767 768 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 769 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | 770 AMDGPU_PTE_EXECUTABLE; 771 772 return amdgpu_gart_table_vram_alloc(adev); 773 } 774 775 static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 776 { 777 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 778 struct amdgpu_device *adev = ip_block->adev; 779 780 adev->gfxhub.funcs->init(adev); 781 782 adev->mmhub.funcs->init(adev); 783 784 spin_lock_init(&adev->gmc.invalidate_lock); 785 786 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 787 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 788 adev->gmc.vram_width = 64; 789 } else if (amdgpu_emu_mode == 1) { 790 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 791 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 792 } else { 793 r = amdgpu_atomfirmware_get_vram_info(adev, 794 &vram_width, &vram_type, &vram_vendor); 795 adev->gmc.vram_width = vram_width; 796 797 adev->gmc.vram_type = vram_type; 798 adev->gmc.vram_vendor = vram_vendor; 799 } 800 801 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 802 case IP_VERSION(10, 3, 0): 803 adev->gmc.mall_size = 128 * 1024 * 1024; 804 break; 805 case IP_VERSION(10, 3, 2): 806 adev->gmc.mall_size = 96 * 1024 * 1024; 807 break; 808 case IP_VERSION(10, 3, 4): 809 adev->gmc.mall_size = 32 * 1024 * 1024; 810 break; 811 case IP_VERSION(10, 3, 5): 812 adev->gmc.mall_size = 16 * 1024 * 1024; 813 break; 814 default: 815 adev->gmc.mall_size = 0; 816 break; 817 } 818 819 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 820 case IP_VERSION(10, 1, 10): 821 case IP_VERSION(10, 1, 1): 822 case IP_VERSION(10, 1, 2): 823 case IP_VERSION(10, 1, 3): 824 case IP_VERSION(10, 1, 4): 825 case IP_VERSION(10, 3, 0): 826 case IP_VERSION(10, 3, 2): 827 case IP_VERSION(10, 3, 1): 828 case IP_VERSION(10, 3, 4): 829 case IP_VERSION(10, 3, 5): 830 case IP_VERSION(10, 3, 6): 831 case IP_VERSION(10, 3, 3): 832 case IP_VERSION(10, 3, 7): 833 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 834 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 835 /* 836 * To fulfill 4-level page support, 837 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 838 * block size 512 (9bit) 839 */ 840 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 841 break; 842 default: 843 break; 844 } 845 846 /* This interrupt is VMC page fault.*/ 847 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 848 VMC_1_0__SRCID__VM_FAULT, 849 &adev->gmc.vm_fault); 850 851 if (r) 852 return r; 853 854 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 855 UTCL2_1_0__SRCID__FAULT, 856 &adev->gmc.vm_fault); 857 if (r) 858 return r; 859 860 if (!amdgpu_sriov_vf(adev)) { 861 /* interrupt sent to DF. */ 862 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 863 &adev->gmc.ecc_irq); 864 if (r) 865 return r; 866 } 867 868 /* 869 * Set the internal MC address mask This is the max address of the GPU's 870 * internal address space. 871 */ 872 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 873 874 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 875 if (r) { 876 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 877 return r; 878 } 879 880 adev->need_swiotlb = drm_need_swiotlb(44); 881 882 r = gmc_v10_0_mc_init(adev); 883 if (r) 884 return r; 885 886 amdgpu_gmc_get_vbios_allocations(adev); 887 888 /* Memory manager */ 889 r = amdgpu_bo_init(adev); 890 if (r) 891 return r; 892 893 r = gmc_v10_0_gart_init(adev); 894 if (r) 895 return r; 896 897 /* 898 * number of VMs 899 * VMID 0 is reserved for System 900 * amdgpu graphics/compute will use VMIDs 1-7 901 * amdkfd will use VMIDs 8-15 902 */ 903 adev->vm_manager.first_kfd_vmid = 8; 904 905 amdgpu_vm_manager_init(adev); 906 907 r = amdgpu_gmc_ras_sw_init(adev); 908 if (r) 909 return r; 910 911 return 0; 912 } 913 914 /** 915 * gmc_v10_0_gart_fini - vm fini callback 916 * 917 * @adev: amdgpu_device pointer 918 * 919 * Tears down the driver GART/VM setup (CIK). 920 */ 921 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 922 { 923 amdgpu_gart_table_vram_free(adev); 924 } 925 926 static int gmc_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 927 { 928 struct amdgpu_device *adev = ip_block->adev; 929 930 amdgpu_vm_manager_fini(adev); 931 gmc_v10_0_gart_fini(adev); 932 amdgpu_gem_force_release(adev); 933 amdgpu_bo_fini(adev); 934 935 return 0; 936 } 937 938 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 939 { 940 } 941 942 /** 943 * gmc_v10_0_gart_enable - gart enable 944 * 945 * @adev: amdgpu_device pointer 946 */ 947 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 948 { 949 int r; 950 bool value; 951 952 if (adev->gart.bo == NULL) { 953 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 954 return -EINVAL; 955 } 956 957 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 958 959 if (!adev->in_s0ix) { 960 r = adev->gfxhub.funcs->gart_enable(adev); 961 if (r) 962 return r; 963 } 964 965 r = adev->mmhub.funcs->gart_enable(adev); 966 if (r) 967 return r; 968 969 adev->hdp.funcs->init_registers(adev); 970 971 /* Flush HDP after it is initialized */ 972 adev->hdp.funcs->flush_hdp(adev, NULL); 973 974 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 975 false : true; 976 977 if (!adev->in_s0ix) 978 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 979 adev->mmhub.funcs->set_fault_enable_default(adev, value); 980 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 981 if (!adev->in_s0ix) 982 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 983 984 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 985 (unsigned int)(adev->gmc.gart_size >> 20), 986 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 987 988 return 0; 989 } 990 991 static int gmc_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 992 { 993 struct amdgpu_device *adev = ip_block->adev; 994 int r; 995 996 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; 997 998 /* The sequence of these two function calls matters.*/ 999 gmc_v10_0_init_golden_registers(adev); 1000 1001 /* 1002 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 1003 * register setup within GMC, or else system hang when harvesting SA. 1004 */ 1005 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 1006 adev->gfxhub.funcs->utcl2_harvest(adev); 1007 1008 r = gmc_v10_0_gart_enable(adev); 1009 if (r) 1010 return r; 1011 1012 if (amdgpu_emu_mode == 1) { 1013 r = amdgpu_gmc_vram_checking(adev); 1014 if (r) 1015 return r; 1016 } 1017 1018 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1019 adev->umc.funcs->init_registers(adev); 1020 1021 return 0; 1022 } 1023 1024 /** 1025 * gmc_v10_0_gart_disable - gart disable 1026 * 1027 * @adev: amdgpu_device pointer 1028 * 1029 * This disables all VM page table. 1030 */ 1031 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1032 { 1033 if (!adev->in_s0ix) 1034 adev->gfxhub.funcs->gart_disable(adev); 1035 adev->mmhub.funcs->gart_disable(adev); 1036 } 1037 1038 static int gmc_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 1039 { 1040 struct amdgpu_device *adev = ip_block->adev; 1041 1042 gmc_v10_0_gart_disable(adev); 1043 1044 if (amdgpu_sriov_vf(adev)) { 1045 /* full access mode, so don't touch any GMC register */ 1046 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1047 return 0; 1048 } 1049 1050 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1051 1052 if (adev->gmc.ecc_irq.funcs && 1053 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1054 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1055 1056 return 0; 1057 } 1058 1059 static int gmc_v10_0_suspend(struct amdgpu_ip_block *ip_block) 1060 { 1061 gmc_v10_0_hw_fini(ip_block); 1062 1063 return 0; 1064 } 1065 1066 static int gmc_v10_0_resume(struct amdgpu_ip_block *ip_block) 1067 { 1068 int r; 1069 1070 r = gmc_v10_0_hw_init(ip_block); 1071 if (r) 1072 return r; 1073 1074 amdgpu_vmid_reset_all(ip_block->adev); 1075 1076 return 0; 1077 } 1078 1079 static bool gmc_v10_0_is_idle(void *handle) 1080 { 1081 /* MC is always ready in GMC v10.*/ 1082 return true; 1083 } 1084 1085 static int gmc_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1086 { 1087 /* There is no need to wait for MC idle in GMC v10.*/ 1088 return 0; 1089 } 1090 1091 static int gmc_v10_0_set_clockgating_state(void *handle, 1092 enum amd_clockgating_state state) 1093 { 1094 int r; 1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1096 1097 /* 1098 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1099 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1100 * seen any issue on the DF 3.0.2 series platform. 1101 */ 1102 if (adev->in_s0ix && 1103 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) { 1104 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1105 return 0; 1106 } 1107 1108 r = adev->mmhub.funcs->set_clockgating(adev, state); 1109 if (r) 1110 return r; 1111 1112 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1113 return athub_v2_1_set_clockgating(adev, state); 1114 else 1115 return athub_v2_0_set_clockgating(adev, state); 1116 } 1117 1118 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) 1119 { 1120 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1121 1122 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || 1123 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) 1124 return; 1125 1126 adev->mmhub.funcs->get_clockgating(adev, flags); 1127 1128 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1129 athub_v2_1_get_clockgating(adev, flags); 1130 else 1131 athub_v2_0_get_clockgating(adev, flags); 1132 } 1133 1134 static int gmc_v10_0_set_powergating_state(void *handle, 1135 enum amd_powergating_state state) 1136 { 1137 return 0; 1138 } 1139 1140 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1141 .name = "gmc_v10_0", 1142 .early_init = gmc_v10_0_early_init, 1143 .late_init = gmc_v10_0_late_init, 1144 .sw_init = gmc_v10_0_sw_init, 1145 .sw_fini = gmc_v10_0_sw_fini, 1146 .hw_init = gmc_v10_0_hw_init, 1147 .hw_fini = gmc_v10_0_hw_fini, 1148 .suspend = gmc_v10_0_suspend, 1149 .resume = gmc_v10_0_resume, 1150 .is_idle = gmc_v10_0_is_idle, 1151 .wait_for_idle = gmc_v10_0_wait_for_idle, 1152 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1153 .set_powergating_state = gmc_v10_0_set_powergating_state, 1154 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1155 }; 1156 1157 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = { 1158 .type = AMD_IP_BLOCK_TYPE_GMC, 1159 .major = 10, 1160 .minor = 0, 1161 .rev = 0, 1162 .funcs = &gmc_v10_0_ip_funcs, 1163 }; 1164