1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 55 struct amdgpu_irq_src *src, 56 unsigned int type, 57 enum amdgpu_interrupt_state state) 58 { 59 return 0; 60 } 61 62 static int 63 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 64 struct amdgpu_irq_src *src, unsigned int type, 65 enum amdgpu_interrupt_state state) 66 { 67 switch (state) { 68 case AMDGPU_IRQ_STATE_DISABLE: 69 /* MM HUB */ 70 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 71 /* GFX HUB */ 72 /* This works because this interrupt is only 73 * enabled at init/resume and disabled in 74 * fini/suspend, so the overall state doesn't 75 * change over the course of suspend/resume. 76 */ 77 if (!adev->in_s0ix) 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 83 /* GFX HUB */ 84 /* This works because this interrupt is only 85 * enabled at init/resume and disabled in 86 * fini/suspend, so the overall state doesn't 87 * change over the course of suspend/resume. 88 */ 89 if (!adev->in_s0ix) 90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 91 break; 92 default: 93 break; 94 } 95 96 return 0; 97 } 98 99 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 100 struct amdgpu_irq_src *source, 101 struct amdgpu_iv_entry *entry) 102 { 103 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? 104 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 105 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 106 bool retry_fault = !!(entry->src_data[1] & 107 AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY); 108 bool write_fault = !!(entry->src_data[1] & 109 AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE); 110 struct amdgpu_task_info *task_info; 111 uint32_t status = 0; 112 u64 addr; 113 114 addr = (u64)entry->src_data[0] << 12; 115 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 116 117 if (retry_fault) { 118 /* Returning 1 here also prevents sending the IV to the KFD */ 119 120 /* Process it onyl if it's the first fault for this address */ 121 if (entry->ih != &adev->irq.ih_soft && 122 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 123 entry->timestamp)) 124 return 1; 125 126 /* Delegate it to a different ring if the hardware hasn't 127 * already done it. 128 */ 129 if (entry->ih == &adev->irq.ih) { 130 amdgpu_irq_delegate(adev, entry, 8); 131 return 1; 132 } 133 134 /* Try to handle the recoverable page faults by filling page 135 * tables 136 */ 137 if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, 138 entry->timestamp, write_fault)) 139 return 1; 140 } 141 142 if (!amdgpu_sriov_vf(adev)) { 143 /* 144 * Issue a dummy read to wait for the status register to 145 * be updated to avoid reading an incorrect value due to 146 * the new fast GRBM interface. 147 */ 148 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 149 (amdgpu_ip_version(adev, GC_HWIP, 0) < 150 IP_VERSION(10, 3, 0))) 151 RREG32(hub->vm_l2_pro_fault_status); 152 153 status = RREG32(hub->vm_l2_pro_fault_status); 154 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 155 156 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 157 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 158 } 159 160 if (!printk_ratelimit()) 161 return 0; 162 163 dev_err(adev->dev, 164 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 165 entry->vmid_src ? "mmhub" : "gfxhub", 166 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 167 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 168 if (task_info) { 169 amdgpu_vm_print_task_info(adev, task_info); 170 amdgpu_vm_put_task_info(task_info); 171 } 172 173 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 174 addr, entry->client_id, 175 soc15_ih_clientid_name[entry->client_id]); 176 177 /* Only print L2 fault status if the status register could be read and 178 * contains useful information 179 */ 180 if (status != 0) 181 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 182 status); 183 184 return 0; 185 } 186 187 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 188 .set = gmc_v10_0_vm_fault_interrupt_state, 189 .process = gmc_v10_0_process_interrupt, 190 }; 191 192 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 193 .set = gmc_v10_0_ecc_interrupt_state, 194 .process = amdgpu_umc_process_ecc_irq, 195 }; 196 197 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 198 { 199 adev->gmc.vm_fault.num_types = 1; 200 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 201 202 if (!amdgpu_sriov_vf(adev)) { 203 adev->gmc.ecc_irq.num_types = 1; 204 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 205 } 206 } 207 208 /** 209 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 210 * 211 * @adev: amdgpu_device pointer 212 * @vmhub: vmhub type 213 * 214 */ 215 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 216 uint32_t vmhub) 217 { 218 return ((vmhub == AMDGPU_MMHUB0(0)) && 219 (!amdgpu_sriov_vf(adev))); 220 } 221 222 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 223 struct amdgpu_device *adev, 224 uint8_t vmid, uint16_t *p_pasid) 225 { 226 uint32_t value; 227 228 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 229 + vmid); 230 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 231 232 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 233 } 234 235 /* 236 * GART 237 * VMID 0 is the physical GPU addresses as used by the kernel. 238 * VMIDs 1-15 are used for userspace clients and are handled 239 * by the amdgpu vm/hsa code. 240 */ 241 242 /** 243 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 244 * 245 * @adev: amdgpu_device pointer 246 * @vmid: vm instance to flush 247 * @vmhub: vmhub type 248 * @flush_type: the flush type 249 * 250 * Flush the TLB for the requested page table. 251 */ 252 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 253 uint32_t vmhub, uint32_t flush_type) 254 { 255 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 256 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 257 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 258 /* Use register 17 for GART */ 259 const unsigned int eng = 17; 260 unsigned char hub_ip = 0; 261 u32 sem, req, ack; 262 unsigned int i; 263 u32 tmp; 264 265 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 266 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 267 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 268 269 /* flush hdp cache */ 270 amdgpu_device_flush_hdp(adev, NULL); 271 272 /* This is necessary for SRIOV as well as for GFXOFF to function 273 * properly under bare metal 274 */ 275 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && 276 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 277 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 278 1 << vmid, GET_INST(GC, 0)); 279 return; 280 } 281 282 /* This path is needed before KIQ/MES/GFXOFF are set up */ 283 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; 284 285 spin_lock(&adev->gmc.invalidate_lock); 286 /* 287 * It may lose gpuvm invalidate acknowldege state across power-gating 288 * off cycle, add semaphore acquire before invalidation and semaphore 289 * release after invalidation to avoid entering power gated state 290 * to WA the Issue 291 */ 292 293 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 294 if (use_semaphore) { 295 for (i = 0; i < adev->usec_timeout; i++) { 296 /* a read return value of 1 means semaphore acuqire */ 297 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); 298 if (tmp & 0x1) 299 break; 300 udelay(1); 301 } 302 303 if (i >= adev->usec_timeout) 304 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 305 } 306 307 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); 308 309 /* 310 * Issue a dummy read to wait for the ACK register to be cleared 311 * to avoid a false ACK due to the new fast GRBM interface. 312 */ 313 if ((vmhub == AMDGPU_GFXHUB(0)) && 314 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) 315 RREG32_RLC_NO_KIQ(req, hub_ip); 316 317 /* Wait for ACK with a delay.*/ 318 for (i = 0; i < adev->usec_timeout; i++) { 319 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); 320 tmp &= 1 << vmid; 321 if (tmp) 322 break; 323 324 udelay(1); 325 } 326 327 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 328 if (use_semaphore) 329 WREG32_RLC_NO_KIQ(sem, 0, hub_ip); 330 331 spin_unlock(&adev->gmc.invalidate_lock); 332 333 if (i >= adev->usec_timeout) 334 dev_err(adev->dev, "Timeout waiting for VM flush hub: %d!\n", 335 vmhub); 336 } 337 338 /** 339 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 340 * 341 * @adev: amdgpu_device pointer 342 * @pasid: pasid to be flush 343 * @flush_type: the flush type 344 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 345 * @inst: is used to select which instance of KIQ to use for the invalidation 346 * 347 * Flush the TLB for the requested pasid. 348 */ 349 static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 350 uint16_t pasid, uint32_t flush_type, 351 bool all_hub, uint32_t inst) 352 { 353 uint16_t queried; 354 int vmid, i; 355 356 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 357 bool valid; 358 359 valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 360 &queried); 361 if (!valid || queried != pasid) 362 continue; 363 364 if (all_hub) { 365 for_each_set_bit(i, adev->vmhubs_mask, 366 AMDGPU_MAX_VMHUBS) 367 gmc_v10_0_flush_gpu_tlb(adev, vmid, i, 368 flush_type); 369 } else { 370 gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 371 flush_type); 372 } 373 } 374 } 375 376 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 377 unsigned int vmid, uint64_t pd_addr) 378 { 379 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 380 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 381 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 382 unsigned int eng = ring->vm_inv_eng; 383 384 /* 385 * It may lose gpuvm invalidate acknowldege state across power-gating 386 * off cycle, add semaphore acquire before invalidation and semaphore 387 * release after invalidation to avoid entering power gated state 388 * to WA the Issue 389 */ 390 391 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 392 if (use_semaphore) 393 /* a read return value of 1 means semaphore acuqire */ 394 amdgpu_ring_emit_reg_wait(ring, 395 hub->vm_inv_eng0_sem + 396 hub->eng_distance * eng, 0x1, 0x1); 397 398 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 399 (hub->ctx_addr_distance * vmid), 400 lower_32_bits(pd_addr)); 401 402 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 403 (hub->ctx_addr_distance * vmid), 404 upper_32_bits(pd_addr)); 405 406 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 407 hub->eng_distance * eng, 408 hub->vm_inv_eng0_ack + 409 hub->eng_distance * eng, 410 req, 1 << vmid); 411 412 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 413 if (use_semaphore) 414 /* 415 * add semaphore release after invalidation, 416 * write with 0 means semaphore release 417 */ 418 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 419 hub->eng_distance * eng, 0); 420 421 return pd_addr; 422 } 423 424 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 425 unsigned int pasid) 426 { 427 struct amdgpu_device *adev = ring->adev; 428 uint32_t reg; 429 430 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 431 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 432 else 433 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 434 435 amdgpu_ring_emit_wreg(ring, reg, pasid); 436 } 437 438 /* 439 * PTE format on NAVI 10: 440 * 63:59 reserved 441 * 58 reserved and for sienna_cichlid is used for MALL noalloc 442 * 57 reserved 443 * 56 F 444 * 55 L 445 * 54 reserved 446 * 53:52 SW 447 * 51 T 448 * 50:48 mtype 449 * 47:12 4k physical page base address 450 * 11:7 fragment 451 * 6 write 452 * 5 read 453 * 4 exe 454 * 3 Z 455 * 2 snooped 456 * 1 system 457 * 0 valid 458 * 459 * PDE format on NAVI 10: 460 * 63:59 block fragment size 461 * 58:55 reserved 462 * 54 P 463 * 53:48 reserved 464 * 47:6 physical base address of PD or PTE 465 * 5:3 reserved 466 * 2 C 467 * 1 system 468 * 0 valid 469 */ 470 471 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 472 uint64_t *addr, uint64_t *flags) 473 { 474 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 475 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 476 BUG_ON(*addr & 0xFFFF00000000003FULL); 477 478 if (!adev->gmc.translate_further) 479 return; 480 481 if (level == AMDGPU_VM_PDB1) { 482 /* Set the block fragment size */ 483 if (!(*flags & AMDGPU_PDE_PTE)) 484 *flags |= AMDGPU_PDE_BFS(0x9); 485 486 } else if (level == AMDGPU_VM_PDB0) { 487 if (*flags & AMDGPU_PDE_PTE) 488 *flags &= ~AMDGPU_PDE_PTE; 489 else 490 *flags |= AMDGPU_PTE_TF; 491 } 492 } 493 494 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 495 struct amdgpu_vm *vm, 496 struct amdgpu_bo *bo, 497 uint32_t vm_flags, 498 uint64_t *flags) 499 { 500 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 501 *flags |= AMDGPU_PTE_EXECUTABLE; 502 else 503 *flags &= ~AMDGPU_PTE_EXECUTABLE; 504 505 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 506 case AMDGPU_VM_MTYPE_DEFAULT: 507 case AMDGPU_VM_MTYPE_NC: 508 default: 509 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC); 510 break; 511 case AMDGPU_VM_MTYPE_WC: 512 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC); 513 break; 514 case AMDGPU_VM_MTYPE_CC: 515 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC); 516 break; 517 case AMDGPU_VM_MTYPE_UC: 518 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); 519 break; 520 } 521 522 if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) 523 *flags |= AMDGPU_PTE_NOALLOC; 524 else 525 *flags &= ~AMDGPU_PTE_NOALLOC; 526 527 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 528 *flags |= AMDGPU_PTE_PRT; 529 *flags |= AMDGPU_PTE_SNOOPED; 530 *flags |= AMDGPU_PTE_LOG; 531 *flags |= AMDGPU_PTE_SYSTEM; 532 *flags &= ~AMDGPU_PTE_VALID; 533 } 534 535 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 536 AMDGPU_GEM_CREATE_EXT_COHERENT | 537 AMDGPU_GEM_CREATE_UNCACHED)) 538 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); 539 } 540 541 static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 542 { 543 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 544 unsigned int size; 545 546 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 547 size = AMDGPU_VBIOS_VGA_ALLOCATION; 548 } else { 549 u32 viewport; 550 u32 pitch; 551 552 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 553 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 554 size = (REG_GET_FIELD(viewport, 555 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 556 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 557 4); 558 } 559 560 return size; 561 } 562 563 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 564 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 565 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 566 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 567 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 568 .get_vm_pde = gmc_v10_0_get_vm_pde, 569 .get_vm_pte = gmc_v10_0_get_vm_pte, 570 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 571 }; 572 573 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 574 { 575 if (adev->gmc.gmc_funcs == NULL) 576 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 577 } 578 579 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 580 { 581 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 582 case IP_VERSION(8, 7, 0): 583 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 584 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 585 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 586 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 587 adev->umc.retire_unit = 1; 588 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 589 adev->umc.ras = &umc_v8_7_ras; 590 break; 591 default: 592 break; 593 } 594 } 595 596 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 597 { 598 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 599 case IP_VERSION(2, 3, 0): 600 case IP_VERSION(2, 4, 0): 601 case IP_VERSION(2, 4, 1): 602 adev->mmhub.funcs = &mmhub_v2_3_funcs; 603 break; 604 default: 605 adev->mmhub.funcs = &mmhub_v2_0_funcs; 606 break; 607 } 608 } 609 610 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 611 { 612 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 613 case IP_VERSION(10, 3, 0): 614 case IP_VERSION(10, 3, 2): 615 case IP_VERSION(10, 3, 1): 616 case IP_VERSION(10, 3, 4): 617 case IP_VERSION(10, 3, 5): 618 case IP_VERSION(10, 3, 6): 619 case IP_VERSION(10, 3, 3): 620 case IP_VERSION(10, 3, 7): 621 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 622 break; 623 default: 624 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 625 break; 626 } 627 } 628 629 630 static int gmc_v10_0_early_init(struct amdgpu_ip_block *ip_block) 631 { 632 struct amdgpu_device *adev = ip_block->adev; 633 634 gmc_v10_0_set_mmhub_funcs(adev); 635 gmc_v10_0_set_gfxhub_funcs(adev); 636 gmc_v10_0_set_gmc_funcs(adev); 637 gmc_v10_0_set_irq_funcs(adev); 638 gmc_v10_0_set_umc_funcs(adev); 639 640 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 641 adev->gmc.shared_aperture_end = 642 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 643 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 644 adev->gmc.private_aperture_end = 645 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 646 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 647 648 return 0; 649 } 650 651 static int gmc_v10_0_late_init(struct amdgpu_ip_block *ip_block) 652 { 653 struct amdgpu_device *adev = ip_block->adev; 654 int r; 655 656 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 657 if (r) 658 return r; 659 660 r = amdgpu_gmc_ras_late_init(adev); 661 if (r) 662 return r; 663 664 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 665 } 666 667 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 668 struct amdgpu_gmc *mc) 669 { 670 u64 base = 0; 671 672 base = adev->gfxhub.funcs->get_fb_location(adev); 673 674 /* add the xgmi offset of the physical node */ 675 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 676 677 amdgpu_gmc_set_agp_default(adev, mc); 678 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 679 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 680 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 681 amdgpu_gmc_agp_location(adev, mc); 682 683 /* base offset of vram pages */ 684 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 685 686 /* add the xgmi offset of the physical node */ 687 adev->vm_manager.vram_base_offset += 688 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 689 } 690 691 /** 692 * gmc_v10_0_mc_init - initialize the memory controller driver params 693 * 694 * @adev: amdgpu_device pointer 695 * 696 * Look up the amount of vram, vram width, and decide how to place 697 * vram and gart within the GPU's physical address space. 698 * Returns 0 for success. 699 */ 700 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 701 { 702 int r; 703 704 /* size in MB on si */ 705 adev->gmc.mc_vram_size = 706 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 707 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 708 709 if (!(adev->flags & AMD_IS_APU)) { 710 r = amdgpu_device_resize_fb_bar(adev); 711 if (r) 712 return r; 713 } 714 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 715 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 716 717 #ifdef CONFIG_X86_64 718 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 719 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 720 adev->gmc.aper_size = adev->gmc.real_vram_size; 721 } 722 #endif 723 724 adev->gmc.visible_vram_size = adev->gmc.aper_size; 725 726 /* set the gart size */ 727 if (amdgpu_gart_size == -1) { 728 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 729 default: 730 adev->gmc.gart_size = 512ULL << 20; 731 break; 732 case IP_VERSION(10, 3, 1): /* DCE SG support */ 733 case IP_VERSION(10, 3, 3): /* DCE SG support */ 734 case IP_VERSION(10, 3, 6): /* DCE SG support */ 735 case IP_VERSION(10, 3, 7): /* DCE SG support */ 736 adev->gmc.gart_size = 1024ULL << 20; 737 break; 738 } 739 } else { 740 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 741 } 742 743 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 744 745 return 0; 746 } 747 748 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 749 { 750 int r; 751 752 if (adev->gart.bo) { 753 WARN(1, "NAVI10 PCIE GART already initialized\n"); 754 return 0; 755 } 756 757 /* Initialize common gart structure */ 758 r = amdgpu_gart_init(adev); 759 if (r) 760 return r; 761 762 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 763 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | 764 AMDGPU_PTE_EXECUTABLE; 765 766 return amdgpu_gart_table_vram_alloc(adev); 767 } 768 769 static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 770 { 771 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 772 struct amdgpu_device *adev = ip_block->adev; 773 774 adev->gfxhub.funcs->init(adev); 775 776 adev->mmhub.funcs->init(adev); 777 778 spin_lock_init(&adev->gmc.invalidate_lock); 779 780 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 781 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 782 adev->gmc.vram_width = 64; 783 } else if (amdgpu_emu_mode == 1) { 784 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 785 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 786 } else { 787 r = amdgpu_atomfirmware_get_vram_info(adev, 788 &vram_width, &vram_type, &vram_vendor); 789 adev->gmc.vram_width = vram_width; 790 791 adev->gmc.vram_type = vram_type; 792 adev->gmc.vram_vendor = vram_vendor; 793 } 794 795 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 796 case IP_VERSION(10, 3, 0): 797 adev->gmc.mall_size = 128 * 1024 * 1024; 798 break; 799 case IP_VERSION(10, 3, 2): 800 adev->gmc.mall_size = 96 * 1024 * 1024; 801 break; 802 case IP_VERSION(10, 3, 4): 803 adev->gmc.mall_size = 32 * 1024 * 1024; 804 break; 805 case IP_VERSION(10, 3, 5): 806 adev->gmc.mall_size = 16 * 1024 * 1024; 807 break; 808 default: 809 adev->gmc.mall_size = 0; 810 break; 811 } 812 813 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 814 case IP_VERSION(10, 1, 10): 815 case IP_VERSION(10, 1, 1): 816 case IP_VERSION(10, 1, 2): 817 case IP_VERSION(10, 1, 3): 818 case IP_VERSION(10, 1, 4): 819 case IP_VERSION(10, 3, 0): 820 case IP_VERSION(10, 3, 2): 821 case IP_VERSION(10, 3, 1): 822 case IP_VERSION(10, 3, 4): 823 case IP_VERSION(10, 3, 5): 824 case IP_VERSION(10, 3, 6): 825 case IP_VERSION(10, 3, 3): 826 case IP_VERSION(10, 3, 7): 827 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 828 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 829 /* 830 * To fulfill 4-level page support, 831 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 832 * block size 512 (9bit) 833 */ 834 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 835 break; 836 default: 837 break; 838 } 839 840 /* This interrupt is VMC page fault.*/ 841 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 842 VMC_1_0__SRCID__VM_FAULT, 843 &adev->gmc.vm_fault); 844 845 if (r) 846 return r; 847 848 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 849 UTCL2_1_0__SRCID__FAULT, 850 &adev->gmc.vm_fault); 851 if (r) 852 return r; 853 854 if (!amdgpu_sriov_vf(adev)) { 855 /* interrupt sent to DF. */ 856 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 857 &adev->gmc.ecc_irq); 858 if (r) 859 return r; 860 } 861 862 /* 863 * Set the internal MC address mask This is the max address of the GPU's 864 * internal address space. 865 */ 866 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 867 868 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 869 if (r) { 870 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 871 return r; 872 } 873 874 adev->need_swiotlb = drm_need_swiotlb(44); 875 876 r = gmc_v10_0_mc_init(adev); 877 if (r) 878 return r; 879 880 amdgpu_gmc_get_vbios_allocations(adev); 881 882 /* Memory manager */ 883 r = amdgpu_bo_init(adev); 884 if (r) 885 return r; 886 887 r = gmc_v10_0_gart_init(adev); 888 if (r) 889 return r; 890 891 /* 892 * number of VMs 893 * VMID 0 is reserved for System 894 * amdgpu graphics/compute will use VMIDs 1-7 895 * amdkfd will use VMIDs 8-15 896 */ 897 adev->vm_manager.first_kfd_vmid = 8; 898 899 amdgpu_vm_manager_init(adev); 900 901 r = amdgpu_gmc_ras_sw_init(adev); 902 if (r) 903 return r; 904 905 return 0; 906 } 907 908 /** 909 * gmc_v10_0_gart_fini - vm fini callback 910 * 911 * @adev: amdgpu_device pointer 912 * 913 * Tears down the driver GART/VM setup (CIK). 914 */ 915 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 916 { 917 amdgpu_gart_table_vram_free(adev); 918 } 919 920 static int gmc_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 921 { 922 struct amdgpu_device *adev = ip_block->adev; 923 924 amdgpu_vm_manager_fini(adev); 925 gmc_v10_0_gart_fini(adev); 926 amdgpu_gem_force_release(adev); 927 amdgpu_bo_fini(adev); 928 929 return 0; 930 } 931 932 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 933 { 934 } 935 936 /** 937 * gmc_v10_0_gart_enable - gart enable 938 * 939 * @adev: amdgpu_device pointer 940 */ 941 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 942 { 943 int r; 944 bool value; 945 946 if (adev->gart.bo == NULL) { 947 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 948 return -EINVAL; 949 } 950 951 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 952 953 if (!adev->in_s0ix) { 954 r = adev->gfxhub.funcs->gart_enable(adev); 955 if (r) 956 return r; 957 } 958 959 r = adev->mmhub.funcs->gart_enable(adev); 960 if (r) 961 return r; 962 963 adev->hdp.funcs->init_registers(adev); 964 965 /* Flush HDP after it is initialized */ 966 amdgpu_device_flush_hdp(adev, NULL); 967 968 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 969 970 if (!adev->in_s0ix) 971 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 972 adev->mmhub.funcs->set_fault_enable_default(adev, value); 973 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 974 if (!adev->in_s0ix) 975 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 976 977 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 978 (unsigned int)(adev->gmc.gart_size >> 20), 979 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 980 981 return 0; 982 } 983 984 static int gmc_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 985 { 986 struct amdgpu_device *adev = ip_block->adev; 987 int r; 988 989 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; 990 991 /* The sequence of these two function calls matters.*/ 992 gmc_v10_0_init_golden_registers(adev); 993 994 /* 995 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 996 * register setup within GMC, or else system hang when harvesting SA. 997 */ 998 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 999 adev->gfxhub.funcs->utcl2_harvest(adev); 1000 1001 r = gmc_v10_0_gart_enable(adev); 1002 if (r) 1003 return r; 1004 1005 if (amdgpu_emu_mode == 1) { 1006 r = amdgpu_gmc_vram_checking(adev); 1007 if (r) 1008 return r; 1009 } 1010 1011 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1012 adev->umc.funcs->init_registers(adev); 1013 1014 return 0; 1015 } 1016 1017 /** 1018 * gmc_v10_0_gart_disable - gart disable 1019 * 1020 * @adev: amdgpu_device pointer 1021 * 1022 * This disables all VM page table. 1023 */ 1024 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1025 { 1026 if (!adev->in_s0ix) 1027 adev->gfxhub.funcs->gart_disable(adev); 1028 adev->mmhub.funcs->gart_disable(adev); 1029 } 1030 1031 static int gmc_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 1032 { 1033 struct amdgpu_device *adev = ip_block->adev; 1034 1035 gmc_v10_0_gart_disable(adev); 1036 1037 if (amdgpu_sriov_vf(adev)) { 1038 /* full access mode, so don't touch any GMC register */ 1039 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1040 return 0; 1041 } 1042 1043 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1044 1045 if (adev->gmc.ecc_irq.funcs && 1046 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1047 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1048 1049 return 0; 1050 } 1051 1052 static int gmc_v10_0_suspend(struct amdgpu_ip_block *ip_block) 1053 { 1054 gmc_v10_0_hw_fini(ip_block); 1055 1056 return 0; 1057 } 1058 1059 static int gmc_v10_0_resume(struct amdgpu_ip_block *ip_block) 1060 { 1061 int r; 1062 1063 r = gmc_v10_0_hw_init(ip_block); 1064 if (r) 1065 return r; 1066 1067 amdgpu_vmid_reset_all(ip_block->adev); 1068 1069 return 0; 1070 } 1071 1072 static bool gmc_v10_0_is_idle(struct amdgpu_ip_block *ip_block) 1073 { 1074 /* MC is always ready in GMC v10.*/ 1075 return true; 1076 } 1077 1078 static int gmc_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1079 { 1080 /* There is no need to wait for MC idle in GMC v10.*/ 1081 return 0; 1082 } 1083 1084 static int gmc_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1085 enum amd_clockgating_state state) 1086 { 1087 int r; 1088 struct amdgpu_device *adev = ip_block->adev; 1089 1090 /* 1091 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1092 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1093 * seen any issue on the DF 3.0.2 series platform. 1094 */ 1095 if (adev->in_s0ix && 1096 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) { 1097 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1098 return 0; 1099 } 1100 1101 r = adev->mmhub.funcs->set_clockgating(adev, state); 1102 if (r) 1103 return r; 1104 1105 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1106 return athub_v2_1_set_clockgating(adev, state); 1107 else 1108 return athub_v2_0_set_clockgating(adev, state); 1109 } 1110 1111 static void gmc_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1112 { 1113 struct amdgpu_device *adev = ip_block->adev; 1114 1115 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || 1116 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) 1117 return; 1118 1119 adev->mmhub.funcs->get_clockgating(adev, flags); 1120 1121 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1122 athub_v2_1_get_clockgating(adev, flags); 1123 else 1124 athub_v2_0_get_clockgating(adev, flags); 1125 } 1126 1127 static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1128 enum amd_powergating_state state) 1129 { 1130 return 0; 1131 } 1132 1133 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1134 .name = "gmc_v10_0", 1135 .early_init = gmc_v10_0_early_init, 1136 .late_init = gmc_v10_0_late_init, 1137 .sw_init = gmc_v10_0_sw_init, 1138 .sw_fini = gmc_v10_0_sw_fini, 1139 .hw_init = gmc_v10_0_hw_init, 1140 .hw_fini = gmc_v10_0_hw_fini, 1141 .suspend = gmc_v10_0_suspend, 1142 .resume = gmc_v10_0_resume, 1143 .is_idle = gmc_v10_0_is_idle, 1144 .wait_for_idle = gmc_v10_0_wait_for_idle, 1145 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1146 .set_powergating_state = gmc_v10_0_set_powergating_state, 1147 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1148 }; 1149 1150 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = { 1151 .type = AMD_IP_BLOCK_TYPE_GMC, 1152 .major = 10, 1153 .minor = 0, 1154 .rev = 0, 1155 .funcs = &gmc_v10_0_ip_funcs, 1156 }; 1157