1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 55 struct amdgpu_irq_src *src, 56 unsigned int type, 57 enum amdgpu_interrupt_state state) 58 { 59 return 0; 60 } 61 62 static int 63 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 64 struct amdgpu_irq_src *src, unsigned int type, 65 enum amdgpu_interrupt_state state) 66 { 67 switch (state) { 68 case AMDGPU_IRQ_STATE_DISABLE: 69 /* MM HUB */ 70 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 71 /* GFX HUB */ 72 /* This works because this interrupt is only 73 * enabled at init/resume and disabled in 74 * fini/suspend, so the overall state doesn't 75 * change over the course of suspend/resume. 76 */ 77 if (!adev->in_s0ix) 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 83 /* GFX HUB */ 84 /* This works because this interrupt is only 85 * enabled at init/resume and disabled in 86 * fini/suspend, so the overall state doesn't 87 * change over the course of suspend/resume. 88 */ 89 if (!adev->in_s0ix) 90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 91 break; 92 default: 93 break; 94 } 95 96 return 0; 97 } 98 99 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 100 struct amdgpu_irq_src *source, 101 struct amdgpu_iv_entry *entry) 102 { 103 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? 104 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 105 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 106 bool retry_fault = !!(entry->src_data[1] & 0x80); 107 bool write_fault = !!(entry->src_data[1] & 0x20); 108 struct amdgpu_task_info task_info; 109 uint32_t status = 0; 110 u64 addr; 111 112 addr = (u64)entry->src_data[0] << 12; 113 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 114 115 if (retry_fault) { 116 /* Returning 1 here also prevents sending the IV to the KFD */ 117 118 /* Process it onyl if it's the first fault for this address */ 119 if (entry->ih != &adev->irq.ih_soft && 120 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 121 entry->timestamp)) 122 return 1; 123 124 /* Delegate it to a different ring if the hardware hasn't 125 * already done it. 126 */ 127 if (entry->ih == &adev->irq.ih) { 128 amdgpu_irq_delegate(adev, entry, 8); 129 return 1; 130 } 131 132 /* Try to handle the recoverable page faults by filling page 133 * tables 134 */ 135 if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, write_fault)) 136 return 1; 137 } 138 139 if (!amdgpu_sriov_vf(adev)) { 140 /* 141 * Issue a dummy read to wait for the status register to 142 * be updated to avoid reading an incorrect value due to 143 * the new fast GRBM interface. 144 */ 145 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 146 (amdgpu_ip_version(adev, GC_HWIP, 0) < 147 IP_VERSION(10, 3, 0))) 148 RREG32(hub->vm_l2_pro_fault_status); 149 150 status = RREG32(hub->vm_l2_pro_fault_status); 151 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 152 153 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 154 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 155 } 156 157 if (!printk_ratelimit()) 158 return 0; 159 160 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 161 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 162 163 dev_err(adev->dev, 164 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 165 entry->vmid_src ? "mmhub" : "gfxhub", 166 entry->src_id, entry->ring_id, entry->vmid, 167 entry->pasid, task_info.process_name, task_info.tgid, 168 task_info.task_name, task_info.pid); 169 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 170 addr, entry->client_id, 171 soc15_ih_clientid_name[entry->client_id]); 172 173 if (!amdgpu_sriov_vf(adev)) 174 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 175 status); 176 177 return 0; 178 } 179 180 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 181 .set = gmc_v10_0_vm_fault_interrupt_state, 182 .process = gmc_v10_0_process_interrupt, 183 }; 184 185 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 186 .set = gmc_v10_0_ecc_interrupt_state, 187 .process = amdgpu_umc_process_ecc_irq, 188 }; 189 190 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 191 { 192 adev->gmc.vm_fault.num_types = 1; 193 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 194 195 if (!amdgpu_sriov_vf(adev)) { 196 adev->gmc.ecc_irq.num_types = 1; 197 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 198 } 199 } 200 201 /** 202 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 203 * 204 * @adev: amdgpu_device pointer 205 * @vmhub: vmhub type 206 * 207 */ 208 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 209 uint32_t vmhub) 210 { 211 return ((vmhub == AMDGPU_MMHUB0(0)) && 212 (!amdgpu_sriov_vf(adev))); 213 } 214 215 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 216 struct amdgpu_device *adev, 217 uint8_t vmid, uint16_t *p_pasid) 218 { 219 uint32_t value; 220 221 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 222 + vmid); 223 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 224 225 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 226 } 227 228 /* 229 * GART 230 * VMID 0 is the physical GPU addresses as used by the kernel. 231 * VMIDs 1-15 are used for userspace clients and are handled 232 * by the amdgpu vm/hsa code. 233 */ 234 235 /** 236 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 237 * 238 * @adev: amdgpu_device pointer 239 * @vmid: vm instance to flush 240 * @vmhub: vmhub type 241 * @flush_type: the flush type 242 * 243 * Flush the TLB for the requested page table. 244 */ 245 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 246 uint32_t vmhub, uint32_t flush_type) 247 { 248 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 249 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 250 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 251 /* Use register 17 for GART */ 252 const unsigned int eng = 17; 253 unsigned char hub_ip = 0; 254 u32 sem, req, ack; 255 unsigned int i; 256 u32 tmp; 257 258 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 259 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 260 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 261 262 /* flush hdp cache */ 263 adev->hdp.funcs->flush_hdp(adev, NULL); 264 265 /* This is necessary for SRIOV as well as for GFXOFF to function 266 * properly under bare metal 267 */ 268 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && 269 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 270 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 271 1 << vmid, GET_INST(GC, 0)); 272 return; 273 } 274 275 /* This path is needed before KIQ/MES/GFXOFF are set up */ 276 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; 277 278 spin_lock(&adev->gmc.invalidate_lock); 279 /* 280 * It may lose gpuvm invalidate acknowldege state across power-gating 281 * off cycle, add semaphore acquire before invalidation and semaphore 282 * release after invalidation to avoid entering power gated state 283 * to WA the Issue 284 */ 285 286 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 287 if (use_semaphore) { 288 for (i = 0; i < adev->usec_timeout; i++) { 289 /* a read return value of 1 means semaphore acuqire */ 290 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); 291 if (tmp & 0x1) 292 break; 293 udelay(1); 294 } 295 296 if (i >= adev->usec_timeout) 297 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 298 } 299 300 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); 301 302 /* 303 * Issue a dummy read to wait for the ACK register to be cleared 304 * to avoid a false ACK due to the new fast GRBM interface. 305 */ 306 if ((vmhub == AMDGPU_GFXHUB(0)) && 307 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) 308 RREG32_RLC_NO_KIQ(req, hub_ip); 309 310 /* Wait for ACK with a delay.*/ 311 for (i = 0; i < adev->usec_timeout; i++) { 312 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); 313 tmp &= 1 << vmid; 314 if (tmp) 315 break; 316 317 udelay(1); 318 } 319 320 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 321 if (use_semaphore) 322 WREG32_RLC_NO_KIQ(sem, 0, hub_ip); 323 324 spin_unlock(&adev->gmc.invalidate_lock); 325 326 if (i >= adev->usec_timeout) 327 dev_err(adev->dev, "Timeout waiting for VM flush hub: %d!\n", 328 vmhub); 329 } 330 331 /** 332 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 333 * 334 * @adev: amdgpu_device pointer 335 * @pasid: pasid to be flush 336 * @flush_type: the flush type 337 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 338 * @inst: is used to select which instance of KIQ to use for the invalidation 339 * 340 * Flush the TLB for the requested pasid. 341 */ 342 static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 343 uint16_t pasid, uint32_t flush_type, 344 bool all_hub, uint32_t inst) 345 { 346 uint16_t queried; 347 int vmid, i; 348 349 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 350 bool valid; 351 352 valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 353 &queried); 354 if (!valid || queried != pasid) 355 continue; 356 357 if (all_hub) { 358 for_each_set_bit(i, adev->vmhubs_mask, 359 AMDGPU_MAX_VMHUBS) 360 gmc_v10_0_flush_gpu_tlb(adev, vmid, i, 361 flush_type); 362 } else { 363 gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 364 flush_type); 365 } 366 } 367 } 368 369 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 370 unsigned int vmid, uint64_t pd_addr) 371 { 372 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 373 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 374 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 375 unsigned int eng = ring->vm_inv_eng; 376 377 /* 378 * It may lose gpuvm invalidate acknowldege state across power-gating 379 * off cycle, add semaphore acquire before invalidation and semaphore 380 * release after invalidation to avoid entering power gated state 381 * to WA the Issue 382 */ 383 384 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 385 if (use_semaphore) 386 /* a read return value of 1 means semaphore acuqire */ 387 amdgpu_ring_emit_reg_wait(ring, 388 hub->vm_inv_eng0_sem + 389 hub->eng_distance * eng, 0x1, 0x1); 390 391 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 392 (hub->ctx_addr_distance * vmid), 393 lower_32_bits(pd_addr)); 394 395 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 396 (hub->ctx_addr_distance * vmid), 397 upper_32_bits(pd_addr)); 398 399 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 400 hub->eng_distance * eng, 401 hub->vm_inv_eng0_ack + 402 hub->eng_distance * eng, 403 req, 1 << vmid); 404 405 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 406 if (use_semaphore) 407 /* 408 * add semaphore release after invalidation, 409 * write with 0 means semaphore release 410 */ 411 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 412 hub->eng_distance * eng, 0); 413 414 return pd_addr; 415 } 416 417 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 418 unsigned int pasid) 419 { 420 struct amdgpu_device *adev = ring->adev; 421 uint32_t reg; 422 423 /* MES fw manages IH_VMID_x_LUT updating */ 424 if (ring->is_mes_queue) 425 return; 426 427 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 428 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 429 else 430 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 431 432 amdgpu_ring_emit_wreg(ring, reg, pasid); 433 } 434 435 /* 436 * PTE format on NAVI 10: 437 * 63:59 reserved 438 * 58 reserved and for sienna_cichlid is used for MALL noalloc 439 * 57 reserved 440 * 56 F 441 * 55 L 442 * 54 reserved 443 * 53:52 SW 444 * 51 T 445 * 50:48 mtype 446 * 47:12 4k physical page base address 447 * 11:7 fragment 448 * 6 write 449 * 5 read 450 * 4 exe 451 * 3 Z 452 * 2 snooped 453 * 1 system 454 * 0 valid 455 * 456 * PDE format on NAVI 10: 457 * 63:59 block fragment size 458 * 58:55 reserved 459 * 54 P 460 * 53:48 reserved 461 * 47:6 physical base address of PD or PTE 462 * 5:3 reserved 463 * 2 C 464 * 1 system 465 * 0 valid 466 */ 467 468 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 469 { 470 switch (flags) { 471 case AMDGPU_VM_MTYPE_DEFAULT: 472 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 473 case AMDGPU_VM_MTYPE_NC: 474 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 475 case AMDGPU_VM_MTYPE_WC: 476 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 477 case AMDGPU_VM_MTYPE_CC: 478 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 479 case AMDGPU_VM_MTYPE_UC: 480 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 481 default: 482 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 483 } 484 } 485 486 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 487 uint64_t *addr, uint64_t *flags) 488 { 489 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 490 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 491 BUG_ON(*addr & 0xFFFF00000000003FULL); 492 493 if (!adev->gmc.translate_further) 494 return; 495 496 if (level == AMDGPU_VM_PDB1) { 497 /* Set the block fragment size */ 498 if (!(*flags & AMDGPU_PDE_PTE)) 499 *flags |= AMDGPU_PDE_BFS(0x9); 500 501 } else if (level == AMDGPU_VM_PDB0) { 502 if (*flags & AMDGPU_PDE_PTE) 503 *flags &= ~AMDGPU_PDE_PTE; 504 else 505 *flags |= AMDGPU_PTE_TF; 506 } 507 } 508 509 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 510 struct amdgpu_bo_va_mapping *mapping, 511 uint64_t *flags) 512 { 513 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 514 515 *flags &= ~AMDGPU_PTE_EXECUTABLE; 516 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 517 518 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 519 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 520 521 *flags &= ~AMDGPU_PTE_NOALLOC; 522 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 523 524 if (mapping->flags & AMDGPU_PTE_PRT) { 525 *flags |= AMDGPU_PTE_PRT; 526 *flags |= AMDGPU_PTE_SNOOPED; 527 *flags |= AMDGPU_PTE_LOG; 528 *flags |= AMDGPU_PTE_SYSTEM; 529 *flags &= ~AMDGPU_PTE_VALID; 530 } 531 532 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 533 AMDGPU_GEM_CREATE_EXT_COHERENT | 534 AMDGPU_GEM_CREATE_UNCACHED)) 535 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 536 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 537 } 538 539 static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 540 { 541 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 542 unsigned int size; 543 544 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 545 size = AMDGPU_VBIOS_VGA_ALLOCATION; 546 } else { 547 u32 viewport; 548 u32 pitch; 549 550 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 551 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 552 size = (REG_GET_FIELD(viewport, 553 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 554 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 555 4); 556 } 557 558 return size; 559 } 560 561 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 562 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 563 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 564 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 565 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 566 .map_mtype = gmc_v10_0_map_mtype, 567 .get_vm_pde = gmc_v10_0_get_vm_pde, 568 .get_vm_pte = gmc_v10_0_get_vm_pte, 569 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 570 }; 571 572 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 573 { 574 if (adev->gmc.gmc_funcs == NULL) 575 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 576 } 577 578 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 579 { 580 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 581 case IP_VERSION(8, 7, 0): 582 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 583 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 584 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 585 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 586 adev->umc.retire_unit = 1; 587 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 588 adev->umc.ras = &umc_v8_7_ras; 589 break; 590 default: 591 break; 592 } 593 } 594 595 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 596 { 597 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 598 case IP_VERSION(2, 3, 0): 599 case IP_VERSION(2, 4, 0): 600 case IP_VERSION(2, 4, 1): 601 adev->mmhub.funcs = &mmhub_v2_3_funcs; 602 break; 603 default: 604 adev->mmhub.funcs = &mmhub_v2_0_funcs; 605 break; 606 } 607 } 608 609 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 610 { 611 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 612 case IP_VERSION(10, 3, 0): 613 case IP_VERSION(10, 3, 2): 614 case IP_VERSION(10, 3, 1): 615 case IP_VERSION(10, 3, 4): 616 case IP_VERSION(10, 3, 5): 617 case IP_VERSION(10, 3, 6): 618 case IP_VERSION(10, 3, 3): 619 case IP_VERSION(10, 3, 7): 620 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 621 break; 622 default: 623 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 624 break; 625 } 626 } 627 628 629 static int gmc_v10_0_early_init(void *handle) 630 { 631 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 632 633 gmc_v10_0_set_mmhub_funcs(adev); 634 gmc_v10_0_set_gfxhub_funcs(adev); 635 gmc_v10_0_set_gmc_funcs(adev); 636 gmc_v10_0_set_irq_funcs(adev); 637 gmc_v10_0_set_umc_funcs(adev); 638 639 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 640 adev->gmc.shared_aperture_end = 641 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 642 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 643 adev->gmc.private_aperture_end = 644 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 645 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 646 647 return 0; 648 } 649 650 static int gmc_v10_0_late_init(void *handle) 651 { 652 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 653 int r; 654 655 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 656 if (r) 657 return r; 658 659 r = amdgpu_gmc_ras_late_init(adev); 660 if (r) 661 return r; 662 663 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 664 } 665 666 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 667 struct amdgpu_gmc *mc) 668 { 669 u64 base = 0; 670 671 base = adev->gfxhub.funcs->get_fb_location(adev); 672 673 /* add the xgmi offset of the physical node */ 674 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 675 676 amdgpu_gmc_set_agp_default(adev, mc); 677 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 678 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 679 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 680 amdgpu_gmc_agp_location(adev, mc); 681 682 /* base offset of vram pages */ 683 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 684 685 /* add the xgmi offset of the physical node */ 686 adev->vm_manager.vram_base_offset += 687 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 688 } 689 690 /** 691 * gmc_v10_0_mc_init - initialize the memory controller driver params 692 * 693 * @adev: amdgpu_device pointer 694 * 695 * Look up the amount of vram, vram width, and decide how to place 696 * vram and gart within the GPU's physical address space. 697 * Returns 0 for success. 698 */ 699 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 700 { 701 int r; 702 703 /* size in MB on si */ 704 adev->gmc.mc_vram_size = 705 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 706 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 707 708 if (!(adev->flags & AMD_IS_APU)) { 709 r = amdgpu_device_resize_fb_bar(adev); 710 if (r) 711 return r; 712 } 713 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 714 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 715 716 #ifdef CONFIG_X86_64 717 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 718 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 719 adev->gmc.aper_size = adev->gmc.real_vram_size; 720 } 721 #endif 722 723 adev->gmc.visible_vram_size = adev->gmc.aper_size; 724 725 /* set the gart size */ 726 if (amdgpu_gart_size == -1) { 727 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 728 default: 729 adev->gmc.gart_size = 512ULL << 20; 730 break; 731 case IP_VERSION(10, 3, 1): /* DCE SG support */ 732 case IP_VERSION(10, 3, 3): /* DCE SG support */ 733 case IP_VERSION(10, 3, 6): /* DCE SG support */ 734 case IP_VERSION(10, 3, 7): /* DCE SG support */ 735 adev->gmc.gart_size = 1024ULL << 20; 736 break; 737 } 738 } else { 739 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 740 } 741 742 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 743 744 return 0; 745 } 746 747 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 748 { 749 int r; 750 751 if (adev->gart.bo) { 752 WARN(1, "NAVI10 PCIE GART already initialized\n"); 753 return 0; 754 } 755 756 /* Initialize common gart structure */ 757 r = amdgpu_gart_init(adev); 758 if (r) 759 return r; 760 761 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 762 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 763 AMDGPU_PTE_EXECUTABLE; 764 765 return amdgpu_gart_table_vram_alloc(adev); 766 } 767 768 static int gmc_v10_0_sw_init(void *handle) 769 { 770 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 771 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 772 773 adev->gfxhub.funcs->init(adev); 774 775 adev->mmhub.funcs->init(adev); 776 777 spin_lock_init(&adev->gmc.invalidate_lock); 778 779 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 780 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 781 adev->gmc.vram_width = 64; 782 } else if (amdgpu_emu_mode == 1) { 783 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 784 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 785 } else { 786 r = amdgpu_atomfirmware_get_vram_info(adev, 787 &vram_width, &vram_type, &vram_vendor); 788 adev->gmc.vram_width = vram_width; 789 790 adev->gmc.vram_type = vram_type; 791 adev->gmc.vram_vendor = vram_vendor; 792 } 793 794 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 795 case IP_VERSION(10, 3, 0): 796 adev->gmc.mall_size = 128 * 1024 * 1024; 797 break; 798 case IP_VERSION(10, 3, 2): 799 adev->gmc.mall_size = 96 * 1024 * 1024; 800 break; 801 case IP_VERSION(10, 3, 4): 802 adev->gmc.mall_size = 32 * 1024 * 1024; 803 break; 804 case IP_VERSION(10, 3, 5): 805 adev->gmc.mall_size = 16 * 1024 * 1024; 806 break; 807 default: 808 adev->gmc.mall_size = 0; 809 break; 810 } 811 812 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 813 case IP_VERSION(10, 1, 10): 814 case IP_VERSION(10, 1, 1): 815 case IP_VERSION(10, 1, 2): 816 case IP_VERSION(10, 1, 3): 817 case IP_VERSION(10, 1, 4): 818 case IP_VERSION(10, 3, 0): 819 case IP_VERSION(10, 3, 2): 820 case IP_VERSION(10, 3, 1): 821 case IP_VERSION(10, 3, 4): 822 case IP_VERSION(10, 3, 5): 823 case IP_VERSION(10, 3, 6): 824 case IP_VERSION(10, 3, 3): 825 case IP_VERSION(10, 3, 7): 826 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 827 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 828 /* 829 * To fulfill 4-level page support, 830 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 831 * block size 512 (9bit) 832 */ 833 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 834 break; 835 default: 836 break; 837 } 838 839 /* This interrupt is VMC page fault.*/ 840 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 841 VMC_1_0__SRCID__VM_FAULT, 842 &adev->gmc.vm_fault); 843 844 if (r) 845 return r; 846 847 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 848 UTCL2_1_0__SRCID__FAULT, 849 &adev->gmc.vm_fault); 850 if (r) 851 return r; 852 853 if (!amdgpu_sriov_vf(adev)) { 854 /* interrupt sent to DF. */ 855 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 856 &adev->gmc.ecc_irq); 857 if (r) 858 return r; 859 } 860 861 /* 862 * Set the internal MC address mask This is the max address of the GPU's 863 * internal address space. 864 */ 865 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 866 867 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 868 if (r) { 869 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 870 return r; 871 } 872 873 adev->need_swiotlb = drm_need_swiotlb(44); 874 875 r = gmc_v10_0_mc_init(adev); 876 if (r) 877 return r; 878 879 amdgpu_gmc_get_vbios_allocations(adev); 880 881 /* Memory manager */ 882 r = amdgpu_bo_init(adev); 883 if (r) 884 return r; 885 886 r = gmc_v10_0_gart_init(adev); 887 if (r) 888 return r; 889 890 /* 891 * number of VMs 892 * VMID 0 is reserved for System 893 * amdgpu graphics/compute will use VMIDs 1-7 894 * amdkfd will use VMIDs 8-15 895 */ 896 adev->vm_manager.first_kfd_vmid = 8; 897 898 amdgpu_vm_manager_init(adev); 899 900 r = amdgpu_gmc_ras_sw_init(adev); 901 if (r) 902 return r; 903 904 return 0; 905 } 906 907 /** 908 * gmc_v10_0_gart_fini - vm fini callback 909 * 910 * @adev: amdgpu_device pointer 911 * 912 * Tears down the driver GART/VM setup (CIK). 913 */ 914 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 915 { 916 amdgpu_gart_table_vram_free(adev); 917 } 918 919 static int gmc_v10_0_sw_fini(void *handle) 920 { 921 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 922 923 amdgpu_vm_manager_fini(adev); 924 gmc_v10_0_gart_fini(adev); 925 amdgpu_gem_force_release(adev); 926 amdgpu_bo_fini(adev); 927 928 return 0; 929 } 930 931 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 932 { 933 } 934 935 /** 936 * gmc_v10_0_gart_enable - gart enable 937 * 938 * @adev: amdgpu_device pointer 939 */ 940 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 941 { 942 int r; 943 bool value; 944 945 if (adev->gart.bo == NULL) { 946 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 947 return -EINVAL; 948 } 949 950 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 951 952 if (!adev->in_s0ix) { 953 r = adev->gfxhub.funcs->gart_enable(adev); 954 if (r) 955 return r; 956 } 957 958 r = adev->mmhub.funcs->gart_enable(adev); 959 if (r) 960 return r; 961 962 adev->hdp.funcs->init_registers(adev); 963 964 /* Flush HDP after it is initialized */ 965 adev->hdp.funcs->flush_hdp(adev, NULL); 966 967 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 968 false : true; 969 970 if (!adev->in_s0ix) 971 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 972 adev->mmhub.funcs->set_fault_enable_default(adev, value); 973 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 974 if (!adev->in_s0ix) 975 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 976 977 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 978 (unsigned int)(adev->gmc.gart_size >> 20), 979 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 980 981 return 0; 982 } 983 984 static int gmc_v10_0_hw_init(void *handle) 985 { 986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 987 int r; 988 989 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; 990 991 /* The sequence of these two function calls matters.*/ 992 gmc_v10_0_init_golden_registers(adev); 993 994 /* 995 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 996 * register setup within GMC, or else system hang when harvesting SA. 997 */ 998 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 999 adev->gfxhub.funcs->utcl2_harvest(adev); 1000 1001 r = gmc_v10_0_gart_enable(adev); 1002 if (r) 1003 return r; 1004 1005 if (amdgpu_emu_mode == 1) { 1006 r = amdgpu_gmc_vram_checking(adev); 1007 if (r) 1008 return r; 1009 } 1010 1011 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1012 adev->umc.funcs->init_registers(adev); 1013 1014 return 0; 1015 } 1016 1017 /** 1018 * gmc_v10_0_gart_disable - gart disable 1019 * 1020 * @adev: amdgpu_device pointer 1021 * 1022 * This disables all VM page table. 1023 */ 1024 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1025 { 1026 if (!adev->in_s0ix) 1027 adev->gfxhub.funcs->gart_disable(adev); 1028 adev->mmhub.funcs->gart_disable(adev); 1029 } 1030 1031 static int gmc_v10_0_hw_fini(void *handle) 1032 { 1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1034 1035 gmc_v10_0_gart_disable(adev); 1036 1037 if (amdgpu_sriov_vf(adev)) { 1038 /* full access mode, so don't touch any GMC register */ 1039 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1040 return 0; 1041 } 1042 1043 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1044 1045 if (adev->gmc.ecc_irq.funcs && 1046 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1047 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1048 1049 return 0; 1050 } 1051 1052 static int gmc_v10_0_suspend(void *handle) 1053 { 1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1055 1056 gmc_v10_0_hw_fini(adev); 1057 1058 return 0; 1059 } 1060 1061 static int gmc_v10_0_resume(void *handle) 1062 { 1063 int r; 1064 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1065 1066 r = gmc_v10_0_hw_init(adev); 1067 if (r) 1068 return r; 1069 1070 amdgpu_vmid_reset_all(adev); 1071 1072 return 0; 1073 } 1074 1075 static bool gmc_v10_0_is_idle(void *handle) 1076 { 1077 /* MC is always ready in GMC v10.*/ 1078 return true; 1079 } 1080 1081 static int gmc_v10_0_wait_for_idle(void *handle) 1082 { 1083 /* There is no need to wait for MC idle in GMC v10.*/ 1084 return 0; 1085 } 1086 1087 static int gmc_v10_0_soft_reset(void *handle) 1088 { 1089 return 0; 1090 } 1091 1092 static int gmc_v10_0_set_clockgating_state(void *handle, 1093 enum amd_clockgating_state state) 1094 { 1095 int r; 1096 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1097 1098 /* 1099 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1100 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1101 * seen any issue on the DF 3.0.2 series platform. 1102 */ 1103 if (adev->in_s0ix && 1104 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) { 1105 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1106 return 0; 1107 } 1108 1109 r = adev->mmhub.funcs->set_clockgating(adev, state); 1110 if (r) 1111 return r; 1112 1113 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1114 return athub_v2_1_set_clockgating(adev, state); 1115 else 1116 return athub_v2_0_set_clockgating(adev, state); 1117 } 1118 1119 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) 1120 { 1121 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1122 1123 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || 1124 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) 1125 return; 1126 1127 adev->mmhub.funcs->get_clockgating(adev, flags); 1128 1129 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1130 athub_v2_1_get_clockgating(adev, flags); 1131 else 1132 athub_v2_0_get_clockgating(adev, flags); 1133 } 1134 1135 static int gmc_v10_0_set_powergating_state(void *handle, 1136 enum amd_powergating_state state) 1137 { 1138 return 0; 1139 } 1140 1141 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1142 .name = "gmc_v10_0", 1143 .early_init = gmc_v10_0_early_init, 1144 .late_init = gmc_v10_0_late_init, 1145 .sw_init = gmc_v10_0_sw_init, 1146 .sw_fini = gmc_v10_0_sw_fini, 1147 .hw_init = gmc_v10_0_hw_init, 1148 .hw_fini = gmc_v10_0_hw_fini, 1149 .suspend = gmc_v10_0_suspend, 1150 .resume = gmc_v10_0_resume, 1151 .is_idle = gmc_v10_0_is_idle, 1152 .wait_for_idle = gmc_v10_0_wait_for_idle, 1153 .soft_reset = gmc_v10_0_soft_reset, 1154 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1155 .set_powergating_state = gmc_v10_0_set_powergating_state, 1156 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1157 }; 1158 1159 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = { 1160 .type = AMD_IP_BLOCK_TYPE_GMC, 1161 .major = 10, 1162 .minor = 0, 1163 .rev = 0, 1164 .funcs = &gmc_v10_0_ip_funcs, 1165 }; 1166