1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 #include "amdgpu_reset.h" 55 56 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 57 struct amdgpu_irq_src *src, 58 unsigned int type, 59 enum amdgpu_interrupt_state state) 60 { 61 return 0; 62 } 63 64 static int 65 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 66 struct amdgpu_irq_src *src, unsigned int type, 67 enum amdgpu_interrupt_state state) 68 { 69 switch (state) { 70 case AMDGPU_IRQ_STATE_DISABLE: 71 /* MM HUB */ 72 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 73 /* GFX HUB */ 74 /* This works because this interrupt is only 75 * enabled at init/resume and disabled in 76 * fini/suspend, so the overall state doesn't 77 * change over the course of suspend/resume. 78 */ 79 if (!adev->in_s0ix) 80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 81 break; 82 case AMDGPU_IRQ_STATE_ENABLE: 83 /* MM HUB */ 84 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 85 /* GFX HUB */ 86 /* This works because this interrupt is only 87 * enabled at init/resume and disabled in 88 * fini/suspend, so the overall state doesn't 89 * change over the course of suspend/resume. 90 */ 91 if (!adev->in_s0ix) 92 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 93 break; 94 default: 95 break; 96 } 97 98 return 0; 99 } 100 101 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 102 struct amdgpu_irq_src *source, 103 struct amdgpu_iv_entry *entry) 104 { 105 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? 106 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 107 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 108 bool retry_fault = !!(entry->src_data[1] & 0x80); 109 bool write_fault = !!(entry->src_data[1] & 0x20); 110 struct amdgpu_task_info task_info; 111 uint32_t status = 0; 112 u64 addr; 113 114 addr = (u64)entry->src_data[0] << 12; 115 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 116 117 if (retry_fault) { 118 /* Returning 1 here also prevents sending the IV to the KFD */ 119 120 /* Process it onyl if it's the first fault for this address */ 121 if (entry->ih != &adev->irq.ih_soft && 122 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 123 entry->timestamp)) 124 return 1; 125 126 /* Delegate it to a different ring if the hardware hasn't 127 * already done it. 128 */ 129 if (entry->ih == &adev->irq.ih) { 130 amdgpu_irq_delegate(adev, entry, 8); 131 return 1; 132 } 133 134 /* Try to handle the recoverable page faults by filling page 135 * tables 136 */ 137 if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, write_fault)) 138 return 1; 139 } 140 141 if (!amdgpu_sriov_vf(adev)) { 142 /* 143 * Issue a dummy read to wait for the status register to 144 * be updated to avoid reading an incorrect value due to 145 * the new fast GRBM interface. 146 */ 147 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 148 (amdgpu_ip_version(adev, GC_HWIP, 0) < 149 IP_VERSION(10, 3, 0))) 150 RREG32(hub->vm_l2_pro_fault_status); 151 152 status = RREG32(hub->vm_l2_pro_fault_status); 153 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 154 } 155 156 if (!printk_ratelimit()) 157 return 0; 158 159 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 160 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 161 162 dev_err(adev->dev, 163 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 164 entry->vmid_src ? "mmhub" : "gfxhub", 165 entry->src_id, entry->ring_id, entry->vmid, 166 entry->pasid, task_info.process_name, task_info.tgid, 167 task_info.task_name, task_info.pid); 168 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 169 addr, entry->client_id, 170 soc15_ih_clientid_name[entry->client_id]); 171 172 if (!amdgpu_sriov_vf(adev)) 173 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 174 status); 175 176 return 0; 177 } 178 179 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 180 .set = gmc_v10_0_vm_fault_interrupt_state, 181 .process = gmc_v10_0_process_interrupt, 182 }; 183 184 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 185 .set = gmc_v10_0_ecc_interrupt_state, 186 .process = amdgpu_umc_process_ecc_irq, 187 }; 188 189 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 190 { 191 adev->gmc.vm_fault.num_types = 1; 192 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 193 194 if (!amdgpu_sriov_vf(adev)) { 195 adev->gmc.ecc_irq.num_types = 1; 196 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 197 } 198 } 199 200 /** 201 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 202 * 203 * @adev: amdgpu_device pointer 204 * @vmhub: vmhub type 205 * 206 */ 207 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 208 uint32_t vmhub) 209 { 210 return ((vmhub == AMDGPU_MMHUB0(0)) && 211 (!amdgpu_sriov_vf(adev))); 212 } 213 214 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 215 struct amdgpu_device *adev, 216 uint8_t vmid, uint16_t *p_pasid) 217 { 218 uint32_t value; 219 220 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 221 + vmid); 222 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 223 224 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 225 } 226 227 /* 228 * GART 229 * VMID 0 is the physical GPU addresses as used by the kernel. 230 * VMIDs 1-15 are used for userspace clients and are handled 231 * by the amdgpu vm/hsa code. 232 */ 233 234 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 235 unsigned int vmhub, uint32_t flush_type) 236 { 237 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 238 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 239 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 240 u32 tmp; 241 /* Use register 17 for GART */ 242 const unsigned int eng = 17; 243 unsigned int i; 244 unsigned char hub_ip = 0; 245 246 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? 247 GC_HWIP : MMHUB_HWIP; 248 249 spin_lock(&adev->gmc.invalidate_lock); 250 /* 251 * It may lose gpuvm invalidate acknowldege state across power-gating 252 * off cycle, add semaphore acquire before invalidation and semaphore 253 * release after invalidation to avoid entering power gated state 254 * to WA the Issue 255 */ 256 257 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 258 if (use_semaphore) { 259 for (i = 0; i < adev->usec_timeout; i++) { 260 /* a read return value of 1 means semaphore acuqire */ 261 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 262 hub->eng_distance * eng, hub_ip); 263 264 if (tmp & 0x1) 265 break; 266 udelay(1); 267 } 268 269 if (i >= adev->usec_timeout) 270 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 271 } 272 273 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 274 hub->eng_distance * eng, 275 inv_req, hub_ip); 276 277 /* 278 * Issue a dummy read to wait for the ACK register to be cleared 279 * to avoid a false ACK due to the new fast GRBM interface. 280 */ 281 if ((vmhub == AMDGPU_GFXHUB(0)) && 282 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) 283 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req + 284 hub->eng_distance * eng, hub_ip); 285 286 /* Wait for ACK with a delay.*/ 287 for (i = 0; i < adev->usec_timeout; i++) { 288 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack + 289 hub->eng_distance * eng, hub_ip); 290 291 tmp &= 1 << vmid; 292 if (tmp) 293 break; 294 295 udelay(1); 296 } 297 298 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 299 if (use_semaphore) 300 /* 301 * add semaphore release after invalidation, 302 * write with 0 means semaphore release 303 */ 304 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem + 305 hub->eng_distance * eng, 0, hub_ip); 306 307 spin_unlock(&adev->gmc.invalidate_lock); 308 309 if (i < adev->usec_timeout) 310 return; 311 312 DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub); 313 } 314 315 /** 316 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 317 * 318 * @adev: amdgpu_device pointer 319 * @vmid: vm instance to flush 320 * @vmhub: vmhub type 321 * @flush_type: the flush type 322 * 323 * Flush the TLB for the requested page table. 324 */ 325 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 326 uint32_t vmhub, uint32_t flush_type) 327 { 328 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 329 struct dma_fence *fence; 330 struct amdgpu_job *job; 331 332 int r; 333 334 /* flush hdp cache */ 335 adev->hdp.funcs->flush_hdp(adev, NULL); 336 337 /* For SRIOV run time, driver shouldn't access the register through MMIO 338 * Directly use kiq to do the vm invalidation instead 339 */ 340 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && 341 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && 342 down_read_trylock(&adev->reset_domain->sem)) { 343 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 344 const unsigned int eng = 17; 345 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 346 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 347 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 348 349 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 350 1 << vmid); 351 352 up_read(&adev->reset_domain->sem); 353 return; 354 } 355 356 mutex_lock(&adev->mman.gtt_window_lock); 357 358 if (vmhub == AMDGPU_MMHUB0(0)) { 359 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB0(0), 0); 360 mutex_unlock(&adev->mman.gtt_window_lock); 361 return; 362 } 363 364 BUG_ON(vmhub != AMDGPU_GFXHUB(0)); 365 366 if (!adev->mman.buffer_funcs_enabled || 367 !adev->ib_pool_ready || 368 amdgpu_in_reset(adev) || 369 ring->sched.ready == false) { 370 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB(0), 0); 371 mutex_unlock(&adev->mman.gtt_window_lock); 372 return; 373 } 374 375 /* The SDMA on Navi has a bug which can theoretically result in memory 376 * corruption if an invalidation happens at the same time as an VA 377 * translation. Avoid this by doing the invalidation from the SDMA 378 * itself. 379 */ 380 r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr, 381 AMDGPU_FENCE_OWNER_UNDEFINED, 382 16 * 4, AMDGPU_IB_POOL_IMMEDIATE, 383 &job); 384 if (r) 385 goto error_alloc; 386 387 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo); 388 job->vm_needs_flush = true; 389 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop; 390 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 391 fence = amdgpu_job_submit(job); 392 393 mutex_unlock(&adev->mman.gtt_window_lock); 394 395 dma_fence_wait(fence, false); 396 dma_fence_put(fence); 397 398 return; 399 400 error_alloc: 401 mutex_unlock(&adev->mman.gtt_window_lock); 402 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r); 403 } 404 405 /** 406 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 407 * 408 * @adev: amdgpu_device pointer 409 * @pasid: pasid to be flush 410 * @flush_type: the flush type 411 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 412 * @inst: is used to select which instance of KIQ to use for the invalidation 413 * 414 * Flush the TLB for the requested pasid. 415 */ 416 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 417 uint16_t pasid, uint32_t flush_type, 418 bool all_hub, uint32_t inst) 419 { 420 int vmid, i; 421 signed long r; 422 uint32_t seq; 423 uint16_t queried_pasid; 424 bool ret; 425 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; 426 struct amdgpu_ring *ring = &adev->gfx.kiq[0].ring; 427 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 428 429 if (amdgpu_emu_mode == 0 && ring->sched.ready) { 430 spin_lock(&adev->gfx.kiq[0].ring_lock); 431 /* 2 dwords flush + 8 dwords fence */ 432 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8); 433 kiq->pmf->kiq_invalidate_tlbs(ring, 434 pasid, flush_type, all_hub); 435 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 436 if (r) { 437 amdgpu_ring_undo(ring); 438 spin_unlock(&adev->gfx.kiq[0].ring_lock); 439 return -ETIME; 440 } 441 442 amdgpu_ring_commit(ring); 443 spin_unlock(&adev->gfx.kiq[0].ring_lock); 444 r = amdgpu_fence_wait_polling(ring, seq, usec_timeout); 445 if (r < 1) { 446 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r); 447 return -ETIME; 448 } 449 450 return 0; 451 } 452 453 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 454 455 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 456 &queried_pasid); 457 if (ret && queried_pasid == pasid) { 458 if (all_hub) { 459 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 460 gmc_v10_0_flush_gpu_tlb(adev, vmid, 461 i, flush_type); 462 } else { 463 gmc_v10_0_flush_gpu_tlb(adev, vmid, 464 AMDGPU_GFXHUB(0), flush_type); 465 } 466 if (!adev->enable_mes) 467 break; 468 } 469 } 470 471 return 0; 472 } 473 474 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 475 unsigned int vmid, uint64_t pd_addr) 476 { 477 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 478 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 479 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 480 unsigned int eng = ring->vm_inv_eng; 481 482 /* 483 * It may lose gpuvm invalidate acknowldege state across power-gating 484 * off cycle, add semaphore acquire before invalidation and semaphore 485 * release after invalidation to avoid entering power gated state 486 * to WA the Issue 487 */ 488 489 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 490 if (use_semaphore) 491 /* a read return value of 1 means semaphore acuqire */ 492 amdgpu_ring_emit_reg_wait(ring, 493 hub->vm_inv_eng0_sem + 494 hub->eng_distance * eng, 0x1, 0x1); 495 496 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 497 (hub->ctx_addr_distance * vmid), 498 lower_32_bits(pd_addr)); 499 500 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 501 (hub->ctx_addr_distance * vmid), 502 upper_32_bits(pd_addr)); 503 504 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 505 hub->eng_distance * eng, 506 hub->vm_inv_eng0_ack + 507 hub->eng_distance * eng, 508 req, 1 << vmid); 509 510 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 511 if (use_semaphore) 512 /* 513 * add semaphore release after invalidation, 514 * write with 0 means semaphore release 515 */ 516 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 517 hub->eng_distance * eng, 0); 518 519 return pd_addr; 520 } 521 522 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 523 unsigned int pasid) 524 { 525 struct amdgpu_device *adev = ring->adev; 526 uint32_t reg; 527 528 /* MES fw manages IH_VMID_x_LUT updating */ 529 if (ring->is_mes_queue) 530 return; 531 532 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 533 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 534 else 535 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 536 537 amdgpu_ring_emit_wreg(ring, reg, pasid); 538 } 539 540 /* 541 * PTE format on NAVI 10: 542 * 63:59 reserved 543 * 58 reserved and for sienna_cichlid is used for MALL noalloc 544 * 57 reserved 545 * 56 F 546 * 55 L 547 * 54 reserved 548 * 53:52 SW 549 * 51 T 550 * 50:48 mtype 551 * 47:12 4k physical page base address 552 * 11:7 fragment 553 * 6 write 554 * 5 read 555 * 4 exe 556 * 3 Z 557 * 2 snooped 558 * 1 system 559 * 0 valid 560 * 561 * PDE format on NAVI 10: 562 * 63:59 block fragment size 563 * 58:55 reserved 564 * 54 P 565 * 53:48 reserved 566 * 47:6 physical base address of PD or PTE 567 * 5:3 reserved 568 * 2 C 569 * 1 system 570 * 0 valid 571 */ 572 573 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 574 { 575 switch (flags) { 576 case AMDGPU_VM_MTYPE_DEFAULT: 577 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 578 case AMDGPU_VM_MTYPE_NC: 579 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 580 case AMDGPU_VM_MTYPE_WC: 581 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 582 case AMDGPU_VM_MTYPE_CC: 583 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 584 case AMDGPU_VM_MTYPE_UC: 585 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 586 default: 587 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 588 } 589 } 590 591 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 592 uint64_t *addr, uint64_t *flags) 593 { 594 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 595 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 596 BUG_ON(*addr & 0xFFFF00000000003FULL); 597 598 if (!adev->gmc.translate_further) 599 return; 600 601 if (level == AMDGPU_VM_PDB1) { 602 /* Set the block fragment size */ 603 if (!(*flags & AMDGPU_PDE_PTE)) 604 *flags |= AMDGPU_PDE_BFS(0x9); 605 606 } else if (level == AMDGPU_VM_PDB0) { 607 if (*flags & AMDGPU_PDE_PTE) 608 *flags &= ~AMDGPU_PDE_PTE; 609 else 610 *flags |= AMDGPU_PTE_TF; 611 } 612 } 613 614 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 615 struct amdgpu_bo_va_mapping *mapping, 616 uint64_t *flags) 617 { 618 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 619 620 *flags &= ~AMDGPU_PTE_EXECUTABLE; 621 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 622 623 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 624 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 625 626 *flags &= ~AMDGPU_PTE_NOALLOC; 627 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 628 629 if (mapping->flags & AMDGPU_PTE_PRT) { 630 *flags |= AMDGPU_PTE_PRT; 631 *flags |= AMDGPU_PTE_SNOOPED; 632 *flags |= AMDGPU_PTE_LOG; 633 *flags |= AMDGPU_PTE_SYSTEM; 634 *flags &= ~AMDGPU_PTE_VALID; 635 } 636 637 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 638 AMDGPU_GEM_CREATE_EXT_COHERENT | 639 AMDGPU_GEM_CREATE_UNCACHED)) 640 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 641 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 642 } 643 644 static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 645 { 646 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 647 unsigned int size; 648 649 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 650 size = AMDGPU_VBIOS_VGA_ALLOCATION; 651 } else { 652 u32 viewport; 653 u32 pitch; 654 655 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 656 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 657 size = (REG_GET_FIELD(viewport, 658 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 659 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 660 4); 661 } 662 663 return size; 664 } 665 666 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 667 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 668 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 669 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 670 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 671 .map_mtype = gmc_v10_0_map_mtype, 672 .get_vm_pde = gmc_v10_0_get_vm_pde, 673 .get_vm_pte = gmc_v10_0_get_vm_pte, 674 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 675 }; 676 677 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 678 { 679 if (adev->gmc.gmc_funcs == NULL) 680 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 681 } 682 683 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 684 { 685 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 686 case IP_VERSION(8, 7, 0): 687 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 688 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 689 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 690 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 691 adev->umc.retire_unit = 1; 692 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 693 adev->umc.ras = &umc_v8_7_ras; 694 break; 695 default: 696 break; 697 } 698 } 699 700 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 701 { 702 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 703 case IP_VERSION(2, 3, 0): 704 case IP_VERSION(2, 4, 0): 705 case IP_VERSION(2, 4, 1): 706 adev->mmhub.funcs = &mmhub_v2_3_funcs; 707 break; 708 default: 709 adev->mmhub.funcs = &mmhub_v2_0_funcs; 710 break; 711 } 712 } 713 714 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 715 { 716 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 717 case IP_VERSION(10, 3, 0): 718 case IP_VERSION(10, 3, 2): 719 case IP_VERSION(10, 3, 1): 720 case IP_VERSION(10, 3, 4): 721 case IP_VERSION(10, 3, 5): 722 case IP_VERSION(10, 3, 6): 723 case IP_VERSION(10, 3, 3): 724 case IP_VERSION(10, 3, 7): 725 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 726 break; 727 default: 728 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 729 break; 730 } 731 } 732 733 734 static int gmc_v10_0_early_init(void *handle) 735 { 736 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 737 738 gmc_v10_0_set_mmhub_funcs(adev); 739 gmc_v10_0_set_gfxhub_funcs(adev); 740 gmc_v10_0_set_gmc_funcs(adev); 741 gmc_v10_0_set_irq_funcs(adev); 742 gmc_v10_0_set_umc_funcs(adev); 743 744 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 745 adev->gmc.shared_aperture_end = 746 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 747 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 748 adev->gmc.private_aperture_end = 749 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 750 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 751 752 return 0; 753 } 754 755 static int gmc_v10_0_late_init(void *handle) 756 { 757 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 758 int r; 759 760 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 761 if (r) 762 return r; 763 764 r = amdgpu_gmc_ras_late_init(adev); 765 if (r) 766 return r; 767 768 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 769 } 770 771 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 772 struct amdgpu_gmc *mc) 773 { 774 u64 base = 0; 775 776 base = adev->gfxhub.funcs->get_fb_location(adev); 777 778 /* add the xgmi offset of the physical node */ 779 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 780 781 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 782 amdgpu_gmc_gart_location(adev, mc); 783 amdgpu_gmc_agp_location(adev, mc); 784 785 /* base offset of vram pages */ 786 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 787 788 /* add the xgmi offset of the physical node */ 789 adev->vm_manager.vram_base_offset += 790 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 791 } 792 793 /** 794 * gmc_v10_0_mc_init - initialize the memory controller driver params 795 * 796 * @adev: amdgpu_device pointer 797 * 798 * Look up the amount of vram, vram width, and decide how to place 799 * vram and gart within the GPU's physical address space. 800 * Returns 0 for success. 801 */ 802 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 803 { 804 int r; 805 806 /* size in MB on si */ 807 adev->gmc.mc_vram_size = 808 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 809 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 810 811 if (!(adev->flags & AMD_IS_APU)) { 812 r = amdgpu_device_resize_fb_bar(adev); 813 if (r) 814 return r; 815 } 816 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 817 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 818 819 #ifdef CONFIG_X86_64 820 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 821 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 822 adev->gmc.aper_size = adev->gmc.real_vram_size; 823 } 824 #endif 825 826 adev->gmc.visible_vram_size = adev->gmc.aper_size; 827 828 /* set the gart size */ 829 if (amdgpu_gart_size == -1) { 830 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 831 default: 832 adev->gmc.gart_size = 512ULL << 20; 833 break; 834 case IP_VERSION(10, 3, 1): /* DCE SG support */ 835 case IP_VERSION(10, 3, 3): /* DCE SG support */ 836 case IP_VERSION(10, 3, 6): /* DCE SG support */ 837 case IP_VERSION(10, 3, 7): /* DCE SG support */ 838 adev->gmc.gart_size = 1024ULL << 20; 839 break; 840 } 841 } else { 842 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 843 } 844 845 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 846 847 return 0; 848 } 849 850 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 851 { 852 int r; 853 854 if (adev->gart.bo) { 855 WARN(1, "NAVI10 PCIE GART already initialized\n"); 856 return 0; 857 } 858 859 /* Initialize common gart structure */ 860 r = amdgpu_gart_init(adev); 861 if (r) 862 return r; 863 864 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 865 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 866 AMDGPU_PTE_EXECUTABLE; 867 868 return amdgpu_gart_table_vram_alloc(adev); 869 } 870 871 static int gmc_v10_0_sw_init(void *handle) 872 { 873 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 875 876 adev->gfxhub.funcs->init(adev); 877 878 adev->mmhub.funcs->init(adev); 879 880 spin_lock_init(&adev->gmc.invalidate_lock); 881 882 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 883 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 884 adev->gmc.vram_width = 64; 885 } else if (amdgpu_emu_mode == 1) { 886 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 887 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 888 } else { 889 r = amdgpu_atomfirmware_get_vram_info(adev, 890 &vram_width, &vram_type, &vram_vendor); 891 adev->gmc.vram_width = vram_width; 892 893 adev->gmc.vram_type = vram_type; 894 adev->gmc.vram_vendor = vram_vendor; 895 } 896 897 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 898 case IP_VERSION(10, 3, 0): 899 adev->gmc.mall_size = 128 * 1024 * 1024; 900 break; 901 case IP_VERSION(10, 3, 2): 902 adev->gmc.mall_size = 96 * 1024 * 1024; 903 break; 904 case IP_VERSION(10, 3, 4): 905 adev->gmc.mall_size = 32 * 1024 * 1024; 906 break; 907 case IP_VERSION(10, 3, 5): 908 adev->gmc.mall_size = 16 * 1024 * 1024; 909 break; 910 default: 911 adev->gmc.mall_size = 0; 912 break; 913 } 914 915 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 916 case IP_VERSION(10, 1, 10): 917 case IP_VERSION(10, 1, 1): 918 case IP_VERSION(10, 1, 2): 919 case IP_VERSION(10, 1, 3): 920 case IP_VERSION(10, 1, 4): 921 case IP_VERSION(10, 3, 0): 922 case IP_VERSION(10, 3, 2): 923 case IP_VERSION(10, 3, 1): 924 case IP_VERSION(10, 3, 4): 925 case IP_VERSION(10, 3, 5): 926 case IP_VERSION(10, 3, 6): 927 case IP_VERSION(10, 3, 3): 928 case IP_VERSION(10, 3, 7): 929 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 930 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 931 /* 932 * To fulfill 4-level page support, 933 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 934 * block size 512 (9bit) 935 */ 936 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 937 break; 938 default: 939 break; 940 } 941 942 /* This interrupt is VMC page fault.*/ 943 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 944 VMC_1_0__SRCID__VM_FAULT, 945 &adev->gmc.vm_fault); 946 947 if (r) 948 return r; 949 950 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 951 UTCL2_1_0__SRCID__FAULT, 952 &adev->gmc.vm_fault); 953 if (r) 954 return r; 955 956 if (!amdgpu_sriov_vf(adev)) { 957 /* interrupt sent to DF. */ 958 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 959 &adev->gmc.ecc_irq); 960 if (r) 961 return r; 962 } 963 964 /* 965 * Set the internal MC address mask This is the max address of the GPU's 966 * internal address space. 967 */ 968 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 969 970 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 971 if (r) { 972 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 973 return r; 974 } 975 976 adev->need_swiotlb = drm_need_swiotlb(44); 977 978 r = gmc_v10_0_mc_init(adev); 979 if (r) 980 return r; 981 982 amdgpu_gmc_get_vbios_allocations(adev); 983 984 /* Memory manager */ 985 r = amdgpu_bo_init(adev); 986 if (r) 987 return r; 988 989 r = gmc_v10_0_gart_init(adev); 990 if (r) 991 return r; 992 993 /* 994 * number of VMs 995 * VMID 0 is reserved for System 996 * amdgpu graphics/compute will use VMIDs 1-7 997 * amdkfd will use VMIDs 8-15 998 */ 999 adev->vm_manager.first_kfd_vmid = 8; 1000 1001 amdgpu_vm_manager_init(adev); 1002 1003 r = amdgpu_gmc_ras_sw_init(adev); 1004 if (r) 1005 return r; 1006 1007 return 0; 1008 } 1009 1010 /** 1011 * gmc_v10_0_gart_fini - vm fini callback 1012 * 1013 * @adev: amdgpu_device pointer 1014 * 1015 * Tears down the driver GART/VM setup (CIK). 1016 */ 1017 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 1018 { 1019 amdgpu_gart_table_vram_free(adev); 1020 } 1021 1022 static int gmc_v10_0_sw_fini(void *handle) 1023 { 1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1025 1026 amdgpu_vm_manager_fini(adev); 1027 gmc_v10_0_gart_fini(adev); 1028 amdgpu_gem_force_release(adev); 1029 amdgpu_bo_fini(adev); 1030 1031 return 0; 1032 } 1033 1034 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 1035 { 1036 } 1037 1038 /** 1039 * gmc_v10_0_gart_enable - gart enable 1040 * 1041 * @adev: amdgpu_device pointer 1042 */ 1043 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 1044 { 1045 int r; 1046 bool value; 1047 1048 if (adev->gart.bo == NULL) { 1049 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 1050 return -EINVAL; 1051 } 1052 1053 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 1054 1055 if (!adev->in_s0ix) { 1056 r = adev->gfxhub.funcs->gart_enable(adev); 1057 if (r) 1058 return r; 1059 } 1060 1061 r = adev->mmhub.funcs->gart_enable(adev); 1062 if (r) 1063 return r; 1064 1065 adev->hdp.funcs->init_registers(adev); 1066 1067 /* Flush HDP after it is initialized */ 1068 adev->hdp.funcs->flush_hdp(adev, NULL); 1069 1070 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 1071 false : true; 1072 1073 if (!adev->in_s0ix) 1074 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 1075 adev->mmhub.funcs->set_fault_enable_default(adev, value); 1076 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 1077 if (!adev->in_s0ix) 1078 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 1079 1080 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 1081 (unsigned int)(adev->gmc.gart_size >> 20), 1082 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 1083 1084 return 0; 1085 } 1086 1087 static int gmc_v10_0_hw_init(void *handle) 1088 { 1089 int r; 1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1091 1092 /* The sequence of these two function calls matters.*/ 1093 gmc_v10_0_init_golden_registers(adev); 1094 1095 /* 1096 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 1097 * register setup within GMC, or else system hang when harvesting SA. 1098 */ 1099 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 1100 adev->gfxhub.funcs->utcl2_harvest(adev); 1101 1102 r = gmc_v10_0_gart_enable(adev); 1103 if (r) 1104 return r; 1105 1106 if (amdgpu_emu_mode == 1) { 1107 r = amdgpu_gmc_vram_checking(adev); 1108 if (r) 1109 return r; 1110 } 1111 1112 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1113 adev->umc.funcs->init_registers(adev); 1114 1115 return 0; 1116 } 1117 1118 /** 1119 * gmc_v10_0_gart_disable - gart disable 1120 * 1121 * @adev: amdgpu_device pointer 1122 * 1123 * This disables all VM page table. 1124 */ 1125 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1126 { 1127 if (!adev->in_s0ix) 1128 adev->gfxhub.funcs->gart_disable(adev); 1129 adev->mmhub.funcs->gart_disable(adev); 1130 } 1131 1132 static int gmc_v10_0_hw_fini(void *handle) 1133 { 1134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1135 1136 gmc_v10_0_gart_disable(adev); 1137 1138 if (amdgpu_sriov_vf(adev)) { 1139 /* full access mode, so don't touch any GMC register */ 1140 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1141 return 0; 1142 } 1143 1144 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1145 1146 return 0; 1147 } 1148 1149 static int gmc_v10_0_suspend(void *handle) 1150 { 1151 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1152 1153 gmc_v10_0_hw_fini(adev); 1154 1155 return 0; 1156 } 1157 1158 static int gmc_v10_0_resume(void *handle) 1159 { 1160 int r; 1161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1162 1163 r = gmc_v10_0_hw_init(adev); 1164 if (r) 1165 return r; 1166 1167 amdgpu_vmid_reset_all(adev); 1168 1169 return 0; 1170 } 1171 1172 static bool gmc_v10_0_is_idle(void *handle) 1173 { 1174 /* MC is always ready in GMC v10.*/ 1175 return true; 1176 } 1177 1178 static int gmc_v10_0_wait_for_idle(void *handle) 1179 { 1180 /* There is no need to wait for MC idle in GMC v10.*/ 1181 return 0; 1182 } 1183 1184 static int gmc_v10_0_soft_reset(void *handle) 1185 { 1186 return 0; 1187 } 1188 1189 static int gmc_v10_0_set_clockgating_state(void *handle, 1190 enum amd_clockgating_state state) 1191 { 1192 int r; 1193 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1194 1195 /* 1196 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1197 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1198 * seen any issue on the DF 3.0.2 series platform. 1199 */ 1200 if (adev->in_s0ix && 1201 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) { 1202 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1203 return 0; 1204 } 1205 1206 r = adev->mmhub.funcs->set_clockgating(adev, state); 1207 if (r) 1208 return r; 1209 1210 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1211 return athub_v2_1_set_clockgating(adev, state); 1212 else 1213 return athub_v2_0_set_clockgating(adev, state); 1214 } 1215 1216 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) 1217 { 1218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1219 1220 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || 1221 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) 1222 return; 1223 1224 adev->mmhub.funcs->get_clockgating(adev, flags); 1225 1226 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1227 athub_v2_1_get_clockgating(adev, flags); 1228 else 1229 athub_v2_0_get_clockgating(adev, flags); 1230 } 1231 1232 static int gmc_v10_0_set_powergating_state(void *handle, 1233 enum amd_powergating_state state) 1234 { 1235 return 0; 1236 } 1237 1238 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1239 .name = "gmc_v10_0", 1240 .early_init = gmc_v10_0_early_init, 1241 .late_init = gmc_v10_0_late_init, 1242 .sw_init = gmc_v10_0_sw_init, 1243 .sw_fini = gmc_v10_0_sw_fini, 1244 .hw_init = gmc_v10_0_hw_init, 1245 .hw_fini = gmc_v10_0_hw_fini, 1246 .suspend = gmc_v10_0_suspend, 1247 .resume = gmc_v10_0_resume, 1248 .is_idle = gmc_v10_0_is_idle, 1249 .wait_for_idle = gmc_v10_0_wait_for_idle, 1250 .soft_reset = gmc_v10_0_soft_reset, 1251 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1252 .set_powergating_state = gmc_v10_0_set_powergating_state, 1253 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1254 }; 1255 1256 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = { 1257 .type = AMD_IP_BLOCK_TYPE_GMC, 1258 .major = 10, 1259 .minor = 0, 1260 .rev = 0, 1261 .funcs = &gmc_v10_0_ip_funcs, 1262 }; 1263