xref: /linux/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c (revision 1d1997db870f4058676439ef7014390ba9e24eb2)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include <linux/firmware.h>
24 #include <linux/pci.h>
25 #include "amdgpu.h"
26 #include "amdgpu_atomfirmware.h"
27 #include "gmc_v10_0.h"
28 
29 #include "hdp/hdp_5_0_0_offset.h"
30 #include "hdp/hdp_5_0_0_sh_mask.h"
31 #include "gc/gc_10_1_0_sh_mask.h"
32 #include "mmhub/mmhub_2_0_0_sh_mask.h"
33 #include "dcn/dcn_2_0_0_offset.h"
34 #include "dcn/dcn_2_0_0_sh_mask.h"
35 #include "oss/osssys_5_0_0_offset.h"
36 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
37 #include "navi10_enum.h"
38 
39 #include "soc15.h"
40 #include "soc15_common.h"
41 
42 #include "nbio_v2_3.h"
43 
44 #include "gfxhub_v2_0.h"
45 #include "mmhub_v2_0.h"
46 #include "athub_v2_0.h"
47 /* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
48 #define AMDGPU_NUM_OF_VMIDS			8
49 
50 #if 0
51 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
52 {
53 	/* TODO add golden setting for hdp */
54 };
55 #endif
56 
57 static int
58 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
59 				   struct amdgpu_irq_src *src, unsigned type,
60 				   enum amdgpu_interrupt_state state)
61 {
62 	struct amdgpu_vmhub *hub;
63 	u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
64 
65 	bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
66 		GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
67 		GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
68 		GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
69 		GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
70 		GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
71 		GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
72 
73 	bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
74 		MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
75 		MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
76 		MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
77 		MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
78 		MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
79 		MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
80 
81 	switch (state) {
82 	case AMDGPU_IRQ_STATE_DISABLE:
83 		/* MM HUB */
84 		hub = &adev->vmhub[AMDGPU_MMHUB_0];
85 		for (i = 0; i < 16; i++) {
86 			reg = hub->vm_context0_cntl + i;
87 			tmp = RREG32(reg);
88 			tmp &= ~bits[AMDGPU_MMHUB_0];
89 			WREG32(reg, tmp);
90 		}
91 
92 		/* GFX HUB */
93 		hub = &adev->vmhub[AMDGPU_GFXHUB_0];
94 		for (i = 0; i < 16; i++) {
95 			reg = hub->vm_context0_cntl + i;
96 			tmp = RREG32(reg);
97 			tmp &= ~bits[AMDGPU_GFXHUB_0];
98 			WREG32(reg, tmp);
99 		}
100 		break;
101 	case AMDGPU_IRQ_STATE_ENABLE:
102 		/* MM HUB */
103 		hub = &adev->vmhub[AMDGPU_MMHUB_0];
104 		for (i = 0; i < 16; i++) {
105 			reg = hub->vm_context0_cntl + i;
106 			tmp = RREG32(reg);
107 			tmp |= bits[AMDGPU_MMHUB_0];
108 			WREG32(reg, tmp);
109 		}
110 
111 		/* GFX HUB */
112 		hub = &adev->vmhub[AMDGPU_GFXHUB_0];
113 		for (i = 0; i < 16; i++) {
114 			reg = hub->vm_context0_cntl + i;
115 			tmp = RREG32(reg);
116 			tmp |= bits[AMDGPU_GFXHUB_0];
117 			WREG32(reg, tmp);
118 		}
119 		break;
120 	default:
121 		break;
122 	}
123 
124 	return 0;
125 }
126 
127 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
128 				       struct amdgpu_irq_src *source,
129 				       struct amdgpu_iv_entry *entry)
130 {
131 	struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
132 	uint32_t status = 0;
133 	u64 addr;
134 
135 	addr = (u64)entry->src_data[0] << 12;
136 	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
137 
138 	if (!amdgpu_sriov_vf(adev)) {
139 		/*
140 		 * Issue a dummy read to wait for the status register to
141 		 * be updated to avoid reading an incorrect value due to
142 		 * the new fast GRBM interface.
143 		 */
144 		if (entry->vmid_src == AMDGPU_GFXHUB_0)
145 			RREG32(hub->vm_l2_pro_fault_status);
146 
147 		status = RREG32(hub->vm_l2_pro_fault_status);
148 		WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
149 	}
150 
151 	if (printk_ratelimit()) {
152 		struct amdgpu_task_info task_info;
153 
154 		memset(&task_info, 0, sizeof(struct amdgpu_task_info));
155 		amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
156 
157 		dev_err(adev->dev,
158 			"[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
159 			"for process %s pid %d thread %s pid %d)\n",
160 			entry->vmid_src ? "mmhub" : "gfxhub",
161 			entry->src_id, entry->ring_id, entry->vmid,
162 			entry->pasid, task_info.process_name, task_info.tgid,
163 			task_info.task_name, task_info.pid);
164 		dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
165 			addr, entry->client_id);
166 		if (!amdgpu_sriov_vf(adev)) {
167 			dev_err(adev->dev,
168 				"GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
169 				status);
170 			dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
171 				REG_GET_FIELD(status,
172 				GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
173 			dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
174 				REG_GET_FIELD(status,
175 				GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
176 			dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
177 				REG_GET_FIELD(status,
178 				GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
179 			dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
180 				REG_GET_FIELD(status,
181 				GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
182 			dev_err(adev->dev, "\t RW: 0x%lx\n",
183 				REG_GET_FIELD(status,
184 				GCVM_L2_PROTECTION_FAULT_STATUS, RW));
185 		}
186 	}
187 
188 	return 0;
189 }
190 
191 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
192 	.set = gmc_v10_0_vm_fault_interrupt_state,
193 	.process = gmc_v10_0_process_interrupt,
194 };
195 
196 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
197 {
198 	adev->gmc.vm_fault.num_types = 1;
199 	adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
200 }
201 
202 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
203 					     uint32_t flush_type)
204 {
205 	u32 req = 0;
206 
207 	/* invalidate using legacy mode on vmid*/
208 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
209 			    PER_VMID_INVALIDATE_REQ, 1 << vmid);
210 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
211 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
212 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
213 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
214 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
215 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
216 	req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
217 			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);
218 
219 	return req;
220 }
221 
222 /*
223  * GART
224  * VMID 0 is the physical GPU addresses as used by the kernel.
225  * VMIDs 1-15 are used for userspace clients and are handled
226  * by the amdgpu vm/hsa code.
227  */
228 
229 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
230 				   unsigned int vmhub, uint32_t flush_type)
231 {
232 	struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
233 	u32 tmp = gmc_v10_0_get_invalidate_req(vmid, flush_type);
234 	/* Use register 17 for GART */
235 	const unsigned eng = 17;
236 	unsigned int i;
237 
238 	spin_lock(&adev->gmc.invalidate_lock);
239 	/*
240 	 * It may lose gpuvm invalidate acknowldege state across power-gating
241 	 * off cycle, add semaphore acquire before invalidation and semaphore
242 	 * release after invalidation to avoid entering power gated state
243 	 * to WA the Issue
244 	 */
245 
246 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
247 	if (vmhub == AMDGPU_MMHUB_0 ||
248 	    vmhub == AMDGPU_MMHUB_1) {
249 		for (i = 0; i < adev->usec_timeout; i++) {
250 			/* a read return value of 1 means semaphore acuqire */
251 			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng);
252 			if (tmp & 0x1)
253 				break;
254 			udelay(1);
255 		}
256 
257 		if (i >= adev->usec_timeout)
258 			DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
259 	}
260 
261 	WREG32_NO_KIQ(hub->vm_inv_eng0_req + eng, tmp);
262 
263 	/*
264 	 * Issue a dummy read to wait for the ACK register to be cleared
265 	 * to avoid a false ACK due to the new fast GRBM interface.
266 	 */
267 	if (vmhub == AMDGPU_GFXHUB_0)
268 		RREG32_NO_KIQ(hub->vm_inv_eng0_req + eng);
269 
270 	/* Wait for ACK with a delay.*/
271 	for (i = 0; i < adev->usec_timeout; i++) {
272 		tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack + eng);
273 		tmp &= 1 << vmid;
274 		if (tmp)
275 			break;
276 
277 		udelay(1);
278 	}
279 
280 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
281 	if (vmhub == AMDGPU_MMHUB_0 ||
282 	    vmhub == AMDGPU_MMHUB_1)
283 		/*
284 		 * add semaphore release after invalidation,
285 		 * write with 0 means semaphore release
286 		 */
287 		WREG32_NO_KIQ(hub->vm_inv_eng0_sem + eng, 0);
288 
289 	spin_unlock(&adev->gmc.invalidate_lock);
290 
291 	if (i < adev->usec_timeout)
292 		return;
293 
294 	DRM_ERROR("Timeout waiting for VM flush ACK!\n");
295 }
296 
297 /**
298  * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
299  *
300  * @adev: amdgpu_device pointer
301  * @vmid: vm instance to flush
302  *
303  * Flush the TLB for the requested page table.
304  */
305 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
306 					uint32_t vmhub, uint32_t flush_type)
307 {
308 	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
309 	struct dma_fence *fence;
310 	struct amdgpu_job *job;
311 
312 	int r;
313 
314 	/* flush hdp cache */
315 	adev->nbio.funcs->hdp_flush(adev, NULL);
316 
317 	mutex_lock(&adev->mman.gtt_window_lock);
318 
319 	if (vmhub == AMDGPU_MMHUB_0) {
320 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
321 		mutex_unlock(&adev->mman.gtt_window_lock);
322 		return;
323 	}
324 
325 	BUG_ON(vmhub != AMDGPU_GFXHUB_0);
326 
327 	if (!adev->mman.buffer_funcs_enabled ||
328 	    !adev->ib_pool_ready ||
329 	    adev->in_gpu_reset ||
330 	    ring->sched.ready == false) {
331 		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
332 		mutex_unlock(&adev->mman.gtt_window_lock);
333 		return;
334 	}
335 
336 	/* The SDMA on Navi has a bug which can theoretically result in memory
337 	 * corruption if an invalidation happens at the same time as an VA
338 	 * translation. Avoid this by doing the invalidation from the SDMA
339 	 * itself.
340 	 */
341 	r = amdgpu_job_alloc_with_ib(adev, 16 * 4, &job);
342 	if (r)
343 		goto error_alloc;
344 
345 	job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
346 	job->vm_needs_flush = true;
347 	job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
348 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
349 	r = amdgpu_job_submit(job, &adev->mman.entity,
350 			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
351 	if (r)
352 		goto error_submit;
353 
354 	mutex_unlock(&adev->mman.gtt_window_lock);
355 
356 	dma_fence_wait(fence, false);
357 	dma_fence_put(fence);
358 
359 	return;
360 
361 error_submit:
362 	amdgpu_job_free(job);
363 
364 error_alloc:
365 	mutex_unlock(&adev->mman.gtt_window_lock);
366 	DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
367 }
368 
369 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
370 					     unsigned vmid, uint64_t pd_addr)
371 {
372 	struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
373 	uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
374 	unsigned eng = ring->vm_inv_eng;
375 
376 	/*
377 	 * It may lose gpuvm invalidate acknowldege state across power-gating
378 	 * off cycle, add semaphore acquire before invalidation and semaphore
379 	 * release after invalidation to avoid entering power gated state
380 	 * to WA the Issue
381 	 */
382 
383 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
384 	if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
385 	    ring->funcs->vmhub == AMDGPU_MMHUB_1)
386 		/* a read return value of 1 means semaphore acuqire */
387 		amdgpu_ring_emit_reg_wait(ring,
388 					  hub->vm_inv_eng0_sem + eng, 0x1, 0x1);
389 
390 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
391 			      lower_32_bits(pd_addr));
392 
393 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + (2 * vmid),
394 			      upper_32_bits(pd_addr));
395 
396 	amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + eng,
397 					    hub->vm_inv_eng0_ack + eng,
398 					    req, 1 << vmid);
399 
400 	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
401 	if (ring->funcs->vmhub == AMDGPU_MMHUB_0 ||
402 	    ring->funcs->vmhub == AMDGPU_MMHUB_1)
403 		/*
404 		 * add semaphore release after invalidation,
405 		 * write with 0 means semaphore release
406 		 */
407 		amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + eng, 0);
408 
409 	return pd_addr;
410 }
411 
412 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
413 					 unsigned pasid)
414 {
415 	struct amdgpu_device *adev = ring->adev;
416 	uint32_t reg;
417 
418 	if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
419 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
420 	else
421 		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
422 
423 	amdgpu_ring_emit_wreg(ring, reg, pasid);
424 }
425 
426 /*
427  * PTE format on NAVI 10:
428  * 63:59 reserved
429  * 58:57 reserved
430  * 56 F
431  * 55 L
432  * 54 reserved
433  * 53:52 SW
434  * 51 T
435  * 50:48 mtype
436  * 47:12 4k physical page base address
437  * 11:7 fragment
438  * 6 write
439  * 5 read
440  * 4 exe
441  * 3 Z
442  * 2 snooped
443  * 1 system
444  * 0 valid
445  *
446  * PDE format on NAVI 10:
447  * 63:59 block fragment size
448  * 58:55 reserved
449  * 54 P
450  * 53:48 reserved
451  * 47:6 physical base address of PD or PTE
452  * 5:3 reserved
453  * 2 C
454  * 1 system
455  * 0 valid
456  */
457 
458 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
459 {
460 	switch (flags) {
461 	case AMDGPU_VM_MTYPE_DEFAULT:
462 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
463 	case AMDGPU_VM_MTYPE_NC:
464 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
465 	case AMDGPU_VM_MTYPE_WC:
466 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
467 	case AMDGPU_VM_MTYPE_CC:
468 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
469 	case AMDGPU_VM_MTYPE_UC:
470 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
471 	default:
472 		return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
473 	}
474 }
475 
476 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
477 				 uint64_t *addr, uint64_t *flags)
478 {
479 	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
480 		*addr = adev->vm_manager.vram_base_offset + *addr -
481 			adev->gmc.vram_start;
482 	BUG_ON(*addr & 0xFFFF00000000003FULL);
483 
484 	if (!adev->gmc.translate_further)
485 		return;
486 
487 	if (level == AMDGPU_VM_PDB1) {
488 		/* Set the block fragment size */
489 		if (!(*flags & AMDGPU_PDE_PTE))
490 			*flags |= AMDGPU_PDE_BFS(0x9);
491 
492 	} else if (level == AMDGPU_VM_PDB0) {
493 		if (*flags & AMDGPU_PDE_PTE)
494 			*flags &= ~AMDGPU_PDE_PTE;
495 		else
496 			*flags |= AMDGPU_PTE_TF;
497 	}
498 }
499 
500 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
501 				 struct amdgpu_bo_va_mapping *mapping,
502 				 uint64_t *flags)
503 {
504 	*flags &= ~AMDGPU_PTE_EXECUTABLE;
505 	*flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
506 
507 	*flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
508 	*flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
509 
510 	if (mapping->flags & AMDGPU_PTE_PRT) {
511 		*flags |= AMDGPU_PTE_PRT;
512 		*flags |= AMDGPU_PTE_SNOOPED;
513 		*flags |= AMDGPU_PTE_LOG;
514 		*flags |= AMDGPU_PTE_SYSTEM;
515 		*flags &= ~AMDGPU_PTE_VALID;
516 	}
517 }
518 
519 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
520 	.flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
521 	.emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
522 	.emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
523 	.map_mtype = gmc_v10_0_map_mtype,
524 	.get_vm_pde = gmc_v10_0_get_vm_pde,
525 	.get_vm_pte = gmc_v10_0_get_vm_pte
526 };
527 
528 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
529 {
530 	if (adev->gmc.gmc_funcs == NULL)
531 		adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
532 }
533 
534 static int gmc_v10_0_early_init(void *handle)
535 {
536 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
537 
538 	gmc_v10_0_set_gmc_funcs(adev);
539 	gmc_v10_0_set_irq_funcs(adev);
540 
541 	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
542 	adev->gmc.shared_aperture_end =
543 		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
544 	adev->gmc.private_aperture_start = 0x1000000000000000ULL;
545 	adev->gmc.private_aperture_end =
546 		adev->gmc.private_aperture_start + (4ULL << 30) - 1;
547 
548 	return 0;
549 }
550 
551 static int gmc_v10_0_late_init(void *handle)
552 {
553 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
554 	unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 };
555 	unsigned i;
556 
557 	for(i = 0; i < adev->num_rings; ++i) {
558 		struct amdgpu_ring *ring = adev->rings[i];
559 		unsigned vmhub = ring->funcs->vmhub;
560 
561 		ring->vm_inv_eng = vm_inv_eng[vmhub]++;
562 		dev_info(adev->dev, "ring %u(%s) uses VM inv eng %u on hub %u\n",
563 			 ring->idx, ring->name, ring->vm_inv_eng,
564 			 ring->funcs->vmhub);
565 	}
566 
567 	/* Engine 17 is used for GART flushes */
568 	for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i)
569 		BUG_ON(vm_inv_eng[i] > 17);
570 
571 	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
572 }
573 
574 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
575 					struct amdgpu_gmc *mc)
576 {
577 	u64 base = 0;
578 
579 	base = gfxhub_v2_0_get_fb_location(adev);
580 
581 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);
582 	amdgpu_gmc_gart_location(adev, mc);
583 
584 	/* base offset of vram pages */
585 	adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
586 }
587 
588 /**
589  * gmc_v10_0_mc_init - initialize the memory controller driver params
590  *
591  * @adev: amdgpu_device pointer
592  *
593  * Look up the amount of vram, vram width, and decide how to place
594  * vram and gart within the GPU's physical address space.
595  * Returns 0 for success.
596  */
597 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
598 {
599 	/* Could aper size report 0 ? */
600 	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
601 	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
602 
603 	/* size in MB on si */
604 	adev->gmc.mc_vram_size =
605 		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
606 	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
607 	adev->gmc.visible_vram_size = adev->gmc.aper_size;
608 
609 	/* In case the PCI BAR is larger than the actual amount of vram */
610 	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
611 		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
612 
613 	/* set the gart size */
614 	if (amdgpu_gart_size == -1) {
615 		switch (adev->asic_type) {
616 		case CHIP_NAVI10:
617 		case CHIP_NAVI14:
618 		case CHIP_NAVI12:
619 		default:
620 			adev->gmc.gart_size = 512ULL << 20;
621 			break;
622 		}
623 	} else
624 		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
625 
626 	gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
627 
628 	return 0;
629 }
630 
631 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
632 {
633 	int r;
634 
635 	if (adev->gart.bo) {
636 		WARN(1, "NAVI10 PCIE GART already initialized\n");
637 		return 0;
638 	}
639 
640 	/* Initialize common gart structure */
641 	r = amdgpu_gart_init(adev);
642 	if (r)
643 		return r;
644 
645 	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
646 	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
647 				 AMDGPU_PTE_EXECUTABLE;
648 
649 	return amdgpu_gart_table_vram_alloc(adev);
650 }
651 
652 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
653 {
654 	u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
655 	unsigned size;
656 
657 	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
658 		size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
659 	} else {
660 		u32 viewport;
661 		u32 pitch;
662 
663 		viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
664 		pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
665 		size = (REG_GET_FIELD(viewport,
666 					HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
667 				REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
668 				4);
669 	}
670 	/* return 0 if the pre-OS buffer uses up most of vram */
671 	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) {
672 		DRM_ERROR("Warning: pre-OS buffer uses most of vram, \
673 				be aware of gart table overwrite\n");
674 		return 0;
675 	}
676 
677 	return size;
678 }
679 
680 
681 
682 static int gmc_v10_0_sw_init(void *handle)
683 {
684 	int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
685 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
686 
687 	gfxhub_v2_0_init(adev);
688 	mmhub_v2_0_init(adev);
689 
690 	spin_lock_init(&adev->gmc.invalidate_lock);
691 
692 	r = amdgpu_atomfirmware_get_vram_info(adev,
693 		&vram_width, &vram_type, &vram_vendor);
694 	if (!amdgpu_emu_mode)
695 		adev->gmc.vram_width = vram_width;
696 	else
697 		adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
698 
699 	adev->gmc.vram_type = vram_type;
700 	adev->gmc.vram_vendor = vram_vendor;
701 	switch (adev->asic_type) {
702 	case CHIP_NAVI10:
703 	case CHIP_NAVI14:
704 	case CHIP_NAVI12:
705 		adev->num_vmhubs = 2;
706 		/*
707 		 * To fulfill 4-level page support,
708 		 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
709 		 * block size 512 (9bit)
710 		 */
711 		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
712 		break;
713 	default:
714 		break;
715 	}
716 
717 	/* This interrupt is VMC page fault.*/
718 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
719 			      VMC_1_0__SRCID__VM_FAULT,
720 			      &adev->gmc.vm_fault);
721 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
722 			      UTCL2_1_0__SRCID__FAULT,
723 			      &adev->gmc.vm_fault);
724 	if (r)
725 		return r;
726 
727 	/*
728 	 * Set the internal MC address mask This is the max address of the GPU's
729 	 * internal address space.
730 	 */
731 	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
732 
733 	/*
734 	 * Reserve 8M stolen memory for navi10 like vega10
735 	 * TODO: will check if it's really needed on asic.
736 	 */
737 	if (amdgpu_emu_mode == 1)
738 		adev->gmc.stolen_size = 0;
739 	else
740 		adev->gmc.stolen_size = 9 * 1024 *1024;
741 
742 	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
743 	if (r) {
744 		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
745 		return r;
746 	}
747 
748 	r = gmc_v10_0_mc_init(adev);
749 	if (r)
750 		return r;
751 
752 	adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev);
753 
754 	/* Memory manager */
755 	r = amdgpu_bo_init(adev);
756 	if (r)
757 		return r;
758 
759 	r = gmc_v10_0_gart_init(adev);
760 	if (r)
761 		return r;
762 
763 	/*
764 	 * number of VMs
765 	 * VMID 0 is reserved for System
766 	 * amdgpu graphics/compute will use VMIDs 1-7
767 	 * amdkfd will use VMIDs 8-15
768 	 */
769 	adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
770 	adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
771 
772 	amdgpu_vm_manager_init(adev);
773 
774 	return 0;
775 }
776 
777 /**
778  * gmc_v8_0_gart_fini - vm fini callback
779  *
780  * @adev: amdgpu_device pointer
781  *
782  * Tears down the driver GART/VM setup (CIK).
783  */
784 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
785 {
786 	amdgpu_gart_table_vram_free(adev);
787 	amdgpu_gart_fini(adev);
788 }
789 
790 static int gmc_v10_0_sw_fini(void *handle)
791 {
792 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
793 
794 	amdgpu_vm_manager_fini(adev);
795 	gmc_v10_0_gart_fini(adev);
796 	amdgpu_gem_force_release(adev);
797 	amdgpu_bo_fini(adev);
798 
799 	return 0;
800 }
801 
802 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
803 {
804 	switch (adev->asic_type) {
805 	case CHIP_NAVI10:
806 	case CHIP_NAVI14:
807 	case CHIP_NAVI12:
808 		break;
809 	default:
810 		break;
811 	}
812 }
813 
814 /**
815  * gmc_v10_0_gart_enable - gart enable
816  *
817  * @adev: amdgpu_device pointer
818  */
819 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
820 {
821 	int r;
822 	bool value;
823 	u32 tmp;
824 
825 	if (adev->gart.bo == NULL) {
826 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
827 		return -EINVAL;
828 	}
829 
830 	r = amdgpu_gart_table_vram_pin(adev);
831 	if (r)
832 		return r;
833 
834 	r = gfxhub_v2_0_gart_enable(adev);
835 	if (r)
836 		return r;
837 
838 	r = mmhub_v2_0_gart_enable(adev);
839 	if (r)
840 		return r;
841 
842 	tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
843 	tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
844 	WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
845 
846 	tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
847 	WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
848 
849 	/* Flush HDP after it is initialized */
850 	adev->nbio.funcs->hdp_flush(adev, NULL);
851 
852 	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
853 		false : true;
854 
855 	gfxhub_v2_0_set_fault_enable_default(adev, value);
856 	mmhub_v2_0_set_fault_enable_default(adev, value);
857 	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
858 	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
859 
860 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
861 		 (unsigned)(adev->gmc.gart_size >> 20),
862 		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
863 
864 	adev->gart.ready = true;
865 
866 	return 0;
867 }
868 
869 static int gmc_v10_0_hw_init(void *handle)
870 {
871 	int r;
872 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
873 
874 	/* The sequence of these two function calls matters.*/
875 	gmc_v10_0_init_golden_registers(adev);
876 
877 	r = gmc_v10_0_gart_enable(adev);
878 	if (r)
879 		return r;
880 
881 	return 0;
882 }
883 
884 /**
885  * gmc_v10_0_gart_disable - gart disable
886  *
887  * @adev: amdgpu_device pointer
888  *
889  * This disables all VM page table.
890  */
891 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
892 {
893 	gfxhub_v2_0_gart_disable(adev);
894 	mmhub_v2_0_gart_disable(adev);
895 	amdgpu_gart_table_vram_unpin(adev);
896 }
897 
898 static int gmc_v10_0_hw_fini(void *handle)
899 {
900 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
901 
902 	if (amdgpu_sriov_vf(adev)) {
903 		/* full access mode, so don't touch any GMC register */
904 		DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
905 		return 0;
906 	}
907 
908 	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
909 	gmc_v10_0_gart_disable(adev);
910 
911 	return 0;
912 }
913 
914 static int gmc_v10_0_suspend(void *handle)
915 {
916 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
917 
918 	gmc_v10_0_hw_fini(adev);
919 
920 	return 0;
921 }
922 
923 static int gmc_v10_0_resume(void *handle)
924 {
925 	int r;
926 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
927 
928 	r = gmc_v10_0_hw_init(adev);
929 	if (r)
930 		return r;
931 
932 	amdgpu_vmid_reset_all(adev);
933 
934 	return 0;
935 }
936 
937 static bool gmc_v10_0_is_idle(void *handle)
938 {
939 	/* MC is always ready in GMC v10.*/
940 	return true;
941 }
942 
943 static int gmc_v10_0_wait_for_idle(void *handle)
944 {
945 	/* There is no need to wait for MC idle in GMC v10.*/
946 	return 0;
947 }
948 
949 static int gmc_v10_0_soft_reset(void *handle)
950 {
951 	return 0;
952 }
953 
954 static int gmc_v10_0_set_clockgating_state(void *handle,
955 					   enum amd_clockgating_state state)
956 {
957 	int r;
958 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
959 
960 	r = mmhub_v2_0_set_clockgating(adev, state);
961 	if (r)
962 		return r;
963 
964 	return athub_v2_0_set_clockgating(adev, state);
965 }
966 
967 static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
968 {
969 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
970 
971 	mmhub_v2_0_get_clockgating(adev, flags);
972 
973 	athub_v2_0_get_clockgating(adev, flags);
974 }
975 
976 static int gmc_v10_0_set_powergating_state(void *handle,
977 					   enum amd_powergating_state state)
978 {
979 	return 0;
980 }
981 
982 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
983 	.name = "gmc_v10_0",
984 	.early_init = gmc_v10_0_early_init,
985 	.late_init = gmc_v10_0_late_init,
986 	.sw_init = gmc_v10_0_sw_init,
987 	.sw_fini = gmc_v10_0_sw_fini,
988 	.hw_init = gmc_v10_0_hw_init,
989 	.hw_fini = gmc_v10_0_hw_fini,
990 	.suspend = gmc_v10_0_suspend,
991 	.resume = gmc_v10_0_resume,
992 	.is_idle = gmc_v10_0_is_idle,
993 	.wait_for_idle = gmc_v10_0_wait_for_idle,
994 	.soft_reset = gmc_v10_0_soft_reset,
995 	.set_clockgating_state = gmc_v10_0_set_clockgating_state,
996 	.set_powergating_state = gmc_v10_0_set_powergating_state,
997 	.get_clockgating_state = gmc_v10_0_get_clockgating_state,
998 };
999 
1000 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1001 {
1002 	.type = AMD_IP_BLOCK_TYPE_GMC,
1003 	.major = 10,
1004 	.minor = 0,
1005 	.rev = 0,
1006 	.funcs = &gmc_v10_0_ip_funcs,
1007 };
1008