1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 55 struct amdgpu_irq_src *src, 56 unsigned int type, 57 enum amdgpu_interrupt_state state) 58 { 59 return 0; 60 } 61 62 static int 63 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 64 struct amdgpu_irq_src *src, unsigned int type, 65 enum amdgpu_interrupt_state state) 66 { 67 switch (state) { 68 case AMDGPU_IRQ_STATE_DISABLE: 69 /* MM HUB */ 70 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 71 /* GFX HUB */ 72 /* This works because this interrupt is only 73 * enabled at init/resume and disabled in 74 * fini/suspend, so the overall state doesn't 75 * change over the course of suspend/resume. 76 */ 77 if (!adev->in_s0ix) 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 83 /* GFX HUB */ 84 /* This works because this interrupt is only 85 * enabled at init/resume and disabled in 86 * fini/suspend, so the overall state doesn't 87 * change over the course of suspend/resume. 88 */ 89 if (!adev->in_s0ix) 90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 91 break; 92 default: 93 break; 94 } 95 96 return 0; 97 } 98 99 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 100 struct amdgpu_irq_src *source, 101 struct amdgpu_iv_entry *entry) 102 { 103 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? 104 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 105 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 106 bool retry_fault = !!(entry->src_data[1] & 0x80); 107 bool write_fault = !!(entry->src_data[1] & 0x20); 108 struct amdgpu_task_info *task_info; 109 uint32_t status = 0; 110 u64 addr; 111 112 addr = (u64)entry->src_data[0] << 12; 113 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 114 115 if (retry_fault) { 116 /* Returning 1 here also prevents sending the IV to the KFD */ 117 118 /* Process it onyl if it's the first fault for this address */ 119 if (entry->ih != &adev->irq.ih_soft && 120 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 121 entry->timestamp)) 122 return 1; 123 124 /* Delegate it to a different ring if the hardware hasn't 125 * already done it. 126 */ 127 if (entry->ih == &adev->irq.ih) { 128 amdgpu_irq_delegate(adev, entry, 8); 129 return 1; 130 } 131 132 /* Try to handle the recoverable page faults by filling page 133 * tables 134 */ 135 if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, 136 entry->timestamp, write_fault)) 137 return 1; 138 } 139 140 if (!amdgpu_sriov_vf(adev)) { 141 /* 142 * Issue a dummy read to wait for the status register to 143 * be updated to avoid reading an incorrect value due to 144 * the new fast GRBM interface. 145 */ 146 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 147 (amdgpu_ip_version(adev, GC_HWIP, 0) < 148 IP_VERSION(10, 3, 0))) 149 RREG32(hub->vm_l2_pro_fault_status); 150 151 status = RREG32(hub->vm_l2_pro_fault_status); 152 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 153 154 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 155 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 156 } 157 158 if (!printk_ratelimit()) 159 return 0; 160 161 dev_err(adev->dev, 162 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", 163 entry->vmid_src ? "mmhub" : "gfxhub", 164 entry->src_id, entry->ring_id, entry->vmid, entry->pasid); 165 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid); 166 if (task_info) { 167 amdgpu_vm_print_task_info(adev, task_info); 168 amdgpu_vm_put_task_info(task_info); 169 } 170 171 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 172 addr, entry->client_id, 173 soc15_ih_clientid_name[entry->client_id]); 174 175 /* Only print L2 fault status if the status register could be read and 176 * contains useful information 177 */ 178 if (status != 0) 179 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 180 status); 181 182 return 0; 183 } 184 185 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 186 .set = gmc_v10_0_vm_fault_interrupt_state, 187 .process = gmc_v10_0_process_interrupt, 188 }; 189 190 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 191 .set = gmc_v10_0_ecc_interrupt_state, 192 .process = amdgpu_umc_process_ecc_irq, 193 }; 194 195 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 196 { 197 adev->gmc.vm_fault.num_types = 1; 198 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 199 200 if (!amdgpu_sriov_vf(adev)) { 201 adev->gmc.ecc_irq.num_types = 1; 202 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 203 } 204 } 205 206 /** 207 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 208 * 209 * @adev: amdgpu_device pointer 210 * @vmhub: vmhub type 211 * 212 */ 213 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 214 uint32_t vmhub) 215 { 216 return ((vmhub == AMDGPU_MMHUB0(0)) && 217 (!amdgpu_sriov_vf(adev))); 218 } 219 220 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 221 struct amdgpu_device *adev, 222 uint8_t vmid, uint16_t *p_pasid) 223 { 224 uint32_t value; 225 226 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 227 + vmid); 228 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 229 230 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 231 } 232 233 /* 234 * GART 235 * VMID 0 is the physical GPU addresses as used by the kernel. 236 * VMIDs 1-15 are used for userspace clients and are handled 237 * by the amdgpu vm/hsa code. 238 */ 239 240 /** 241 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 242 * 243 * @adev: amdgpu_device pointer 244 * @vmid: vm instance to flush 245 * @vmhub: vmhub type 246 * @flush_type: the flush type 247 * 248 * Flush the TLB for the requested page table. 249 */ 250 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 251 uint32_t vmhub, uint32_t flush_type) 252 { 253 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 254 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 255 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 256 /* Use register 17 for GART */ 257 const unsigned int eng = 17; 258 unsigned char hub_ip = 0; 259 u32 sem, req, ack; 260 unsigned int i; 261 u32 tmp; 262 263 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 264 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 265 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 266 267 /* flush hdp cache */ 268 amdgpu_device_flush_hdp(adev, NULL); 269 270 /* This is necessary for SRIOV as well as for GFXOFF to function 271 * properly under bare metal 272 */ 273 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && 274 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 275 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req, 276 1 << vmid, GET_INST(GC, 0)); 277 return; 278 } 279 280 /* This path is needed before KIQ/MES/GFXOFF are set up */ 281 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; 282 283 spin_lock(&adev->gmc.invalidate_lock); 284 /* 285 * It may lose gpuvm invalidate acknowldege state across power-gating 286 * off cycle, add semaphore acquire before invalidation and semaphore 287 * release after invalidation to avoid entering power gated state 288 * to WA the Issue 289 */ 290 291 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 292 if (use_semaphore) { 293 for (i = 0; i < adev->usec_timeout; i++) { 294 /* a read return value of 1 means semaphore acuqire */ 295 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); 296 if (tmp & 0x1) 297 break; 298 udelay(1); 299 } 300 301 if (i >= adev->usec_timeout) 302 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 303 } 304 305 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); 306 307 /* 308 * Issue a dummy read to wait for the ACK register to be cleared 309 * to avoid a false ACK due to the new fast GRBM interface. 310 */ 311 if ((vmhub == AMDGPU_GFXHUB(0)) && 312 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) 313 RREG32_RLC_NO_KIQ(req, hub_ip); 314 315 /* Wait for ACK with a delay.*/ 316 for (i = 0; i < adev->usec_timeout; i++) { 317 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); 318 tmp &= 1 << vmid; 319 if (tmp) 320 break; 321 322 udelay(1); 323 } 324 325 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 326 if (use_semaphore) 327 WREG32_RLC_NO_KIQ(sem, 0, hub_ip); 328 329 spin_unlock(&adev->gmc.invalidate_lock); 330 331 if (i >= adev->usec_timeout) 332 dev_err(adev->dev, "Timeout waiting for VM flush hub: %d!\n", 333 vmhub); 334 } 335 336 /** 337 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 338 * 339 * @adev: amdgpu_device pointer 340 * @pasid: pasid to be flush 341 * @flush_type: the flush type 342 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 343 * @inst: is used to select which instance of KIQ to use for the invalidation 344 * 345 * Flush the TLB for the requested pasid. 346 */ 347 static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 348 uint16_t pasid, uint32_t flush_type, 349 bool all_hub, uint32_t inst) 350 { 351 uint16_t queried; 352 int vmid, i; 353 354 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 355 bool valid; 356 357 valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 358 &queried); 359 if (!valid || queried != pasid) 360 continue; 361 362 if (all_hub) { 363 for_each_set_bit(i, adev->vmhubs_mask, 364 AMDGPU_MAX_VMHUBS) 365 gmc_v10_0_flush_gpu_tlb(adev, vmid, i, 366 flush_type); 367 } else { 368 gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 369 flush_type); 370 } 371 } 372 } 373 374 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 375 unsigned int vmid, uint64_t pd_addr) 376 { 377 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 378 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 379 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 380 unsigned int eng = ring->vm_inv_eng; 381 382 /* 383 * It may lose gpuvm invalidate acknowldege state across power-gating 384 * off cycle, add semaphore acquire before invalidation and semaphore 385 * release after invalidation to avoid entering power gated state 386 * to WA the Issue 387 */ 388 389 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 390 if (use_semaphore) 391 /* a read return value of 1 means semaphore acuqire */ 392 amdgpu_ring_emit_reg_wait(ring, 393 hub->vm_inv_eng0_sem + 394 hub->eng_distance * eng, 0x1, 0x1); 395 396 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 397 (hub->ctx_addr_distance * vmid), 398 lower_32_bits(pd_addr)); 399 400 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 401 (hub->ctx_addr_distance * vmid), 402 upper_32_bits(pd_addr)); 403 404 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 405 hub->eng_distance * eng, 406 hub->vm_inv_eng0_ack + 407 hub->eng_distance * eng, 408 req, 1 << vmid); 409 410 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 411 if (use_semaphore) 412 /* 413 * add semaphore release after invalidation, 414 * write with 0 means semaphore release 415 */ 416 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 417 hub->eng_distance * eng, 0); 418 419 return pd_addr; 420 } 421 422 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 423 unsigned int pasid) 424 { 425 struct amdgpu_device *adev = ring->adev; 426 uint32_t reg; 427 428 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 429 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 430 else 431 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 432 433 amdgpu_ring_emit_wreg(ring, reg, pasid); 434 } 435 436 /* 437 * PTE format on NAVI 10: 438 * 63:59 reserved 439 * 58 reserved and for sienna_cichlid is used for MALL noalloc 440 * 57 reserved 441 * 56 F 442 * 55 L 443 * 54 reserved 444 * 53:52 SW 445 * 51 T 446 * 50:48 mtype 447 * 47:12 4k physical page base address 448 * 11:7 fragment 449 * 6 write 450 * 5 read 451 * 4 exe 452 * 3 Z 453 * 2 snooped 454 * 1 system 455 * 0 valid 456 * 457 * PDE format on NAVI 10: 458 * 63:59 block fragment size 459 * 58:55 reserved 460 * 54 P 461 * 53:48 reserved 462 * 47:6 physical base address of PD or PTE 463 * 5:3 reserved 464 * 2 C 465 * 1 system 466 * 0 valid 467 */ 468 469 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 470 uint64_t *addr, uint64_t *flags) 471 { 472 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 473 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 474 BUG_ON(*addr & 0xFFFF00000000003FULL); 475 476 if (!adev->gmc.translate_further) 477 return; 478 479 if (level == AMDGPU_VM_PDB1) { 480 /* Set the block fragment size */ 481 if (!(*flags & AMDGPU_PDE_PTE)) 482 *flags |= AMDGPU_PDE_BFS(0x9); 483 484 } else if (level == AMDGPU_VM_PDB0) { 485 if (*flags & AMDGPU_PDE_PTE) 486 *flags &= ~AMDGPU_PDE_PTE; 487 else 488 *flags |= AMDGPU_PTE_TF; 489 } 490 } 491 492 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 493 struct amdgpu_vm *vm, 494 struct amdgpu_bo *bo, 495 uint32_t vm_flags, 496 uint64_t *flags) 497 { 498 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE) 499 *flags |= AMDGPU_PTE_EXECUTABLE; 500 else 501 *flags &= ~AMDGPU_PTE_EXECUTABLE; 502 503 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) { 504 case AMDGPU_VM_MTYPE_DEFAULT: 505 case AMDGPU_VM_MTYPE_NC: 506 default: 507 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_NC); 508 break; 509 case AMDGPU_VM_MTYPE_WC: 510 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_WC); 511 break; 512 case AMDGPU_VM_MTYPE_CC: 513 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_CC); 514 break; 515 case AMDGPU_VM_MTYPE_UC: 516 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); 517 break; 518 } 519 520 if (vm_flags & AMDGPU_VM_PAGE_NOALLOC) 521 *flags |= AMDGPU_PTE_NOALLOC; 522 else 523 *flags &= ~AMDGPU_PTE_NOALLOC; 524 525 if (vm_flags & AMDGPU_VM_PAGE_PRT) { 526 *flags |= AMDGPU_PTE_PRT; 527 *flags |= AMDGPU_PTE_SNOOPED; 528 *flags |= AMDGPU_PTE_LOG; 529 *flags |= AMDGPU_PTE_SYSTEM; 530 *flags &= ~AMDGPU_PTE_VALID; 531 } 532 533 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 534 AMDGPU_GEM_CREATE_EXT_COHERENT | 535 AMDGPU_GEM_CREATE_UNCACHED)) 536 *flags = AMDGPU_PTE_MTYPE_NV10(*flags, MTYPE_UC); 537 } 538 539 static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 540 { 541 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 542 unsigned int size; 543 544 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 545 size = AMDGPU_VBIOS_VGA_ALLOCATION; 546 } else { 547 u32 viewport; 548 u32 pitch; 549 550 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 551 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 552 size = (REG_GET_FIELD(viewport, 553 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 554 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 555 4); 556 } 557 558 return size; 559 } 560 561 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 562 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 563 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 564 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 565 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 566 .get_vm_pde = gmc_v10_0_get_vm_pde, 567 .get_vm_pte = gmc_v10_0_get_vm_pte, 568 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 569 }; 570 571 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 572 { 573 if (adev->gmc.gmc_funcs == NULL) 574 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 575 } 576 577 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 578 { 579 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 580 case IP_VERSION(8, 7, 0): 581 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 582 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 583 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 584 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 585 adev->umc.retire_unit = 1; 586 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 587 adev->umc.ras = &umc_v8_7_ras; 588 break; 589 default: 590 break; 591 } 592 } 593 594 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 595 { 596 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 597 case IP_VERSION(2, 3, 0): 598 case IP_VERSION(2, 4, 0): 599 case IP_VERSION(2, 4, 1): 600 adev->mmhub.funcs = &mmhub_v2_3_funcs; 601 break; 602 default: 603 adev->mmhub.funcs = &mmhub_v2_0_funcs; 604 break; 605 } 606 } 607 608 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 609 { 610 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 611 case IP_VERSION(10, 3, 0): 612 case IP_VERSION(10, 3, 2): 613 case IP_VERSION(10, 3, 1): 614 case IP_VERSION(10, 3, 4): 615 case IP_VERSION(10, 3, 5): 616 case IP_VERSION(10, 3, 6): 617 case IP_VERSION(10, 3, 3): 618 case IP_VERSION(10, 3, 7): 619 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 620 break; 621 default: 622 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 623 break; 624 } 625 } 626 627 628 static int gmc_v10_0_early_init(struct amdgpu_ip_block *ip_block) 629 { 630 struct amdgpu_device *adev = ip_block->adev; 631 632 gmc_v10_0_set_mmhub_funcs(adev); 633 gmc_v10_0_set_gfxhub_funcs(adev); 634 gmc_v10_0_set_gmc_funcs(adev); 635 gmc_v10_0_set_irq_funcs(adev); 636 gmc_v10_0_set_umc_funcs(adev); 637 638 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 639 adev->gmc.shared_aperture_end = 640 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 641 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 642 adev->gmc.private_aperture_end = 643 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 644 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 645 646 return 0; 647 } 648 649 static int gmc_v10_0_late_init(struct amdgpu_ip_block *ip_block) 650 { 651 struct amdgpu_device *adev = ip_block->adev; 652 int r; 653 654 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 655 if (r) 656 return r; 657 658 r = amdgpu_gmc_ras_late_init(adev); 659 if (r) 660 return r; 661 662 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 663 } 664 665 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 666 struct amdgpu_gmc *mc) 667 { 668 u64 base = 0; 669 670 base = adev->gfxhub.funcs->get_fb_location(adev); 671 672 /* add the xgmi offset of the physical node */ 673 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 674 675 amdgpu_gmc_set_agp_default(adev, mc); 676 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 677 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 678 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) 679 amdgpu_gmc_agp_location(adev, mc); 680 681 /* base offset of vram pages */ 682 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 683 684 /* add the xgmi offset of the physical node */ 685 adev->vm_manager.vram_base_offset += 686 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 687 } 688 689 /** 690 * gmc_v10_0_mc_init - initialize the memory controller driver params 691 * 692 * @adev: amdgpu_device pointer 693 * 694 * Look up the amount of vram, vram width, and decide how to place 695 * vram and gart within the GPU's physical address space. 696 * Returns 0 for success. 697 */ 698 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 699 { 700 int r; 701 702 /* size in MB on si */ 703 adev->gmc.mc_vram_size = 704 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 705 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 706 707 if (!(adev->flags & AMD_IS_APU)) { 708 r = amdgpu_device_resize_fb_bar(adev); 709 if (r) 710 return r; 711 } 712 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 713 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 714 715 #ifdef CONFIG_X86_64 716 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 717 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 718 adev->gmc.aper_size = adev->gmc.real_vram_size; 719 } 720 #endif 721 722 adev->gmc.visible_vram_size = adev->gmc.aper_size; 723 724 /* set the gart size */ 725 if (amdgpu_gart_size == -1) { 726 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 727 default: 728 adev->gmc.gart_size = 512ULL << 20; 729 break; 730 case IP_VERSION(10, 3, 1): /* DCE SG support */ 731 case IP_VERSION(10, 3, 3): /* DCE SG support */ 732 case IP_VERSION(10, 3, 6): /* DCE SG support */ 733 case IP_VERSION(10, 3, 7): /* DCE SG support */ 734 adev->gmc.gart_size = 1024ULL << 20; 735 break; 736 } 737 } else { 738 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 739 } 740 741 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 742 743 return 0; 744 } 745 746 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 747 { 748 int r; 749 750 if (adev->gart.bo) { 751 WARN(1, "NAVI10 PCIE GART already initialized\n"); 752 return 0; 753 } 754 755 /* Initialize common gart structure */ 756 r = amdgpu_gart_init(adev); 757 if (r) 758 return r; 759 760 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 761 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | 762 AMDGPU_PTE_EXECUTABLE; 763 764 return amdgpu_gart_table_vram_alloc(adev); 765 } 766 767 static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block) 768 { 769 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 770 struct amdgpu_device *adev = ip_block->adev; 771 772 adev->gfxhub.funcs->init(adev); 773 774 adev->mmhub.funcs->init(adev); 775 776 spin_lock_init(&adev->gmc.invalidate_lock); 777 778 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 779 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 780 adev->gmc.vram_width = 64; 781 } else if (amdgpu_emu_mode == 1) { 782 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 783 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 784 } else { 785 r = amdgpu_atomfirmware_get_vram_info(adev, 786 &vram_width, &vram_type, &vram_vendor); 787 adev->gmc.vram_width = vram_width; 788 789 adev->gmc.vram_type = vram_type; 790 adev->gmc.vram_vendor = vram_vendor; 791 } 792 793 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 794 case IP_VERSION(10, 3, 0): 795 adev->gmc.mall_size = 128 * 1024 * 1024; 796 break; 797 case IP_VERSION(10, 3, 2): 798 adev->gmc.mall_size = 96 * 1024 * 1024; 799 break; 800 case IP_VERSION(10, 3, 4): 801 adev->gmc.mall_size = 32 * 1024 * 1024; 802 break; 803 case IP_VERSION(10, 3, 5): 804 adev->gmc.mall_size = 16 * 1024 * 1024; 805 break; 806 default: 807 adev->gmc.mall_size = 0; 808 break; 809 } 810 811 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 812 case IP_VERSION(10, 1, 10): 813 case IP_VERSION(10, 1, 1): 814 case IP_VERSION(10, 1, 2): 815 case IP_VERSION(10, 1, 3): 816 case IP_VERSION(10, 1, 4): 817 case IP_VERSION(10, 3, 0): 818 case IP_VERSION(10, 3, 2): 819 case IP_VERSION(10, 3, 1): 820 case IP_VERSION(10, 3, 4): 821 case IP_VERSION(10, 3, 5): 822 case IP_VERSION(10, 3, 6): 823 case IP_VERSION(10, 3, 3): 824 case IP_VERSION(10, 3, 7): 825 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 826 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 827 /* 828 * To fulfill 4-level page support, 829 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 830 * block size 512 (9bit) 831 */ 832 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 833 break; 834 default: 835 break; 836 } 837 838 /* This interrupt is VMC page fault.*/ 839 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 840 VMC_1_0__SRCID__VM_FAULT, 841 &adev->gmc.vm_fault); 842 843 if (r) 844 return r; 845 846 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 847 UTCL2_1_0__SRCID__FAULT, 848 &adev->gmc.vm_fault); 849 if (r) 850 return r; 851 852 if (!amdgpu_sriov_vf(adev)) { 853 /* interrupt sent to DF. */ 854 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 855 &adev->gmc.ecc_irq); 856 if (r) 857 return r; 858 } 859 860 /* 861 * Set the internal MC address mask This is the max address of the GPU's 862 * internal address space. 863 */ 864 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 865 866 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 867 if (r) { 868 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 869 return r; 870 } 871 872 adev->need_swiotlb = drm_need_swiotlb(44); 873 874 r = gmc_v10_0_mc_init(adev); 875 if (r) 876 return r; 877 878 amdgpu_gmc_get_vbios_allocations(adev); 879 880 /* Memory manager */ 881 r = amdgpu_bo_init(adev); 882 if (r) 883 return r; 884 885 r = gmc_v10_0_gart_init(adev); 886 if (r) 887 return r; 888 889 /* 890 * number of VMs 891 * VMID 0 is reserved for System 892 * amdgpu graphics/compute will use VMIDs 1-7 893 * amdkfd will use VMIDs 8-15 894 */ 895 adev->vm_manager.first_kfd_vmid = 8; 896 897 amdgpu_vm_manager_init(adev); 898 899 r = amdgpu_gmc_ras_sw_init(adev); 900 if (r) 901 return r; 902 903 return 0; 904 } 905 906 /** 907 * gmc_v10_0_gart_fini - vm fini callback 908 * 909 * @adev: amdgpu_device pointer 910 * 911 * Tears down the driver GART/VM setup (CIK). 912 */ 913 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 914 { 915 amdgpu_gart_table_vram_free(adev); 916 } 917 918 static int gmc_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) 919 { 920 struct amdgpu_device *adev = ip_block->adev; 921 922 amdgpu_vm_manager_fini(adev); 923 gmc_v10_0_gart_fini(adev); 924 amdgpu_gem_force_release(adev); 925 amdgpu_bo_fini(adev); 926 927 return 0; 928 } 929 930 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 931 { 932 } 933 934 /** 935 * gmc_v10_0_gart_enable - gart enable 936 * 937 * @adev: amdgpu_device pointer 938 */ 939 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 940 { 941 int r; 942 bool value; 943 944 if (adev->gart.bo == NULL) { 945 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 946 return -EINVAL; 947 } 948 949 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 950 951 if (!adev->in_s0ix) { 952 r = adev->gfxhub.funcs->gart_enable(adev); 953 if (r) 954 return r; 955 } 956 957 r = adev->mmhub.funcs->gart_enable(adev); 958 if (r) 959 return r; 960 961 adev->hdp.funcs->init_registers(adev); 962 963 /* Flush HDP after it is initialized */ 964 amdgpu_device_flush_hdp(adev, NULL); 965 966 value = amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS; 967 968 if (!adev->in_s0ix) 969 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 970 adev->mmhub.funcs->set_fault_enable_default(adev, value); 971 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 972 if (!adev->in_s0ix) 973 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 974 975 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 976 (unsigned int)(adev->gmc.gart_size >> 20), 977 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 978 979 return 0; 980 } 981 982 static int gmc_v10_0_hw_init(struct amdgpu_ip_block *ip_block) 983 { 984 struct amdgpu_device *adev = ip_block->adev; 985 int r; 986 987 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; 988 989 /* The sequence of these two function calls matters.*/ 990 gmc_v10_0_init_golden_registers(adev); 991 992 /* 993 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 994 * register setup within GMC, or else system hang when harvesting SA. 995 */ 996 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 997 adev->gfxhub.funcs->utcl2_harvest(adev); 998 999 r = gmc_v10_0_gart_enable(adev); 1000 if (r) 1001 return r; 1002 1003 if (amdgpu_emu_mode == 1) { 1004 r = amdgpu_gmc_vram_checking(adev); 1005 if (r) 1006 return r; 1007 } 1008 1009 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1010 adev->umc.funcs->init_registers(adev); 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * gmc_v10_0_gart_disable - gart disable 1017 * 1018 * @adev: amdgpu_device pointer 1019 * 1020 * This disables all VM page table. 1021 */ 1022 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1023 { 1024 if (!adev->in_s0ix) 1025 adev->gfxhub.funcs->gart_disable(adev); 1026 adev->mmhub.funcs->gart_disable(adev); 1027 } 1028 1029 static int gmc_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) 1030 { 1031 struct amdgpu_device *adev = ip_block->adev; 1032 1033 gmc_v10_0_gart_disable(adev); 1034 1035 if (amdgpu_sriov_vf(adev)) { 1036 /* full access mode, so don't touch any GMC register */ 1037 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1038 return 0; 1039 } 1040 1041 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1042 1043 if (adev->gmc.ecc_irq.funcs && 1044 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) 1045 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); 1046 1047 return 0; 1048 } 1049 1050 static int gmc_v10_0_suspend(struct amdgpu_ip_block *ip_block) 1051 { 1052 gmc_v10_0_hw_fini(ip_block); 1053 1054 return 0; 1055 } 1056 1057 static int gmc_v10_0_resume(struct amdgpu_ip_block *ip_block) 1058 { 1059 int r; 1060 1061 r = gmc_v10_0_hw_init(ip_block); 1062 if (r) 1063 return r; 1064 1065 amdgpu_vmid_reset_all(ip_block->adev); 1066 1067 return 0; 1068 } 1069 1070 static bool gmc_v10_0_is_idle(struct amdgpu_ip_block *ip_block) 1071 { 1072 /* MC is always ready in GMC v10.*/ 1073 return true; 1074 } 1075 1076 static int gmc_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) 1077 { 1078 /* There is no need to wait for MC idle in GMC v10.*/ 1079 return 0; 1080 } 1081 1082 static int gmc_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block, 1083 enum amd_clockgating_state state) 1084 { 1085 int r; 1086 struct amdgpu_device *adev = ip_block->adev; 1087 1088 /* 1089 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1090 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1091 * seen any issue on the DF 3.0.2 series platform. 1092 */ 1093 if (adev->in_s0ix && 1094 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) { 1095 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1096 return 0; 1097 } 1098 1099 r = adev->mmhub.funcs->set_clockgating(adev, state); 1100 if (r) 1101 return r; 1102 1103 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1104 return athub_v2_1_set_clockgating(adev, state); 1105 else 1106 return athub_v2_0_set_clockgating(adev, state); 1107 } 1108 1109 static void gmc_v10_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 1110 { 1111 struct amdgpu_device *adev = ip_block->adev; 1112 1113 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || 1114 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) 1115 return; 1116 1117 adev->mmhub.funcs->get_clockgating(adev, flags); 1118 1119 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1120 athub_v2_1_get_clockgating(adev, flags); 1121 else 1122 athub_v2_0_get_clockgating(adev, flags); 1123 } 1124 1125 static int gmc_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block, 1126 enum amd_powergating_state state) 1127 { 1128 return 0; 1129 } 1130 1131 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1132 .name = "gmc_v10_0", 1133 .early_init = gmc_v10_0_early_init, 1134 .late_init = gmc_v10_0_late_init, 1135 .sw_init = gmc_v10_0_sw_init, 1136 .sw_fini = gmc_v10_0_sw_fini, 1137 .hw_init = gmc_v10_0_hw_init, 1138 .hw_fini = gmc_v10_0_hw_fini, 1139 .suspend = gmc_v10_0_suspend, 1140 .resume = gmc_v10_0_resume, 1141 .is_idle = gmc_v10_0_is_idle, 1142 .wait_for_idle = gmc_v10_0_wait_for_idle, 1143 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1144 .set_powergating_state = gmc_v10_0_set_powergating_state, 1145 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1146 }; 1147 1148 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = { 1149 .type = AMD_IP_BLOCK_TYPE_GMC, 1150 .major = 10, 1151 .minor = 0, 1152 .rev = 0, 1153 .funcs = &gmc_v10_0_ip_funcs, 1154 }; 1155