1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/pci.h> 25 26 #include <drm/drm_cache.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atomfirmware.h" 30 #include "gmc_v10_0.h" 31 #include "umc_v8_7.h" 32 33 #include "athub/athub_2_0_0_sh_mask.h" 34 #include "athub/athub_2_0_0_offset.h" 35 #include "dcn/dcn_2_0_0_offset.h" 36 #include "dcn/dcn_2_0_0_sh_mask.h" 37 #include "oss/osssys_5_0_0_offset.h" 38 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h" 39 #include "navi10_enum.h" 40 41 #include "soc15.h" 42 #include "soc15d.h" 43 #include "soc15_common.h" 44 45 #include "nbio_v2_3.h" 46 47 #include "gfxhub_v2_0.h" 48 #include "gfxhub_v2_1.h" 49 #include "mmhub_v2_0.h" 50 #include "mmhub_v2_3.h" 51 #include "athub_v2_0.h" 52 #include "athub_v2_1.h" 53 54 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev, 55 struct amdgpu_irq_src *src, 56 unsigned int type, 57 enum amdgpu_interrupt_state state) 58 { 59 return 0; 60 } 61 62 static int 63 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 64 struct amdgpu_irq_src *src, unsigned int type, 65 enum amdgpu_interrupt_state state) 66 { 67 switch (state) { 68 case AMDGPU_IRQ_STATE_DISABLE: 69 /* MM HUB */ 70 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), false); 71 /* GFX HUB */ 72 /* This works because this interrupt is only 73 * enabled at init/resume and disabled in 74 * fini/suspend, so the overall state doesn't 75 * change over the course of suspend/resume. 76 */ 77 if (!adev->in_s0ix) 78 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), false); 79 break; 80 case AMDGPU_IRQ_STATE_ENABLE: 81 /* MM HUB */ 82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB0(0), true); 83 /* GFX HUB */ 84 /* This works because this interrupt is only 85 * enabled at init/resume and disabled in 86 * fini/suspend, so the overall state doesn't 87 * change over the course of suspend/resume. 88 */ 89 if (!adev->in_s0ix) 90 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), true); 91 break; 92 default: 93 break; 94 } 95 96 return 0; 97 } 98 99 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, 100 struct amdgpu_irq_src *source, 101 struct amdgpu_iv_entry *entry) 102 { 103 uint32_t vmhub_index = entry->client_id == SOC15_IH_CLIENTID_VMC ? 104 AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0); 105 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub_index]; 106 bool retry_fault = !!(entry->src_data[1] & 0x80); 107 bool write_fault = !!(entry->src_data[1] & 0x20); 108 struct amdgpu_task_info task_info; 109 uint32_t status = 0; 110 u64 addr; 111 112 addr = (u64)entry->src_data[0] << 12; 113 addr |= ((u64)entry->src_data[1] & 0xf) << 44; 114 115 if (retry_fault) { 116 /* Returning 1 here also prevents sending the IV to the KFD */ 117 118 /* Process it onyl if it's the first fault for this address */ 119 if (entry->ih != &adev->irq.ih_soft && 120 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid, 121 entry->timestamp)) 122 return 1; 123 124 /* Delegate it to a different ring if the hardware hasn't 125 * already done it. 126 */ 127 if (entry->ih == &adev->irq.ih) { 128 amdgpu_irq_delegate(adev, entry, 8); 129 return 1; 130 } 131 132 /* Try to handle the recoverable page faults by filling page 133 * tables 134 */ 135 if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, write_fault)) 136 return 1; 137 } 138 139 if (!amdgpu_sriov_vf(adev)) { 140 /* 141 * Issue a dummy read to wait for the status register to 142 * be updated to avoid reading an incorrect value due to 143 * the new fast GRBM interface. 144 */ 145 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) && 146 (amdgpu_ip_version(adev, GC_HWIP, 0) < 147 IP_VERSION(10, 3, 0))) 148 RREG32(hub->vm_l2_pro_fault_status); 149 150 status = RREG32(hub->vm_l2_pro_fault_status); 151 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); 152 153 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, 154 entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); 155 } 156 157 if (!printk_ratelimit()) 158 return 0; 159 160 memset(&task_info, 0, sizeof(struct amdgpu_task_info)); 161 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info); 162 163 dev_err(adev->dev, 164 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", 165 entry->vmid_src ? "mmhub" : "gfxhub", 166 entry->src_id, entry->ring_id, entry->vmid, 167 entry->pasid, task_info.process_name, task_info.tgid, 168 task_info.task_name, task_info.pid); 169 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n", 170 addr, entry->client_id, 171 soc15_ih_clientid_name[entry->client_id]); 172 173 if (!amdgpu_sriov_vf(adev)) 174 hub->vmhub_funcs->print_l2_protection_fault_status(adev, 175 status); 176 177 return 0; 178 } 179 180 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = { 181 .set = gmc_v10_0_vm_fault_interrupt_state, 182 .process = gmc_v10_0_process_interrupt, 183 }; 184 185 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = { 186 .set = gmc_v10_0_ecc_interrupt_state, 187 .process = amdgpu_umc_process_ecc_irq, 188 }; 189 190 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev) 191 { 192 adev->gmc.vm_fault.num_types = 1; 193 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs; 194 195 if (!amdgpu_sriov_vf(adev)) { 196 adev->gmc.ecc_irq.num_types = 1; 197 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs; 198 } 199 } 200 201 /** 202 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore 203 * 204 * @adev: amdgpu_device pointer 205 * @vmhub: vmhub type 206 * 207 */ 208 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev, 209 uint32_t vmhub) 210 { 211 return ((vmhub == AMDGPU_MMHUB0(0)) && 212 (!amdgpu_sriov_vf(adev))); 213 } 214 215 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info( 216 struct amdgpu_device *adev, 217 uint8_t vmid, uint16_t *p_pasid) 218 { 219 uint32_t value; 220 221 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 222 + vmid); 223 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 224 225 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 226 } 227 228 /* 229 * GART 230 * VMID 0 is the physical GPU addresses as used by the kernel. 231 * VMIDs 1-15 are used for userspace clients and are handled 232 * by the amdgpu vm/hsa code. 233 */ 234 235 /** 236 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback 237 * 238 * @adev: amdgpu_device pointer 239 * @vmid: vm instance to flush 240 * @vmhub: vmhub type 241 * @flush_type: the flush type 242 * 243 * Flush the TLB for the requested page table. 244 */ 245 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 246 uint32_t vmhub, uint32_t flush_type) 247 { 248 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub); 249 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub]; 250 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type); 251 /* Use register 17 for GART */ 252 const unsigned int eng = 17; 253 unsigned char hub_ip = 0; 254 u32 sem, req, ack; 255 unsigned int i; 256 u32 tmp; 257 258 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng; 259 req = hub->vm_inv_eng0_req + hub->eng_distance * eng; 260 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng; 261 262 /* flush hdp cache */ 263 adev->hdp.funcs->flush_hdp(adev, NULL); 264 265 /* For SRIOV run time, driver shouldn't access the register through MMIO 266 * Directly use kiq to do the vm invalidation instead 267 */ 268 if (adev->gfx.kiq[0].ring.sched.ready && !adev->enable_mes && 269 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { 270 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req, 271 1 << vmid); 272 return; 273 } 274 275 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; 276 277 spin_lock(&adev->gmc.invalidate_lock); 278 /* 279 * It may lose gpuvm invalidate acknowldege state across power-gating 280 * off cycle, add semaphore acquire before invalidation and semaphore 281 * release after invalidation to avoid entering power gated state 282 * to WA the Issue 283 */ 284 285 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 286 if (use_semaphore) { 287 for (i = 0; i < adev->usec_timeout; i++) { 288 /* a read return value of 1 means semaphore acuqire */ 289 tmp = RREG32_RLC_NO_KIQ(sem, hub_ip); 290 if (tmp & 0x1) 291 break; 292 udelay(1); 293 } 294 295 if (i >= adev->usec_timeout) 296 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n"); 297 } 298 299 WREG32_RLC_NO_KIQ(req, inv_req, hub_ip); 300 301 /* 302 * Issue a dummy read to wait for the ACK register to be cleared 303 * to avoid a false ACK due to the new fast GRBM interface. 304 */ 305 if ((vmhub == AMDGPU_GFXHUB(0)) && 306 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 3, 0))) 307 RREG32_RLC_NO_KIQ(req, hub_ip); 308 309 /* Wait for ACK with a delay.*/ 310 for (i = 0; i < adev->usec_timeout; i++) { 311 tmp = RREG32_RLC_NO_KIQ(ack, hub_ip); 312 tmp &= 1 << vmid; 313 if (tmp) 314 break; 315 316 udelay(1); 317 } 318 319 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 320 if (use_semaphore) 321 WREG32_RLC_NO_KIQ(sem, 0, hub_ip); 322 323 spin_unlock(&adev->gmc.invalidate_lock); 324 325 if (i >= adev->usec_timeout) 326 dev_err(adev->dev, "Timeout waiting for VM flush hub: %d!\n", 327 vmhub); 328 } 329 330 /** 331 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid 332 * 333 * @adev: amdgpu_device pointer 334 * @pasid: pasid to be flush 335 * @flush_type: the flush type 336 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB() 337 * @inst: is used to select which instance of KIQ to use for the invalidation 338 * 339 * Flush the TLB for the requested pasid. 340 */ 341 static void gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 342 uint16_t pasid, uint32_t flush_type, 343 bool all_hub, uint32_t inst) 344 { 345 uint16_t queried; 346 int vmid, i; 347 348 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 349 bool valid; 350 351 valid = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid, 352 &queried); 353 if (!valid || queried != pasid) 354 continue; 355 356 if (all_hub) { 357 for_each_set_bit(i, adev->vmhubs_mask, 358 AMDGPU_MAX_VMHUBS) 359 gmc_v10_0_flush_gpu_tlb(adev, vmid, i, 360 flush_type); 361 } else { 362 gmc_v10_0_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 363 flush_type); 364 } 365 } 366 } 367 368 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, 369 unsigned int vmid, uint64_t pd_addr) 370 { 371 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->vm_hub); 372 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 373 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); 374 unsigned int eng = ring->vm_inv_eng; 375 376 /* 377 * It may lose gpuvm invalidate acknowldege state across power-gating 378 * off cycle, add semaphore acquire before invalidation and semaphore 379 * release after invalidation to avoid entering power gated state 380 * to WA the Issue 381 */ 382 383 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 384 if (use_semaphore) 385 /* a read return value of 1 means semaphore acuqire */ 386 amdgpu_ring_emit_reg_wait(ring, 387 hub->vm_inv_eng0_sem + 388 hub->eng_distance * eng, 0x1, 0x1); 389 390 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + 391 (hub->ctx_addr_distance * vmid), 392 lower_32_bits(pd_addr)); 393 394 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + 395 (hub->ctx_addr_distance * vmid), 396 upper_32_bits(pd_addr)); 397 398 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req + 399 hub->eng_distance * eng, 400 hub->vm_inv_eng0_ack + 401 hub->eng_distance * eng, 402 req, 1 << vmid); 403 404 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */ 405 if (use_semaphore) 406 /* 407 * add semaphore release after invalidation, 408 * write with 0 means semaphore release 409 */ 410 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + 411 hub->eng_distance * eng, 0); 412 413 return pd_addr; 414 } 415 416 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid, 417 unsigned int pasid) 418 { 419 struct amdgpu_device *adev = ring->adev; 420 uint32_t reg; 421 422 /* MES fw manages IH_VMID_x_LUT updating */ 423 if (ring->is_mes_queue) 424 return; 425 426 if (ring->vm_hub == AMDGPU_GFXHUB(0)) 427 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; 428 else 429 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; 430 431 amdgpu_ring_emit_wreg(ring, reg, pasid); 432 } 433 434 /* 435 * PTE format on NAVI 10: 436 * 63:59 reserved 437 * 58 reserved and for sienna_cichlid is used for MALL noalloc 438 * 57 reserved 439 * 56 F 440 * 55 L 441 * 54 reserved 442 * 53:52 SW 443 * 51 T 444 * 50:48 mtype 445 * 47:12 4k physical page base address 446 * 11:7 fragment 447 * 6 write 448 * 5 read 449 * 4 exe 450 * 3 Z 451 * 2 snooped 452 * 1 system 453 * 0 valid 454 * 455 * PDE format on NAVI 10: 456 * 63:59 block fragment size 457 * 58:55 reserved 458 * 54 P 459 * 53:48 reserved 460 * 47:6 physical base address of PD or PTE 461 * 5:3 reserved 462 * 2 C 463 * 1 system 464 * 0 valid 465 */ 466 467 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags) 468 { 469 switch (flags) { 470 case AMDGPU_VM_MTYPE_DEFAULT: 471 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 472 case AMDGPU_VM_MTYPE_NC: 473 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 474 case AMDGPU_VM_MTYPE_WC: 475 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC); 476 case AMDGPU_VM_MTYPE_CC: 477 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC); 478 case AMDGPU_VM_MTYPE_UC: 479 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 480 default: 481 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC); 482 } 483 } 484 485 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level, 486 uint64_t *addr, uint64_t *flags) 487 { 488 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM)) 489 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr); 490 BUG_ON(*addr & 0xFFFF00000000003FULL); 491 492 if (!adev->gmc.translate_further) 493 return; 494 495 if (level == AMDGPU_VM_PDB1) { 496 /* Set the block fragment size */ 497 if (!(*flags & AMDGPU_PDE_PTE)) 498 *flags |= AMDGPU_PDE_BFS(0x9); 499 500 } else if (level == AMDGPU_VM_PDB0) { 501 if (*flags & AMDGPU_PDE_PTE) 502 *flags &= ~AMDGPU_PDE_PTE; 503 else 504 *flags |= AMDGPU_PTE_TF; 505 } 506 } 507 508 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev, 509 struct amdgpu_bo_va_mapping *mapping, 510 uint64_t *flags) 511 { 512 struct amdgpu_bo *bo = mapping->bo_va->base.bo; 513 514 *flags &= ~AMDGPU_PTE_EXECUTABLE; 515 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; 516 517 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK; 518 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK); 519 520 *flags &= ~AMDGPU_PTE_NOALLOC; 521 *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC); 522 523 if (mapping->flags & AMDGPU_PTE_PRT) { 524 *flags |= AMDGPU_PTE_PRT; 525 *flags |= AMDGPU_PTE_SNOOPED; 526 *flags |= AMDGPU_PTE_LOG; 527 *flags |= AMDGPU_PTE_SYSTEM; 528 *flags &= ~AMDGPU_PTE_VALID; 529 } 530 531 if (bo && bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 532 AMDGPU_GEM_CREATE_EXT_COHERENT | 533 AMDGPU_GEM_CREATE_UNCACHED)) 534 *flags = (*flags & ~AMDGPU_PTE_MTYPE_NV10_MASK) | 535 AMDGPU_PTE_MTYPE_NV10(MTYPE_UC); 536 } 537 538 static unsigned int gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev) 539 { 540 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL); 541 unsigned int size; 542 543 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) { 544 size = AMDGPU_VBIOS_VGA_ALLOCATION; 545 } else { 546 u32 viewport; 547 u32 pitch; 548 549 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION); 550 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH); 551 size = (REG_GET_FIELD(viewport, 552 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) * 553 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) * 554 4); 555 } 556 557 return size; 558 } 559 560 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = { 561 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb, 562 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid, 563 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb, 564 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping, 565 .map_mtype = gmc_v10_0_map_mtype, 566 .get_vm_pde = gmc_v10_0_get_vm_pde, 567 .get_vm_pte = gmc_v10_0_get_vm_pte, 568 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size, 569 }; 570 571 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev) 572 { 573 if (adev->gmc.gmc_funcs == NULL) 574 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs; 575 } 576 577 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev) 578 { 579 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) { 580 case IP_VERSION(8, 7, 0): 581 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM; 582 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM; 583 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM; 584 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA; 585 adev->umc.retire_unit = 1; 586 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0]; 587 adev->umc.ras = &umc_v8_7_ras; 588 break; 589 default: 590 break; 591 } 592 } 593 594 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev) 595 { 596 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { 597 case IP_VERSION(2, 3, 0): 598 case IP_VERSION(2, 4, 0): 599 case IP_VERSION(2, 4, 1): 600 adev->mmhub.funcs = &mmhub_v2_3_funcs; 601 break; 602 default: 603 adev->mmhub.funcs = &mmhub_v2_0_funcs; 604 break; 605 } 606 } 607 608 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) 609 { 610 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 611 case IP_VERSION(10, 3, 0): 612 case IP_VERSION(10, 3, 2): 613 case IP_VERSION(10, 3, 1): 614 case IP_VERSION(10, 3, 4): 615 case IP_VERSION(10, 3, 5): 616 case IP_VERSION(10, 3, 6): 617 case IP_VERSION(10, 3, 3): 618 case IP_VERSION(10, 3, 7): 619 adev->gfxhub.funcs = &gfxhub_v2_1_funcs; 620 break; 621 default: 622 adev->gfxhub.funcs = &gfxhub_v2_0_funcs; 623 break; 624 } 625 } 626 627 628 static int gmc_v10_0_early_init(void *handle) 629 { 630 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 631 632 gmc_v10_0_set_mmhub_funcs(adev); 633 gmc_v10_0_set_gfxhub_funcs(adev); 634 gmc_v10_0_set_gmc_funcs(adev); 635 gmc_v10_0_set_irq_funcs(adev); 636 gmc_v10_0_set_umc_funcs(adev); 637 638 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 639 adev->gmc.shared_aperture_end = 640 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 641 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 642 adev->gmc.private_aperture_end = 643 adev->gmc.private_aperture_start + (4ULL << 30) - 1; 644 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 645 646 return 0; 647 } 648 649 static int gmc_v10_0_late_init(void *handle) 650 { 651 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 652 int r; 653 654 r = amdgpu_gmc_allocate_vm_inv_eng(adev); 655 if (r) 656 return r; 657 658 r = amdgpu_gmc_ras_late_init(adev); 659 if (r) 660 return r; 661 662 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); 663 } 664 665 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, 666 struct amdgpu_gmc *mc) 667 { 668 u64 base = 0; 669 670 base = adev->gfxhub.funcs->get_fb_location(adev); 671 672 /* add the xgmi offset of the physical node */ 673 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 674 675 amdgpu_gmc_vram_location(adev, &adev->gmc, base); 676 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); 677 if (!amdgpu_sriov_vf(adev)) 678 amdgpu_gmc_agp_location(adev, mc); 679 680 /* base offset of vram pages */ 681 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev); 682 683 /* add the xgmi offset of the physical node */ 684 adev->vm_manager.vram_base_offset += 685 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; 686 } 687 688 /** 689 * gmc_v10_0_mc_init - initialize the memory controller driver params 690 * 691 * @adev: amdgpu_device pointer 692 * 693 * Look up the amount of vram, vram width, and decide how to place 694 * vram and gart within the GPU's physical address space. 695 * Returns 0 for success. 696 */ 697 static int gmc_v10_0_mc_init(struct amdgpu_device *adev) 698 { 699 int r; 700 701 /* size in MB on si */ 702 adev->gmc.mc_vram_size = 703 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL; 704 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; 705 706 if (!(adev->flags & AMD_IS_APU)) { 707 r = amdgpu_device_resize_fb_bar(adev); 708 if (r) 709 return r; 710 } 711 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); 712 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); 713 714 #ifdef CONFIG_X86_64 715 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) { 716 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); 717 adev->gmc.aper_size = adev->gmc.real_vram_size; 718 } 719 #endif 720 721 adev->gmc.visible_vram_size = adev->gmc.aper_size; 722 723 /* set the gart size */ 724 if (amdgpu_gart_size == -1) { 725 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 726 default: 727 adev->gmc.gart_size = 512ULL << 20; 728 break; 729 case IP_VERSION(10, 3, 1): /* DCE SG support */ 730 case IP_VERSION(10, 3, 3): /* DCE SG support */ 731 case IP_VERSION(10, 3, 6): /* DCE SG support */ 732 case IP_VERSION(10, 3, 7): /* DCE SG support */ 733 adev->gmc.gart_size = 1024ULL << 20; 734 break; 735 } 736 } else { 737 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; 738 } 739 740 gmc_v10_0_vram_gtt_location(adev, &adev->gmc); 741 742 return 0; 743 } 744 745 static int gmc_v10_0_gart_init(struct amdgpu_device *adev) 746 { 747 int r; 748 749 if (adev->gart.bo) { 750 WARN(1, "NAVI10 PCIE GART already initialized\n"); 751 return 0; 752 } 753 754 /* Initialize common gart structure */ 755 r = amdgpu_gart_init(adev); 756 if (r) 757 return r; 758 759 adev->gart.table_size = adev->gart.num_gpu_pages * 8; 760 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) | 761 AMDGPU_PTE_EXECUTABLE; 762 763 return amdgpu_gart_table_vram_alloc(adev); 764 } 765 766 static int gmc_v10_0_sw_init(void *handle) 767 { 768 int r, vram_width = 0, vram_type = 0, vram_vendor = 0; 769 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 770 771 adev->gfxhub.funcs->init(adev); 772 773 adev->mmhub.funcs->init(adev); 774 775 spin_lock_init(&adev->gmc.invalidate_lock); 776 777 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) { 778 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4; 779 adev->gmc.vram_width = 64; 780 } else if (amdgpu_emu_mode == 1) { 781 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6; 782 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */ 783 } else { 784 r = amdgpu_atomfirmware_get_vram_info(adev, 785 &vram_width, &vram_type, &vram_vendor); 786 adev->gmc.vram_width = vram_width; 787 788 adev->gmc.vram_type = vram_type; 789 adev->gmc.vram_vendor = vram_vendor; 790 } 791 792 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 793 case IP_VERSION(10, 3, 0): 794 adev->gmc.mall_size = 128 * 1024 * 1024; 795 break; 796 case IP_VERSION(10, 3, 2): 797 adev->gmc.mall_size = 96 * 1024 * 1024; 798 break; 799 case IP_VERSION(10, 3, 4): 800 adev->gmc.mall_size = 32 * 1024 * 1024; 801 break; 802 case IP_VERSION(10, 3, 5): 803 adev->gmc.mall_size = 16 * 1024 * 1024; 804 break; 805 default: 806 adev->gmc.mall_size = 0; 807 break; 808 } 809 810 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 811 case IP_VERSION(10, 1, 10): 812 case IP_VERSION(10, 1, 1): 813 case IP_VERSION(10, 1, 2): 814 case IP_VERSION(10, 1, 3): 815 case IP_VERSION(10, 1, 4): 816 case IP_VERSION(10, 3, 0): 817 case IP_VERSION(10, 3, 2): 818 case IP_VERSION(10, 3, 1): 819 case IP_VERSION(10, 3, 4): 820 case IP_VERSION(10, 3, 5): 821 case IP_VERSION(10, 3, 6): 822 case IP_VERSION(10, 3, 3): 823 case IP_VERSION(10, 3, 7): 824 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); 825 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask); 826 /* 827 * To fulfill 4-level page support, 828 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12, 829 * block size 512 (9bit) 830 */ 831 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); 832 break; 833 default: 834 break; 835 } 836 837 /* This interrupt is VMC page fault.*/ 838 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 839 VMC_1_0__SRCID__VM_FAULT, 840 &adev->gmc.vm_fault); 841 842 if (r) 843 return r; 844 845 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 846 UTCL2_1_0__SRCID__FAULT, 847 &adev->gmc.vm_fault); 848 if (r) 849 return r; 850 851 if (!amdgpu_sriov_vf(adev)) { 852 /* interrupt sent to DF. */ 853 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0, 854 &adev->gmc.ecc_irq); 855 if (r) 856 return r; 857 } 858 859 /* 860 * Set the internal MC address mask This is the max address of the GPU's 861 * internal address space. 862 */ 863 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ 864 865 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44)); 866 if (r) { 867 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n"); 868 return r; 869 } 870 871 adev->need_swiotlb = drm_need_swiotlb(44); 872 873 r = gmc_v10_0_mc_init(adev); 874 if (r) 875 return r; 876 877 amdgpu_gmc_get_vbios_allocations(adev); 878 879 /* Memory manager */ 880 r = amdgpu_bo_init(adev); 881 if (r) 882 return r; 883 884 r = gmc_v10_0_gart_init(adev); 885 if (r) 886 return r; 887 888 /* 889 * number of VMs 890 * VMID 0 is reserved for System 891 * amdgpu graphics/compute will use VMIDs 1-7 892 * amdkfd will use VMIDs 8-15 893 */ 894 adev->vm_manager.first_kfd_vmid = 8; 895 896 amdgpu_vm_manager_init(adev); 897 898 r = amdgpu_gmc_ras_sw_init(adev); 899 if (r) 900 return r; 901 902 return 0; 903 } 904 905 /** 906 * gmc_v10_0_gart_fini - vm fini callback 907 * 908 * @adev: amdgpu_device pointer 909 * 910 * Tears down the driver GART/VM setup (CIK). 911 */ 912 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) 913 { 914 amdgpu_gart_table_vram_free(adev); 915 } 916 917 static int gmc_v10_0_sw_fini(void *handle) 918 { 919 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 920 921 amdgpu_vm_manager_fini(adev); 922 gmc_v10_0_gart_fini(adev); 923 amdgpu_gem_force_release(adev); 924 amdgpu_bo_fini(adev); 925 926 return 0; 927 } 928 929 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev) 930 { 931 } 932 933 /** 934 * gmc_v10_0_gart_enable - gart enable 935 * 936 * @adev: amdgpu_device pointer 937 */ 938 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 939 { 940 int r; 941 bool value; 942 943 if (adev->gart.bo == NULL) { 944 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); 945 return -EINVAL; 946 } 947 948 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr); 949 950 if (!adev->in_s0ix) { 951 r = adev->gfxhub.funcs->gart_enable(adev); 952 if (r) 953 return r; 954 } 955 956 r = adev->mmhub.funcs->gart_enable(adev); 957 if (r) 958 return r; 959 960 adev->hdp.funcs->init_registers(adev); 961 962 /* Flush HDP after it is initialized */ 963 adev->hdp.funcs->flush_hdp(adev, NULL); 964 965 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 966 false : true; 967 968 if (!adev->in_s0ix) 969 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 970 adev->mmhub.funcs->set_fault_enable_default(adev, value); 971 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB0(0), 0); 972 if (!adev->in_s0ix) 973 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0); 974 975 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 976 (unsigned int)(adev->gmc.gart_size >> 20), 977 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo)); 978 979 return 0; 980 } 981 982 static int gmc_v10_0_hw_init(void *handle) 983 { 984 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 985 int r; 986 987 adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; 988 989 /* The sequence of these two function calls matters.*/ 990 gmc_v10_0_init_golden_registers(adev); 991 992 /* 993 * harvestable groups in gc_utcl2 need to be programmed before any GFX block 994 * register setup within GMC, or else system hang when harvesting SA. 995 */ 996 if (!adev->in_s0ix && adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest) 997 adev->gfxhub.funcs->utcl2_harvest(adev); 998 999 r = gmc_v10_0_gart_enable(adev); 1000 if (r) 1001 return r; 1002 1003 if (amdgpu_emu_mode == 1) { 1004 r = amdgpu_gmc_vram_checking(adev); 1005 if (r) 1006 return r; 1007 } 1008 1009 if (adev->umc.funcs && adev->umc.funcs->init_registers) 1010 adev->umc.funcs->init_registers(adev); 1011 1012 return 0; 1013 } 1014 1015 /** 1016 * gmc_v10_0_gart_disable - gart disable 1017 * 1018 * @adev: amdgpu_device pointer 1019 * 1020 * This disables all VM page table. 1021 */ 1022 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) 1023 { 1024 if (!adev->in_s0ix) 1025 adev->gfxhub.funcs->gart_disable(adev); 1026 adev->mmhub.funcs->gart_disable(adev); 1027 } 1028 1029 static int gmc_v10_0_hw_fini(void *handle) 1030 { 1031 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1032 1033 gmc_v10_0_gart_disable(adev); 1034 1035 if (amdgpu_sriov_vf(adev)) { 1036 /* full access mode, so don't touch any GMC register */ 1037 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 1038 return 0; 1039 } 1040 1041 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); 1042 1043 return 0; 1044 } 1045 1046 static int gmc_v10_0_suspend(void *handle) 1047 { 1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1049 1050 gmc_v10_0_hw_fini(adev); 1051 1052 return 0; 1053 } 1054 1055 static int gmc_v10_0_resume(void *handle) 1056 { 1057 int r; 1058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1059 1060 r = gmc_v10_0_hw_init(adev); 1061 if (r) 1062 return r; 1063 1064 amdgpu_vmid_reset_all(adev); 1065 1066 return 0; 1067 } 1068 1069 static bool gmc_v10_0_is_idle(void *handle) 1070 { 1071 /* MC is always ready in GMC v10.*/ 1072 return true; 1073 } 1074 1075 static int gmc_v10_0_wait_for_idle(void *handle) 1076 { 1077 /* There is no need to wait for MC idle in GMC v10.*/ 1078 return 0; 1079 } 1080 1081 static int gmc_v10_0_soft_reset(void *handle) 1082 { 1083 return 0; 1084 } 1085 1086 static int gmc_v10_0_set_clockgating_state(void *handle, 1087 enum amd_clockgating_state state) 1088 { 1089 int r; 1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1091 1092 /* 1093 * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled 1094 * is a new problem observed at DF 3.0.3, however with the same suspend sequence not 1095 * seen any issue on the DF 3.0.2 series platform. 1096 */ 1097 if (adev->in_s0ix && 1098 amdgpu_ip_version(adev, DF_HWIP, 0) > IP_VERSION(3, 0, 2)) { 1099 dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n"); 1100 return 0; 1101 } 1102 1103 r = adev->mmhub.funcs->set_clockgating(adev, state); 1104 if (r) 1105 return r; 1106 1107 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1108 return athub_v2_1_set_clockgating(adev, state); 1109 else 1110 return athub_v2_0_set_clockgating(adev, state); 1111 } 1112 1113 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags) 1114 { 1115 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1116 1117 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 3) || 1118 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 1, 4)) 1119 return; 1120 1121 adev->mmhub.funcs->get_clockgating(adev, flags); 1122 1123 if (amdgpu_ip_version(adev, ATHUB_HWIP, 0) >= IP_VERSION(2, 1, 0)) 1124 athub_v2_1_get_clockgating(adev, flags); 1125 else 1126 athub_v2_0_get_clockgating(adev, flags); 1127 } 1128 1129 static int gmc_v10_0_set_powergating_state(void *handle, 1130 enum amd_powergating_state state) 1131 { 1132 return 0; 1133 } 1134 1135 const struct amd_ip_funcs gmc_v10_0_ip_funcs = { 1136 .name = "gmc_v10_0", 1137 .early_init = gmc_v10_0_early_init, 1138 .late_init = gmc_v10_0_late_init, 1139 .sw_init = gmc_v10_0_sw_init, 1140 .sw_fini = gmc_v10_0_sw_fini, 1141 .hw_init = gmc_v10_0_hw_init, 1142 .hw_fini = gmc_v10_0_hw_fini, 1143 .suspend = gmc_v10_0_suspend, 1144 .resume = gmc_v10_0_resume, 1145 .is_idle = gmc_v10_0_is_idle, 1146 .wait_for_idle = gmc_v10_0_wait_for_idle, 1147 .soft_reset = gmc_v10_0_soft_reset, 1148 .set_clockgating_state = gmc_v10_0_set_clockgating_state, 1149 .set_powergating_state = gmc_v10_0_set_powergating_state, 1150 .get_clockgating_state = gmc_v10_0_get_clockgating_state, 1151 }; 1152 1153 const struct amdgpu_ip_block_version gmc_v10_0_ip_block = { 1154 .type = AMD_IP_BLOCK_TYPE_GMC, 1155 .major = 10, 1156 .minor = 0, 1157 .rev = 0, 1158 .funcs = &gmc_v10_0_ip_funcs, 1159 }; 1160