1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "gfxhub_v1_0.h" 25 #include "gfxhub_v1_1.h" 26 27 #include "gc/gc_9_0_offset.h" 28 #include "gc/gc_9_0_sh_mask.h" 29 #include "gc/gc_9_0_default.h" 30 #include "vega10_enum.h" 31 32 #include "soc15_common.h" 33 34 static u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) 35 { 36 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; 37 } 38 39 static void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, 40 uint32_t vmid, 41 uint64_t page_table_base) 42 { 43 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 44 45 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 46 hub->ctx_addr_distance * vmid, 47 lower_32_bits(page_table_base)); 48 49 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 50 hub->ctx_addr_distance * vmid, 51 upper_32_bits(page_table_base)); 52 } 53 54 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 55 { 56 uint64_t pt_base; 57 58 if (adev->gmc.pdb0_bo) 59 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); 60 else 61 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 62 63 gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); 64 65 /* If use GART for FB translation, vmid0 page table covers both 66 * vram and system memory (gart) 67 */ 68 if (adev->gmc.pdb0_bo) { 69 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 70 (u32)(adev->gmc.fb_start >> 12)); 71 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 72 (u32)(adev->gmc.fb_start >> 44)); 73 74 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 75 (u32)(adev->gmc.gart_end >> 12)); 76 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 77 (u32)(adev->gmc.gart_end >> 44)); 78 } else { 79 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 80 (u32)(adev->gmc.gart_start >> 12)); 81 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 82 (u32)(adev->gmc.gart_start >> 44)); 83 84 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 85 (u32)(adev->gmc.gart_end >> 12)); 86 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 87 (u32)(adev->gmc.gart_end >> 44)); 88 } 89 } 90 91 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 92 { 93 uint64_t value; 94 95 /* Program the AGP BAR */ 96 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); 97 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 98 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 99 100 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) { 101 /* Program the system aperture low logical page number. */ 102 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 103 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 104 105 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 106 /* 107 * Raven2 has a HW issue that it is unable to use the 108 * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. 109 * So here is the workaround that increase system 110 * aperture high address (add 1) to get rid of the VM 111 * fault and hardware hang. 112 */ 113 WREG32_SOC15_RLC(GC, 0, 114 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 115 max((adev->gmc.fb_end >> 18) + 0x1, 116 adev->gmc.agp_end >> 18)); 117 else 118 WREG32_SOC15_RLC( 119 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 120 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 121 122 /* Set default page address. */ 123 value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr); 124 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 125 (u32)(value >> 12)); 126 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 127 (u32)(value >> 44)); 128 129 /* Program "protection fault". */ 130 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 131 (u32)(adev->dummy_page_addr >> 12)); 132 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 133 (u32)((u64)adev->dummy_page_addr >> 44)); 134 135 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, 136 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 137 } 138 139 /* In the case squeezing vram into GART aperture, we don't use 140 * FB aperture and AGP aperture. Disable them. 141 */ 142 if (adev->gmc.pdb0_bo) { 143 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0); 144 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); 145 WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0); 146 WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF); 147 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF); 148 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0); 149 } 150 } 151 152 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 153 { 154 uint32_t tmp; 155 156 /* Setup TLB control */ 157 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 158 159 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 160 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 161 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 162 ENABLE_ADVANCED_DRIVER_MODEL, 1); 163 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 164 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 165 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 166 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 167 MTYPE, MTYPE_UC);/* XXX for emulation. */ 168 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 169 170 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 171 } 172 173 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 174 { 175 uint32_t tmp; 176 177 /* Setup L2 cache */ 178 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); 179 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 180 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 181 /* XXX for emulation, Refer to closed source code.*/ 182 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 183 0); 184 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 185 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 186 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 187 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); 188 189 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); 190 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 191 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 192 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); 193 194 tmp = mmVM_L2_CNTL3_DEFAULT; 195 if (adev->gmc.translate_further) { 196 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 197 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 198 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 199 } else { 200 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 201 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 202 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 203 } 204 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); 205 206 tmp = mmVM_L2_CNTL4_DEFAULT; 207 if (adev->gmc.xgmi.connected_to_cpu) { 208 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); 209 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); 210 } else { 211 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 212 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 213 } 214 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp); 215 } 216 217 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 218 { 219 uint32_t tmp; 220 221 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); 222 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 223 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 224 adev->gmc.vmid0_page_table_depth); 225 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, 226 adev->gmc.vmid0_page_table_block_size); 227 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, 228 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 229 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); 230 } 231 232 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 233 { 234 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 235 0XFFFFFFFF); 236 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 237 0x0000000F); 238 239 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 240 0); 241 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 242 0); 243 244 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 245 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 246 247 } 248 249 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 250 { 251 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 252 unsigned num_level, block_size; 253 uint32_t tmp; 254 int i; 255 256 num_level = adev->vm_manager.num_level; 257 block_size = adev->vm_manager.block_size; 258 if (adev->gmc.translate_further) 259 num_level -= 1; 260 else 261 block_size -= 9; 262 263 for (i = 0; i <= 14; i++) { 264 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); 265 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 266 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 267 num_level); 268 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 269 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 270 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 271 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 272 1); 273 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 274 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 275 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 276 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 277 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 278 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 279 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 280 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 281 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 282 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 283 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 284 PAGE_TABLE_BLOCK_SIZE, 285 block_size); 286 /* Send no-retry XNACK on fault to suppress VM fault storm. 287 * On Aldebaran, XNACK can be enabled in the SQ per-process. 288 * Retry faults need to be enabled for that to work. 289 */ 290 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 291 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 292 !adev->gmc.noretry || 293 adev->asic_type == CHIP_ALDEBARAN); 294 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, 295 i * hub->ctx_distance, tmp); 296 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 297 i * hub->ctx_addr_distance, 0); 298 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 299 i * hub->ctx_addr_distance, 0); 300 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 301 i * hub->ctx_addr_distance, 302 lower_32_bits(adev->vm_manager.max_pfn - 1)); 303 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 304 i * hub->ctx_addr_distance, 305 upper_32_bits(adev->vm_manager.max_pfn - 1)); 306 } 307 } 308 309 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev) 310 { 311 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 312 unsigned i; 313 314 for (i = 0 ; i < 18; ++i) { 315 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 316 i * hub->eng_addr_distance, 0xffffffff); 317 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 318 i * hub->eng_addr_distance, 0x1f); 319 } 320 } 321 322 static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 323 { 324 if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) { 325 /* 326 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 327 * VF copy registers so vbios post doesn't program them, for 328 * SRIOV driver need to program them 329 */ 330 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE, 331 adev->gmc.vram_start >> 24); 332 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP, 333 adev->gmc.vram_end >> 24); 334 } 335 336 /* GART Enable. */ 337 gfxhub_v1_0_init_gart_aperture_regs(adev); 338 gfxhub_v1_0_init_system_aperture_regs(adev); 339 gfxhub_v1_0_init_tlb_regs(adev); 340 if (!amdgpu_sriov_vf(adev)) 341 gfxhub_v1_0_init_cache_regs(adev); 342 343 gfxhub_v1_0_enable_system_domain(adev); 344 if (!amdgpu_sriov_vf(adev)) 345 gfxhub_v1_0_disable_identity_aperture(adev); 346 gfxhub_v1_0_setup_vmid_config(adev); 347 gfxhub_v1_0_program_invalidation(adev); 348 349 return 0; 350 } 351 352 static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) 353 { 354 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 355 u32 tmp; 356 u32 i; 357 358 /* Disable all tables */ 359 for (i = 0; i < 16; i++) 360 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, 361 i * hub->ctx_distance, 0); 362 363 /* Setup TLB control */ 364 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 365 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 366 tmp = REG_SET_FIELD(tmp, 367 MC_VM_MX_L1_TLB_CNTL, 368 ENABLE_ADVANCED_DRIVER_MODEL, 369 0); 370 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 371 372 /* Setup L2 cache */ 373 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 374 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); 375 } 376 377 /** 378 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling 379 * 380 * @adev: amdgpu_device pointer 381 * @value: true redirects VM faults to the default page 382 */ 383 static void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, 384 bool value) 385 { 386 u32 tmp; 387 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 388 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 389 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 390 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 391 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 392 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 393 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 394 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 395 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 396 tmp = REG_SET_FIELD(tmp, 397 VM_L2_PROTECTION_FAULT_CNTL, 398 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 399 value); 400 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 401 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 402 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 403 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 404 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 405 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 406 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 407 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 408 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 409 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 410 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 411 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 412 if (!value) { 413 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 414 CRASH_ON_NO_RETRY_FAULT, 1); 415 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 416 CRASH_ON_RETRY_FAULT, 1); 417 } 418 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 419 } 420 421 static void gfxhub_v1_0_init(struct amdgpu_device *adev) 422 { 423 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 424 425 hub->ctx0_ptb_addr_lo32 = 426 SOC15_REG_OFFSET(GC, 0, 427 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 428 hub->ctx0_ptb_addr_hi32 = 429 SOC15_REG_OFFSET(GC, 0, 430 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 431 hub->vm_inv_eng0_sem = 432 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM); 433 hub->vm_inv_eng0_req = 434 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); 435 hub->vm_inv_eng0_ack = 436 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); 437 hub->vm_context0_cntl = 438 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); 439 hub->vm_l2_pro_fault_status = 440 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 441 hub->vm_l2_pro_fault_cntl = 442 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 443 444 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; 445 hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 446 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 447 hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ; 448 hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 449 mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 450 } 451 452 453 const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = { 454 .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset, 455 .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs, 456 .gart_enable = gfxhub_v1_0_gart_enable, 457 .gart_disable = gfxhub_v1_0_gart_disable, 458 .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default, 459 .init = gfxhub_v1_0_init, 460 .get_xgmi_info = gfxhub_v1_1_get_xgmi_info, 461 }; 462