1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "gfxhub_v1_0.h" 25 #include "gfxhub_v1_1.h" 26 27 #include "gc/gc_9_0_offset.h" 28 #include "gc/gc_9_0_sh_mask.h" 29 #include "gc/gc_9_0_default.h" 30 #include "vega10_enum.h" 31 32 #include "soc15_common.h" 33 34 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev) 35 { 36 return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24; 37 } 38 39 void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid, 40 uint64_t page_table_base) 41 { 42 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 43 44 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 45 hub->ctx_addr_distance * vmid, 46 lower_32_bits(page_table_base)); 47 48 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 49 hub->ctx_addr_distance * vmid, 50 upper_32_bits(page_table_base)); 51 } 52 53 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) 54 { 55 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 56 57 gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); 58 59 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 60 (u32)(adev->gmc.gart_start >> 12)); 61 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 62 (u32)(adev->gmc.gart_start >> 44)); 63 64 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 65 (u32)(adev->gmc.gart_end >> 12)); 66 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 67 (u32)(adev->gmc.gart_end >> 44)); 68 } 69 70 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 71 { 72 uint64_t value; 73 74 /* Program the AGP BAR */ 75 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0); 76 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 77 WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 78 79 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) { 80 /* Program the system aperture low logical page number. */ 81 WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 82 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 83 84 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 85 /* 86 * Raven2 has a HW issue that it is unable to use the 87 * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. 88 * So here is the workaround that increase system 89 * aperture high address (add 1) to get rid of the VM 90 * fault and hardware hang. 91 */ 92 WREG32_SOC15_RLC(GC, 0, 93 mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 94 max((adev->gmc.fb_end >> 18) + 0x1, 95 adev->gmc.agp_end >> 18)); 96 else 97 WREG32_SOC15_RLC( 98 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 99 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 100 101 /* Set default page address. */ 102 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + 103 adev->vm_manager.vram_base_offset; 104 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 105 (u32)(value >> 12)); 106 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 107 (u32)(value >> 44)); 108 109 /* Program "protection fault". */ 110 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 111 (u32)(adev->dummy_page_addr >> 12)); 112 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 113 (u32)((u64)adev->dummy_page_addr >> 44)); 114 115 WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2, 116 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 117 } 118 } 119 120 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 121 { 122 uint32_t tmp; 123 124 /* Setup TLB control */ 125 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 126 127 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 128 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 129 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 130 ENABLE_ADVANCED_DRIVER_MODEL, 1); 131 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 132 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 133 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 134 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, 135 MTYPE, MTYPE_UC);/* XXX for emulation. */ 136 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); 137 138 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 139 } 140 141 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 142 { 143 uint32_t tmp; 144 145 /* Setup L2 cache */ 146 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL); 147 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); 148 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); 149 /* XXX for emulation, Refer to closed source code.*/ 150 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, 151 0); 152 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 153 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 154 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 155 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp); 156 157 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); 158 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 159 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 160 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); 161 162 tmp = mmVM_L2_CNTL3_DEFAULT; 163 if (adev->gmc.translate_further) { 164 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); 165 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 166 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 167 } else { 168 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); 169 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, 170 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 171 } 172 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); 173 174 tmp = mmVM_L2_CNTL4_DEFAULT; 175 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 176 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 177 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp); 178 } 179 180 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev) 181 { 182 uint32_t tmp; 183 184 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); 185 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 186 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 187 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, 188 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 189 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); 190 } 191 192 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) 193 { 194 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 195 0XFFFFFFFF); 196 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 197 0x0000000F); 198 199 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 200 0); 201 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 202 0); 203 204 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 205 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 206 207 } 208 209 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) 210 { 211 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 212 unsigned num_level, block_size; 213 uint32_t tmp; 214 int i; 215 216 num_level = adev->vm_manager.num_level; 217 block_size = adev->vm_manager.block_size; 218 if (adev->gmc.translate_further) 219 num_level -= 1; 220 else 221 block_size -= 9; 222 223 for (i = 0; i <= 14; i++) { 224 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); 225 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 226 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 227 num_level); 228 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 229 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 230 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 231 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 232 1); 233 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 234 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 235 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 236 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 237 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 238 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 239 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 240 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 241 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 242 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 243 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 244 PAGE_TABLE_BLOCK_SIZE, 245 block_size); 246 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 247 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 248 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 249 !adev->gmc.noretry); 250 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, 251 i * hub->ctx_distance, tmp); 252 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 253 i * hub->ctx_addr_distance, 0); 254 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 255 i * hub->ctx_addr_distance, 0); 256 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 257 i * hub->ctx_addr_distance, 258 lower_32_bits(adev->vm_manager.max_pfn - 1)); 259 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 260 i * hub->ctx_addr_distance, 261 upper_32_bits(adev->vm_manager.max_pfn - 1)); 262 } 263 } 264 265 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev) 266 { 267 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 268 unsigned i; 269 270 for (i = 0 ; i < 18; ++i) { 271 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 272 i * hub->eng_addr_distance, 0xffffffff); 273 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 274 i * hub->eng_addr_distance, 0x1f); 275 } 276 } 277 278 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) 279 { 280 if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) { 281 /* 282 * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 283 * VF copy registers so vbios post doesn't program them, for 284 * SRIOV driver need to program them 285 */ 286 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_BASE, 287 adev->gmc.vram_start >> 24); 288 WREG32_SOC15_RLC(GC, 0, mmMC_VM_FB_LOCATION_TOP, 289 adev->gmc.vram_end >> 24); 290 } 291 292 /* GART Enable. */ 293 gfxhub_v1_0_init_gart_aperture_regs(adev); 294 gfxhub_v1_0_init_system_aperture_regs(adev); 295 gfxhub_v1_0_init_tlb_regs(adev); 296 if (!amdgpu_sriov_vf(adev)) 297 gfxhub_v1_0_init_cache_regs(adev); 298 299 gfxhub_v1_0_enable_system_domain(adev); 300 if (!amdgpu_sriov_vf(adev)) 301 gfxhub_v1_0_disable_identity_aperture(adev); 302 gfxhub_v1_0_setup_vmid_config(adev); 303 gfxhub_v1_0_program_invalidation(adev); 304 305 return 0; 306 } 307 308 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev) 309 { 310 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 311 u32 tmp; 312 u32 i; 313 314 /* Disable all tables */ 315 for (i = 0; i < 16; i++) 316 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, 317 i * hub->ctx_distance, 0); 318 319 /* Setup TLB control */ 320 tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL); 321 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 322 tmp = REG_SET_FIELD(tmp, 323 MC_VM_MX_L1_TLB_CNTL, 324 ENABLE_ADVANCED_DRIVER_MODEL, 325 0); 326 WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); 327 328 /* Setup L2 cache */ 329 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); 330 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); 331 } 332 333 /** 334 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling 335 * 336 * @adev: amdgpu_device pointer 337 * @value: true redirects VM faults to the default page 338 */ 339 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, 340 bool value) 341 { 342 u32 tmp; 343 tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 344 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 345 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 346 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 347 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 348 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 349 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 350 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 351 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 352 tmp = REG_SET_FIELD(tmp, 353 VM_L2_PROTECTION_FAULT_CNTL, 354 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 355 value); 356 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 357 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 358 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 359 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 360 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 361 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 362 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 363 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 364 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 365 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 366 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 367 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 368 if (!value) { 369 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 370 CRASH_ON_NO_RETRY_FAULT, 1); 371 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, 372 CRASH_ON_RETRY_FAULT, 1); 373 } 374 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); 375 } 376 377 void gfxhub_v1_0_init(struct amdgpu_device *adev) 378 { 379 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 380 381 hub->ctx0_ptb_addr_lo32 = 382 SOC15_REG_OFFSET(GC, 0, 383 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 384 hub->ctx0_ptb_addr_hi32 = 385 SOC15_REG_OFFSET(GC, 0, 386 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 387 hub->vm_inv_eng0_sem = 388 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM); 389 hub->vm_inv_eng0_req = 390 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ); 391 hub->vm_inv_eng0_ack = 392 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK); 393 hub->vm_context0_cntl = 394 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); 395 hub->vm_l2_pro_fault_status = 396 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS); 397 hub->vm_l2_pro_fault_cntl = 398 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL); 399 400 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; 401 hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 402 mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 403 hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ; 404 hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 405 mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 406 } 407 408 409 const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = { 410 .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset, 411 .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs, 412 .gart_enable = gfxhub_v1_0_gart_enable, 413 .gart_disable = gfxhub_v1_0_gart_disable, 414 .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default, 415 .init = gfxhub_v1_0_init, 416 .get_xgmi_info = gfxhub_v1_1_get_xgmi_info, 417 }; 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