1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "amdgpu_xcp.h" 25 #include "gfxhub_v12_1.h" 26 27 #include "gc/gc_12_1_0_offset.h" 28 #include "gc/gc_12_1_0_sh_mask.h" 29 #include "soc_v1_0_enum.h" 30 31 #include "soc15_common.h" 32 33 #define regGCVM_L2_CNTL3_DEFAULT 0x80120007 34 #define regGCVM_L2_CNTL4_DEFAULT 0x000000c1 35 #define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0 36 #define regGRBM_GFX_INDEX_DEFAULT 0xe0000000 37 38 39 static u64 gfxhub_v12_1_get_fb_location(struct amdgpu_device *adev) 40 { 41 u64 base; 42 43 base = RREG32_SOC15(GC, GET_INST(GC, 0), 44 regGCMC_VM_FB_LOCATION_BASE_LO32); 45 base &= GCMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32_MASK; 46 base <<= 24; 47 48 base |= ((u64)(GCMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1_MASK & 49 RREG32_SOC15(GC, GET_INST(GC, 0), 50 regGCMC_VM_FB_LOCATION_BASE_HI32)) << 56); 51 return base; 52 } 53 54 static u64 gfxhub_v12_1_get_mc_fb_offset(struct amdgpu_device *adev) 55 { 56 return (u64)(RREG32_SOC15(GC, GET_INST(GC, 0), 57 regGCMC_VM_FB_OFFSET) << 24); 58 } 59 60 static void gfxhub_v12_1_xcc_setup_vm_pt_regs(struct amdgpu_device *adev, 61 uint32_t vmid, 62 uint64_t page_table_base, 63 uint32_t xcc_mask) 64 { 65 struct amdgpu_vmhub *hub; 66 int i; 67 68 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 69 hub = &adev->vmhub[AMDGPU_GFXHUB(i)]; 70 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), 71 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 72 hub->ctx_addr_distance * vmid, 73 lower_32_bits(page_table_base)); 74 75 WREG32_SOC15_OFFSET(GC, GET_INST(GC, i), 76 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 77 hub->ctx_addr_distance * vmid, 78 upper_32_bits(page_table_base)); 79 } 80 } 81 82 static void gfxhub_v12_1_setup_vm_pt_regs(struct amdgpu_device *adev, 83 uint32_t vmid, 84 uint64_t page_table_base) 85 { 86 gfxhub_v12_1_xcc_setup_vm_pt_regs(adev, vmid, page_table_base, 87 adev->gfx.xcc_mask); 88 } 89 90 static void gfxhub_v12_1_xcc_init_gart_aperture_regs(struct amdgpu_device *adev, 91 uint32_t xcc_mask) 92 { 93 uint64_t pt_base; 94 int i; 95 96 if (adev->gmc.pdb0_bo) 97 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); 98 else 99 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 100 101 gfxhub_v12_1_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask); 102 103 /* If use GART for FB translation, vmid0 page table covers both 104 * vram and system memory (gart) 105 */ 106 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 107 if (adev->gmc.pdb0_bo) { 108 WREG32_SOC15(GC, GET_INST(GC, i), 109 regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 110 (u32)(adev->gmc.fb_start >> 12)); 111 WREG32_SOC15(GC, GET_INST(GC, i), 112 regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 113 (u32)(adev->gmc.fb_start >> 44)); 114 115 WREG32_SOC15(GC, GET_INST(GC, i), 116 regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 117 (u32)(adev->gmc.gart_end >> 12)); 118 WREG32_SOC15(GC, GET_INST(GC, i), 119 regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 120 (u32)(adev->gmc.gart_end >> 44)); 121 } else { 122 WREG32_SOC15(GC, GET_INST(GC, i), 123 regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 124 (u32)(adev->gmc.gart_start >> 12)); 125 WREG32_SOC15(GC, GET_INST(GC, i), 126 regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 127 (u32)(adev->gmc.gart_start >> 44)); 128 129 WREG32_SOC15(GC, GET_INST(GC, i), 130 regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 131 (u32)(adev->gmc.gart_end >> 12)); 132 WREG32_SOC15(GC, GET_INST(GC, i), 133 regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 134 (u32)(adev->gmc.gart_end >> 44)); 135 } 136 } 137 } 138 139 static void gfxhub_v12_1_xcc_init_system_aperture_regs(struct amdgpu_device *adev, 140 uint32_t xcc_mask) 141 { 142 uint64_t value; 143 uint32_t tmp; 144 int i; 145 146 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 147 /* Program the AGP BAR */ 148 WREG32_SOC15_RLC(GC, GET_INST(GC, i), 149 regGCMC_VM_AGP_BASE_LO32, 0); 150 WREG32_SOC15_RLC(GC, GET_INST(GC, i), 151 regGCMC_VM_AGP_BASE_HI32, 0); 152 WREG32_SOC15_RLC(GC, GET_INST(GC, i), 153 regGCMC_VM_AGP_BOT_LO32, 154 lower_32_bits(adev->gmc.agp_start >> 24)); 155 WREG32_SOC15_RLC(GC, GET_INST(GC, i), 156 regGCMC_VM_AGP_BOT_HI32, 157 upper_32_bits(adev->gmc.agp_start >> 24)); 158 WREG32_SOC15_RLC(GC, GET_INST(GC, i), 159 regGCMC_VM_AGP_TOP_LO32, 160 lower_32_bits(adev->gmc.agp_end >> 24)); 161 WREG32_SOC15_RLC(GC, GET_INST(GC, i), 162 regGCMC_VM_AGP_TOP_HI32, 163 upper_32_bits(adev->gmc.agp_end >> 24)); 164 165 if (!amdgpu_sriov_vf(adev)) { 166 /* Program the system aperture low logical page number. */ 167 WREG32_SOC15(GC, GET_INST(GC, i), 168 regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, 169 lower_32_bits(min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18)); 170 WREG32_SOC15(GC, GET_INST(GC, i), 171 regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, 172 upper_32_bits(min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18)); 173 WREG32_SOC15(GC, GET_INST(GC, i), 174 regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 175 lower_32_bits(max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18)); 176 WREG32_SOC15(GC, GET_INST(GC, i), 177 regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 178 upper_32_bits(max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18)); 179 180 /* Set default page address. */ 181 value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); 182 WREG32_SOC15(GC, GET_INST(GC, i), 183 regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 184 (u32)(value >> 12)); 185 WREG32_SOC15(GC, GET_INST(GC, i), 186 regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 187 (u32)(value >> 44)); 188 189 /* Program "protection fault". */ 190 WREG32_SOC15(GC, GET_INST(GC, i), 191 regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 192 (u32)(adev->dummy_page_addr >> 12)); 193 WREG32_SOC15(GC, GET_INST(GC, i), 194 regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 195 (u32)((u64)adev->dummy_page_addr >> 44)); 196 197 tmp = RREG32_SOC15(GC, GET_INST(GC, i), 198 regGCVM_L2_PROTECTION_FAULT_CNTL2); 199 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, 200 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 201 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL2, 202 ENABLE_RETRY_FAULT_INTERRUPT, 0x1); 203 WREG32_SOC15(GC, GET_INST(GC, i), 204 regGCVM_L2_PROTECTION_FAULT_CNTL2, tmp); 205 } 206 207 /* In the case squeezing vram into GART aperture, we don't use 208 * FB aperture and AGP aperture. Disable them. 209 */ 210 if (adev->gmc.pdb0_bo) { 211 WREG32_SOC15(GC, GET_INST(GC, i), 212 regGCMC_VM_FB_LOCATION_TOP_LO32, 0); 213 WREG32_SOC15(GC, GET_INST(GC, i), 214 regGCMC_VM_FB_LOCATION_TOP_HI32, 0); 215 WREG32_SOC15(GC, GET_INST(GC, i), 216 regGCMC_VM_FB_LOCATION_BASE_LO32, 217 0xFFFFFFFF); 218 WREG32_SOC15(GC, GET_INST(GC, i), 219 regGCMC_VM_FB_LOCATION_BASE_HI32, 1); 220 WREG32_SOC15(GC, GET_INST(GC, i), 221 regGCMC_VM_AGP_TOP_LO32, 0); 222 WREG32_SOC15(GC, GET_INST(GC, i), 223 regGCMC_VM_AGP_TOP_HI32, 0); 224 WREG32_SOC15(GC, GET_INST(GC, i), 225 regGCMC_VM_AGP_BOT_LO32, 0xFFFFFFFF); 226 WREG32_SOC15(GC, GET_INST(GC, i), 227 regGCMC_VM_AGP_BOT_HI32, 1); 228 WREG32_SOC15(GC, GET_INST(GC, i), 229 regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32, 230 0xFFFFFFFF); 231 WREG32_SOC15(GC, GET_INST(GC, i), 232 regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32, 233 0x7F); 234 WREG32_SOC15(GC, GET_INST(GC, i), 235 regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 0); 236 WREG32_SOC15(GC, GET_INST(GC, i), 237 regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 0); 238 } 239 } 240 } 241 242 static void gfxhub_v12_1_xcc_init_tlb_regs(struct amdgpu_device *adev, 243 uint32_t xcc_mask) 244 { 245 uint32_t tmp; 246 int i; 247 248 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 249 /* Setup TLB control */ 250 tmp = RREG32_SOC15(GC, GET_INST(GC, i), 251 regGCMC_VM_MX_L1_TLB_CNTL); 252 253 tmp = REG_SET_FIELD(tmp, 254 GCMC_VM_MX_L1_TLB_CNTL, 255 ENABLE_L1_TLB, 1); 256 tmp = REG_SET_FIELD(tmp, 257 GCMC_VM_MX_L1_TLB_CNTL, 258 SYSTEM_ACCESS_MODE, 3); 259 tmp = REG_SET_FIELD(tmp, 260 GCMC_VM_MX_L1_TLB_CNTL, 261 ENABLE_ADVANCED_DRIVER_MODEL, 1); 262 tmp = REG_SET_FIELD(tmp, 263 GCMC_VM_MX_L1_TLB_CNTL, 264 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 265 tmp = REG_SET_FIELD(tmp, 266 GCMC_VM_MX_L1_TLB_CNTL, 267 ECO_BITS, 0); 268 tmp = REG_SET_FIELD(tmp, 269 GCMC_VM_MX_L1_TLB_CNTL, 270 MTYPE, MTYPE_UC); 271 272 WREG32_SOC15_RLC(GC, GET_INST(GC, i), 273 regGCMC_VM_MX_L1_TLB_CNTL, tmp); 274 } 275 } 276 277 static void gfxhub_v12_1_xcc_init_cache_regs(struct amdgpu_device *adev, 278 uint32_t xcc_mask) 279 { 280 uint32_t tmp; 281 int i; 282 283 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 284 /* Setup L2 cache */ 285 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL); 286 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 287 ENABLE_L2_CACHE, 1); 288 /*TODO: set ENABLE_L2_FRAGMENT_PROCESSING to 1? */ 289 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 290 ENABLE_L2_FRAGMENT_PROCESSING, 0); 291 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 292 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 293 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 294 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 295 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 296 PDE_FAULT_CLASSIFICATION, 0); 297 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 298 CONTEXT1_IDENTITY_ACCESS_MODE, 1); 299 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 300 IDENTITY_MODE_FRAGMENT_SIZE, 0); 301 WREG32_SOC15_RLC(GC, GET_INST(GC, i), 302 regGCVM_L2_CNTL, tmp); 303 304 tmp = RREG32_SOC15(GC, GET_INST(GC, i), regGCVM_L2_CNTL2); 305 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, 306 INVALIDATE_ALL_L1_TLBS, 1); 307 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, 308 INVALIDATE_L2_CACHE, 1); 309 WREG32_SOC15_RLC(GC, GET_INST(GC, i), 310 regGCVM_L2_CNTL2, tmp); 311 312 tmp = regGCVM_L2_CNTL3_DEFAULT; 313 if (adev->gmc.translate_further) { 314 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 315 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 316 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 317 } else { 318 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 319 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 320 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 321 } 322 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL3, tmp); 323 324 tmp = regGCVM_L2_CNTL4_DEFAULT; 325 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, 326 VMC_TAP_PDE_REQUEST_PHYSICAL, 1); 327 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, 328 VMC_TAP_PTE_REQUEST_PHYSICAL, 1); 329 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL4, tmp); 330 331 tmp = regGCVM_L2_CNTL5_DEFAULT; 332 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, 333 L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 334 WREG32_SOC15_RLC(GC, GET_INST(GC, i), regGCVM_L2_CNTL5, tmp); 335 } 336 } 337 338 static void gfxhub_v12_1_xcc_enable_system_domain(struct amdgpu_device *adev, 339 uint32_t xcc_mask) 340 { 341 uint32_t tmp; 342 int i; 343 344 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 345 tmp = RREG32_SOC15(GC, GET_INST(GC, i), 346 regGCVM_CONTEXT0_CNTL); 347 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 348 ENABLE_CONTEXT, 1); 349 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 350 PAGE_TABLE_DEPTH, 351 adev->gmc.vmid0_page_table_depth); 352 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 353 PAGE_TABLE_BLOCK_SIZE, 354 adev->gmc.vmid0_page_table_block_size); 355 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 356 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 357 WREG32_SOC15(GC, GET_INST(GC, i), 358 regGCVM_CONTEXT0_CNTL, tmp); 359 } 360 } 361 362 static void gfxhub_v12_1_xcc_disable_identity_aperture(struct amdgpu_device *adev, 363 uint32_t xcc_mask) 364 { 365 int i; 366 367 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 368 WREG32_SOC15(GC, GET_INST(GC, i), 369 regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 370 0XFFFFFFFF); 371 WREG32_SOC15(GC, GET_INST(GC, i), 372 regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 373 0x00001FFF); 374 375 WREG32_SOC15(GC, GET_INST(GC, i), 376 regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 377 0); 378 WREG32_SOC15(GC, GET_INST(GC, i), 379 regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 380 0); 381 382 WREG32_SOC15(GC, GET_INST(GC, i), 383 regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 384 0); 385 WREG32_SOC15(GC, GET_INST(GC, i), 386 regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 387 0); 388 } 389 } 390 391 static void gfxhub_v12_1_xcc_setup_vmid_config(struct amdgpu_device *adev, 392 uint32_t xcc_mask) 393 { 394 struct amdgpu_vmhub *hub; 395 unsigned int num_level, block_size; 396 uint32_t tmp; 397 int i, j; 398 399 num_level = adev->vm_manager.num_level; 400 block_size = adev->vm_manager.block_size; 401 block_size -= 9; 402 403 for (j = 0; j < NUM_XCC(xcc_mask); j++) { 404 hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; 405 for (i = 0; i <= 14; i++) { 406 tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 407 regGCVM_CONTEXT1_CNTL, 408 i * hub->ctx_distance); 409 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 410 ENABLE_CONTEXT, 1); 411 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 412 PAGE_TABLE_DEPTH, num_level); 413 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 414 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 415 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 416 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 417 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 418 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 419 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 420 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 421 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 422 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 423 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 424 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 425 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 426 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 427 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 428 PAGE_TABLE_BLOCK_SIZE, block_size); 429 /* Send no-retry XNACK on fault to suppress VM fault storm */ 430 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 431 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 432 1); 433 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regGCVM_CONTEXT1_CNTL, 434 i * hub->ctx_distance, tmp); 435 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 436 regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 437 i * hub->ctx_addr_distance, 0); 438 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 439 regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 440 i * hub->ctx_addr_distance, 0); 441 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 442 regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 443 i * hub->ctx_addr_distance, 444 lower_32_bits(adev->vm_manager.max_pfn - 1)); 445 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 446 regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 447 i * hub->ctx_addr_distance, 448 upper_32_bits(adev->vm_manager.max_pfn - 1)); 449 } 450 451 hub->vm_cntx_cntl = tmp; 452 } 453 } 454 455 static void gfxhub_v12_1_xcc_program_invalidation(struct amdgpu_device *adev, 456 uint32_t xcc_mask) 457 { 458 struct amdgpu_vmhub *hub; 459 unsigned int i, j; 460 461 for (j = 0; j < NUM_XCC(xcc_mask); j++) { 462 hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; 463 464 for (i = 0 ; i < 18; ++i) { 465 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 466 regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 467 i * hub->eng_addr_distance, 0xFFFFFFFF); 468 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 469 regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 470 i * hub->eng_addr_distance, 0x3FFF); 471 } 472 } 473 } 474 475 static int gfxhub_v12_1_xcc_gart_enable(struct amdgpu_device *adev, 476 uint32_t xcc_mask) 477 { 478 uint32_t i; 479 480 if (amdgpu_sriov_vf(adev)) { 481 /* GCMC_VM_FB_LOCATION_BASE/TOP are VF copy registers 482 * VBIO post does not program them at boot up phase 483 * Need driver to program them from guest side */ 484 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 485 WREG32_SOC15(GC, GET_INST(GC, i), 486 regGCMC_VM_FB_LOCATION_BASE_LO32, 487 lower_32_bits(adev->gmc.vram_start >> 24)); 488 WREG32_SOC15(GC, GET_INST(GC, i), 489 regGCMC_VM_FB_LOCATION_BASE_HI32, 490 upper_32_bits(adev->gmc.vram_start >> 24)); 491 WREG32_SOC15(GC, GET_INST(GC, i), 492 regGCMC_VM_FB_LOCATION_TOP_LO32, 493 lower_32_bits(adev->gmc.vram_end >> 24)); 494 WREG32_SOC15(GC, GET_INST(GC, i), 495 regGCMC_VM_FB_LOCATION_TOP_HI32, 496 upper_32_bits(adev->gmc.vram_end >> 24)); 497 } 498 } 499 /* GART Enable. */ 500 gfxhub_v12_1_xcc_init_gart_aperture_regs(adev, xcc_mask); 501 gfxhub_v12_1_xcc_init_system_aperture_regs(adev, xcc_mask); 502 gfxhub_v12_1_xcc_init_tlb_regs(adev, xcc_mask); 503 if (!amdgpu_sriov_vf(adev)) 504 gfxhub_v12_1_xcc_init_cache_regs(adev, xcc_mask); 505 506 gfxhub_v12_1_xcc_enable_system_domain(adev, xcc_mask); 507 if (!amdgpu_sriov_vf(adev)) 508 gfxhub_v12_1_xcc_disable_identity_aperture(adev, xcc_mask); 509 gfxhub_v12_1_xcc_setup_vmid_config(adev, xcc_mask); 510 gfxhub_v12_1_xcc_program_invalidation(adev, xcc_mask); 511 512 return 0; 513 } 514 515 static int gfxhub_v12_1_gart_enable(struct amdgpu_device *adev) 516 { 517 return gfxhub_v12_1_xcc_gart_enable(adev, 518 adev->gfx.xcc_mask); 519 } 520 521 static void gfxhub_v12_1_xcc_gart_disable(struct amdgpu_device *adev, 522 uint32_t xcc_mask) 523 { 524 struct amdgpu_vmhub *hub; 525 u32 tmp; 526 u32 i, j; 527 528 for (j = 0; j < NUM_XCC(xcc_mask); j++) { 529 hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; 530 /* Disable all tables */ 531 for (i = 0; i < 16; i++) 532 WREG32_SOC15_OFFSET(GC, GET_INST(GC, j), 533 regGCVM_CONTEXT0_CNTL, 534 i * hub->ctx_distance, 0); 535 536 /* Setup TLB control */ 537 tmp = RREG32_SOC15(GC, GET_INST(GC, j), 538 regGCMC_VM_MX_L1_TLB_CNTL); 539 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 540 ENABLE_L1_TLB, 0); 541 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 542 ENABLE_ADVANCED_DRIVER_MODEL, 0); 543 WREG32_SOC15_RLC(GC, GET_INST(GC, j), 544 regGCMC_VM_MX_L1_TLB_CNTL, tmp); 545 546 /* Setup L2 cache */ 547 if (!amdgpu_sriov_vf(adev)) { 548 tmp = RREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL); 549 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 550 WREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL, tmp); 551 WREG32_SOC15(GC, GET_INST(GC, j), regGCVM_L2_CNTL3, 0); 552 } 553 } 554 } 555 556 static void gfxhub_v12_1_gart_disable(struct amdgpu_device *adev) 557 { 558 gfxhub_v12_1_xcc_gart_disable(adev, adev->gfx.xcc_mask); 559 } 560 561 static void gfxhub_v12_1_xcc_set_fault_enable_default(struct amdgpu_device *adev, 562 bool value, uint32_t xcc_mask) 563 { 564 u32 tmp; 565 int i; 566 567 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 568 tmp = RREG32_SOC15(GC, GET_INST(GC, i), 569 regGCVM_L2_PROTECTION_FAULT_CNTL_LO32); 570 tmp = REG_SET_FIELD(tmp, 571 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 572 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 573 tmp = REG_SET_FIELD(tmp, 574 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 575 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 576 tmp = REG_SET_FIELD(tmp, 577 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 578 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 579 tmp = REG_SET_FIELD(tmp, 580 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 581 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 582 tmp = REG_SET_FIELD(tmp, 583 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 584 PDE3_PROTECTION_FAULT_ENABLE_DEFAULT, value); 585 tmp = REG_SET_FIELD(tmp, 586 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 587 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 588 value); 589 tmp = REG_SET_FIELD(tmp, 590 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 591 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 592 tmp = REG_SET_FIELD(tmp, 593 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 594 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 595 tmp = REG_SET_FIELD(tmp, 596 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 597 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 598 tmp = REG_SET_FIELD(tmp, 599 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 600 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 601 tmp = REG_SET_FIELD(tmp, 602 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 603 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 604 tmp = REG_SET_FIELD(tmp, 605 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 606 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 607 tmp = REG_SET_FIELD(tmp, 608 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 609 CLIENT_ID_NO_RETRY_FAULT_INTERRUPT, value ? 0xFFFF:0); 610 tmp = REG_SET_FIELD(tmp, 611 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 612 OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT, value); 613 if (!value) 614 tmp = REG_SET_FIELD(tmp, 615 GCVM_L2_PROTECTION_FAULT_CNTL_LO32, 616 CRASH_ON_NO_RETRY_FAULT, 1); 617 WREG32_SOC15(GC, GET_INST(GC, i), 618 regGCVM_L2_PROTECTION_FAULT_CNTL_LO32, tmp); 619 620 tmp = RREG32_SOC15(GC, GET_INST(GC, i), 621 regGCVM_L2_PROTECTION_FAULT_CNTL_HI32); 622 if (!value) 623 tmp = REG_SET_FIELD(tmp, 624 GCVM_L2_PROTECTION_FAULT_CNTL_HI32, 625 CRASH_ON_RETRY_FAULT, 1); 626 WREG32_SOC15(GC, GET_INST(GC, i), 627 regGCVM_L2_PROTECTION_FAULT_CNTL_HI32, tmp); 628 } 629 } 630 631 /** 632 * gfxhub_v12_1_set_fault_enable_default - update GART/VM fault handling 633 * 634 * @adev: amdgpu_device pointer 635 * @value: true redirects VM faults to the default page 636 */ 637 static void gfxhub_v12_1_set_fault_enable_default(struct amdgpu_device *adev, 638 bool value) 639 { 640 gfxhub_v12_1_xcc_set_fault_enable_default(adev, value, adev->gfx.xcc_mask); 641 } 642 643 static uint32_t gfxhub_v12_1_get_invalidate_req(unsigned int vmid, 644 uint32_t flush_type) 645 { 646 u32 req = 0; 647 648 /* invalidate using legacy mode on vmid*/ 649 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 650 PER_VMID_INVALIDATE_REQ, 1 << vmid); 651 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 652 FLUSH_TYPE, flush_type); 653 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 654 INVALIDATE_L2_PTES, 1); 655 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 656 INVALIDATE_L2_PDE0, 1); 657 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 658 INVALIDATE_L2_PDE1, 1); 659 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 660 INVALIDATE_L2_PDE2, 1); 661 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 662 INVALIDATE_L2_PDE3, 1); 663 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 664 INVALIDATE_L1_PTES, 1); 665 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 666 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 667 668 return req; 669 } 670 671 static const char *gfxhub_v12_1_client_ids[] = { 672 "CB", 673 "DB", 674 "GE1", 675 "GE2", 676 "CPF", 677 "CPC", 678 "CPG", 679 "RLC", 680 "TCP", 681 "SQC (inst)", 682 "SQC (data)", 683 "SQG/PC/SC", 684 "Reserved", 685 "SDMA0", 686 "SDMA1", 687 "GCR", 688 "Reserved", 689 "Reserved", 690 "WGS", 691 "DSM", 692 "PA" 693 }; 694 695 /*TODO: l2 protection fault status is increased to 64bits. 696 * some critical fields like FED are moved to STATUS_HI32 */ 697 static void gfxhub_v12_1_print_l2_protection_fault_status(struct amdgpu_device *adev, 698 uint32_t status) 699 { 700 u32 cid = REG_GET_FIELD(status, 701 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, 702 CID); 703 704 dev_err(adev->dev, 705 "GCVM_L2_PROTECTION_FAULT_STATUS_LO32:0x%08X\n", 706 status); 707 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 708 cid >= ARRAY_SIZE(gfxhub_v12_1_client_ids) ? 709 "unknown" : gfxhub_v12_1_client_ids[cid], cid); 710 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 711 REG_GET_FIELD(status, 712 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS)); 713 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 714 REG_GET_FIELD(status, 715 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR)); 716 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 717 REG_GET_FIELD(status, 718 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS)); 719 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 720 REG_GET_FIELD(status, 721 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR)); 722 dev_err(adev->dev, "\t RW: 0x%lx\n", 723 REG_GET_FIELD(status, 724 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, RW)); 725 } 726 727 static const struct amdgpu_vmhub_funcs gfxhub_v12_1_vmhub_funcs = { 728 .print_l2_protection_fault_status = gfxhub_v12_1_print_l2_protection_fault_status, 729 .get_invalidate_req = gfxhub_v12_1_get_invalidate_req, 730 }; 731 732 static void gfxhub_v12_1_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask) 733 { 734 struct amdgpu_vmhub *hub; 735 int i; 736 737 for (i = 0; i < NUM_XCC(xcc_mask); i++) { 738 hub = &adev->vmhub[AMDGPU_GFXHUB(i)]; 739 740 hub->ctx0_ptb_addr_lo32 = 741 SOC15_REG_OFFSET(GC, GET_INST(GC, i), 742 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 743 hub->ctx0_ptb_addr_hi32 = 744 SOC15_REG_OFFSET(GC, GET_INST(GC, i), 745 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 746 hub->vm_inv_eng0_sem = 747 SOC15_REG_OFFSET(GC, GET_INST(GC, i), 748 regGCVM_INVALIDATE_ENG0_SEM); 749 hub->vm_inv_eng0_req = 750 SOC15_REG_OFFSET(GC, GET_INST(GC, i), 751 regGCVM_INVALIDATE_ENG0_REQ); 752 hub->vm_inv_eng0_ack = 753 SOC15_REG_OFFSET(GC, GET_INST(GC, i), 754 regGCVM_INVALIDATE_ENG0_ACK); 755 hub->vm_context0_cntl = 756 SOC15_REG_OFFSET(GC, GET_INST(GC, i), 757 regGCVM_CONTEXT0_CNTL); 758 /* TODO: add a new member to accomandate additional fault status/cntl reg */ 759 hub->vm_l2_pro_fault_status = 760 SOC15_REG_OFFSET(GC, GET_INST(GC, i), 761 regGCVM_L2_PROTECTION_FAULT_STATUS_LO32); 762 hub->vm_l2_pro_fault_cntl = 763 SOC15_REG_OFFSET(GC, GET_INST(GC, i), 764 regGCVM_L2_PROTECTION_FAULT_CNTL_LO32); 765 hub->ctx_distance = 766 regGCVM_CONTEXT1_CNTL - 767 regGCVM_CONTEXT0_CNTL; 768 hub->ctx_addr_distance = 769 regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 770 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 771 hub->eng_distance = 772 regGCVM_INVALIDATE_ENG1_REQ - 773 regGCVM_INVALIDATE_ENG0_REQ; 774 hub->eng_addr_distance = 775 regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 776 regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 777 778 hub->vm_cntx_cntl_vm_fault = 779 GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 780 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 781 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 782 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 783 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 784 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 785 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 786 787 hub->vmhub_funcs = &gfxhub_v12_1_vmhub_funcs; 788 } 789 } 790 791 static void gfxhub_v12_1_init(struct amdgpu_device *adev) 792 { 793 gfxhub_v12_1_xcc_init(adev, adev->gfx.xcc_mask); 794 } 795 796 static int gfxhub_v12_1_get_xgmi_info(struct amdgpu_device *adev) 797 { 798 u32 max_num_physical_nodes; 799 u32 max_physical_node_id; 800 u32 xgmi_lfb_cntl; 801 u32 max_region; 802 u64 seg_size; 803 804 xgmi_lfb_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), 805 regGCMC_VM_XGMI_LFB_CNTL); 806 seg_size = REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, 0), 807 regGCMC_VM_XGMI_LFB_SIZE), 808 GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24; 809 max_region = REG_GET_FIELD(xgmi_lfb_cntl, 810 GCMC_VM_XGMI_LFB_CNTL, 811 PF_MAX_REGION); 812 813 max_num_physical_nodes = 8; 814 max_physical_node_id = 7; 815 816 /* PF_MAX_REGION=0 means xgmi is disabled */ 817 if (max_region || adev->gmc.xgmi.connected_to_cpu) { 818 adev->gmc.xgmi.num_physical_nodes = max_region + 1; 819 820 if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes) 821 return -EINVAL; 822 823 adev->gmc.xgmi.physical_node_id = 824 REG_GET_FIELD(xgmi_lfb_cntl, 825 GCMC_VM_XGMI_LFB_CNTL, 826 PF_LFB_REGION); 827 828 if (adev->gmc.xgmi.physical_node_id > max_physical_node_id) 829 return -EINVAL; 830 831 adev->gmc.xgmi.node_segment_size = seg_size; 832 } 833 834 return 0; 835 } 836 837 const struct amdgpu_gfxhub_funcs gfxhub_v12_1_funcs = { 838 .get_fb_location = gfxhub_v12_1_get_fb_location, 839 .get_mc_fb_offset = gfxhub_v12_1_get_mc_fb_offset, 840 .setup_vm_pt_regs = gfxhub_v12_1_setup_vm_pt_regs, 841 .gart_enable = gfxhub_v12_1_gart_enable, 842 .gart_disable = gfxhub_v12_1_gart_disable, 843 .set_fault_enable_default = gfxhub_v12_1_set_fault_enable_default, 844 .init = gfxhub_v12_1_init, 845 .get_xgmi_info = gfxhub_v12_1_get_xgmi_info, 846 }; 847 848 static int gfxhub_v12_1_xcp_resume(void *handle, uint32_t inst_mask) 849 { 850 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 851 bool value; 852 853 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) 854 value = false; 855 else 856 value = true; 857 858 gfxhub_v12_1_xcc_set_fault_enable_default(adev, value, inst_mask); 859 860 if (!amdgpu_sriov_vf(adev)) 861 return gfxhub_v12_1_xcc_gart_enable(adev, inst_mask); 862 863 return 0; 864 } 865 866 static int gfxhub_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) 867 { 868 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 869 870 if (!amdgpu_sriov_vf(adev)) 871 gfxhub_v12_1_xcc_gart_disable(adev, inst_mask); 872 873 return 0; 874 } 875 876 struct amdgpu_xcp_ip_funcs gfxhub_v12_1_xcp_funcs = { 877 .suspend = &gfxhub_v12_1_xcp_suspend, 878 .resume = &gfxhub_v12_1_xcp_resume 879 }; 880