1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu.h" 25 #include "gfxhub_v12_0.h" 26 27 #include "gc/gc_12_0_0_offset.h" 28 #include "gc/gc_12_0_0_sh_mask.h" 29 #include "soc24_enum.h" 30 #include "soc15_common.h" 31 32 #define regGCVM_L2_CNTL3_DEFAULT 0x80120007 33 #define regGCVM_L2_CNTL4_DEFAULT 0x000000c1 34 #define regGCVM_L2_CNTL5_DEFAULT 0x00003fe0 35 #define regGRBM_GFX_INDEX_DEFAULT 0xe0000000 36 37 static const char *gfxhub_client_ids[] = { 38 /* TODO */ 39 }; 40 41 static uint32_t gfxhub_v12_0_get_invalidate_req(unsigned int vmid, 42 uint32_t flush_type) 43 { 44 u32 req = 0; 45 46 /* invalidate using legacy mode on vmid*/ 47 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 48 PER_VMID_INVALIDATE_REQ, 1 << vmid); 49 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type); 50 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1); 51 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1); 52 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1); 53 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1); 54 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1); 55 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, 56 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0); 57 58 return req; 59 } 60 61 static void 62 gfxhub_v12_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 63 uint32_t status) 64 { 65 u32 cid = REG_GET_FIELD(status, 66 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, CID); 67 68 dev_err(adev->dev, 69 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n", 70 status); 71 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n", 72 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid], 73 cid); 74 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n", 75 REG_GET_FIELD(status, 76 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, MORE_FAULTS)); 77 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n", 78 REG_GET_FIELD(status, 79 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, WALKER_ERROR)); 80 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n", 81 REG_GET_FIELD(status, 82 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, PERMISSION_FAULTS)); 83 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n", 84 REG_GET_FIELD(status, 85 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, MAPPING_ERROR)); 86 dev_err(adev->dev, "\t RW: 0x%lx\n", 87 REG_GET_FIELD(status, 88 GCVM_L2_PROTECTION_FAULT_STATUS_LO32, RW)); 89 } 90 91 static u64 gfxhub_v12_0_get_fb_location(struct amdgpu_device *adev) 92 { 93 u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE); 94 95 base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK; 96 base <<= 24; 97 98 return base; 99 } 100 101 static u64 gfxhub_v12_0_get_mc_fb_offset(struct amdgpu_device *adev) 102 { 103 return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24; 104 } 105 106 static void gfxhub_v12_0_setup_vm_pt_regs(struct amdgpu_device *adev, 107 uint32_t vmid, 108 uint64_t page_table_base) 109 { 110 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 111 112 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, 113 hub->ctx_addr_distance * vmid, 114 lower_32_bits(page_table_base)); 115 116 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, 117 hub->ctx_addr_distance * vmid, 118 upper_32_bits(page_table_base)); 119 } 120 121 static void gfxhub_v12_0_init_gart_aperture_regs(struct amdgpu_device *adev) 122 { 123 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); 124 125 gfxhub_v12_0_setup_vm_pt_regs(adev, 0, pt_base); 126 127 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 128 (u32)(adev->gmc.gart_start >> 12)); 129 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 130 (u32)(adev->gmc.gart_start >> 44)); 131 132 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 133 (u32)(adev->gmc.gart_end >> 12)); 134 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 135 (u32)(adev->gmc.gart_end >> 44)); 136 } 137 138 static void gfxhub_v12_0_init_system_aperture_regs(struct amdgpu_device *adev) 139 { 140 uint64_t value; 141 142 /* Program the AGP BAR */ 143 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); 144 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 145 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 146 147 /* Program the system aperture low logical page number. */ 148 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 149 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); 150 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 151 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); 152 153 /* Set default page address. */ 154 value = adev->mem_scratch.gpu_addr - adev->gmc.vram_start 155 + adev->vm_manager.vram_base_offset; 156 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 157 (u32)(value >> 12)); 158 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 159 (u32)(value >> 44)); 160 161 /* Program "protection fault". */ 162 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 163 (u32)(adev->dummy_page_addr >> 12)); 164 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 165 (u32)((u64)adev->dummy_page_addr >> 44)); 166 167 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2, 168 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); 169 } 170 171 172 static void gfxhub_v12_0_init_tlb_regs(struct amdgpu_device *adev) 173 { 174 uint32_t tmp; 175 176 /* Setup TLB control */ 177 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); 178 179 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); 180 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); 181 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 182 ENABLE_ADVANCED_DRIVER_MODEL, 1); 183 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 184 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); 185 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); 186 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 187 MTYPE, MTYPE_UC); /* UC, uncached */ 188 189 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); 190 } 191 192 static void gfxhub_v12_0_init_cache_regs(struct amdgpu_device *adev) 193 { 194 uint32_t tmp; 195 196 /* These registers are not accessible to VF-SRIOV. 197 * The PF will program them instead. 198 */ 199 if (amdgpu_sriov_vf(adev)) 200 return; 201 202 /* Setup L2 cache */ 203 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL); 204 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); 205 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0); 206 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 207 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1); 208 /* XXX for emulation, Refer to closed source code.*/ 209 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, 210 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0); 211 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 212 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); 213 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); 214 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp); 215 216 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2); 217 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); 218 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); 219 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp); 220 221 tmp = regGCVM_L2_CNTL3_DEFAULT; 222 if (adev->gmc.translate_further) { 223 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); 224 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 225 L2_CACHE_BIGK_FRAGMENT_SIZE, 9); 226 } else { 227 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); 228 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, 229 L2_CACHE_BIGK_FRAGMENT_SIZE, 6); 230 } 231 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp); 232 233 tmp = regGCVM_L2_CNTL4_DEFAULT; 234 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); 235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); 236 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp); 237 238 tmp = regGCVM_L2_CNTL5_DEFAULT; 239 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0); 240 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp); 241 } 242 243 static void gfxhub_v12_0_enable_system_domain(struct amdgpu_device *adev) 244 { 245 uint32_t tmp; 246 247 tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL); 248 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); 249 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); 250 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, 251 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); 252 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp); 253 } 254 255 static void gfxhub_v12_0_disable_identity_aperture(struct amdgpu_device *adev) 256 { 257 /* These registers are not accessible to VF-SRIOV. 258 * The PF will program them instead. 259 */ 260 if (amdgpu_sriov_vf(adev)) 261 return; 262 263 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 264 0xFFFFFFFF); 265 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 266 0x0000000F); 267 268 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 269 0); 270 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 271 0); 272 273 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0); 274 WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0); 275 276 } 277 278 static void gfxhub_v12_0_setup_vmid_config(struct amdgpu_device *adev) 279 { 280 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 281 int i; 282 uint32_t tmp; 283 284 for (i = 0; i <= 14; i++) { 285 tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); 286 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); 287 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 288 adev->vm_manager.num_level); 289 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 290 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 291 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 292 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 293 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 294 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 295 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 296 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 297 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 298 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 299 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 300 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 301 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 302 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); 303 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 304 PAGE_TABLE_BLOCK_SIZE, 305 adev->vm_manager.block_size - 9); 306 /* Send no-retry XNACK on fault to suppress VM fault storm. */ 307 tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, 308 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 309 !amdgpu_noretry); 310 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, 311 i * hub->ctx_distance, tmp); 312 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, 313 i * hub->ctx_addr_distance, 0); 314 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, 315 i * hub->ctx_addr_distance, 0); 316 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, 317 i * hub->ctx_addr_distance, 318 lower_32_bits(adev->vm_manager.max_pfn - 1)); 319 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, 320 i * hub->ctx_addr_distance, 321 upper_32_bits(adev->vm_manager.max_pfn - 1)); 322 } 323 324 hub->vm_cntx_cntl = tmp; 325 } 326 327 static void gfxhub_v12_0_program_invalidation(struct amdgpu_device *adev) 328 { 329 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 330 unsigned i; 331 332 for (i = 0 ; i < 18; ++i) { 333 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, 334 i * hub->eng_addr_distance, 0xffffffff); 335 WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, 336 i * hub->eng_addr_distance, 0x1f); 337 } 338 } 339 340 static int gfxhub_v12_0_gart_enable(struct amdgpu_device *adev) 341 { 342 if (amdgpu_sriov_vf(adev)) { 343 /* 344 * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are 345 * VF copy registers so vbios post doesn't program them, for 346 * SRIOV driver need to program them 347 */ 348 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE, 349 adev->gmc.vram_start >> 24); 350 WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP, 351 adev->gmc.vram_end >> 24); 352 } 353 354 /* GART Enable. */ 355 gfxhub_v12_0_init_gart_aperture_regs(adev); 356 gfxhub_v12_0_init_system_aperture_regs(adev); 357 gfxhub_v12_0_init_tlb_regs(adev); 358 gfxhub_v12_0_init_cache_regs(adev); 359 360 gfxhub_v12_0_enable_system_domain(adev); 361 gfxhub_v12_0_disable_identity_aperture(adev); 362 gfxhub_v12_0_setup_vmid_config(adev); 363 gfxhub_v12_0_program_invalidation(adev); 364 365 return 0; 366 } 367 368 static void gfxhub_v12_0_gart_disable(struct amdgpu_device *adev) 369 { 370 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 371 u32 tmp; 372 u32 i; 373 374 /* Disable all tables */ 375 for (i = 0; i < 16; i++) 376 WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL, 377 i * hub->ctx_distance, 0); 378 379 /* Setup TLB control */ 380 tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL); 381 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); 382 tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, 383 ENABLE_ADVANCED_DRIVER_MODEL, 0); 384 WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp); 385 386 /* Setup L2 cache */ 387 WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); 388 WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0); 389 } 390 391 /** 392 * gfxhub_v12_0_set_fault_enable_default - update GART/VM fault handling 393 * 394 * @adev: amdgpu_device pointer 395 * @value: true redirects VM faults to the default page 396 */ 397 static void gfxhub_v12_0_set_fault_enable_default(struct amdgpu_device *adev, 398 bool value) 399 { 400 u32 tmp; 401 402 /* NO halt CP when page fault */ 403 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); 404 tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1); 405 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); 406 407 /* These registers are not accessible to VF-SRIOV. 408 * The PF will program them instead. 409 */ 410 if (amdgpu_sriov_vf(adev)) 411 return; 412 413 tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); 414 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 415 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 416 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 417 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); 418 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 419 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); 420 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 421 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); 422 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 423 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, 424 value); 425 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 426 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); 427 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 428 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 429 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 430 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); 431 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 432 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); 433 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 434 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 435 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 436 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); 437 if (!value) { 438 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 439 CRASH_ON_NO_RETRY_FAULT, 1); 440 tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, 441 CRASH_ON_RETRY_FAULT, 1); 442 } 443 WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp); 444 } 445 446 static const struct amdgpu_vmhub_funcs gfxhub_v12_0_vmhub_funcs = { 447 .print_l2_protection_fault_status = gfxhub_v12_0_print_l2_protection_fault_status, 448 .get_invalidate_req = gfxhub_v12_0_get_invalidate_req, 449 }; 450 451 static void gfxhub_v12_0_init(struct amdgpu_device *adev) 452 { 453 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; 454 455 hub->ctx0_ptb_addr_lo32 = 456 SOC15_REG_OFFSET(GC, 0, 457 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); 458 hub->ctx0_ptb_addr_hi32 = 459 SOC15_REG_OFFSET(GC, 0, 460 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); 461 hub->vm_inv_eng0_sem = 462 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM); 463 hub->vm_inv_eng0_req = 464 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ); 465 hub->vm_inv_eng0_ack = 466 SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK); 467 hub->vm_context0_cntl = 468 SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL); 469 hub->vm_l2_pro_fault_status = 470 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32); 471 hub->vm_l2_pro_fault_cntl = 472 SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); 473 474 hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL; 475 hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 - 476 regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 477 hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ - 478 regGCVM_INVALIDATE_ENG0_REQ; 479 hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 - 480 regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; 481 482 hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 483 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 484 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 485 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 486 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 487 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | 488 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; 489 490 hub->vmhub_funcs = &gfxhub_v12_0_vmhub_funcs; 491 } 492 493 const struct amdgpu_gfxhub_funcs gfxhub_v12_0_funcs = { 494 .get_fb_location = gfxhub_v12_0_get_fb_location, 495 .get_mc_fb_offset = gfxhub_v12_0_get_mc_fb_offset, 496 .setup_vm_pt_regs = gfxhub_v12_0_setup_vm_pt_regs, 497 .gart_enable = gfxhub_v12_0_gart_enable, 498 .gart_disable = gfxhub_v12_0_gart_disable, 499 .set_fault_enable_default = gfxhub_v12_0_set_fault_enable_default, 500 .init = gfxhub_v12_0_init, 501 }; 502