1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* cp header registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP), 111 /* SE status registers */ 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 113 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 115 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 116 }; 117 118 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 119 /* compute queue registers */ 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 157 }; 158 159 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 160 161 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 162 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 163 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 164 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 165 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 166 struct amdgpu_cu_info *cu_info); 167 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 168 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 169 170 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 171 uint64_t queue_mask) 172 { 173 struct amdgpu_device *adev = kiq_ring->adev; 174 u64 shader_mc_addr; 175 176 /* Cleaner shader MC address */ 177 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 178 179 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 180 amdgpu_ring_write(kiq_ring, 181 PACKET3_SET_RESOURCES_VMID_MASK(0) | 182 /* vmid_mask:0* queue_type:0 (KIQ) */ 183 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 184 amdgpu_ring_write(kiq_ring, 185 lower_32_bits(queue_mask)); /* queue mask lo */ 186 amdgpu_ring_write(kiq_ring, 187 upper_32_bits(queue_mask)); /* queue mask hi */ 188 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 189 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 190 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 191 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 192 } 193 194 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 195 struct amdgpu_ring *ring) 196 { 197 struct amdgpu_device *adev = kiq_ring->adev; 198 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 199 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 200 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 201 202 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 203 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 204 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 205 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 206 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 207 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 208 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 209 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 210 /*queue_type: normal compute queue */ 211 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 212 /* alloc format: all_on_one_pipe */ 213 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 214 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 215 /* num_queues: must be 1 */ 216 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 217 amdgpu_ring_write(kiq_ring, 218 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 219 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 220 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 221 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 222 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 223 } 224 225 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 226 struct amdgpu_ring *ring, 227 enum amdgpu_unmap_queues_action action, 228 u64 gpu_addr, u64 seq) 229 { 230 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 231 232 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 233 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 234 PACKET3_UNMAP_QUEUES_ACTION(action) | 235 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 236 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 237 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 238 amdgpu_ring_write(kiq_ring, 239 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 240 241 if (action == PREEMPT_QUEUES_NO_UNMAP) { 242 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 243 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 244 amdgpu_ring_write(kiq_ring, seq); 245 } else { 246 amdgpu_ring_write(kiq_ring, 0); 247 amdgpu_ring_write(kiq_ring, 0); 248 amdgpu_ring_write(kiq_ring, 0); 249 } 250 } 251 252 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 253 struct amdgpu_ring *ring, 254 u64 addr, 255 u64 seq) 256 { 257 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 258 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 260 amdgpu_ring_write(kiq_ring, 261 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 262 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 263 PACKET3_QUERY_STATUS_COMMAND(2)); 264 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 267 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 268 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 269 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 270 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 271 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 272 } 273 274 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 275 uint16_t pasid, uint32_t flush_type, 276 bool all_hub) 277 { 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 279 amdgpu_ring_write(kiq_ring, 280 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 281 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 282 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 283 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 284 } 285 286 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 287 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 288 uint32_t xcc_id, uint32_t vmid) 289 { 290 struct amdgpu_device *adev = kiq_ring->adev; 291 unsigned i; 292 293 /* enter save mode */ 294 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 295 mutex_lock(&adev->srbm_mutex); 296 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 297 298 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 301 /* wait till dequeue take effects */ 302 for (i = 0; i < adev->usec_timeout; i++) { 303 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 304 break; 305 udelay(1); 306 } 307 if (i >= adev->usec_timeout) 308 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 309 } else { 310 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 311 } 312 313 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 314 mutex_unlock(&adev->srbm_mutex); 315 /* exit safe mode */ 316 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 317 } 318 319 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 320 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 321 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 322 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 323 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 324 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 325 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 326 .set_resources_size = 8, 327 .map_queues_size = 7, 328 .unmap_queues_size = 6, 329 .query_status_size = 7, 330 .invalidate_tlbs_size = 2, 331 }; 332 333 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 334 { 335 int i, num_xcc; 336 337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 338 for (i = 0; i < num_xcc; i++) 339 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 340 } 341 342 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 343 { 344 int i, num_xcc, dev_inst; 345 346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 347 for (i = 0; i < num_xcc; i++) { 348 dev_inst = GET_INST(GC, i); 349 350 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 351 GOLDEN_GB_ADDR_CONFIG); 352 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 353 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 354 } else { 355 /* Golden settings applied by driver for ASIC with rev_id 0 */ 356 if (adev->rev_id == 0) { 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 358 REDUCE_FIFO_DEPTH_BY_2, 2); 359 } else { 360 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 361 SPARE, 0x1); 362 } 363 } 364 } 365 } 366 367 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 368 { 369 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 370 371 /* If it is an XCC reg, normalize the reg to keep 372 lower 16 bits in local xcc */ 373 374 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 375 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 376 return normalized_reg; 377 else 378 return reg; 379 } 380 381 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 382 bool wc, uint32_t reg, uint32_t val) 383 { 384 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 385 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 386 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 387 WRITE_DATA_DST_SEL(0) | 388 (wc ? WR_CONFIRM : 0)); 389 amdgpu_ring_write(ring, reg); 390 amdgpu_ring_write(ring, 0); 391 amdgpu_ring_write(ring, val); 392 } 393 394 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 395 int mem_space, int opt, uint32_t addr0, 396 uint32_t addr1, uint32_t ref, uint32_t mask, 397 uint32_t inv) 398 { 399 /* Only do the normalization on regspace */ 400 if (mem_space == 0) { 401 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 402 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 403 } 404 405 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 406 amdgpu_ring_write(ring, 407 /* memory (1) or register (0) */ 408 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 409 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 410 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 411 WAIT_REG_MEM_ENGINE(eng_sel))); 412 413 if (mem_space) 414 BUG_ON(addr0 & 0x3); /* Dword align */ 415 amdgpu_ring_write(ring, addr0); 416 amdgpu_ring_write(ring, addr1); 417 amdgpu_ring_write(ring, ref); 418 amdgpu_ring_write(ring, mask); 419 amdgpu_ring_write(ring, inv); /* poll interval */ 420 } 421 422 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 423 { 424 uint32_t scratch_reg0_offset, xcc_offset; 425 struct amdgpu_device *adev = ring->adev; 426 uint32_t tmp = 0; 427 unsigned i; 428 int r; 429 430 /* Use register offset which is local to XCC in the packet */ 431 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 432 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 433 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 434 tmp = RREG32(scratch_reg0_offset); 435 436 r = amdgpu_ring_alloc(ring, 3); 437 if (r) 438 return r; 439 440 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 441 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 442 amdgpu_ring_write(ring, 0xDEADBEEF); 443 amdgpu_ring_commit(ring); 444 445 for (i = 0; i < adev->usec_timeout; i++) { 446 tmp = RREG32(scratch_reg0_offset); 447 if (tmp == 0xDEADBEEF) 448 break; 449 udelay(1); 450 } 451 452 if (i >= adev->usec_timeout) 453 r = -ETIMEDOUT; 454 return r; 455 } 456 457 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 458 { 459 struct amdgpu_device *adev = ring->adev; 460 struct amdgpu_ib ib; 461 struct dma_fence *f = NULL; 462 463 unsigned index; 464 uint64_t gpu_addr; 465 uint32_t tmp; 466 long r; 467 468 r = amdgpu_device_wb_get(adev, &index); 469 if (r) 470 return r; 471 472 gpu_addr = adev->wb.gpu_addr + (index * 4); 473 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 474 memset(&ib, 0, sizeof(ib)); 475 476 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 477 if (r) 478 goto err1; 479 480 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 481 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 482 ib.ptr[2] = lower_32_bits(gpu_addr); 483 ib.ptr[3] = upper_32_bits(gpu_addr); 484 ib.ptr[4] = 0xDEADBEEF; 485 ib.length_dw = 5; 486 487 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 488 if (r) 489 goto err2; 490 491 r = dma_fence_wait_timeout(f, false, timeout); 492 if (r == 0) { 493 r = -ETIMEDOUT; 494 goto err2; 495 } else if (r < 0) { 496 goto err2; 497 } 498 499 tmp = adev->wb.wb[index]; 500 if (tmp == 0xDEADBEEF) 501 r = 0; 502 else 503 r = -EINVAL; 504 505 err2: 506 amdgpu_ib_free(&ib, NULL); 507 dma_fence_put(f); 508 err1: 509 amdgpu_device_wb_free(adev, index); 510 return r; 511 } 512 513 514 /* This value might differs per partition */ 515 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 516 { 517 uint64_t clock; 518 519 mutex_lock(&adev->gfx.gpu_clock_mutex); 520 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 521 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 522 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 523 mutex_unlock(&adev->gfx.gpu_clock_mutex); 524 525 return clock; 526 } 527 528 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 529 { 530 amdgpu_ucode_release(&adev->gfx.pfp_fw); 531 amdgpu_ucode_release(&adev->gfx.me_fw); 532 amdgpu_ucode_release(&adev->gfx.ce_fw); 533 amdgpu_ucode_release(&adev->gfx.rlc_fw); 534 amdgpu_ucode_release(&adev->gfx.mec_fw); 535 amdgpu_ucode_release(&adev->gfx.mec2_fw); 536 537 kfree(adev->gfx.rlc.register_list_format); 538 } 539 540 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 541 const char *chip_name) 542 { 543 int err; 544 const struct rlc_firmware_header_v2_0 *rlc_hdr; 545 uint16_t version_major; 546 uint16_t version_minor; 547 548 549 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 550 AMDGPU_UCODE_REQUIRED, 551 "amdgpu/%s_rlc.bin", chip_name); 552 if (err) 553 goto out; 554 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 555 556 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 557 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 558 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 559 out: 560 if (err) 561 amdgpu_ucode_release(&adev->gfx.rlc_fw); 562 563 return err; 564 } 565 566 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 567 { 568 return true; 569 } 570 571 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 572 { 573 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 574 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 575 } 576 577 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 578 const char *chip_name) 579 { 580 int err; 581 582 if (amdgpu_sriov_vf(adev)) { 583 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 584 AMDGPU_UCODE_REQUIRED, 585 "amdgpu/%s_sjt_mec.bin", chip_name); 586 587 if (err) 588 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 589 AMDGPU_UCODE_REQUIRED, 590 "amdgpu/%s_mec.bin", chip_name); 591 } else 592 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 593 AMDGPU_UCODE_REQUIRED, 594 "amdgpu/%s_mec.bin", chip_name); 595 if (err) 596 goto out; 597 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 598 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 599 600 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 601 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 602 603 gfx_v9_4_3_check_if_need_gfxoff(adev); 604 605 out: 606 if (err) 607 amdgpu_ucode_release(&adev->gfx.mec_fw); 608 return err; 609 } 610 611 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 612 { 613 char ucode_prefix[15]; 614 int r; 615 616 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 617 618 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 619 if (r) 620 return r; 621 622 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 623 if (r) 624 return r; 625 626 return r; 627 } 628 629 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 630 { 631 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 632 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 633 } 634 635 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 636 { 637 int r, i, num_xcc; 638 u32 *hpd; 639 const __le32 *fw_data; 640 unsigned fw_size; 641 u32 *fw; 642 size_t mec_hpd_size; 643 644 const struct gfx_firmware_header_v1_0 *mec_hdr; 645 646 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 647 for (i = 0; i < num_xcc; i++) 648 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 649 AMDGPU_MAX_COMPUTE_QUEUES); 650 651 /* take ownership of the relevant compute queues */ 652 amdgpu_gfx_compute_queue_acquire(adev); 653 mec_hpd_size = 654 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 655 if (mec_hpd_size) { 656 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 657 AMDGPU_GEM_DOMAIN_VRAM | 658 AMDGPU_GEM_DOMAIN_GTT, 659 &adev->gfx.mec.hpd_eop_obj, 660 &adev->gfx.mec.hpd_eop_gpu_addr, 661 (void **)&hpd); 662 if (r) { 663 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 664 gfx_v9_4_3_mec_fini(adev); 665 return r; 666 } 667 668 if (amdgpu_emu_mode == 1) { 669 for (i = 0; i < mec_hpd_size / 4; i++) { 670 memset((void *)(hpd + i), 0, 4); 671 if (i % 50 == 0) 672 msleep(1); 673 } 674 } else { 675 memset(hpd, 0, mec_hpd_size); 676 } 677 678 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 679 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 680 } 681 682 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 683 684 fw_data = (const __le32 *) 685 (adev->gfx.mec_fw->data + 686 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 687 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 688 689 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 690 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 691 &adev->gfx.mec.mec_fw_obj, 692 &adev->gfx.mec.mec_fw_gpu_addr, 693 (void **)&fw); 694 if (r) { 695 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 696 gfx_v9_4_3_mec_fini(adev); 697 return r; 698 } 699 700 memcpy(fw, fw_data, fw_size); 701 702 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 703 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 704 705 return 0; 706 } 707 708 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 709 u32 sh_num, u32 instance, int xcc_id) 710 { 711 u32 data; 712 713 if (instance == 0xffffffff) 714 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 715 INSTANCE_BROADCAST_WRITES, 1); 716 else 717 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 718 INSTANCE_INDEX, instance); 719 720 if (se_num == 0xffffffff) 721 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 722 SE_BROADCAST_WRITES, 1); 723 else 724 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 725 726 if (sh_num == 0xffffffff) 727 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 728 SH_BROADCAST_WRITES, 1); 729 else 730 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 731 732 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 733 } 734 735 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 736 { 737 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 738 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 739 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 740 (address << SQ_IND_INDEX__INDEX__SHIFT) | 741 (SQ_IND_INDEX__FORCE_READ_MASK)); 742 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 743 } 744 745 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 746 uint32_t wave, uint32_t thread, 747 uint32_t regno, uint32_t num, uint32_t *out) 748 { 749 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 750 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 751 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 752 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 753 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 754 (SQ_IND_INDEX__FORCE_READ_MASK) | 755 (SQ_IND_INDEX__AUTO_INCR_MASK)); 756 while (num--) 757 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 758 } 759 760 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 761 uint32_t xcc_id, uint32_t simd, uint32_t wave, 762 uint32_t *dst, int *no_fields) 763 { 764 /* type 1 wave data */ 765 dst[(*no_fields)++] = 1; 766 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 767 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 768 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 769 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 770 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 771 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 772 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 773 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 774 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 775 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 776 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 777 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 778 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 779 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 780 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 781 } 782 783 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 784 uint32_t wave, uint32_t start, 785 uint32_t size, uint32_t *dst) 786 { 787 wave_read_regs(adev, xcc_id, simd, wave, 0, 788 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 789 } 790 791 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 792 uint32_t wave, uint32_t thread, 793 uint32_t start, uint32_t size, 794 uint32_t *dst) 795 { 796 wave_read_regs(adev, xcc_id, simd, wave, thread, 797 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 798 } 799 800 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 801 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 802 { 803 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 804 } 805 806 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 807 { 808 u32 xcp_ctl; 809 810 /* Value is expected to be the same on all, fetch from first instance */ 811 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 812 813 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 814 } 815 816 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 817 int num_xccs_per_xcp) 818 { 819 int ret, i, num_xcc; 820 u32 tmp = 0; 821 822 if (adev->psp.funcs) { 823 ret = psp_spatial_partition(&adev->psp, 824 NUM_XCC(adev->gfx.xcc_mask) / 825 num_xccs_per_xcp); 826 if (ret) 827 return ret; 828 } else { 829 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 830 831 for (i = 0; i < num_xcc; i++) { 832 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 833 num_xccs_per_xcp); 834 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 835 i % num_xccs_per_xcp); 836 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 837 tmp); 838 } 839 ret = 0; 840 } 841 842 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 843 844 return ret; 845 } 846 847 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 848 { 849 int xcc; 850 851 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 852 if (!xcc) { 853 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 854 return -EINVAL; 855 } 856 857 return xcc - 1; 858 } 859 860 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 861 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 862 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 863 .read_wave_data = &gfx_v9_4_3_read_wave_data, 864 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 865 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 866 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 867 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 868 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 869 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 870 }; 871 872 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 873 struct aca_bank *bank, enum aca_smu_type type, 874 void *data) 875 { 876 struct aca_bank_info info; 877 u64 misc0; 878 u32 instlo; 879 int ret; 880 881 ret = aca_bank_info_decode(bank, &info); 882 if (ret) 883 return ret; 884 885 /* NOTE: overwrite info.die_id with xcd id for gfx */ 886 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 887 instlo &= GENMASK(31, 1); 888 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 889 890 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 891 892 switch (type) { 893 case ACA_SMU_TYPE_UE: 894 bank->aca_err_type = ACA_ERROR_TYPE_UE; 895 ret = aca_error_cache_log_bank_error(handle, &info, 896 ACA_ERROR_TYPE_UE, 1ULL); 897 break; 898 case ACA_SMU_TYPE_CE: 899 bank->aca_err_type = ACA_ERROR_TYPE_CE; 900 ret = aca_error_cache_log_bank_error(handle, &info, 901 ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0)); 902 break; 903 default: 904 return -EINVAL; 905 } 906 907 return ret; 908 } 909 910 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 911 enum aca_smu_type type, void *data) 912 { 913 u32 instlo; 914 915 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 916 instlo &= GENMASK(31, 1); 917 switch (instlo) { 918 case mmSMNAID_XCD0_MCA_SMU: 919 case mmSMNAID_XCD1_MCA_SMU: 920 case mmSMNXCD_XCD0_MCA_SMU: 921 return true; 922 default: 923 break; 924 } 925 926 return false; 927 } 928 929 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 930 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 931 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 932 }; 933 934 static const struct aca_info gfx_v9_4_3_aca_info = { 935 .hwip = ACA_HWIP_TYPE_SMU, 936 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 937 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 938 }; 939 940 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 941 { 942 u32 gb_addr_config; 943 944 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 945 adev->gfx.ras = &gfx_v9_4_3_ras; 946 947 adev->gfx.config.max_hw_contexts = 8; 948 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 949 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 950 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 951 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 952 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 953 954 adev->gfx.config.gb_addr_config = gb_addr_config; 955 956 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 957 REG_GET_FIELD( 958 adev->gfx.config.gb_addr_config, 959 GB_ADDR_CONFIG, 960 NUM_PIPES); 961 962 adev->gfx.config.max_tile_pipes = 963 adev->gfx.config.gb_addr_config_fields.num_pipes; 964 965 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 966 REG_GET_FIELD( 967 adev->gfx.config.gb_addr_config, 968 GB_ADDR_CONFIG, 969 NUM_BANKS); 970 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 971 REG_GET_FIELD( 972 adev->gfx.config.gb_addr_config, 973 GB_ADDR_CONFIG, 974 MAX_COMPRESSED_FRAGS); 975 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 976 REG_GET_FIELD( 977 adev->gfx.config.gb_addr_config, 978 GB_ADDR_CONFIG, 979 NUM_RB_PER_SE); 980 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 981 REG_GET_FIELD( 982 adev->gfx.config.gb_addr_config, 983 GB_ADDR_CONFIG, 984 NUM_SHADER_ENGINES); 985 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 986 REG_GET_FIELD( 987 adev->gfx.config.gb_addr_config, 988 GB_ADDR_CONFIG, 989 PIPE_INTERLEAVE_SIZE)); 990 991 return 0; 992 } 993 994 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 995 int xcc_id, int mec, int pipe, int queue) 996 { 997 unsigned irq_type; 998 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 999 unsigned int hw_prio; 1000 uint32_t xcc_doorbell_start; 1001 1002 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 1003 ring_id]; 1004 1005 /* mec0 is me1 */ 1006 ring->xcc_id = xcc_id; 1007 ring->me = mec + 1; 1008 ring->pipe = pipe; 1009 ring->queue = queue; 1010 1011 ring->ring_obj = NULL; 1012 ring->use_doorbell = true; 1013 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 1014 xcc_id * adev->doorbell_index.xcc_doorbell_range; 1015 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 1016 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 1017 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 1018 GFX9_MEC_HPD_SIZE; 1019 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1020 sprintf(ring->name, "comp_%d.%d.%d.%d", 1021 ring->xcc_id, ring->me, ring->pipe, ring->queue); 1022 1023 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1024 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1025 + ring->pipe; 1026 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1027 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1028 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1029 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1030 hw_prio, NULL); 1031 } 1032 1033 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1034 { 1035 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1036 uint32_t *ptr, num_xcc, inst; 1037 1038 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1039 1040 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1041 if (!ptr) { 1042 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1043 adev->gfx.ip_dump_core = NULL; 1044 } else { 1045 adev->gfx.ip_dump_core = ptr; 1046 } 1047 1048 /* Allocate memory for compute queue registers for all the instances */ 1049 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1050 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1051 adev->gfx.mec.num_queue_per_pipe; 1052 1053 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1054 if (!ptr) { 1055 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1056 adev->gfx.ip_dump_compute_queues = NULL; 1057 } else { 1058 adev->gfx.ip_dump_compute_queues = ptr; 1059 } 1060 } 1061 1062 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1063 { 1064 int i, j, k, r, ring_id, xcc_id, num_xcc; 1065 struct amdgpu_device *adev = ip_block->adev; 1066 1067 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1068 case IP_VERSION(9, 4, 3): 1069 case IP_VERSION(9, 4, 4): 1070 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1071 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1072 if (adev->gfx.mec_fw_version >= 153) { 1073 adev->gfx.enable_cleaner_shader = true; 1074 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1075 if (r) { 1076 adev->gfx.enable_cleaner_shader = false; 1077 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1078 } 1079 } 1080 break; 1081 default: 1082 adev->gfx.enable_cleaner_shader = false; 1083 break; 1084 } 1085 1086 adev->gfx.mec.num_mec = 2; 1087 adev->gfx.mec.num_pipe_per_mec = 4; 1088 adev->gfx.mec.num_queue_per_pipe = 8; 1089 1090 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1091 1092 /* EOP Event */ 1093 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1094 if (r) 1095 return r; 1096 1097 /* Bad opcode Event */ 1098 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1099 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1100 &adev->gfx.bad_op_irq); 1101 if (r) 1102 return r; 1103 1104 /* Privileged reg */ 1105 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1106 &adev->gfx.priv_reg_irq); 1107 if (r) 1108 return r; 1109 1110 /* Privileged inst */ 1111 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1112 &adev->gfx.priv_inst_irq); 1113 if (r) 1114 return r; 1115 1116 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1117 1118 r = adev->gfx.rlc.funcs->init(adev); 1119 if (r) { 1120 DRM_ERROR("Failed to init rlc BOs!\n"); 1121 return r; 1122 } 1123 1124 r = gfx_v9_4_3_mec_init(adev); 1125 if (r) { 1126 DRM_ERROR("Failed to init MEC BOs!\n"); 1127 return r; 1128 } 1129 1130 /* set up the compute queues - allocate horizontally across pipes */ 1131 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1132 ring_id = 0; 1133 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1134 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1135 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1136 k++) { 1137 if (!amdgpu_gfx_is_mec_queue_enabled( 1138 adev, xcc_id, i, k, j)) 1139 continue; 1140 1141 r = gfx_v9_4_3_compute_ring_init(adev, 1142 ring_id, 1143 xcc_id, 1144 i, k, j); 1145 if (r) 1146 return r; 1147 1148 ring_id++; 1149 } 1150 } 1151 } 1152 1153 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1154 if (r) { 1155 DRM_ERROR("Failed to init KIQ BOs!\n"); 1156 return r; 1157 } 1158 1159 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1160 if (r) 1161 return r; 1162 1163 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1164 r = amdgpu_gfx_mqd_sw_init(adev, 1165 sizeof(struct v9_mqd_allocation), xcc_id); 1166 if (r) 1167 return r; 1168 } 1169 1170 adev->gfx.compute_supported_reset = 1171 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1172 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1173 case IP_VERSION(9, 4, 3): 1174 case IP_VERSION(9, 4, 4): 1175 if (adev->gfx.mec_fw_version >= 155) { 1176 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1177 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1178 } 1179 break; 1180 default: 1181 break; 1182 } 1183 r = gfx_v9_4_3_gpu_early_init(adev); 1184 if (r) 1185 return r; 1186 1187 r = amdgpu_gfx_ras_sw_init(adev); 1188 if (r) 1189 return r; 1190 1191 r = amdgpu_gfx_sysfs_init(adev); 1192 if (r) 1193 return r; 1194 1195 gfx_v9_4_3_alloc_ip_dump(adev); 1196 1197 return 0; 1198 } 1199 1200 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1201 { 1202 int i, num_xcc; 1203 struct amdgpu_device *adev = ip_block->adev; 1204 1205 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1206 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1207 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1208 1209 for (i = 0; i < num_xcc; i++) { 1210 amdgpu_gfx_mqd_sw_fini(adev, i); 1211 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1212 amdgpu_gfx_kiq_fini(adev, i); 1213 } 1214 1215 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1216 1217 gfx_v9_4_3_mec_fini(adev); 1218 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1219 gfx_v9_4_3_free_microcode(adev); 1220 amdgpu_gfx_sysfs_fini(adev); 1221 1222 kfree(adev->gfx.ip_dump_core); 1223 kfree(adev->gfx.ip_dump_compute_queues); 1224 1225 return 0; 1226 } 1227 1228 #define DEFAULT_SH_MEM_BASES (0x6000) 1229 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1230 int xcc_id) 1231 { 1232 int i; 1233 uint32_t sh_mem_config; 1234 uint32_t sh_mem_bases; 1235 uint32_t data; 1236 1237 /* 1238 * Configure apertures: 1239 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1240 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1241 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1242 */ 1243 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1244 1245 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1246 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1247 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1248 1249 mutex_lock(&adev->srbm_mutex); 1250 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1251 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1252 /* CP and shaders */ 1253 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1254 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1255 1256 /* Enable trap for each kfd vmid. */ 1257 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1258 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1259 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1260 } 1261 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1262 mutex_unlock(&adev->srbm_mutex); 1263 1264 /* 1265 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1266 * access. These should be enabled by FW for target VMIDs. 1267 */ 1268 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1269 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1270 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1271 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1272 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1273 } 1274 } 1275 1276 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1277 { 1278 int vmid; 1279 1280 /* 1281 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1282 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1283 * the driver can enable them for graphics. VMID0 should maintain 1284 * access so that HWS firmware can save/restore entries. 1285 */ 1286 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1287 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1288 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1289 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1290 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1291 } 1292 } 1293 1294 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1295 int xcc_id) 1296 { 1297 u32 tmp; 1298 int i; 1299 1300 /* XXX SH_MEM regs */ 1301 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1302 mutex_lock(&adev->srbm_mutex); 1303 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1304 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1305 /* CP and shaders */ 1306 if (i == 0) { 1307 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1308 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1309 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1310 !!adev->gmc.noretry); 1311 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1312 regSH_MEM_CONFIG, tmp); 1313 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1314 regSH_MEM_BASES, 0); 1315 } else { 1316 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1317 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1318 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1319 !!adev->gmc.noretry); 1320 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1321 regSH_MEM_CONFIG, tmp); 1322 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1323 (adev->gmc.private_aperture_start >> 1324 48)); 1325 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1326 (adev->gmc.shared_aperture_start >> 1327 48)); 1328 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1329 regSH_MEM_BASES, tmp); 1330 } 1331 } 1332 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1333 1334 mutex_unlock(&adev->srbm_mutex); 1335 1336 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1337 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1338 } 1339 1340 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1341 { 1342 int i, num_xcc; 1343 1344 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1345 1346 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1347 adev->gfx.config.db_debug2 = 1348 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1349 1350 for (i = 0; i < num_xcc; i++) 1351 gfx_v9_4_3_xcc_constants_init(adev, i); 1352 } 1353 1354 static void 1355 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1356 int xcc_id) 1357 { 1358 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1359 } 1360 1361 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1362 { 1363 /* 1364 * Rlc save restore list is workable since v2_1. 1365 * And it's needed by gfxoff feature. 1366 */ 1367 if (adev->gfx.rlc.is_rlc_v2_1) 1368 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1369 } 1370 1371 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1372 { 1373 uint32_t data; 1374 1375 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1376 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1377 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1378 } 1379 1380 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1381 { 1382 uint32_t rlc_setting; 1383 1384 /* if RLC is not enabled, do nothing */ 1385 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1386 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1387 return false; 1388 1389 return true; 1390 } 1391 1392 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1393 { 1394 uint32_t data; 1395 unsigned i; 1396 1397 data = RLC_SAFE_MODE__CMD_MASK; 1398 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1399 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1400 1401 /* wait for RLC_SAFE_MODE */ 1402 for (i = 0; i < adev->usec_timeout; i++) { 1403 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1404 break; 1405 udelay(1); 1406 } 1407 } 1408 1409 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1410 int xcc_id) 1411 { 1412 uint32_t data; 1413 1414 data = RLC_SAFE_MODE__CMD_MASK; 1415 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1416 } 1417 1418 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1419 { 1420 int xcc_id, num_xcc; 1421 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1422 1423 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1424 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1425 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1426 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1427 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1428 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1429 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1430 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1431 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1432 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1433 } 1434 adev->gfx.rlc.rlcg_reg_access_supported = true; 1435 } 1436 1437 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1438 { 1439 /* init spm vmid with 0xf */ 1440 if (adev->gfx.rlc.funcs->update_spm_vmid) 1441 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1442 1443 return 0; 1444 } 1445 1446 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1447 int xcc_id) 1448 { 1449 u32 i, j, k; 1450 u32 mask; 1451 1452 mutex_lock(&adev->grbm_idx_mutex); 1453 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1454 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1455 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1456 xcc_id); 1457 for (k = 0; k < adev->usec_timeout; k++) { 1458 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1459 break; 1460 udelay(1); 1461 } 1462 if (k == adev->usec_timeout) { 1463 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1464 0xffffffff, 1465 0xffffffff, xcc_id); 1466 mutex_unlock(&adev->grbm_idx_mutex); 1467 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1468 i, j); 1469 return; 1470 } 1471 } 1472 } 1473 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1474 xcc_id); 1475 mutex_unlock(&adev->grbm_idx_mutex); 1476 1477 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1478 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1479 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1480 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1481 for (k = 0; k < adev->usec_timeout; k++) { 1482 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1483 break; 1484 udelay(1); 1485 } 1486 } 1487 1488 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1489 bool enable, int xcc_id) 1490 { 1491 u32 tmp; 1492 1493 /* These interrupts should be enabled to drive DS clock */ 1494 1495 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1496 1497 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1498 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1499 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1500 1501 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1502 } 1503 1504 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1505 { 1506 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1507 RLC_ENABLE_F32, 0); 1508 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1509 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1510 } 1511 1512 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1513 { 1514 int i, num_xcc; 1515 1516 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1517 for (i = 0; i < num_xcc; i++) 1518 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1519 } 1520 1521 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1522 { 1523 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1524 SOFT_RESET_RLC, 1); 1525 udelay(50); 1526 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1527 SOFT_RESET_RLC, 0); 1528 udelay(50); 1529 } 1530 1531 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1532 { 1533 int i, num_xcc; 1534 1535 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1536 for (i = 0; i < num_xcc; i++) 1537 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1538 } 1539 1540 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1541 { 1542 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1543 RLC_ENABLE_F32, 1); 1544 udelay(50); 1545 1546 /* carrizo do enable cp interrupt after cp inited */ 1547 if (!(adev->flags & AMD_IS_APU)) { 1548 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1549 udelay(50); 1550 } 1551 } 1552 1553 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1554 { 1555 #ifdef AMDGPU_RLC_DEBUG_RETRY 1556 u32 rlc_ucode_ver; 1557 #endif 1558 int i, num_xcc; 1559 1560 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1561 for (i = 0; i < num_xcc; i++) { 1562 gfx_v9_4_3_xcc_rlc_start(adev, i); 1563 #ifdef AMDGPU_RLC_DEBUG_RETRY 1564 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1565 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1566 if (rlc_ucode_ver == 0x108) { 1567 dev_info(adev->dev, 1568 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1569 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1570 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1571 * default is 0x9C4 to create a 100us interval */ 1572 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1573 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1574 * to disable the page fault retry interrupts, default is 1575 * 0x100 (256) */ 1576 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1577 } 1578 #endif 1579 } 1580 } 1581 1582 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1583 int xcc_id) 1584 { 1585 const struct rlc_firmware_header_v2_0 *hdr; 1586 const __le32 *fw_data; 1587 unsigned i, fw_size; 1588 1589 if (!adev->gfx.rlc_fw) 1590 return -EINVAL; 1591 1592 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1593 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1594 1595 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1596 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1597 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1598 1599 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1600 RLCG_UCODE_LOADING_START_ADDRESS); 1601 for (i = 0; i < fw_size; i++) { 1602 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1603 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1604 msleep(1); 1605 } 1606 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1607 } 1608 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1609 1610 return 0; 1611 } 1612 1613 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1614 { 1615 int r; 1616 1617 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1618 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1619 /* legacy rlc firmware loading */ 1620 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1621 if (r) 1622 return r; 1623 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1624 } 1625 1626 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1627 /* disable CG */ 1628 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1629 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1630 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1631 1632 return 0; 1633 } 1634 1635 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1636 { 1637 int r, i, num_xcc; 1638 1639 if (amdgpu_sriov_vf(adev)) 1640 return 0; 1641 1642 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1643 for (i = 0; i < num_xcc; i++) { 1644 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1645 if (r) 1646 return r; 1647 } 1648 1649 return 0; 1650 } 1651 1652 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1653 unsigned vmid) 1654 { 1655 u32 reg, pre_data, data; 1656 1657 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1658 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1659 pre_data = RREG32_NO_KIQ(reg); 1660 else 1661 pre_data = RREG32(reg); 1662 1663 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1664 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1665 1666 if (pre_data != data) { 1667 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1668 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1669 } else 1670 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1671 } 1672 } 1673 1674 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1675 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1676 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1677 }; 1678 1679 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1680 uint32_t offset, 1681 struct soc15_reg_rlcg *entries, int arr_size) 1682 { 1683 int i, inst; 1684 uint32_t reg; 1685 1686 if (!entries) 1687 return false; 1688 1689 for (i = 0; i < arr_size; i++) { 1690 const struct soc15_reg_rlcg *entry; 1691 1692 entry = &entries[i]; 1693 inst = adev->ip_map.logical_to_dev_inst ? 1694 adev->ip_map.logical_to_dev_inst( 1695 adev, entry->hwip, entry->instance) : 1696 entry->instance; 1697 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1698 entry->reg; 1699 if (offset == reg) 1700 return true; 1701 } 1702 1703 return false; 1704 } 1705 1706 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1707 { 1708 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1709 (void *)rlcg_access_gc_9_4_3, 1710 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1711 } 1712 1713 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1714 bool enable, int xcc_id) 1715 { 1716 if (enable) { 1717 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1718 } else { 1719 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1720 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1721 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1722 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1723 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1724 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1725 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1726 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1727 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1728 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1729 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1730 } 1731 udelay(50); 1732 } 1733 1734 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1735 int xcc_id) 1736 { 1737 const struct gfx_firmware_header_v1_0 *mec_hdr; 1738 const __le32 *fw_data; 1739 unsigned i; 1740 u32 tmp; 1741 u32 mec_ucode_addr_offset; 1742 u32 mec_ucode_data_offset; 1743 1744 if (!adev->gfx.mec_fw) 1745 return -EINVAL; 1746 1747 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1748 1749 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1750 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1751 1752 fw_data = (const __le32 *) 1753 (adev->gfx.mec_fw->data + 1754 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1755 tmp = 0; 1756 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1757 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1758 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1759 1760 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1761 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1762 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1763 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1764 1765 mec_ucode_addr_offset = 1766 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1767 mec_ucode_data_offset = 1768 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1769 1770 /* MEC1 */ 1771 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1772 for (i = 0; i < mec_hdr->jt_size; i++) 1773 WREG32(mec_ucode_data_offset, 1774 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1775 1776 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1777 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1778 1779 return 0; 1780 } 1781 1782 /* KIQ functions */ 1783 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1784 { 1785 uint32_t tmp; 1786 struct amdgpu_device *adev = ring->adev; 1787 1788 /* tell RLC which is KIQ queue */ 1789 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1790 tmp &= 0xffffff00; 1791 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1792 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1793 } 1794 1795 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1796 { 1797 struct amdgpu_device *adev = ring->adev; 1798 1799 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1800 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1801 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1802 mqd->cp_hqd_queue_priority = 1803 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1804 } 1805 } 1806 } 1807 1808 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1809 { 1810 struct amdgpu_device *adev = ring->adev; 1811 struct v9_mqd *mqd = ring->mqd_ptr; 1812 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1813 uint32_t tmp; 1814 1815 mqd->header = 0xC0310800; 1816 mqd->compute_pipelinestat_enable = 0x00000001; 1817 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1818 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1819 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1820 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1821 mqd->compute_misc_reserved = 0x00000003; 1822 1823 mqd->dynamic_cu_mask_addr_lo = 1824 lower_32_bits(ring->mqd_gpu_addr 1825 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1826 mqd->dynamic_cu_mask_addr_hi = 1827 upper_32_bits(ring->mqd_gpu_addr 1828 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1829 1830 eop_base_addr = ring->eop_gpu_addr >> 8; 1831 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1832 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1833 1834 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1835 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1836 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1837 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1838 1839 mqd->cp_hqd_eop_control = tmp; 1840 1841 /* enable doorbell? */ 1842 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1843 1844 if (ring->use_doorbell) { 1845 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1846 DOORBELL_OFFSET, ring->doorbell_index); 1847 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1848 DOORBELL_EN, 1); 1849 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1850 DOORBELL_SOURCE, 0); 1851 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1852 DOORBELL_HIT, 0); 1853 if (amdgpu_sriov_vf(adev)) 1854 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1855 DOORBELL_MODE, 1); 1856 } else { 1857 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1858 DOORBELL_EN, 0); 1859 } 1860 1861 mqd->cp_hqd_pq_doorbell_control = tmp; 1862 1863 /* disable the queue if it's active */ 1864 ring->wptr = 0; 1865 mqd->cp_hqd_dequeue_request = 0; 1866 mqd->cp_hqd_pq_rptr = 0; 1867 mqd->cp_hqd_pq_wptr_lo = 0; 1868 mqd->cp_hqd_pq_wptr_hi = 0; 1869 1870 /* set the pointer to the MQD */ 1871 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1872 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1873 1874 /* set MQD vmid to 0 */ 1875 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1876 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1877 mqd->cp_mqd_control = tmp; 1878 1879 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1880 hqd_gpu_addr = ring->gpu_addr >> 8; 1881 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1882 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1883 1884 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1885 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1886 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1887 (order_base_2(ring->ring_size / 4) - 1)); 1888 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1889 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1890 #ifdef __BIG_ENDIAN 1891 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1892 #endif 1893 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1894 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1895 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1896 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1897 mqd->cp_hqd_pq_control = tmp; 1898 1899 /* set the wb address whether it's enabled or not */ 1900 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1901 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1902 mqd->cp_hqd_pq_rptr_report_addr_hi = 1903 upper_32_bits(wb_gpu_addr) & 0xffff; 1904 1905 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1906 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1907 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1908 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1909 1910 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1911 ring->wptr = 0; 1912 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1913 1914 /* set the vmid for the queue */ 1915 mqd->cp_hqd_vmid = 0; 1916 1917 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1918 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1919 mqd->cp_hqd_persistent_state = tmp; 1920 1921 /* set MIN_IB_AVAIL_SIZE */ 1922 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1923 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1924 mqd->cp_hqd_ib_control = tmp; 1925 1926 /* set static priority for a queue/ring */ 1927 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1928 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1929 1930 /* map_queues packet doesn't need activate the queue, 1931 * so only kiq need set this field. 1932 */ 1933 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1934 mqd->cp_hqd_active = 1; 1935 1936 return 0; 1937 } 1938 1939 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1940 int xcc_id) 1941 { 1942 struct amdgpu_device *adev = ring->adev; 1943 struct v9_mqd *mqd = ring->mqd_ptr; 1944 int j; 1945 1946 /* disable wptr polling */ 1947 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1948 1949 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1950 mqd->cp_hqd_eop_base_addr_lo); 1951 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1952 mqd->cp_hqd_eop_base_addr_hi); 1953 1954 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1955 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1956 mqd->cp_hqd_eop_control); 1957 1958 /* enable doorbell? */ 1959 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1960 mqd->cp_hqd_pq_doorbell_control); 1961 1962 /* disable the queue if it's active */ 1963 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1964 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1965 for (j = 0; j < adev->usec_timeout; j++) { 1966 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1967 break; 1968 udelay(1); 1969 } 1970 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1971 mqd->cp_hqd_dequeue_request); 1972 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1973 mqd->cp_hqd_pq_rptr); 1974 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1975 mqd->cp_hqd_pq_wptr_lo); 1976 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1977 mqd->cp_hqd_pq_wptr_hi); 1978 } 1979 1980 /* set the pointer to the MQD */ 1981 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1982 mqd->cp_mqd_base_addr_lo); 1983 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1984 mqd->cp_mqd_base_addr_hi); 1985 1986 /* set MQD vmid to 0 */ 1987 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1988 mqd->cp_mqd_control); 1989 1990 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1991 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1992 mqd->cp_hqd_pq_base_lo); 1993 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1994 mqd->cp_hqd_pq_base_hi); 1995 1996 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1997 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1998 mqd->cp_hqd_pq_control); 1999 2000 /* set the wb address whether it's enabled or not */ 2001 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2002 mqd->cp_hqd_pq_rptr_report_addr_lo); 2003 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2004 mqd->cp_hqd_pq_rptr_report_addr_hi); 2005 2006 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2007 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2008 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2009 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2010 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2011 2012 /* enable the doorbell if requested */ 2013 if (ring->use_doorbell) { 2014 WREG32_SOC15( 2015 GC, GET_INST(GC, xcc_id), 2016 regCP_MEC_DOORBELL_RANGE_LOWER, 2017 ((adev->doorbell_index.kiq + 2018 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2019 2) << 2); 2020 WREG32_SOC15( 2021 GC, GET_INST(GC, xcc_id), 2022 regCP_MEC_DOORBELL_RANGE_UPPER, 2023 ((adev->doorbell_index.userqueue_end + 2024 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2025 2) << 2); 2026 } 2027 2028 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2029 mqd->cp_hqd_pq_doorbell_control); 2030 2031 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2032 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2033 mqd->cp_hqd_pq_wptr_lo); 2034 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2035 mqd->cp_hqd_pq_wptr_hi); 2036 2037 /* set the vmid for the queue */ 2038 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2039 2040 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2041 mqd->cp_hqd_persistent_state); 2042 2043 /* activate the queue */ 2044 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2045 mqd->cp_hqd_active); 2046 2047 if (ring->use_doorbell) 2048 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2049 2050 return 0; 2051 } 2052 2053 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2054 int xcc_id) 2055 { 2056 struct amdgpu_device *adev = ring->adev; 2057 int j; 2058 2059 /* disable the queue if it's active */ 2060 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2061 2062 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2063 2064 for (j = 0; j < adev->usec_timeout; j++) { 2065 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2066 break; 2067 udelay(1); 2068 } 2069 2070 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2071 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2072 2073 /* Manual disable if dequeue request times out */ 2074 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2075 } 2076 2077 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2078 0); 2079 } 2080 2081 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2082 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2083 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2084 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2085 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2086 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2087 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2088 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2089 2090 return 0; 2091 } 2092 2093 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2094 { 2095 struct amdgpu_device *adev = ring->adev; 2096 struct v9_mqd *mqd = ring->mqd_ptr; 2097 struct v9_mqd *tmp_mqd; 2098 2099 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2100 2101 /* GPU could be in bad state during probe, driver trigger the reset 2102 * after load the SMU, in this case , the mqd is not be initialized. 2103 * driver need to re-init the mqd. 2104 * check mqd->cp_hqd_pq_control since this value should not be 0 2105 */ 2106 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2107 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2108 /* for GPU_RESET case , reset MQD to a clean status */ 2109 if (adev->gfx.kiq[xcc_id].mqd_backup) 2110 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2111 2112 /* reset ring buffer */ 2113 ring->wptr = 0; 2114 amdgpu_ring_clear_ring(ring); 2115 mutex_lock(&adev->srbm_mutex); 2116 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2117 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2118 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2119 mutex_unlock(&adev->srbm_mutex); 2120 } else { 2121 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2122 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2123 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2124 mutex_lock(&adev->srbm_mutex); 2125 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2126 amdgpu_ring_clear_ring(ring); 2127 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2128 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2129 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2130 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2131 mutex_unlock(&adev->srbm_mutex); 2132 2133 if (adev->gfx.kiq[xcc_id].mqd_backup) 2134 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2135 } 2136 2137 return 0; 2138 } 2139 2140 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) 2141 { 2142 struct amdgpu_device *adev = ring->adev; 2143 struct v9_mqd *mqd = ring->mqd_ptr; 2144 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2145 struct v9_mqd *tmp_mqd; 2146 2147 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2148 * is not be initialized before 2149 */ 2150 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2151 2152 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2153 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2154 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2155 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2156 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2157 mutex_lock(&adev->srbm_mutex); 2158 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2159 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2160 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2161 mutex_unlock(&adev->srbm_mutex); 2162 2163 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2164 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2165 } else { 2166 /* restore MQD to a clean status */ 2167 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2168 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2169 /* reset ring buffer */ 2170 ring->wptr = 0; 2171 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2172 amdgpu_ring_clear_ring(ring); 2173 } 2174 2175 return 0; 2176 } 2177 2178 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2179 { 2180 struct amdgpu_ring *ring; 2181 int j; 2182 2183 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2184 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2185 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2186 mutex_lock(&adev->srbm_mutex); 2187 soc15_grbm_select(adev, ring->me, 2188 ring->pipe, 2189 ring->queue, 0, GET_INST(GC, xcc_id)); 2190 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2191 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2192 mutex_unlock(&adev->srbm_mutex); 2193 } 2194 } 2195 2196 return 0; 2197 } 2198 2199 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2200 { 2201 struct amdgpu_ring *ring; 2202 int r; 2203 2204 ring = &adev->gfx.kiq[xcc_id].ring; 2205 2206 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2207 if (unlikely(r != 0)) 2208 return r; 2209 2210 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2211 if (unlikely(r != 0)) { 2212 amdgpu_bo_unreserve(ring->mqd_obj); 2213 return r; 2214 } 2215 2216 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 2217 amdgpu_bo_kunmap(ring->mqd_obj); 2218 ring->mqd_ptr = NULL; 2219 amdgpu_bo_unreserve(ring->mqd_obj); 2220 return 0; 2221 } 2222 2223 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2224 { 2225 struct amdgpu_ring *ring = NULL; 2226 int r = 0, i; 2227 2228 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2229 2230 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2231 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2232 2233 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2234 if (unlikely(r != 0)) 2235 goto done; 2236 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2237 if (!r) { 2238 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2239 amdgpu_bo_kunmap(ring->mqd_obj); 2240 ring->mqd_ptr = NULL; 2241 } 2242 amdgpu_bo_unreserve(ring->mqd_obj); 2243 if (r) 2244 goto done; 2245 } 2246 2247 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2248 done: 2249 return r; 2250 } 2251 2252 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2253 { 2254 struct amdgpu_ring *ring; 2255 int r, j; 2256 2257 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2258 2259 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2260 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2261 2262 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2263 if (r) 2264 return r; 2265 } else { 2266 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2267 } 2268 2269 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2270 if (r) 2271 return r; 2272 2273 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2274 if (r) 2275 return r; 2276 2277 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2278 ring = &adev->gfx.compute_ring 2279 [j + xcc_id * adev->gfx.num_compute_rings]; 2280 r = amdgpu_ring_test_helper(ring); 2281 if (r) 2282 return r; 2283 } 2284 2285 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2286 2287 return 0; 2288 } 2289 2290 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2291 { 2292 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2293 2294 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2295 if (amdgpu_sriov_vf(adev)) { 2296 enum amdgpu_gfx_partition mode; 2297 2298 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2299 AMDGPU_XCP_FL_NONE); 2300 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2301 return -EINVAL; 2302 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2303 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2304 num_xcp = num_xcc / num_xcc_per_xcp; 2305 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2306 2307 } else { 2308 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2309 AMDGPU_XCP_FL_NONE) == 2310 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2311 r = amdgpu_xcp_switch_partition_mode( 2312 adev->xcp_mgr, amdgpu_user_partt_mode); 2313 } 2314 if (r) 2315 return r; 2316 2317 for (i = 0; i < num_xcc; i++) { 2318 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2319 if (r) 2320 return r; 2321 } 2322 2323 return 0; 2324 } 2325 2326 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2327 { 2328 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2329 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2330 2331 if (amdgpu_sriov_vf(adev)) { 2332 /* must disable polling for SRIOV when hw finished, otherwise 2333 * CPC engine may still keep fetching WB address which is already 2334 * invalid after sw finished and trigger DMAR reading error in 2335 * hypervisor side. 2336 */ 2337 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2338 return; 2339 } 2340 2341 /* Use deinitialize sequence from CAIL when unbinding device 2342 * from driver, otherwise KIQ is hanging when binding back 2343 */ 2344 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2345 mutex_lock(&adev->srbm_mutex); 2346 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2347 adev->gfx.kiq[xcc_id].ring.pipe, 2348 adev->gfx.kiq[xcc_id].ring.queue, 0, 2349 GET_INST(GC, xcc_id)); 2350 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2351 xcc_id); 2352 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2353 mutex_unlock(&adev->srbm_mutex); 2354 } 2355 2356 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2357 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2358 } 2359 2360 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2361 { 2362 int r; 2363 struct amdgpu_device *adev = ip_block->adev; 2364 2365 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2366 adev->gfx.cleaner_shader_ptr); 2367 2368 if (!amdgpu_sriov_vf(adev)) 2369 gfx_v9_4_3_init_golden_registers(adev); 2370 2371 gfx_v9_4_3_constants_init(adev); 2372 2373 r = adev->gfx.rlc.funcs->resume(adev); 2374 if (r) 2375 return r; 2376 2377 r = gfx_v9_4_3_cp_resume(adev); 2378 if (r) 2379 return r; 2380 2381 return r; 2382 } 2383 2384 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2385 { 2386 struct amdgpu_device *adev = ip_block->adev; 2387 int i, num_xcc; 2388 2389 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2390 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2391 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2392 2393 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2394 for (i = 0; i < num_xcc; i++) { 2395 gfx_v9_4_3_xcc_fini(adev, i); 2396 } 2397 2398 return 0; 2399 } 2400 2401 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2402 { 2403 return gfx_v9_4_3_hw_fini(ip_block); 2404 } 2405 2406 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2407 { 2408 return gfx_v9_4_3_hw_init(ip_block); 2409 } 2410 2411 static bool gfx_v9_4_3_is_idle(void *handle) 2412 { 2413 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2414 int i, num_xcc; 2415 2416 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2417 for (i = 0; i < num_xcc; i++) { 2418 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2419 GRBM_STATUS, GUI_ACTIVE)) 2420 return false; 2421 } 2422 return true; 2423 } 2424 2425 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2426 { 2427 unsigned i; 2428 struct amdgpu_device *adev = ip_block->adev; 2429 2430 for (i = 0; i < adev->usec_timeout; i++) { 2431 if (gfx_v9_4_3_is_idle(adev)) 2432 return 0; 2433 udelay(1); 2434 } 2435 return -ETIMEDOUT; 2436 } 2437 2438 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2439 { 2440 u32 grbm_soft_reset = 0; 2441 u32 tmp; 2442 struct amdgpu_device *adev = ip_block->adev; 2443 2444 /* GRBM_STATUS */ 2445 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2446 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2447 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2448 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2449 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2450 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2451 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2452 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2453 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2454 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2455 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2456 } 2457 2458 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2459 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2460 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2461 } 2462 2463 /* GRBM_STATUS2 */ 2464 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2465 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2466 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2467 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2468 2469 2470 if (grbm_soft_reset) { 2471 /* stop the rlc */ 2472 adev->gfx.rlc.funcs->stop(adev); 2473 2474 /* Disable MEC parsing/prefetching */ 2475 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2476 2477 if (grbm_soft_reset) { 2478 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2479 tmp |= grbm_soft_reset; 2480 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2481 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2482 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2483 2484 udelay(50); 2485 2486 tmp &= ~grbm_soft_reset; 2487 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2488 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2489 } 2490 2491 /* Wait a little for things to settle down */ 2492 udelay(50); 2493 } 2494 return 0; 2495 } 2496 2497 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2498 uint32_t vmid, 2499 uint32_t gds_base, uint32_t gds_size, 2500 uint32_t gws_base, uint32_t gws_size, 2501 uint32_t oa_base, uint32_t oa_size) 2502 { 2503 struct amdgpu_device *adev = ring->adev; 2504 2505 /* GDS Base */ 2506 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2507 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2508 gds_base); 2509 2510 /* GDS Size */ 2511 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2512 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2513 gds_size); 2514 2515 /* GWS */ 2516 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2517 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2518 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2519 2520 /* OA */ 2521 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2522 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2523 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2524 } 2525 2526 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2527 { 2528 struct amdgpu_device *adev = ip_block->adev; 2529 2530 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2531 AMDGPU_MAX_COMPUTE_RINGS); 2532 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2533 gfx_v9_4_3_set_ring_funcs(adev); 2534 gfx_v9_4_3_set_irq_funcs(adev); 2535 gfx_v9_4_3_set_gds_init(adev); 2536 gfx_v9_4_3_set_rlc_funcs(adev); 2537 2538 /* init rlcg reg access ctrl */ 2539 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2540 2541 return gfx_v9_4_3_init_microcode(adev); 2542 } 2543 2544 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2545 { 2546 struct amdgpu_device *adev = ip_block->adev; 2547 int r; 2548 2549 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2550 if (r) 2551 return r; 2552 2553 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2554 if (r) 2555 return r; 2556 2557 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2558 if (r) 2559 return r; 2560 2561 if (adev->gfx.ras && 2562 adev->gfx.ras->enable_watchdog_timer) 2563 adev->gfx.ras->enable_watchdog_timer(adev); 2564 2565 return 0; 2566 } 2567 2568 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2569 bool enable, int xcc_id) 2570 { 2571 uint32_t def, data; 2572 2573 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2574 return; 2575 2576 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2577 regRLC_CGTT_MGCG_OVERRIDE); 2578 2579 if (enable) 2580 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2581 else 2582 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2583 2584 if (def != data) 2585 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2586 regRLC_CGTT_MGCG_OVERRIDE, data); 2587 2588 } 2589 2590 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2591 bool enable, int xcc_id) 2592 { 2593 uint32_t def, data; 2594 2595 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2596 return; 2597 2598 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2599 regRLC_CGTT_MGCG_OVERRIDE); 2600 2601 if (enable) 2602 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2603 else 2604 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2605 2606 if (def != data) 2607 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2608 regRLC_CGTT_MGCG_OVERRIDE, data); 2609 } 2610 2611 static void 2612 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2613 bool enable, int xcc_id) 2614 { 2615 uint32_t data, def; 2616 2617 /* It is disabled by HW by default */ 2618 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2619 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2620 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2621 2622 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2623 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2624 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2625 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2626 2627 if (def != data) 2628 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2629 2630 /* MGLS is a global flag to control all MGLS in GFX */ 2631 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2632 /* 2 - RLC memory Light sleep */ 2633 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2634 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2635 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2636 if (def != data) 2637 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2638 } 2639 /* 3 - CP memory Light sleep */ 2640 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2641 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2642 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2643 if (def != data) 2644 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2645 } 2646 } 2647 } else { 2648 /* 1 - MGCG_OVERRIDE */ 2649 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2650 2651 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2652 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2653 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2654 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2655 2656 if (def != data) 2657 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2658 2659 /* 2 - disable MGLS in RLC */ 2660 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2661 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2662 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2663 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2664 } 2665 2666 /* 3 - disable MGLS in CP */ 2667 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2668 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2669 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2670 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2671 } 2672 } 2673 2674 } 2675 2676 static void 2677 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2678 bool enable, int xcc_id) 2679 { 2680 uint32_t def, data; 2681 2682 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2683 2684 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2685 /* unset CGCG override */ 2686 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2687 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2688 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2689 else 2690 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2691 /* update CGCG and CGLS override bits */ 2692 if (def != data) 2693 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2694 2695 /* CGCG Hysteresis: 400us */ 2696 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2697 2698 data = (0x2710 2699 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2700 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2701 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2702 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2703 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2704 if (def != data) 2705 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2706 2707 /* set IDLE_POLL_COUNT(0x33450100)*/ 2708 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2709 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2710 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2711 if (def != data) 2712 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2713 } else { 2714 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2715 /* reset CGCG/CGLS bits */ 2716 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2717 /* disable cgcg and cgls in FSM */ 2718 if (def != data) 2719 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2720 } 2721 2722 } 2723 2724 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2725 bool enable, int xcc_id) 2726 { 2727 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2728 2729 if (enable) { 2730 /* FGCG */ 2731 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2732 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2733 2734 /* CGCG/CGLS should be enabled after MGCG/MGLS 2735 * === MGCG + MGLS === 2736 */ 2737 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2738 xcc_id); 2739 /* === CGCG + CGLS === */ 2740 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2741 xcc_id); 2742 } else { 2743 /* CGCG/CGLS should be disabled before MGCG/MGLS 2744 * === CGCG + CGLS === 2745 */ 2746 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2747 xcc_id); 2748 /* === MGCG + MGLS === */ 2749 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2750 xcc_id); 2751 2752 /* FGCG */ 2753 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2754 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2755 } 2756 2757 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2758 2759 return 0; 2760 } 2761 2762 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2763 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2764 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2765 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2766 .init = gfx_v9_4_3_rlc_init, 2767 .resume = gfx_v9_4_3_rlc_resume, 2768 .stop = gfx_v9_4_3_rlc_stop, 2769 .reset = gfx_v9_4_3_rlc_reset, 2770 .start = gfx_v9_4_3_rlc_start, 2771 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2772 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2773 }; 2774 2775 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2776 enum amd_powergating_state state) 2777 { 2778 return 0; 2779 } 2780 2781 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2782 enum amd_clockgating_state state) 2783 { 2784 struct amdgpu_device *adev = ip_block->adev; 2785 int i, num_xcc; 2786 2787 if (amdgpu_sriov_vf(adev)) 2788 return 0; 2789 2790 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2791 for (i = 0; i < num_xcc; i++) 2792 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2793 adev, state == AMD_CG_STATE_GATE, i); 2794 2795 return 0; 2796 } 2797 2798 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2799 { 2800 struct amdgpu_device *adev = ip_block->adev; 2801 int data; 2802 2803 if (amdgpu_sriov_vf(adev)) 2804 *flags = 0; 2805 2806 /* AMD_CG_SUPPORT_GFX_MGCG */ 2807 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2808 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2809 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2810 2811 /* AMD_CG_SUPPORT_GFX_CGCG */ 2812 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2813 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2814 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2815 2816 /* AMD_CG_SUPPORT_GFX_CGLS */ 2817 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2818 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2819 2820 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2821 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2822 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2823 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2824 2825 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2826 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2827 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2828 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2829 } 2830 2831 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2832 { 2833 struct amdgpu_device *adev = ring->adev; 2834 u32 ref_and_mask, reg_mem_engine; 2835 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2836 2837 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2838 switch (ring->me) { 2839 case 1: 2840 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2841 break; 2842 case 2: 2843 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2844 break; 2845 default: 2846 return; 2847 } 2848 reg_mem_engine = 0; 2849 } else { 2850 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2851 reg_mem_engine = 1; /* pfp */ 2852 } 2853 2854 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2855 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2856 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2857 ref_and_mask, ref_and_mask, 0x20); 2858 } 2859 2860 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2861 struct amdgpu_job *job, 2862 struct amdgpu_ib *ib, 2863 uint32_t flags) 2864 { 2865 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2866 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2867 2868 /* Currently, there is a high possibility to get wave ID mismatch 2869 * between ME and GDS, leading to a hw deadlock, because ME generates 2870 * different wave IDs than the GDS expects. This situation happens 2871 * randomly when at least 5 compute pipes use GDS ordered append. 2872 * The wave IDs generated by ME are also wrong after suspend/resume. 2873 * Those are probably bugs somewhere else in the kernel driver. 2874 * 2875 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2876 * GDS to 0 for this ring (me/pipe). 2877 */ 2878 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2879 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2880 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2881 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2882 } 2883 2884 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2885 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2886 amdgpu_ring_write(ring, 2887 #ifdef __BIG_ENDIAN 2888 (2 << 0) | 2889 #endif 2890 lower_32_bits(ib->gpu_addr)); 2891 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2892 amdgpu_ring_write(ring, control); 2893 } 2894 2895 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2896 u64 seq, unsigned flags) 2897 { 2898 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2899 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2900 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2901 2902 /* RELEASE_MEM - flush caches, send int */ 2903 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2904 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2905 EOP_TC_NC_ACTION_EN) : 2906 (EOP_TCL1_ACTION_EN | 2907 EOP_TC_ACTION_EN | 2908 EOP_TC_WB_ACTION_EN | 2909 EOP_TC_MD_ACTION_EN)) | 2910 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2911 EVENT_INDEX(5))); 2912 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2913 2914 /* 2915 * the address should be Qword aligned if 64bit write, Dword 2916 * aligned if only send 32bit data low (discard data high) 2917 */ 2918 if (write64bit) 2919 BUG_ON(addr & 0x7); 2920 else 2921 BUG_ON(addr & 0x3); 2922 amdgpu_ring_write(ring, lower_32_bits(addr)); 2923 amdgpu_ring_write(ring, upper_32_bits(addr)); 2924 amdgpu_ring_write(ring, lower_32_bits(seq)); 2925 amdgpu_ring_write(ring, upper_32_bits(seq)); 2926 amdgpu_ring_write(ring, 0); 2927 } 2928 2929 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2930 { 2931 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2932 uint32_t seq = ring->fence_drv.sync_seq; 2933 uint64_t addr = ring->fence_drv.gpu_addr; 2934 2935 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2936 lower_32_bits(addr), upper_32_bits(addr), 2937 seq, 0xffffffff, 4); 2938 } 2939 2940 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2941 unsigned vmid, uint64_t pd_addr) 2942 { 2943 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2944 } 2945 2946 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2947 { 2948 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2949 } 2950 2951 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2952 { 2953 u64 wptr; 2954 2955 /* XXX check if swapping is necessary on BE */ 2956 if (ring->use_doorbell) 2957 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2958 else 2959 BUG(); 2960 return wptr; 2961 } 2962 2963 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2964 { 2965 struct amdgpu_device *adev = ring->adev; 2966 2967 /* XXX check if swapping is necessary on BE */ 2968 if (ring->use_doorbell) { 2969 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2970 WDOORBELL64(ring->doorbell_index, ring->wptr); 2971 } else { 2972 BUG(); /* only DOORBELL method supported on gfx9 now */ 2973 } 2974 } 2975 2976 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2977 u64 seq, unsigned int flags) 2978 { 2979 struct amdgpu_device *adev = ring->adev; 2980 2981 /* we only allocate 32bit for each seq wb address */ 2982 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2983 2984 /* write fence seq to the "addr" */ 2985 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2986 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2987 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2988 amdgpu_ring_write(ring, lower_32_bits(addr)); 2989 amdgpu_ring_write(ring, upper_32_bits(addr)); 2990 amdgpu_ring_write(ring, lower_32_bits(seq)); 2991 2992 if (flags & AMDGPU_FENCE_FLAG_INT) { 2993 /* set register to trigger INT */ 2994 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2995 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2996 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2997 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2998 amdgpu_ring_write(ring, 0); 2999 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3000 } 3001 } 3002 3003 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3004 uint32_t reg_val_offs) 3005 { 3006 struct amdgpu_device *adev = ring->adev; 3007 3008 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3009 3010 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3011 amdgpu_ring_write(ring, 0 | /* src: register*/ 3012 (5 << 8) | /* dst: memory */ 3013 (1 << 20)); /* write confirm */ 3014 amdgpu_ring_write(ring, reg); 3015 amdgpu_ring_write(ring, 0); 3016 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3017 reg_val_offs * 4)); 3018 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3019 reg_val_offs * 4)); 3020 } 3021 3022 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3023 uint32_t val) 3024 { 3025 uint32_t cmd = 0; 3026 3027 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3028 3029 switch (ring->funcs->type) { 3030 case AMDGPU_RING_TYPE_GFX: 3031 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3032 break; 3033 case AMDGPU_RING_TYPE_KIQ: 3034 cmd = (1 << 16); /* no inc addr */ 3035 break; 3036 default: 3037 cmd = WR_CONFIRM; 3038 break; 3039 } 3040 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3041 amdgpu_ring_write(ring, cmd); 3042 amdgpu_ring_write(ring, reg); 3043 amdgpu_ring_write(ring, 0); 3044 amdgpu_ring_write(ring, val); 3045 } 3046 3047 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3048 uint32_t val, uint32_t mask) 3049 { 3050 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3051 } 3052 3053 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3054 uint32_t reg0, uint32_t reg1, 3055 uint32_t ref, uint32_t mask) 3056 { 3057 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3058 ref, mask); 3059 } 3060 3061 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3062 unsigned vmid) 3063 { 3064 struct amdgpu_device *adev = ring->adev; 3065 uint32_t value = 0; 3066 3067 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3068 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3069 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3070 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3071 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3072 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3073 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3074 } 3075 3076 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3077 struct amdgpu_device *adev, int me, int pipe, 3078 enum amdgpu_interrupt_state state, int xcc_id) 3079 { 3080 u32 mec_int_cntl, mec_int_cntl_reg; 3081 3082 /* 3083 * amdgpu controls only the first MEC. That's why this function only 3084 * handles the setting of interrupts for this specific MEC. All other 3085 * pipes' interrupts are set by amdkfd. 3086 */ 3087 3088 if (me == 1) { 3089 switch (pipe) { 3090 case 0: 3091 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3092 break; 3093 case 1: 3094 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3095 break; 3096 case 2: 3097 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3098 break; 3099 case 3: 3100 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3101 break; 3102 default: 3103 DRM_DEBUG("invalid pipe %d\n", pipe); 3104 return; 3105 } 3106 } else { 3107 DRM_DEBUG("invalid me %d\n", me); 3108 return; 3109 } 3110 3111 switch (state) { 3112 case AMDGPU_IRQ_STATE_DISABLE: 3113 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3114 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3115 TIME_STAMP_INT_ENABLE, 0); 3116 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3117 break; 3118 case AMDGPU_IRQ_STATE_ENABLE: 3119 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3120 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3121 TIME_STAMP_INT_ENABLE, 1); 3122 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3123 break; 3124 default: 3125 break; 3126 } 3127 } 3128 3129 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3130 int xcc_id, int me, int pipe) 3131 { 3132 /* 3133 * amdgpu controls only the first MEC. That's why this function only 3134 * handles the setting of interrupts for this specific MEC. All other 3135 * pipes' interrupts are set by amdkfd. 3136 */ 3137 if (me != 1) 3138 return 0; 3139 3140 switch (pipe) { 3141 case 0: 3142 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3143 case 1: 3144 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3145 case 2: 3146 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3147 case 3: 3148 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3149 default: 3150 return 0; 3151 } 3152 } 3153 3154 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3155 struct amdgpu_irq_src *source, 3156 unsigned type, 3157 enum amdgpu_interrupt_state state) 3158 { 3159 u32 mec_int_cntl_reg, mec_int_cntl; 3160 int i, j, k, num_xcc; 3161 3162 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3163 switch (state) { 3164 case AMDGPU_IRQ_STATE_DISABLE: 3165 case AMDGPU_IRQ_STATE_ENABLE: 3166 for (i = 0; i < num_xcc; i++) { 3167 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3168 PRIV_REG_INT_ENABLE, 3169 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3170 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3171 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3172 /* MECs start at 1 */ 3173 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3174 3175 if (mec_int_cntl_reg) { 3176 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3177 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3178 PRIV_REG_INT_ENABLE, 3179 state == AMDGPU_IRQ_STATE_ENABLE ? 3180 1 : 0); 3181 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3182 } 3183 } 3184 } 3185 } 3186 break; 3187 default: 3188 break; 3189 } 3190 3191 return 0; 3192 } 3193 3194 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3195 struct amdgpu_irq_src *source, 3196 unsigned type, 3197 enum amdgpu_interrupt_state state) 3198 { 3199 u32 mec_int_cntl_reg, mec_int_cntl; 3200 int i, j, k, num_xcc; 3201 3202 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3203 switch (state) { 3204 case AMDGPU_IRQ_STATE_DISABLE: 3205 case AMDGPU_IRQ_STATE_ENABLE: 3206 for (i = 0; i < num_xcc; i++) { 3207 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3208 OPCODE_ERROR_INT_ENABLE, 3209 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3210 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3211 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3212 /* MECs start at 1 */ 3213 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3214 3215 if (mec_int_cntl_reg) { 3216 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3217 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3218 OPCODE_ERROR_INT_ENABLE, 3219 state == AMDGPU_IRQ_STATE_ENABLE ? 3220 1 : 0); 3221 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3222 } 3223 } 3224 } 3225 } 3226 break; 3227 default: 3228 break; 3229 } 3230 3231 return 0; 3232 } 3233 3234 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3235 struct amdgpu_irq_src *source, 3236 unsigned type, 3237 enum amdgpu_interrupt_state state) 3238 { 3239 int i, num_xcc; 3240 3241 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3242 switch (state) { 3243 case AMDGPU_IRQ_STATE_DISABLE: 3244 case AMDGPU_IRQ_STATE_ENABLE: 3245 for (i = 0; i < num_xcc; i++) 3246 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3247 PRIV_INSTR_INT_ENABLE, 3248 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3249 break; 3250 default: 3251 break; 3252 } 3253 3254 return 0; 3255 } 3256 3257 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3258 struct amdgpu_irq_src *src, 3259 unsigned type, 3260 enum amdgpu_interrupt_state state) 3261 { 3262 int i, num_xcc; 3263 3264 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3265 for (i = 0; i < num_xcc; i++) { 3266 switch (type) { 3267 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3268 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3269 adev, 1, 0, state, i); 3270 break; 3271 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3272 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3273 adev, 1, 1, state, i); 3274 break; 3275 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3276 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3277 adev, 1, 2, state, i); 3278 break; 3279 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3280 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3281 adev, 1, 3, state, i); 3282 break; 3283 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3284 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3285 adev, 2, 0, state, i); 3286 break; 3287 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3288 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3289 adev, 2, 1, state, i); 3290 break; 3291 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3292 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3293 adev, 2, 2, state, i); 3294 break; 3295 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3296 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3297 adev, 2, 3, state, i); 3298 break; 3299 default: 3300 break; 3301 } 3302 } 3303 3304 return 0; 3305 } 3306 3307 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3308 struct amdgpu_irq_src *source, 3309 struct amdgpu_iv_entry *entry) 3310 { 3311 int i, xcc_id; 3312 u8 me_id, pipe_id, queue_id; 3313 struct amdgpu_ring *ring; 3314 3315 DRM_DEBUG("IH: CP EOP\n"); 3316 me_id = (entry->ring_id & 0x0c) >> 2; 3317 pipe_id = (entry->ring_id & 0x03) >> 0; 3318 queue_id = (entry->ring_id & 0x70) >> 4; 3319 3320 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3321 3322 if (xcc_id == -EINVAL) 3323 return -EINVAL; 3324 3325 switch (me_id) { 3326 case 0: 3327 case 1: 3328 case 2: 3329 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3330 ring = &adev->gfx.compute_ring 3331 [i + 3332 xcc_id * adev->gfx.num_compute_rings]; 3333 /* Per-queue interrupt is supported for MEC starting from VI. 3334 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3335 */ 3336 3337 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3338 amdgpu_fence_process(ring); 3339 } 3340 break; 3341 } 3342 return 0; 3343 } 3344 3345 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3346 struct amdgpu_iv_entry *entry) 3347 { 3348 u8 me_id, pipe_id, queue_id; 3349 struct amdgpu_ring *ring; 3350 int i, xcc_id; 3351 3352 me_id = (entry->ring_id & 0x0c) >> 2; 3353 pipe_id = (entry->ring_id & 0x03) >> 0; 3354 queue_id = (entry->ring_id & 0x70) >> 4; 3355 3356 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3357 3358 if (xcc_id == -EINVAL) 3359 return; 3360 3361 switch (me_id) { 3362 case 0: 3363 case 1: 3364 case 2: 3365 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3366 ring = &adev->gfx.compute_ring 3367 [i + 3368 xcc_id * adev->gfx.num_compute_rings]; 3369 if (ring->me == me_id && ring->pipe == pipe_id && 3370 ring->queue == queue_id) 3371 drm_sched_fault(&ring->sched); 3372 } 3373 break; 3374 } 3375 } 3376 3377 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3378 struct amdgpu_irq_src *source, 3379 struct amdgpu_iv_entry *entry) 3380 { 3381 DRM_ERROR("Illegal register access in command stream\n"); 3382 gfx_v9_4_3_fault(adev, entry); 3383 return 0; 3384 } 3385 3386 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3387 struct amdgpu_irq_src *source, 3388 struct amdgpu_iv_entry *entry) 3389 { 3390 DRM_ERROR("Illegal opcode in command stream\n"); 3391 gfx_v9_4_3_fault(adev, entry); 3392 return 0; 3393 } 3394 3395 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3396 struct amdgpu_irq_src *source, 3397 struct amdgpu_iv_entry *entry) 3398 { 3399 DRM_ERROR("Illegal instruction in command stream\n"); 3400 gfx_v9_4_3_fault(adev, entry); 3401 return 0; 3402 } 3403 3404 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3405 { 3406 const unsigned int cp_coher_cntl = 3407 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3408 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3409 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3410 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3411 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3412 3413 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3414 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3415 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3416 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3417 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3418 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3419 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3420 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3421 } 3422 3423 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3424 uint32_t pipe, bool enable) 3425 { 3426 struct amdgpu_device *adev = ring->adev; 3427 uint32_t val; 3428 uint32_t wcl_cs_reg; 3429 3430 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3431 val = enable ? 0x1 : 0x7f; 3432 3433 switch (pipe) { 3434 case 0: 3435 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3436 break; 3437 case 1: 3438 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3439 break; 3440 case 2: 3441 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3442 break; 3443 case 3: 3444 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3445 break; 3446 default: 3447 DRM_DEBUG("invalid pipe %d\n", pipe); 3448 return; 3449 } 3450 3451 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3452 3453 } 3454 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3455 { 3456 struct amdgpu_device *adev = ring->adev; 3457 uint32_t val; 3458 int i; 3459 3460 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3461 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3462 * around 25% of gpu resources. 3463 */ 3464 val = enable ? 0x1f : 0x07ffffff; 3465 amdgpu_ring_emit_wreg(ring, 3466 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3467 val); 3468 3469 /* Restrict waves for normal/low priority compute queues as well 3470 * to get best QoS for high priority compute jobs. 3471 * 3472 * amdgpu controls only 1st ME(0-3 CS pipes). 3473 */ 3474 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3475 if (i != ring->pipe) 3476 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3477 3478 } 3479 } 3480 3481 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3482 uint32_t pipe, uint32_t queue, 3483 uint32_t xcc_id) 3484 { 3485 int i, r; 3486 /* make sure dequeue is complete*/ 3487 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3488 mutex_lock(&adev->srbm_mutex); 3489 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3490 for (i = 0; i < adev->usec_timeout; i++) { 3491 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3492 break; 3493 udelay(1); 3494 } 3495 if (i >= adev->usec_timeout) 3496 r = -ETIMEDOUT; 3497 else 3498 r = 0; 3499 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3500 mutex_unlock(&adev->srbm_mutex); 3501 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3502 3503 return r; 3504 3505 } 3506 3507 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3508 { 3509 /*TODO: Need check gfx9.4.4 mec fw whether supports pipe reset as well.*/ 3510 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 3511 adev->gfx.mec_fw_version >= 0x0000009b) 3512 return true; 3513 else 3514 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3515 3516 return false; 3517 } 3518 3519 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3520 { 3521 struct amdgpu_device *adev = ring->adev; 3522 uint32_t reset_pipe, clean_pipe; 3523 int r; 3524 3525 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3526 return -EINVAL; 3527 3528 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3529 mutex_lock(&adev->srbm_mutex); 3530 3531 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3532 clean_pipe = reset_pipe; 3533 3534 if (ring->me == 1) { 3535 switch (ring->pipe) { 3536 case 0: 3537 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3538 MEC_ME1_PIPE0_RESET, 1); 3539 break; 3540 case 1: 3541 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3542 MEC_ME1_PIPE1_RESET, 1); 3543 break; 3544 case 2: 3545 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3546 MEC_ME1_PIPE2_RESET, 1); 3547 break; 3548 case 3: 3549 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3550 MEC_ME1_PIPE3_RESET, 1); 3551 break; 3552 default: 3553 break; 3554 } 3555 } else { 3556 if (ring->pipe) 3557 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3558 MEC_ME2_PIPE1_RESET, 1); 3559 else 3560 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3561 MEC_ME2_PIPE0_RESET, 1); 3562 } 3563 3564 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3565 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3566 mutex_unlock(&adev->srbm_mutex); 3567 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3568 3569 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3570 return r; 3571 } 3572 3573 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3574 unsigned int vmid) 3575 { 3576 struct amdgpu_device *adev = ring->adev; 3577 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3578 struct amdgpu_ring *kiq_ring = &kiq->ring; 3579 unsigned long flags; 3580 int r; 3581 3582 if (amdgpu_sriov_vf(adev)) 3583 return -EINVAL; 3584 3585 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3586 return -EINVAL; 3587 3588 spin_lock_irqsave(&kiq->ring_lock, flags); 3589 3590 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3591 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3592 return -ENOMEM; 3593 } 3594 3595 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3596 0, 0); 3597 amdgpu_ring_commit(kiq_ring); 3598 3599 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3600 3601 r = amdgpu_ring_test_ring(kiq_ring); 3602 if (r) { 3603 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3604 ring->name); 3605 goto pipe_reset; 3606 } 3607 3608 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3609 if (r) 3610 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3611 3612 pipe_reset: 3613 if(r) { 3614 r = gfx_v9_4_3_reset_hw_pipe(ring); 3615 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3616 r ? "failed" : "successfully"); 3617 if (r) 3618 return r; 3619 } 3620 3621 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3622 if (unlikely(r != 0)){ 3623 dev_err(adev->dev, "fail to resv mqd_obj\n"); 3624 return r; 3625 } 3626 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3627 if (!r) { 3628 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3629 amdgpu_bo_kunmap(ring->mqd_obj); 3630 ring->mqd_ptr = NULL; 3631 } 3632 amdgpu_bo_unreserve(ring->mqd_obj); 3633 if (r) { 3634 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 3635 return r; 3636 } 3637 spin_lock_irqsave(&kiq->ring_lock, flags); 3638 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3639 if (r) { 3640 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3641 return -ENOMEM; 3642 } 3643 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3644 amdgpu_ring_commit(kiq_ring); 3645 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3646 3647 r = amdgpu_ring_test_ring(kiq_ring); 3648 if (r) { 3649 dev_err(adev->dev, "fail to remap queue\n"); 3650 return r; 3651 } 3652 return amdgpu_ring_test_ring(ring); 3653 } 3654 3655 enum amdgpu_gfx_cp_ras_mem_id { 3656 AMDGPU_GFX_CP_MEM1 = 1, 3657 AMDGPU_GFX_CP_MEM2, 3658 AMDGPU_GFX_CP_MEM3, 3659 AMDGPU_GFX_CP_MEM4, 3660 AMDGPU_GFX_CP_MEM5, 3661 }; 3662 3663 enum amdgpu_gfx_gcea_ras_mem_id { 3664 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3665 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3666 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3667 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3668 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3669 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3670 AMDGPU_GFX_GCEA_MAM_DMEM0, 3671 AMDGPU_GFX_GCEA_MAM_DMEM1, 3672 AMDGPU_GFX_GCEA_MAM_DMEM2, 3673 AMDGPU_GFX_GCEA_MAM_DMEM3, 3674 AMDGPU_GFX_GCEA_MAM_AMEM0, 3675 AMDGPU_GFX_GCEA_MAM_AMEM1, 3676 AMDGPU_GFX_GCEA_MAM_AMEM2, 3677 AMDGPU_GFX_GCEA_MAM_AMEM3, 3678 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3679 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3680 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3681 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3682 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3683 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3684 }; 3685 3686 enum amdgpu_gfx_gc_cane_ras_mem_id { 3687 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3688 }; 3689 3690 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3691 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3692 }; 3693 3694 enum amdgpu_gfx_gds_ras_mem_id { 3695 AMDGPU_GFX_GDS_MEM0 = 0, 3696 }; 3697 3698 enum amdgpu_gfx_lds_ras_mem_id { 3699 AMDGPU_GFX_LDS_BANK0 = 0, 3700 AMDGPU_GFX_LDS_BANK1, 3701 AMDGPU_GFX_LDS_BANK2, 3702 AMDGPU_GFX_LDS_BANK3, 3703 AMDGPU_GFX_LDS_BANK4, 3704 AMDGPU_GFX_LDS_BANK5, 3705 AMDGPU_GFX_LDS_BANK6, 3706 AMDGPU_GFX_LDS_BANK7, 3707 AMDGPU_GFX_LDS_BANK8, 3708 AMDGPU_GFX_LDS_BANK9, 3709 AMDGPU_GFX_LDS_BANK10, 3710 AMDGPU_GFX_LDS_BANK11, 3711 AMDGPU_GFX_LDS_BANK12, 3712 AMDGPU_GFX_LDS_BANK13, 3713 AMDGPU_GFX_LDS_BANK14, 3714 AMDGPU_GFX_LDS_BANK15, 3715 AMDGPU_GFX_LDS_BANK16, 3716 AMDGPU_GFX_LDS_BANK17, 3717 AMDGPU_GFX_LDS_BANK18, 3718 AMDGPU_GFX_LDS_BANK19, 3719 AMDGPU_GFX_LDS_BANK20, 3720 AMDGPU_GFX_LDS_BANK21, 3721 AMDGPU_GFX_LDS_BANK22, 3722 AMDGPU_GFX_LDS_BANK23, 3723 AMDGPU_GFX_LDS_BANK24, 3724 AMDGPU_GFX_LDS_BANK25, 3725 AMDGPU_GFX_LDS_BANK26, 3726 AMDGPU_GFX_LDS_BANK27, 3727 AMDGPU_GFX_LDS_BANK28, 3728 AMDGPU_GFX_LDS_BANK29, 3729 AMDGPU_GFX_LDS_BANK30, 3730 AMDGPU_GFX_LDS_BANK31, 3731 AMDGPU_GFX_LDS_SP_BUFFER_A, 3732 AMDGPU_GFX_LDS_SP_BUFFER_B, 3733 }; 3734 3735 enum amdgpu_gfx_rlc_ras_mem_id { 3736 AMDGPU_GFX_RLC_GPMF32 = 1, 3737 AMDGPU_GFX_RLC_RLCVF32, 3738 AMDGPU_GFX_RLC_SCRATCH, 3739 AMDGPU_GFX_RLC_SRM_ARAM, 3740 AMDGPU_GFX_RLC_SRM_DRAM, 3741 AMDGPU_GFX_RLC_TCTAG, 3742 AMDGPU_GFX_RLC_SPM_SE, 3743 AMDGPU_GFX_RLC_SPM_GRBMT, 3744 }; 3745 3746 enum amdgpu_gfx_sp_ras_mem_id { 3747 AMDGPU_GFX_SP_SIMDID0 = 0, 3748 }; 3749 3750 enum amdgpu_gfx_spi_ras_mem_id { 3751 AMDGPU_GFX_SPI_MEM0 = 0, 3752 AMDGPU_GFX_SPI_MEM1, 3753 AMDGPU_GFX_SPI_MEM2, 3754 AMDGPU_GFX_SPI_MEM3, 3755 }; 3756 3757 enum amdgpu_gfx_sqc_ras_mem_id { 3758 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3759 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3760 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3761 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3762 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3763 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3764 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3765 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3766 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3767 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3768 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3769 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3770 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3771 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3772 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3773 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3774 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3775 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3776 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3777 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3778 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3779 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3780 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3781 }; 3782 3783 enum amdgpu_gfx_sq_ras_mem_id { 3784 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3785 AMDGPU_GFX_SQ_SGPR_MEM1, 3786 AMDGPU_GFX_SQ_SGPR_MEM2, 3787 AMDGPU_GFX_SQ_SGPR_MEM3, 3788 }; 3789 3790 enum amdgpu_gfx_ta_ras_mem_id { 3791 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3792 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3793 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3794 AMDGPU_GFX_TA_FSX_LFIFO, 3795 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3796 }; 3797 3798 enum amdgpu_gfx_tcc_ras_mem_id { 3799 AMDGPU_GFX_TCC_MEM1 = 1, 3800 }; 3801 3802 enum amdgpu_gfx_tca_ras_mem_id { 3803 AMDGPU_GFX_TCA_MEM1 = 1, 3804 }; 3805 3806 enum amdgpu_gfx_tci_ras_mem_id { 3807 AMDGPU_GFX_TCIW_MEM = 1, 3808 }; 3809 3810 enum amdgpu_gfx_tcp_ras_mem_id { 3811 AMDGPU_GFX_TCP_LFIFO0 = 1, 3812 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3813 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3814 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3815 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3816 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3817 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3818 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3819 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3820 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3821 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3822 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3823 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3824 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3825 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3826 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3827 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3828 AMDGPU_GFX_TCP_VM_FIFO, 3829 AMDGPU_GFX_TCP_DB_TAGRAM0, 3830 AMDGPU_GFX_TCP_DB_TAGRAM1, 3831 AMDGPU_GFX_TCP_DB_TAGRAM2, 3832 AMDGPU_GFX_TCP_DB_TAGRAM3, 3833 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3834 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3835 AMDGPU_GFX_TCP_CMD_FIFO, 3836 }; 3837 3838 enum amdgpu_gfx_td_ras_mem_id { 3839 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3840 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3841 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3842 }; 3843 3844 enum amdgpu_gfx_tcx_ras_mem_id { 3845 AMDGPU_GFX_TCX_FIFOD0 = 0, 3846 AMDGPU_GFX_TCX_FIFOD1, 3847 AMDGPU_GFX_TCX_FIFOD2, 3848 AMDGPU_GFX_TCX_FIFOD3, 3849 AMDGPU_GFX_TCX_FIFOD4, 3850 AMDGPU_GFX_TCX_FIFOD5, 3851 AMDGPU_GFX_TCX_FIFOD6, 3852 AMDGPU_GFX_TCX_FIFOD7, 3853 AMDGPU_GFX_TCX_FIFOB0, 3854 AMDGPU_GFX_TCX_FIFOB1, 3855 AMDGPU_GFX_TCX_FIFOB2, 3856 AMDGPU_GFX_TCX_FIFOB3, 3857 AMDGPU_GFX_TCX_FIFOB4, 3858 AMDGPU_GFX_TCX_FIFOB5, 3859 AMDGPU_GFX_TCX_FIFOB6, 3860 AMDGPU_GFX_TCX_FIFOB7, 3861 AMDGPU_GFX_TCX_FIFOA0, 3862 AMDGPU_GFX_TCX_FIFOA1, 3863 AMDGPU_GFX_TCX_FIFOA2, 3864 AMDGPU_GFX_TCX_FIFOA3, 3865 AMDGPU_GFX_TCX_FIFOA4, 3866 AMDGPU_GFX_TCX_FIFOA5, 3867 AMDGPU_GFX_TCX_FIFOA6, 3868 AMDGPU_GFX_TCX_FIFOA7, 3869 AMDGPU_GFX_TCX_CFIFO0, 3870 AMDGPU_GFX_TCX_CFIFO1, 3871 AMDGPU_GFX_TCX_CFIFO2, 3872 AMDGPU_GFX_TCX_CFIFO3, 3873 AMDGPU_GFX_TCX_CFIFO4, 3874 AMDGPU_GFX_TCX_CFIFO5, 3875 AMDGPU_GFX_TCX_CFIFO6, 3876 AMDGPU_GFX_TCX_CFIFO7, 3877 AMDGPU_GFX_TCX_FIFO_ACKB0, 3878 AMDGPU_GFX_TCX_FIFO_ACKB1, 3879 AMDGPU_GFX_TCX_FIFO_ACKB2, 3880 AMDGPU_GFX_TCX_FIFO_ACKB3, 3881 AMDGPU_GFX_TCX_FIFO_ACKB4, 3882 AMDGPU_GFX_TCX_FIFO_ACKB5, 3883 AMDGPU_GFX_TCX_FIFO_ACKB6, 3884 AMDGPU_GFX_TCX_FIFO_ACKB7, 3885 AMDGPU_GFX_TCX_FIFO_ACKD0, 3886 AMDGPU_GFX_TCX_FIFO_ACKD1, 3887 AMDGPU_GFX_TCX_FIFO_ACKD2, 3888 AMDGPU_GFX_TCX_FIFO_ACKD3, 3889 AMDGPU_GFX_TCX_FIFO_ACKD4, 3890 AMDGPU_GFX_TCX_FIFO_ACKD5, 3891 AMDGPU_GFX_TCX_FIFO_ACKD6, 3892 AMDGPU_GFX_TCX_FIFO_ACKD7, 3893 AMDGPU_GFX_TCX_DST_FIFOA0, 3894 AMDGPU_GFX_TCX_DST_FIFOA1, 3895 AMDGPU_GFX_TCX_DST_FIFOA2, 3896 AMDGPU_GFX_TCX_DST_FIFOA3, 3897 AMDGPU_GFX_TCX_DST_FIFOA4, 3898 AMDGPU_GFX_TCX_DST_FIFOA5, 3899 AMDGPU_GFX_TCX_DST_FIFOA6, 3900 AMDGPU_GFX_TCX_DST_FIFOA7, 3901 AMDGPU_GFX_TCX_DST_FIFOB0, 3902 AMDGPU_GFX_TCX_DST_FIFOB1, 3903 AMDGPU_GFX_TCX_DST_FIFOB2, 3904 AMDGPU_GFX_TCX_DST_FIFOB3, 3905 AMDGPU_GFX_TCX_DST_FIFOB4, 3906 AMDGPU_GFX_TCX_DST_FIFOB5, 3907 AMDGPU_GFX_TCX_DST_FIFOB6, 3908 AMDGPU_GFX_TCX_DST_FIFOB7, 3909 AMDGPU_GFX_TCX_DST_FIFOD0, 3910 AMDGPU_GFX_TCX_DST_FIFOD1, 3911 AMDGPU_GFX_TCX_DST_FIFOD2, 3912 AMDGPU_GFX_TCX_DST_FIFOD3, 3913 AMDGPU_GFX_TCX_DST_FIFOD4, 3914 AMDGPU_GFX_TCX_DST_FIFOD5, 3915 AMDGPU_GFX_TCX_DST_FIFOD6, 3916 AMDGPU_GFX_TCX_DST_FIFOD7, 3917 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3918 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3919 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3920 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3921 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3922 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3923 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3924 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3925 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3926 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3927 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3928 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3929 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3930 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3931 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3932 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3933 }; 3934 3935 enum amdgpu_gfx_atc_l2_ras_mem_id { 3936 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3937 }; 3938 3939 enum amdgpu_gfx_utcl2_ras_mem_id { 3940 AMDGPU_GFX_UTCL2_MEM0 = 0, 3941 }; 3942 3943 enum amdgpu_gfx_vml2_ras_mem_id { 3944 AMDGPU_GFX_VML2_MEM0 = 0, 3945 }; 3946 3947 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3948 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3949 }; 3950 3951 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3952 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3953 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3954 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3955 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3956 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3957 }; 3958 3959 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3960 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3961 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3962 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3963 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3964 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3965 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3966 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3967 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3968 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3969 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3970 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3971 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3972 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3973 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3974 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3975 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3976 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3977 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3978 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3979 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3980 }; 3981 3982 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3983 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3984 }; 3985 3986 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3987 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3988 }; 3989 3990 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3991 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3992 }; 3993 3994 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3995 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3996 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3997 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3998 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3999 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 4000 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 4001 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 4002 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 4003 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 4004 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 4005 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 4006 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 4007 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 4008 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 4009 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 4010 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 4011 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 4012 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 4013 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 4014 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 4015 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 4016 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 4017 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 4018 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 4019 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 4020 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 4021 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 4022 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 4023 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 4024 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 4025 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 4026 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 4027 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 4028 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4029 }; 4030 4031 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4032 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4033 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4034 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4035 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4036 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4037 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4038 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4039 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4040 }; 4041 4042 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4043 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4044 }; 4045 4046 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4047 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4048 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4049 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4050 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4051 }; 4052 4053 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4054 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4055 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4056 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4057 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4058 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4059 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4060 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4061 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4062 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4063 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4064 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4065 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4066 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4067 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4068 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4069 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4070 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4071 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4072 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4073 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4074 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4075 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4076 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4077 }; 4078 4079 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4080 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4081 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4082 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4083 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4084 }; 4085 4086 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4087 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4088 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4089 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4090 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4091 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4092 }; 4093 4094 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4095 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4096 }; 4097 4098 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4099 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4100 }; 4101 4102 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4103 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4104 }; 4105 4106 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4107 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4108 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4109 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4110 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4111 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4112 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4113 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4114 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4115 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4116 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4117 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4118 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4119 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4120 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4121 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4122 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4123 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4124 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4125 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4126 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4127 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4128 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4129 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4130 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4131 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4132 }; 4133 4134 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4135 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4136 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4137 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4138 }; 4139 4140 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4141 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4142 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4143 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4144 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4145 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4146 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4147 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4148 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4149 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4150 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4151 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4152 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4153 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4154 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4155 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4156 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4157 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4158 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4159 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4160 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4161 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4162 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4163 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4164 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4165 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4166 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4167 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4168 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4169 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4170 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4171 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4172 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4173 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4174 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4175 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4176 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4177 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4178 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4179 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4180 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4181 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4182 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4183 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4184 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4185 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4186 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4187 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4188 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4189 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4190 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4191 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4192 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4193 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4194 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4195 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4196 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4197 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4198 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4199 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4200 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4201 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4202 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4203 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4204 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4205 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4206 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4207 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4208 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4209 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4210 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4211 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4212 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4213 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4214 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4215 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4216 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4217 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4218 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4219 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4220 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4221 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4222 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4223 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4224 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4225 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4226 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4227 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4228 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4229 }; 4230 4231 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4232 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4233 }; 4234 4235 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4236 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4237 }; 4238 4239 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4240 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4241 }; 4242 4243 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4244 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4245 }; 4246 4247 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4248 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4249 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4250 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4251 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4252 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4253 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4254 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4255 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4256 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4257 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4258 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4259 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4260 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4261 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4262 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4263 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4264 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4265 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4266 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4267 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4268 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4269 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4270 }; 4271 4272 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4273 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4274 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4275 AMDGPU_GFX_RLC_MEM, 1}, 4276 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4277 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4278 AMDGPU_GFX_CP_MEM, 1}, 4279 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4280 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4281 AMDGPU_GFX_CP_MEM, 1}, 4282 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4283 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4284 AMDGPU_GFX_CP_MEM, 1}, 4285 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4286 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4287 AMDGPU_GFX_GDS_MEM, 1}, 4288 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4289 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4290 AMDGPU_GFX_GC_CANE_MEM, 1}, 4291 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4292 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4293 AMDGPU_GFX_SPI_MEM, 1}, 4294 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4295 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4296 AMDGPU_GFX_SP_MEM, 4}, 4297 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4298 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4299 AMDGPU_GFX_SP_MEM, 4}, 4300 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4301 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4302 AMDGPU_GFX_SQ_MEM, 4}, 4303 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4304 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4305 AMDGPU_GFX_SQC_MEM, 4}, 4306 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4307 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4308 AMDGPU_GFX_TCX_MEM, 1}, 4309 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4310 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4311 AMDGPU_GFX_TCC_MEM, 1}, 4312 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4313 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4314 AMDGPU_GFX_TA_MEM, 4}, 4315 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4316 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4317 AMDGPU_GFX_TCI_MEM, 1}, 4318 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4319 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4320 AMDGPU_GFX_TCP_MEM, 4}, 4321 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4322 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4323 AMDGPU_GFX_TD_MEM, 4}, 4324 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4325 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4326 AMDGPU_GFX_GCEA_MEM, 1}, 4327 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4328 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4329 AMDGPU_GFX_LDS_MEM, 4}, 4330 }; 4331 4332 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4333 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4334 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4335 AMDGPU_GFX_RLC_MEM, 1}, 4336 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4337 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4338 AMDGPU_GFX_CP_MEM, 1}, 4339 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4340 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4341 AMDGPU_GFX_CP_MEM, 1}, 4342 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4343 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4344 AMDGPU_GFX_CP_MEM, 1}, 4345 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4346 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4347 AMDGPU_GFX_GDS_MEM, 1}, 4348 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4349 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4350 AMDGPU_GFX_GC_CANE_MEM, 1}, 4351 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4352 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4353 AMDGPU_GFX_SPI_MEM, 1}, 4354 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4355 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4356 AMDGPU_GFX_SP_MEM, 4}, 4357 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4358 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4359 AMDGPU_GFX_SP_MEM, 4}, 4360 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4361 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4362 AMDGPU_GFX_SQ_MEM, 4}, 4363 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4364 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4365 AMDGPU_GFX_SQC_MEM, 4}, 4366 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4367 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4368 AMDGPU_GFX_TCX_MEM, 1}, 4369 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4370 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4371 AMDGPU_GFX_TCC_MEM, 1}, 4372 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4373 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4374 AMDGPU_GFX_TA_MEM, 4}, 4375 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4376 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4377 AMDGPU_GFX_TCI_MEM, 1}, 4378 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4379 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4380 AMDGPU_GFX_TCP_MEM, 4}, 4381 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4382 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4383 AMDGPU_GFX_TD_MEM, 4}, 4384 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4385 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4386 AMDGPU_GFX_TCA_MEM, 1}, 4387 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4388 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4389 AMDGPU_GFX_GCEA_MEM, 1}, 4390 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4391 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4392 AMDGPU_GFX_LDS_MEM, 4}, 4393 }; 4394 4395 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4396 void *ras_error_status, int xcc_id) 4397 { 4398 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4399 unsigned long ce_count = 0, ue_count = 0; 4400 uint32_t i, j, k; 4401 4402 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4403 struct amdgpu_smuio_mcm_config_info mcm_info = { 4404 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4405 .die_id = xcc_id & 0x01 ? 1 : 0, 4406 }; 4407 4408 mutex_lock(&adev->grbm_idx_mutex); 4409 4410 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4411 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4412 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4413 /* no need to select if instance number is 1 */ 4414 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4415 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4416 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4417 4418 amdgpu_ras_inst_query_ras_error_count(adev, 4419 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4420 1, 4421 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4422 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4423 GET_INST(GC, xcc_id), 4424 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4425 &ce_count); 4426 4427 amdgpu_ras_inst_query_ras_error_count(adev, 4428 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4429 1, 4430 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4431 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4432 GET_INST(GC, xcc_id), 4433 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4434 &ue_count); 4435 } 4436 } 4437 } 4438 4439 /* handle extra register entries of UE */ 4440 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4441 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4442 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4443 /* no need to select if instance number is 1 */ 4444 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4445 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4446 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4447 4448 amdgpu_ras_inst_query_ras_error_count(adev, 4449 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4450 1, 4451 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4452 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4453 GET_INST(GC, xcc_id), 4454 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4455 &ue_count); 4456 } 4457 } 4458 } 4459 4460 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4461 xcc_id); 4462 mutex_unlock(&adev->grbm_idx_mutex); 4463 4464 /* the caller should make sure initialize value of 4465 * err_data->ue_count and err_data->ce_count 4466 */ 4467 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4468 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4469 } 4470 4471 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4472 void *ras_error_status, int xcc_id) 4473 { 4474 uint32_t i, j, k; 4475 4476 mutex_lock(&adev->grbm_idx_mutex); 4477 4478 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4479 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4480 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4481 /* no need to select if instance number is 1 */ 4482 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4483 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4484 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4485 4486 amdgpu_ras_inst_reset_ras_error_count(adev, 4487 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4488 1, 4489 GET_INST(GC, xcc_id)); 4490 4491 amdgpu_ras_inst_reset_ras_error_count(adev, 4492 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4493 1, 4494 GET_INST(GC, xcc_id)); 4495 } 4496 } 4497 } 4498 4499 /* handle extra register entries of UE */ 4500 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4501 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4502 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4503 /* no need to select if instance number is 1 */ 4504 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4505 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4506 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4507 4508 amdgpu_ras_inst_reset_ras_error_count(adev, 4509 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4510 1, 4511 GET_INST(GC, xcc_id)); 4512 } 4513 } 4514 } 4515 4516 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4517 xcc_id); 4518 mutex_unlock(&adev->grbm_idx_mutex); 4519 } 4520 4521 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4522 void *ras_error_status, int xcc_id) 4523 { 4524 uint32_t i; 4525 uint32_t data; 4526 4527 if (amdgpu_sriov_vf(adev)) 4528 return; 4529 4530 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4531 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4532 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4533 4534 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4535 (amdgpu_watchdog_timer.period < 1 || 4536 amdgpu_watchdog_timer.period > 0x23)) { 4537 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4538 amdgpu_watchdog_timer.period = 0x23; 4539 } 4540 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4541 amdgpu_watchdog_timer.period); 4542 4543 mutex_lock(&adev->grbm_idx_mutex); 4544 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4545 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4546 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4547 } 4548 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4549 xcc_id); 4550 mutex_unlock(&adev->grbm_idx_mutex); 4551 } 4552 4553 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4554 void *ras_error_status) 4555 { 4556 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4557 gfx_v9_4_3_inst_query_ras_err_count); 4558 } 4559 4560 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4561 { 4562 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4563 } 4564 4565 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4566 { 4567 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4568 } 4569 4570 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4571 { 4572 /* Header itself is a NOP packet */ 4573 if (num_nop == 1) { 4574 amdgpu_ring_write(ring, ring->funcs->nop); 4575 return; 4576 } 4577 4578 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4579 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4580 4581 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4582 amdgpu_ring_insert_nop(ring, num_nop - 1); 4583 } 4584 4585 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4586 { 4587 struct amdgpu_device *adev = ip_block->adev; 4588 uint32_t i, j, k; 4589 uint32_t xcc_id, xcc_offset, inst_offset; 4590 uint32_t num_xcc, reg, num_inst; 4591 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4592 4593 if (!adev->gfx.ip_dump_core) 4594 return; 4595 4596 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4597 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4598 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4599 xcc_offset = xcc_id * reg_count; 4600 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4601 for (i = 0; i < reg_count; i++) 4602 drm_printf(p, "%-50s \t 0x%08x\n", 4603 gc_reg_list_9_4_3[i].reg_name, 4604 adev->gfx.ip_dump_core[xcc_offset + i]); 4605 } 4606 4607 /* print compute queue registers for all instances */ 4608 if (!adev->gfx.ip_dump_compute_queues) 4609 return; 4610 4611 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4612 adev->gfx.mec.num_queue_per_pipe; 4613 4614 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4615 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4616 num_xcc, 4617 adev->gfx.mec.num_mec, 4618 adev->gfx.mec.num_pipe_per_mec, 4619 adev->gfx.mec.num_queue_per_pipe); 4620 4621 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4622 xcc_offset = xcc_id * reg_count * num_inst; 4623 inst_offset = 0; 4624 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4625 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4626 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4627 drm_printf(p, 4628 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4629 xcc_id, i, j, k); 4630 for (reg = 0; reg < reg_count; reg++) { 4631 drm_printf(p, 4632 "%-50s \t 0x%08x\n", 4633 gc_cp_reg_list_9_4_3[reg].reg_name, 4634 adev->gfx.ip_dump_compute_queues 4635 [xcc_offset + inst_offset + 4636 reg]); 4637 } 4638 inst_offset += reg_count; 4639 } 4640 } 4641 } 4642 } 4643 } 4644 4645 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4646 { 4647 struct amdgpu_device *adev = ip_block->adev; 4648 uint32_t i, j, k; 4649 uint32_t num_xcc, reg, num_inst; 4650 uint32_t xcc_id, xcc_offset, inst_offset; 4651 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4652 4653 if (!adev->gfx.ip_dump_core) 4654 return; 4655 4656 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4657 4658 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4659 xcc_offset = xcc_id * reg_count; 4660 for (i = 0; i < reg_count; i++) 4661 adev->gfx.ip_dump_core[xcc_offset + i] = 4662 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4663 GET_INST(GC, xcc_id))); 4664 } 4665 4666 /* dump compute queue registers for all instances */ 4667 if (!adev->gfx.ip_dump_compute_queues) 4668 return; 4669 4670 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4671 adev->gfx.mec.num_queue_per_pipe; 4672 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4673 mutex_lock(&adev->srbm_mutex); 4674 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4675 xcc_offset = xcc_id * reg_count * num_inst; 4676 inst_offset = 0; 4677 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4678 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4679 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4680 /* ME0 is for GFX so start from 1 for CP */ 4681 soc15_grbm_select(adev, 1 + i, j, k, 0, 4682 GET_INST(GC, xcc_id)); 4683 4684 for (reg = 0; reg < reg_count; reg++) { 4685 adev->gfx.ip_dump_compute_queues 4686 [xcc_offset + 4687 inst_offset + reg] = 4688 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4689 gc_cp_reg_list_9_4_3[reg], 4690 GET_INST(GC, xcc_id))); 4691 } 4692 inst_offset += reg_count; 4693 } 4694 } 4695 } 4696 } 4697 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4698 mutex_unlock(&adev->srbm_mutex); 4699 } 4700 4701 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4702 { 4703 /* Emit the cleaner shader */ 4704 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4705 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4706 } 4707 4708 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4709 .name = "gfx_v9_4_3", 4710 .early_init = gfx_v9_4_3_early_init, 4711 .late_init = gfx_v9_4_3_late_init, 4712 .sw_init = gfx_v9_4_3_sw_init, 4713 .sw_fini = gfx_v9_4_3_sw_fini, 4714 .hw_init = gfx_v9_4_3_hw_init, 4715 .hw_fini = gfx_v9_4_3_hw_fini, 4716 .suspend = gfx_v9_4_3_suspend, 4717 .resume = gfx_v9_4_3_resume, 4718 .is_idle = gfx_v9_4_3_is_idle, 4719 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4720 .soft_reset = gfx_v9_4_3_soft_reset, 4721 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4722 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4723 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4724 .dump_ip_state = gfx_v9_4_3_ip_dump, 4725 .print_ip_state = gfx_v9_4_3_ip_print, 4726 }; 4727 4728 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4729 .type = AMDGPU_RING_TYPE_COMPUTE, 4730 .align_mask = 0xff, 4731 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4732 .support_64bit_ptrs = true, 4733 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4734 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4735 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4736 .emit_frame_size = 4737 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4738 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4739 5 + /* hdp invalidate */ 4740 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4741 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4742 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4743 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4744 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4745 7 + /* gfx_v9_4_3_emit_mem_sync */ 4746 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4747 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4748 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4749 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4750 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4751 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4752 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4753 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4754 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4755 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4756 .test_ring = gfx_v9_4_3_ring_test_ring, 4757 .test_ib = gfx_v9_4_3_ring_test_ib, 4758 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4759 .pad_ib = amdgpu_ring_generic_pad_ib, 4760 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4761 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4762 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4763 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4764 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4765 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4766 .reset = gfx_v9_4_3_reset_kcq, 4767 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4768 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4769 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4770 }; 4771 4772 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4773 .type = AMDGPU_RING_TYPE_KIQ, 4774 .align_mask = 0xff, 4775 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4776 .support_64bit_ptrs = true, 4777 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4778 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4779 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4780 .emit_frame_size = 4781 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4782 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4783 5 + /* hdp invalidate */ 4784 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4785 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4786 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4787 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4788 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4789 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4790 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4791 .test_ring = gfx_v9_4_3_ring_test_ring, 4792 .insert_nop = amdgpu_ring_insert_nop, 4793 .pad_ib = amdgpu_ring_generic_pad_ib, 4794 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4795 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4796 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4797 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4798 }; 4799 4800 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4801 { 4802 int i, j, num_xcc; 4803 4804 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4805 for (i = 0; i < num_xcc; i++) { 4806 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4807 4808 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4809 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4810 = &gfx_v9_4_3_ring_funcs_compute; 4811 } 4812 } 4813 4814 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4815 .set = gfx_v9_4_3_set_eop_interrupt_state, 4816 .process = gfx_v9_4_3_eop_irq, 4817 }; 4818 4819 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4820 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4821 .process = gfx_v9_4_3_priv_reg_irq, 4822 }; 4823 4824 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4825 .set = gfx_v9_4_3_set_bad_op_fault_state, 4826 .process = gfx_v9_4_3_bad_op_irq, 4827 }; 4828 4829 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4830 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4831 .process = gfx_v9_4_3_priv_inst_irq, 4832 }; 4833 4834 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4835 { 4836 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4837 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4838 4839 adev->gfx.priv_reg_irq.num_types = 1; 4840 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4841 4842 adev->gfx.bad_op_irq.num_types = 1; 4843 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4844 4845 adev->gfx.priv_inst_irq.num_types = 1; 4846 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4847 } 4848 4849 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4850 { 4851 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4852 } 4853 4854 4855 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4856 { 4857 /* 9.4.3 variants removed all the GDS internal memory, 4858 * only support GWS opcode in kernel, like barrier 4859 * semaphore.etc */ 4860 4861 /* init asic gds info */ 4862 adev->gds.gds_size = 0; 4863 adev->gds.gds_compute_max_wave_id = 0; 4864 adev->gds.gws_size = 64; 4865 adev->gds.oa_size = 16; 4866 } 4867 4868 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4869 u32 bitmap, int xcc_id) 4870 { 4871 u32 data; 4872 4873 if (!bitmap) 4874 return; 4875 4876 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4877 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4878 4879 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4880 } 4881 4882 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4883 { 4884 u32 data, mask; 4885 4886 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4887 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4888 4889 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4890 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4891 4892 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4893 4894 return (~data) & mask; 4895 } 4896 4897 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4898 struct amdgpu_cu_info *cu_info) 4899 { 4900 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4901 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4902 unsigned disable_masks[4 * 4]; 4903 bool is_symmetric_cus; 4904 4905 if (!adev || !cu_info) 4906 return -EINVAL; 4907 4908 /* 4909 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4910 */ 4911 if (adev->gfx.config.max_shader_engines * 4912 adev->gfx.config.max_sh_per_se > 16) 4913 return -EINVAL; 4914 4915 amdgpu_gfx_parse_disable_cu(disable_masks, 4916 adev->gfx.config.max_shader_engines, 4917 adev->gfx.config.max_sh_per_se); 4918 4919 mutex_lock(&adev->grbm_idx_mutex); 4920 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4921 is_symmetric_cus = true; 4922 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4923 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4924 mask = 1; 4925 ao_bitmap = 0; 4926 counter = 0; 4927 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4928 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4929 adev, 4930 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4931 xcc_id); 4932 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4933 4934 cu_info->bitmap[xcc_id][i][j] = bitmap; 4935 4936 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4937 if (bitmap & mask) { 4938 if (counter < adev->gfx.config.max_cu_per_sh) 4939 ao_bitmap |= mask; 4940 counter++; 4941 } 4942 mask <<= 1; 4943 } 4944 active_cu_number += counter; 4945 if (i < 2 && j < 2) 4946 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4947 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4948 } 4949 if (i && is_symmetric_cus && prev_counter != counter) 4950 is_symmetric_cus = false; 4951 prev_counter = counter; 4952 } 4953 if (is_symmetric_cus) { 4954 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4955 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4956 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4957 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4958 } 4959 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4960 xcc_id); 4961 } 4962 mutex_unlock(&adev->grbm_idx_mutex); 4963 4964 cu_info->number = active_cu_number; 4965 cu_info->ao_cu_mask = ao_cu_mask; 4966 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4967 4968 return 0; 4969 } 4970 4971 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4972 .type = AMD_IP_BLOCK_TYPE_GFX, 4973 .major = 9, 4974 .minor = 4, 4975 .rev = 3, 4976 .funcs = &gfx_v9_4_3_ip_funcs, 4977 }; 4978 4979 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4980 { 4981 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4982 uint32_t tmp_mask; 4983 int i, r; 4984 4985 /* TODO : Initialize golden regs */ 4986 /* gfx_v9_4_3_init_golden_registers(adev); */ 4987 4988 tmp_mask = inst_mask; 4989 for_each_inst(i, tmp_mask) 4990 gfx_v9_4_3_xcc_constants_init(adev, i); 4991 4992 if (!amdgpu_sriov_vf(adev)) { 4993 tmp_mask = inst_mask; 4994 for_each_inst(i, tmp_mask) { 4995 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4996 if (r) 4997 return r; 4998 } 4999 } 5000 5001 tmp_mask = inst_mask; 5002 for_each_inst(i, tmp_mask) { 5003 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 5004 if (r) 5005 return r; 5006 } 5007 5008 return 0; 5009 } 5010 5011 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 5012 { 5013 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5014 int i; 5015 5016 for_each_inst(i, inst_mask) 5017 gfx_v9_4_3_xcc_fini(adev, i); 5018 5019 return 0; 5020 } 5021 5022 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5023 .suspend = &gfx_v9_4_3_xcp_suspend, 5024 .resume = &gfx_v9_4_3_xcp_resume 5025 }; 5026 5027 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5028 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5029 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5030 }; 5031 5032 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5033 { 5034 int r; 5035 5036 r = amdgpu_ras_block_late_init(adev, ras_block); 5037 if (r) 5038 return r; 5039 5040 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5041 &gfx_v9_4_3_aca_info, 5042 NULL); 5043 if (r) 5044 goto late_fini; 5045 5046 return 0; 5047 5048 late_fini: 5049 amdgpu_ras_block_late_fini(adev, ras_block); 5050 5051 return r; 5052 } 5053 5054 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5055 .ras_block = { 5056 .hw_ops = &gfx_v9_4_3_ras_ops, 5057 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5058 }, 5059 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5060 }; 5061