1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 #include "amdgpu_aca.h" 42 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 47 48 #define GFX9_MEC_HPD_SIZE 4096 49 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 50 51 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 52 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 53 54 #define mmSMNAID_XCD0_MCA_SMU 0x36430400 /* SMN AID XCD0 */ 55 #define mmSMNAID_XCD1_MCA_SMU 0x38430400 /* SMN AID XCD1 */ 56 #define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */ 57 58 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 59 60 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 61 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 62 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 63 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 64 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 65 struct amdgpu_cu_info *cu_info); 66 67 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 68 uint64_t queue_mask) 69 { 70 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 71 amdgpu_ring_write(kiq_ring, 72 PACKET3_SET_RESOURCES_VMID_MASK(0) | 73 /* vmid_mask:0* queue_type:0 (KIQ) */ 74 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 75 amdgpu_ring_write(kiq_ring, 76 lower_32_bits(queue_mask)); /* queue mask lo */ 77 amdgpu_ring_write(kiq_ring, 78 upper_32_bits(queue_mask)); /* queue mask hi */ 79 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 80 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 81 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 82 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 83 } 84 85 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 86 struct amdgpu_ring *ring) 87 { 88 struct amdgpu_device *adev = kiq_ring->adev; 89 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 90 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 91 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 92 93 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 94 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 95 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 96 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 97 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 98 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 99 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 100 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 101 /*queue_type: normal compute queue */ 102 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 103 /* alloc format: all_on_one_pipe */ 104 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 105 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 106 /* num_queues: must be 1 */ 107 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 108 amdgpu_ring_write(kiq_ring, 109 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 110 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 111 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 112 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 113 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 114 } 115 116 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 117 struct amdgpu_ring *ring, 118 enum amdgpu_unmap_queues_action action, 119 u64 gpu_addr, u64 seq) 120 { 121 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 122 123 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 124 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 125 PACKET3_UNMAP_QUEUES_ACTION(action) | 126 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 127 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 128 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 129 amdgpu_ring_write(kiq_ring, 130 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 131 132 if (action == PREEMPT_QUEUES_NO_UNMAP) { 133 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 134 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 135 amdgpu_ring_write(kiq_ring, seq); 136 } else { 137 amdgpu_ring_write(kiq_ring, 0); 138 amdgpu_ring_write(kiq_ring, 0); 139 amdgpu_ring_write(kiq_ring, 0); 140 } 141 } 142 143 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 144 struct amdgpu_ring *ring, 145 u64 addr, 146 u64 seq) 147 { 148 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 149 150 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 151 amdgpu_ring_write(kiq_ring, 152 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 153 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 154 PACKET3_QUERY_STATUS_COMMAND(2)); 155 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 156 amdgpu_ring_write(kiq_ring, 157 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 158 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 159 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 160 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 161 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 162 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 163 } 164 165 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 166 uint16_t pasid, uint32_t flush_type, 167 bool all_hub) 168 { 169 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 170 amdgpu_ring_write(kiq_ring, 171 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 172 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 173 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 174 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 175 } 176 177 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 178 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 179 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 180 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 181 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 182 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 183 .set_resources_size = 8, 184 .map_queues_size = 7, 185 .unmap_queues_size = 6, 186 .query_status_size = 7, 187 .invalidate_tlbs_size = 2, 188 }; 189 190 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 191 { 192 int i, num_xcc; 193 194 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 195 for (i = 0; i < num_xcc; i++) 196 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 197 } 198 199 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 200 { 201 int i, num_xcc, dev_inst; 202 203 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 204 for (i = 0; i < num_xcc; i++) { 205 dev_inst = GET_INST(GC, i); 206 207 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 208 GOLDEN_GB_ADDR_CONFIG); 209 /* Golden settings applied by driver for ASIC with rev_id 0 */ 210 if (adev->rev_id == 0) { 211 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 212 REDUCE_FIFO_DEPTH_BY_2, 2); 213 } else { 214 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 215 SPARE, 0x1); 216 } 217 } 218 } 219 220 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 221 bool wc, uint32_t reg, uint32_t val) 222 { 223 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 224 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 225 WRITE_DATA_DST_SEL(0) | 226 (wc ? WR_CONFIRM : 0)); 227 amdgpu_ring_write(ring, reg); 228 amdgpu_ring_write(ring, 0); 229 amdgpu_ring_write(ring, val); 230 } 231 232 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 233 int mem_space, int opt, uint32_t addr0, 234 uint32_t addr1, uint32_t ref, uint32_t mask, 235 uint32_t inv) 236 { 237 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 238 amdgpu_ring_write(ring, 239 /* memory (1) or register (0) */ 240 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 241 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 242 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 243 WAIT_REG_MEM_ENGINE(eng_sel))); 244 245 if (mem_space) 246 BUG_ON(addr0 & 0x3); /* Dword align */ 247 amdgpu_ring_write(ring, addr0); 248 amdgpu_ring_write(ring, addr1); 249 amdgpu_ring_write(ring, ref); 250 amdgpu_ring_write(ring, mask); 251 amdgpu_ring_write(ring, inv); /* poll interval */ 252 } 253 254 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 255 { 256 uint32_t scratch_reg0_offset, xcc_offset; 257 struct amdgpu_device *adev = ring->adev; 258 uint32_t tmp = 0; 259 unsigned i; 260 int r; 261 262 /* Use register offset which is local to XCC in the packet */ 263 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 264 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 265 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 266 tmp = RREG32(scratch_reg0_offset); 267 268 r = amdgpu_ring_alloc(ring, 3); 269 if (r) 270 return r; 271 272 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 273 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 274 amdgpu_ring_write(ring, 0xDEADBEEF); 275 amdgpu_ring_commit(ring); 276 277 for (i = 0; i < adev->usec_timeout; i++) { 278 tmp = RREG32(scratch_reg0_offset); 279 if (tmp == 0xDEADBEEF) 280 break; 281 udelay(1); 282 } 283 284 if (i >= adev->usec_timeout) 285 r = -ETIMEDOUT; 286 return r; 287 } 288 289 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 290 { 291 struct amdgpu_device *adev = ring->adev; 292 struct amdgpu_ib ib; 293 struct dma_fence *f = NULL; 294 295 unsigned index; 296 uint64_t gpu_addr; 297 uint32_t tmp; 298 long r; 299 300 r = amdgpu_device_wb_get(adev, &index); 301 if (r) 302 return r; 303 304 gpu_addr = adev->wb.gpu_addr + (index * 4); 305 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 306 memset(&ib, 0, sizeof(ib)); 307 308 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 309 if (r) 310 goto err1; 311 312 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 313 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 314 ib.ptr[2] = lower_32_bits(gpu_addr); 315 ib.ptr[3] = upper_32_bits(gpu_addr); 316 ib.ptr[4] = 0xDEADBEEF; 317 ib.length_dw = 5; 318 319 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 320 if (r) 321 goto err2; 322 323 r = dma_fence_wait_timeout(f, false, timeout); 324 if (r == 0) { 325 r = -ETIMEDOUT; 326 goto err2; 327 } else if (r < 0) { 328 goto err2; 329 } 330 331 tmp = adev->wb.wb[index]; 332 if (tmp == 0xDEADBEEF) 333 r = 0; 334 else 335 r = -EINVAL; 336 337 err2: 338 amdgpu_ib_free(adev, &ib, NULL); 339 dma_fence_put(f); 340 err1: 341 amdgpu_device_wb_free(adev, index); 342 return r; 343 } 344 345 346 /* This value might differs per partition */ 347 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 348 { 349 uint64_t clock; 350 351 mutex_lock(&adev->gfx.gpu_clock_mutex); 352 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 353 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 354 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 355 mutex_unlock(&adev->gfx.gpu_clock_mutex); 356 357 return clock; 358 } 359 360 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 361 { 362 amdgpu_ucode_release(&adev->gfx.pfp_fw); 363 amdgpu_ucode_release(&adev->gfx.me_fw); 364 amdgpu_ucode_release(&adev->gfx.ce_fw); 365 amdgpu_ucode_release(&adev->gfx.rlc_fw); 366 amdgpu_ucode_release(&adev->gfx.mec_fw); 367 amdgpu_ucode_release(&adev->gfx.mec2_fw); 368 369 kfree(adev->gfx.rlc.register_list_format); 370 } 371 372 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 373 const char *chip_name) 374 { 375 char fw_name[30]; 376 int err; 377 const struct rlc_firmware_header_v2_0 *rlc_hdr; 378 uint16_t version_major; 379 uint16_t version_minor; 380 381 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 382 383 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 384 if (err) 385 goto out; 386 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 387 388 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 389 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 390 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 391 out: 392 if (err) 393 amdgpu_ucode_release(&adev->gfx.rlc_fw); 394 395 return err; 396 } 397 398 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 399 { 400 return true; 401 } 402 403 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 404 { 405 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 406 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 407 } 408 409 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 410 const char *chip_name) 411 { 412 char fw_name[30]; 413 int err; 414 415 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 416 417 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 418 if (err) 419 goto out; 420 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 421 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 422 423 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 424 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 425 426 gfx_v9_4_3_check_if_need_gfxoff(adev); 427 428 out: 429 if (err) 430 amdgpu_ucode_release(&adev->gfx.mec_fw); 431 return err; 432 } 433 434 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 435 { 436 char ucode_prefix[15]; 437 int r; 438 439 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 440 441 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 442 if (r) 443 return r; 444 445 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 446 if (r) 447 return r; 448 449 return r; 450 } 451 452 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 453 { 454 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 455 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 456 } 457 458 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 459 { 460 int r, i, num_xcc; 461 u32 *hpd; 462 const __le32 *fw_data; 463 unsigned fw_size; 464 u32 *fw; 465 size_t mec_hpd_size; 466 467 const struct gfx_firmware_header_v1_0 *mec_hdr; 468 469 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 470 for (i = 0; i < num_xcc; i++) 471 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 472 AMDGPU_MAX_COMPUTE_QUEUES); 473 474 /* take ownership of the relevant compute queues */ 475 amdgpu_gfx_compute_queue_acquire(adev); 476 mec_hpd_size = 477 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 478 if (mec_hpd_size) { 479 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 480 AMDGPU_GEM_DOMAIN_VRAM | 481 AMDGPU_GEM_DOMAIN_GTT, 482 &adev->gfx.mec.hpd_eop_obj, 483 &adev->gfx.mec.hpd_eop_gpu_addr, 484 (void **)&hpd); 485 if (r) { 486 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 487 gfx_v9_4_3_mec_fini(adev); 488 return r; 489 } 490 491 if (amdgpu_emu_mode == 1) { 492 for (i = 0; i < mec_hpd_size / 4; i++) { 493 memset((void *)(hpd + i), 0, 4); 494 if (i % 50 == 0) 495 msleep(1); 496 } 497 } else { 498 memset(hpd, 0, mec_hpd_size); 499 } 500 501 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 502 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 503 } 504 505 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 506 507 fw_data = (const __le32 *) 508 (adev->gfx.mec_fw->data + 509 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 510 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 511 512 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 513 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 514 &adev->gfx.mec.mec_fw_obj, 515 &adev->gfx.mec.mec_fw_gpu_addr, 516 (void **)&fw); 517 if (r) { 518 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 519 gfx_v9_4_3_mec_fini(adev); 520 return r; 521 } 522 523 memcpy(fw, fw_data, fw_size); 524 525 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 526 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 527 528 return 0; 529 } 530 531 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 532 u32 sh_num, u32 instance, int xcc_id) 533 { 534 u32 data; 535 536 if (instance == 0xffffffff) 537 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 538 INSTANCE_BROADCAST_WRITES, 1); 539 else 540 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 541 INSTANCE_INDEX, instance); 542 543 if (se_num == 0xffffffff) 544 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 545 SE_BROADCAST_WRITES, 1); 546 else 547 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 548 549 if (sh_num == 0xffffffff) 550 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 551 SH_BROADCAST_WRITES, 1); 552 else 553 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 554 555 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 556 } 557 558 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 559 { 560 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 561 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 562 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 563 (address << SQ_IND_INDEX__INDEX__SHIFT) | 564 (SQ_IND_INDEX__FORCE_READ_MASK)); 565 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 566 } 567 568 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 569 uint32_t wave, uint32_t thread, 570 uint32_t regno, uint32_t num, uint32_t *out) 571 { 572 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 573 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 574 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 575 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 576 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 577 (SQ_IND_INDEX__FORCE_READ_MASK) | 578 (SQ_IND_INDEX__AUTO_INCR_MASK)); 579 while (num--) 580 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 581 } 582 583 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 584 uint32_t xcc_id, uint32_t simd, uint32_t wave, 585 uint32_t *dst, int *no_fields) 586 { 587 /* type 1 wave data */ 588 dst[(*no_fields)++] = 1; 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 594 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 595 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 596 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 597 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 598 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 599 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 600 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 601 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 602 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 603 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 604 } 605 606 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 607 uint32_t wave, uint32_t start, 608 uint32_t size, uint32_t *dst) 609 { 610 wave_read_regs(adev, xcc_id, simd, wave, 0, 611 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 612 } 613 614 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 615 uint32_t wave, uint32_t thread, 616 uint32_t start, uint32_t size, 617 uint32_t *dst) 618 { 619 wave_read_regs(adev, xcc_id, simd, wave, thread, 620 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 621 } 622 623 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 624 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 625 { 626 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 627 } 628 629 630 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 631 int num_xccs_per_xcp) 632 { 633 int ret, i, num_xcc; 634 u32 tmp = 0; 635 636 if (adev->psp.funcs) { 637 ret = psp_spatial_partition(&adev->psp, 638 NUM_XCC(adev->gfx.xcc_mask) / 639 num_xccs_per_xcp); 640 if (ret) 641 return ret; 642 } else { 643 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 644 645 for (i = 0; i < num_xcc; i++) { 646 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 647 num_xccs_per_xcp); 648 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 649 i % num_xccs_per_xcp); 650 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 651 tmp); 652 } 653 ret = 0; 654 } 655 656 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 657 658 return ret; 659 } 660 661 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 662 { 663 int xcc; 664 665 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 666 if (!xcc) { 667 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 668 return -EINVAL; 669 } 670 671 return xcc - 1; 672 } 673 674 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 675 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 676 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 677 .read_wave_data = &gfx_v9_4_3_read_wave_data, 678 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 679 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 680 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 681 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 682 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 683 }; 684 685 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 686 struct aca_bank *bank, enum aca_smu_type type, 687 void *data) 688 { 689 struct aca_bank_info info; 690 u64 misc0; 691 u32 instlo; 692 int ret; 693 694 ret = aca_bank_info_decode(bank, &info); 695 if (ret) 696 return ret; 697 698 /* NOTE: overwrite info.die_id with xcd id for gfx */ 699 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 700 instlo &= GENMASK(31, 1); 701 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 702 703 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 704 705 switch (type) { 706 case ACA_SMU_TYPE_UE: 707 ret = aca_error_cache_log_bank_error(handle, &info, 708 ACA_ERROR_TYPE_UE, 1ULL); 709 break; 710 case ACA_SMU_TYPE_CE: 711 ret = aca_error_cache_log_bank_error(handle, &info, 712 ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0)); 713 break; 714 default: 715 return -EINVAL; 716 } 717 718 return ret; 719 } 720 721 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 722 enum aca_smu_type type, void *data) 723 { 724 u32 instlo; 725 726 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 727 instlo &= GENMASK(31, 1); 728 switch (instlo) { 729 case mmSMNAID_XCD0_MCA_SMU: 730 case mmSMNAID_XCD1_MCA_SMU: 731 case mmSMNXCD_XCD0_MCA_SMU: 732 return true; 733 default: 734 break; 735 } 736 737 return false; 738 } 739 740 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 741 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 742 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 743 }; 744 745 static const struct aca_info gfx_v9_4_3_aca_info = { 746 .hwip = ACA_HWIP_TYPE_SMU, 747 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 748 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 749 }; 750 751 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 752 { 753 u32 gb_addr_config; 754 755 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 756 adev->gfx.ras = &gfx_v9_4_3_ras; 757 758 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 759 case IP_VERSION(9, 4, 3): 760 case IP_VERSION(9, 4, 4): 761 adev->gfx.config.max_hw_contexts = 8; 762 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 763 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 764 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 765 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 766 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 767 break; 768 default: 769 BUG(); 770 break; 771 } 772 773 adev->gfx.config.gb_addr_config = gb_addr_config; 774 775 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 776 REG_GET_FIELD( 777 adev->gfx.config.gb_addr_config, 778 GB_ADDR_CONFIG, 779 NUM_PIPES); 780 781 adev->gfx.config.max_tile_pipes = 782 adev->gfx.config.gb_addr_config_fields.num_pipes; 783 784 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 785 REG_GET_FIELD( 786 adev->gfx.config.gb_addr_config, 787 GB_ADDR_CONFIG, 788 NUM_BANKS); 789 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 790 REG_GET_FIELD( 791 adev->gfx.config.gb_addr_config, 792 GB_ADDR_CONFIG, 793 MAX_COMPRESSED_FRAGS); 794 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 795 REG_GET_FIELD( 796 adev->gfx.config.gb_addr_config, 797 GB_ADDR_CONFIG, 798 NUM_RB_PER_SE); 799 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 800 REG_GET_FIELD( 801 adev->gfx.config.gb_addr_config, 802 GB_ADDR_CONFIG, 803 NUM_SHADER_ENGINES); 804 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 805 REG_GET_FIELD( 806 adev->gfx.config.gb_addr_config, 807 GB_ADDR_CONFIG, 808 PIPE_INTERLEAVE_SIZE)); 809 810 return 0; 811 } 812 813 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 814 int xcc_id, int mec, int pipe, int queue) 815 { 816 unsigned irq_type; 817 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 818 unsigned int hw_prio; 819 uint32_t xcc_doorbell_start; 820 821 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 822 ring_id]; 823 824 /* mec0 is me1 */ 825 ring->xcc_id = xcc_id; 826 ring->me = mec + 1; 827 ring->pipe = pipe; 828 ring->queue = queue; 829 830 ring->ring_obj = NULL; 831 ring->use_doorbell = true; 832 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 833 xcc_id * adev->doorbell_index.xcc_doorbell_range; 834 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 835 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 836 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 837 GFX9_MEC_HPD_SIZE; 838 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 839 sprintf(ring->name, "comp_%d.%d.%d.%d", 840 ring->xcc_id, ring->me, ring->pipe, ring->queue); 841 842 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 843 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 844 + ring->pipe; 845 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 846 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 847 /* type-2 packets are deprecated on MEC, use type-3 instead */ 848 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 849 hw_prio, NULL); 850 } 851 852 static int gfx_v9_4_3_sw_init(void *handle) 853 { 854 int i, j, k, r, ring_id, xcc_id, num_xcc; 855 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 856 857 adev->gfx.mec.num_mec = 2; 858 adev->gfx.mec.num_pipe_per_mec = 4; 859 adev->gfx.mec.num_queue_per_pipe = 8; 860 861 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 862 863 /* EOP Event */ 864 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 865 if (r) 866 return r; 867 868 /* Privileged reg */ 869 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 870 &adev->gfx.priv_reg_irq); 871 if (r) 872 return r; 873 874 /* Privileged inst */ 875 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 876 &adev->gfx.priv_inst_irq); 877 if (r) 878 return r; 879 880 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 881 882 r = adev->gfx.rlc.funcs->init(adev); 883 if (r) { 884 DRM_ERROR("Failed to init rlc BOs!\n"); 885 return r; 886 } 887 888 r = gfx_v9_4_3_mec_init(adev); 889 if (r) { 890 DRM_ERROR("Failed to init MEC BOs!\n"); 891 return r; 892 } 893 894 /* set up the compute queues - allocate horizontally across pipes */ 895 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 896 ring_id = 0; 897 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 898 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 899 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 900 k++) { 901 if (!amdgpu_gfx_is_mec_queue_enabled( 902 adev, xcc_id, i, k, j)) 903 continue; 904 905 r = gfx_v9_4_3_compute_ring_init(adev, 906 ring_id, 907 xcc_id, 908 i, k, j); 909 if (r) 910 return r; 911 912 ring_id++; 913 } 914 } 915 } 916 917 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 918 if (r) { 919 DRM_ERROR("Failed to init KIQ BOs!\n"); 920 return r; 921 } 922 923 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 924 if (r) 925 return r; 926 927 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 928 r = amdgpu_gfx_mqd_sw_init(adev, 929 sizeof(struct v9_mqd_allocation), xcc_id); 930 if (r) 931 return r; 932 } 933 934 r = gfx_v9_4_3_gpu_early_init(adev); 935 if (r) 936 return r; 937 938 r = amdgpu_gfx_ras_sw_init(adev); 939 if (r) 940 return r; 941 942 943 if (!amdgpu_sriov_vf(adev)) 944 r = amdgpu_gfx_sysfs_init(adev); 945 946 return r; 947 } 948 949 static int gfx_v9_4_3_sw_fini(void *handle) 950 { 951 int i, num_xcc; 952 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 953 954 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 955 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 956 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 957 958 for (i = 0; i < num_xcc; i++) { 959 amdgpu_gfx_mqd_sw_fini(adev, i); 960 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 961 amdgpu_gfx_kiq_fini(adev, i); 962 } 963 964 gfx_v9_4_3_mec_fini(adev); 965 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 966 gfx_v9_4_3_free_microcode(adev); 967 if (!amdgpu_sriov_vf(adev)) 968 amdgpu_gfx_sysfs_fini(adev); 969 970 return 0; 971 } 972 973 #define DEFAULT_SH_MEM_BASES (0x6000) 974 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 975 int xcc_id) 976 { 977 int i; 978 uint32_t sh_mem_config; 979 uint32_t sh_mem_bases; 980 uint32_t data; 981 982 /* 983 * Configure apertures: 984 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 985 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 986 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 987 */ 988 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 989 990 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 991 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 992 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 993 994 mutex_lock(&adev->srbm_mutex); 995 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 996 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 997 /* CP and shaders */ 998 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 999 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1000 1001 /* Enable trap for each kfd vmid. */ 1002 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1003 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1004 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1005 } 1006 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1007 mutex_unlock(&adev->srbm_mutex); 1008 1009 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1010 acccess. These should be enabled by FW for target VMIDs. */ 1011 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1012 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1013 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1014 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1015 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1016 } 1017 } 1018 1019 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1020 { 1021 int vmid; 1022 1023 /* 1024 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1025 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1026 * the driver can enable them for graphics. VMID0 should maintain 1027 * access so that HWS firmware can save/restore entries. 1028 */ 1029 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1030 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1031 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1032 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1033 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1034 } 1035 } 1036 1037 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1038 int xcc_id) 1039 { 1040 u32 tmp; 1041 int i; 1042 1043 /* XXX SH_MEM regs */ 1044 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1045 mutex_lock(&adev->srbm_mutex); 1046 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1047 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1048 /* CP and shaders */ 1049 if (i == 0) { 1050 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1051 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1052 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1053 !!adev->gmc.noretry); 1054 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1055 regSH_MEM_CONFIG, tmp); 1056 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1057 regSH_MEM_BASES, 0); 1058 } else { 1059 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1060 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1061 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1062 !!adev->gmc.noretry); 1063 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1064 regSH_MEM_CONFIG, tmp); 1065 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1066 (adev->gmc.private_aperture_start >> 1067 48)); 1068 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1069 (adev->gmc.shared_aperture_start >> 1070 48)); 1071 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1072 regSH_MEM_BASES, tmp); 1073 } 1074 } 1075 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1076 1077 mutex_unlock(&adev->srbm_mutex); 1078 1079 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1080 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1081 } 1082 1083 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1084 { 1085 int i, num_xcc; 1086 1087 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1088 1089 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1090 adev->gfx.config.db_debug2 = 1091 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1092 1093 for (i = 0; i < num_xcc; i++) 1094 gfx_v9_4_3_xcc_constants_init(adev, i); 1095 } 1096 1097 static void 1098 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1099 int xcc_id) 1100 { 1101 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1102 } 1103 1104 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1105 { 1106 /* 1107 * Rlc save restore list is workable since v2_1. 1108 * And it's needed by gfxoff feature. 1109 */ 1110 if (adev->gfx.rlc.is_rlc_v2_1) 1111 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1112 } 1113 1114 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1115 { 1116 uint32_t data; 1117 1118 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1119 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1120 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1121 } 1122 1123 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1124 { 1125 uint32_t rlc_setting; 1126 1127 /* if RLC is not enabled, do nothing */ 1128 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1129 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1130 return false; 1131 1132 return true; 1133 } 1134 1135 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1136 { 1137 uint32_t data; 1138 unsigned i; 1139 1140 data = RLC_SAFE_MODE__CMD_MASK; 1141 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1142 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1143 1144 /* wait for RLC_SAFE_MODE */ 1145 for (i = 0; i < adev->usec_timeout; i++) { 1146 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1147 break; 1148 udelay(1); 1149 } 1150 } 1151 1152 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1153 int xcc_id) 1154 { 1155 uint32_t data; 1156 1157 data = RLC_SAFE_MODE__CMD_MASK; 1158 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1159 } 1160 1161 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1162 { 1163 int xcc_id, num_xcc; 1164 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1165 1166 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1167 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1168 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1169 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1170 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1171 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1172 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1173 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1174 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1175 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1176 } 1177 adev->gfx.rlc.rlcg_reg_access_supported = true; 1178 } 1179 1180 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1181 { 1182 /* init spm vmid with 0xf */ 1183 if (adev->gfx.rlc.funcs->update_spm_vmid) 1184 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1185 1186 return 0; 1187 } 1188 1189 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1190 int xcc_id) 1191 { 1192 u32 i, j, k; 1193 u32 mask; 1194 1195 mutex_lock(&adev->grbm_idx_mutex); 1196 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1197 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1198 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1199 xcc_id); 1200 for (k = 0; k < adev->usec_timeout; k++) { 1201 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1202 break; 1203 udelay(1); 1204 } 1205 if (k == adev->usec_timeout) { 1206 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1207 0xffffffff, 1208 0xffffffff, xcc_id); 1209 mutex_unlock(&adev->grbm_idx_mutex); 1210 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1211 i, j); 1212 return; 1213 } 1214 } 1215 } 1216 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1217 xcc_id); 1218 mutex_unlock(&adev->grbm_idx_mutex); 1219 1220 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1221 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1222 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1223 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1224 for (k = 0; k < adev->usec_timeout; k++) { 1225 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1226 break; 1227 udelay(1); 1228 } 1229 } 1230 1231 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1232 bool enable, int xcc_id) 1233 { 1234 u32 tmp; 1235 1236 /* These interrupts should be enabled to drive DS clock */ 1237 1238 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1239 1240 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1241 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1242 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1243 1244 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1245 } 1246 1247 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1248 { 1249 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1250 RLC_ENABLE_F32, 0); 1251 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1252 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1253 } 1254 1255 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1256 { 1257 int i, num_xcc; 1258 1259 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1260 for (i = 0; i < num_xcc; i++) 1261 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1262 } 1263 1264 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1265 { 1266 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1267 SOFT_RESET_RLC, 1); 1268 udelay(50); 1269 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1270 SOFT_RESET_RLC, 0); 1271 udelay(50); 1272 } 1273 1274 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1275 { 1276 int i, num_xcc; 1277 1278 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1279 for (i = 0; i < num_xcc; i++) 1280 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1281 } 1282 1283 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1284 { 1285 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1286 RLC_ENABLE_F32, 1); 1287 udelay(50); 1288 1289 /* carrizo do enable cp interrupt after cp inited */ 1290 if (!(adev->flags & AMD_IS_APU)) { 1291 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1292 udelay(50); 1293 } 1294 } 1295 1296 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1297 { 1298 #ifdef AMDGPU_RLC_DEBUG_RETRY 1299 u32 rlc_ucode_ver; 1300 #endif 1301 int i, num_xcc; 1302 1303 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1304 for (i = 0; i < num_xcc; i++) { 1305 gfx_v9_4_3_xcc_rlc_start(adev, i); 1306 #ifdef AMDGPU_RLC_DEBUG_RETRY 1307 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1308 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1309 if (rlc_ucode_ver == 0x108) { 1310 dev_info(adev->dev, 1311 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1312 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1313 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1314 * default is 0x9C4 to create a 100us interval */ 1315 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1316 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1317 * to disable the page fault retry interrupts, default is 1318 * 0x100 (256) */ 1319 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1320 } 1321 #endif 1322 } 1323 } 1324 1325 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1326 int xcc_id) 1327 { 1328 const struct rlc_firmware_header_v2_0 *hdr; 1329 const __le32 *fw_data; 1330 unsigned i, fw_size; 1331 1332 if (!adev->gfx.rlc_fw) 1333 return -EINVAL; 1334 1335 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1336 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1337 1338 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1339 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1340 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1341 1342 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1343 RLCG_UCODE_LOADING_START_ADDRESS); 1344 for (i = 0; i < fw_size; i++) { 1345 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1346 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1347 msleep(1); 1348 } 1349 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1350 } 1351 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1352 1353 return 0; 1354 } 1355 1356 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1357 { 1358 int r; 1359 1360 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1361 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1362 /* legacy rlc firmware loading */ 1363 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1364 if (r) 1365 return r; 1366 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1367 } 1368 1369 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1370 /* disable CG */ 1371 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1372 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1373 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1374 1375 return 0; 1376 } 1377 1378 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1379 { 1380 int r, i, num_xcc; 1381 1382 if (amdgpu_sriov_vf(adev)) 1383 return 0; 1384 1385 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1386 for (i = 0; i < num_xcc; i++) { 1387 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1388 if (r) 1389 return r; 1390 } 1391 1392 return 0; 1393 } 1394 1395 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1396 unsigned vmid) 1397 { 1398 u32 reg, data; 1399 1400 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1401 if (amdgpu_sriov_is_pp_one_vf(adev)) 1402 data = RREG32_NO_KIQ(reg); 1403 else 1404 data = RREG32(reg); 1405 1406 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1407 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1408 1409 if (amdgpu_sriov_is_pp_one_vf(adev)) 1410 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1411 else 1412 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1413 } 1414 1415 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1416 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1417 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1418 }; 1419 1420 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1421 uint32_t offset, 1422 struct soc15_reg_rlcg *entries, int arr_size) 1423 { 1424 int i, inst; 1425 uint32_t reg; 1426 1427 if (!entries) 1428 return false; 1429 1430 for (i = 0; i < arr_size; i++) { 1431 const struct soc15_reg_rlcg *entry; 1432 1433 entry = &entries[i]; 1434 inst = adev->ip_map.logical_to_dev_inst ? 1435 adev->ip_map.logical_to_dev_inst( 1436 adev, entry->hwip, entry->instance) : 1437 entry->instance; 1438 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1439 entry->reg; 1440 if (offset == reg) 1441 return true; 1442 } 1443 1444 return false; 1445 } 1446 1447 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1448 { 1449 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1450 (void *)rlcg_access_gc_9_4_3, 1451 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1452 } 1453 1454 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1455 bool enable, int xcc_id) 1456 { 1457 if (enable) { 1458 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1459 } else { 1460 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1461 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1462 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1463 } 1464 udelay(50); 1465 } 1466 1467 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1468 int xcc_id) 1469 { 1470 const struct gfx_firmware_header_v1_0 *mec_hdr; 1471 const __le32 *fw_data; 1472 unsigned i; 1473 u32 tmp; 1474 u32 mec_ucode_addr_offset; 1475 u32 mec_ucode_data_offset; 1476 1477 if (!adev->gfx.mec_fw) 1478 return -EINVAL; 1479 1480 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1481 1482 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1483 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1484 1485 fw_data = (const __le32 *) 1486 (adev->gfx.mec_fw->data + 1487 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1488 tmp = 0; 1489 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1490 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1491 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1492 1493 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1494 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1495 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1496 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1497 1498 mec_ucode_addr_offset = 1499 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1500 mec_ucode_data_offset = 1501 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1502 1503 /* MEC1 */ 1504 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1505 for (i = 0; i < mec_hdr->jt_size; i++) 1506 WREG32(mec_ucode_data_offset, 1507 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1508 1509 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1510 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1511 1512 return 0; 1513 } 1514 1515 /* KIQ functions */ 1516 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1517 { 1518 uint32_t tmp; 1519 struct amdgpu_device *adev = ring->adev; 1520 1521 /* tell RLC which is KIQ queue */ 1522 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1523 tmp &= 0xffffff00; 1524 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1525 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1526 tmp |= 0x80; 1527 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1528 } 1529 1530 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1531 { 1532 struct amdgpu_device *adev = ring->adev; 1533 1534 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1535 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1536 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1537 mqd->cp_hqd_queue_priority = 1538 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1539 } 1540 } 1541 } 1542 1543 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1544 { 1545 struct amdgpu_device *adev = ring->adev; 1546 struct v9_mqd *mqd = ring->mqd_ptr; 1547 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1548 uint32_t tmp; 1549 1550 mqd->header = 0xC0310800; 1551 mqd->compute_pipelinestat_enable = 0x00000001; 1552 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1553 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1554 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1555 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1556 mqd->compute_misc_reserved = 0x00000003; 1557 1558 mqd->dynamic_cu_mask_addr_lo = 1559 lower_32_bits(ring->mqd_gpu_addr 1560 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1561 mqd->dynamic_cu_mask_addr_hi = 1562 upper_32_bits(ring->mqd_gpu_addr 1563 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1564 1565 eop_base_addr = ring->eop_gpu_addr >> 8; 1566 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1567 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1568 1569 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1570 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1571 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1572 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1573 1574 mqd->cp_hqd_eop_control = tmp; 1575 1576 /* enable doorbell? */ 1577 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1578 1579 if (ring->use_doorbell) { 1580 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1581 DOORBELL_OFFSET, ring->doorbell_index); 1582 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1583 DOORBELL_EN, 1); 1584 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1585 DOORBELL_SOURCE, 0); 1586 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1587 DOORBELL_HIT, 0); 1588 } else { 1589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1590 DOORBELL_EN, 0); 1591 } 1592 1593 mqd->cp_hqd_pq_doorbell_control = tmp; 1594 1595 /* disable the queue if it's active */ 1596 ring->wptr = 0; 1597 mqd->cp_hqd_dequeue_request = 0; 1598 mqd->cp_hqd_pq_rptr = 0; 1599 mqd->cp_hqd_pq_wptr_lo = 0; 1600 mqd->cp_hqd_pq_wptr_hi = 0; 1601 1602 /* set the pointer to the MQD */ 1603 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1604 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1605 1606 /* set MQD vmid to 0 */ 1607 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1608 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1609 mqd->cp_mqd_control = tmp; 1610 1611 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1612 hqd_gpu_addr = ring->gpu_addr >> 8; 1613 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1614 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1615 1616 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1617 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1618 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1619 (order_base_2(ring->ring_size / 4) - 1)); 1620 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1621 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1622 #ifdef __BIG_ENDIAN 1623 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1624 #endif 1625 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1626 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1627 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1628 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1629 mqd->cp_hqd_pq_control = tmp; 1630 1631 /* set the wb address whether it's enabled or not */ 1632 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1633 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1634 mqd->cp_hqd_pq_rptr_report_addr_hi = 1635 upper_32_bits(wb_gpu_addr) & 0xffff; 1636 1637 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1638 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1639 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1640 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1641 1642 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1643 ring->wptr = 0; 1644 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1645 1646 /* set the vmid for the queue */ 1647 mqd->cp_hqd_vmid = 0; 1648 1649 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1650 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1651 mqd->cp_hqd_persistent_state = tmp; 1652 1653 /* set MIN_IB_AVAIL_SIZE */ 1654 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1655 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1656 mqd->cp_hqd_ib_control = tmp; 1657 1658 /* set static priority for a queue/ring */ 1659 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1660 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1661 1662 /* map_queues packet doesn't need activate the queue, 1663 * so only kiq need set this field. 1664 */ 1665 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1666 mqd->cp_hqd_active = 1; 1667 1668 return 0; 1669 } 1670 1671 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1672 int xcc_id) 1673 { 1674 struct amdgpu_device *adev = ring->adev; 1675 struct v9_mqd *mqd = ring->mqd_ptr; 1676 int j; 1677 1678 /* disable wptr polling */ 1679 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1680 1681 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1682 mqd->cp_hqd_eop_base_addr_lo); 1683 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1684 mqd->cp_hqd_eop_base_addr_hi); 1685 1686 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1687 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1688 mqd->cp_hqd_eop_control); 1689 1690 /* enable doorbell? */ 1691 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1692 mqd->cp_hqd_pq_doorbell_control); 1693 1694 /* disable the queue if it's active */ 1695 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1696 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1697 for (j = 0; j < adev->usec_timeout; j++) { 1698 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1699 break; 1700 udelay(1); 1701 } 1702 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1703 mqd->cp_hqd_dequeue_request); 1704 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1705 mqd->cp_hqd_pq_rptr); 1706 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1707 mqd->cp_hqd_pq_wptr_lo); 1708 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1709 mqd->cp_hqd_pq_wptr_hi); 1710 } 1711 1712 /* set the pointer to the MQD */ 1713 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1714 mqd->cp_mqd_base_addr_lo); 1715 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1716 mqd->cp_mqd_base_addr_hi); 1717 1718 /* set MQD vmid to 0 */ 1719 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1720 mqd->cp_mqd_control); 1721 1722 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1723 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1724 mqd->cp_hqd_pq_base_lo); 1725 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1726 mqd->cp_hqd_pq_base_hi); 1727 1728 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1729 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1730 mqd->cp_hqd_pq_control); 1731 1732 /* set the wb address whether it's enabled or not */ 1733 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1734 mqd->cp_hqd_pq_rptr_report_addr_lo); 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1736 mqd->cp_hqd_pq_rptr_report_addr_hi); 1737 1738 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1739 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1740 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1741 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1742 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1743 1744 /* enable the doorbell if requested */ 1745 if (ring->use_doorbell) { 1746 WREG32_SOC15( 1747 GC, GET_INST(GC, xcc_id), 1748 regCP_MEC_DOORBELL_RANGE_LOWER, 1749 ((adev->doorbell_index.kiq + 1750 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1751 2) << 2); 1752 WREG32_SOC15( 1753 GC, GET_INST(GC, xcc_id), 1754 regCP_MEC_DOORBELL_RANGE_UPPER, 1755 ((adev->doorbell_index.userqueue_end + 1756 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1757 2) << 2); 1758 } 1759 1760 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1761 mqd->cp_hqd_pq_doorbell_control); 1762 1763 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1764 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1765 mqd->cp_hqd_pq_wptr_lo); 1766 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1767 mqd->cp_hqd_pq_wptr_hi); 1768 1769 /* set the vmid for the queue */ 1770 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1771 1772 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1773 mqd->cp_hqd_persistent_state); 1774 1775 /* activate the queue */ 1776 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1777 mqd->cp_hqd_active); 1778 1779 if (ring->use_doorbell) 1780 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1781 1782 return 0; 1783 } 1784 1785 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1786 int xcc_id) 1787 { 1788 struct amdgpu_device *adev = ring->adev; 1789 int j; 1790 1791 /* disable the queue if it's active */ 1792 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1793 1794 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1795 1796 for (j = 0; j < adev->usec_timeout; j++) { 1797 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1798 break; 1799 udelay(1); 1800 } 1801 1802 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1803 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1804 1805 /* Manual disable if dequeue request times out */ 1806 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1807 } 1808 1809 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1810 0); 1811 } 1812 1813 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1814 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1815 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 1816 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1817 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1818 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1819 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1820 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1821 1822 return 0; 1823 } 1824 1825 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1826 { 1827 struct amdgpu_device *adev = ring->adev; 1828 struct v9_mqd *mqd = ring->mqd_ptr; 1829 struct v9_mqd *tmp_mqd; 1830 1831 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1832 1833 /* GPU could be in bad state during probe, driver trigger the reset 1834 * after load the SMU, in this case , the mqd is not be initialized. 1835 * driver need to re-init the mqd. 1836 * check mqd->cp_hqd_pq_control since this value should not be 0 1837 */ 1838 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1839 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1840 /* for GPU_RESET case , reset MQD to a clean status */ 1841 if (adev->gfx.kiq[xcc_id].mqd_backup) 1842 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1843 1844 /* reset ring buffer */ 1845 ring->wptr = 0; 1846 amdgpu_ring_clear_ring(ring); 1847 mutex_lock(&adev->srbm_mutex); 1848 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1849 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1850 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1851 mutex_unlock(&adev->srbm_mutex); 1852 } else { 1853 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1854 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1855 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1856 mutex_lock(&adev->srbm_mutex); 1857 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1858 amdgpu_ring_clear_ring(ring); 1859 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1860 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1861 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1862 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1863 mutex_unlock(&adev->srbm_mutex); 1864 1865 if (adev->gfx.kiq[xcc_id].mqd_backup) 1866 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1867 } 1868 1869 return 0; 1870 } 1871 1872 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1873 { 1874 struct amdgpu_device *adev = ring->adev; 1875 struct v9_mqd *mqd = ring->mqd_ptr; 1876 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1877 struct v9_mqd *tmp_mqd; 1878 1879 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1880 * is not be initialized before 1881 */ 1882 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1883 1884 if (!tmp_mqd->cp_hqd_pq_control || 1885 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1886 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1887 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1888 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1889 mutex_lock(&adev->srbm_mutex); 1890 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1891 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1892 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1893 mutex_unlock(&adev->srbm_mutex); 1894 1895 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1896 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1897 } else { 1898 /* restore MQD to a clean status */ 1899 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1900 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1901 /* reset ring buffer */ 1902 ring->wptr = 0; 1903 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1904 amdgpu_ring_clear_ring(ring); 1905 } 1906 1907 return 0; 1908 } 1909 1910 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1911 { 1912 struct amdgpu_ring *ring; 1913 int j; 1914 1915 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1916 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1917 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1918 mutex_lock(&adev->srbm_mutex); 1919 soc15_grbm_select(adev, ring->me, 1920 ring->pipe, 1921 ring->queue, 0, GET_INST(GC, xcc_id)); 1922 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1923 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1924 mutex_unlock(&adev->srbm_mutex); 1925 } 1926 } 1927 1928 return 0; 1929 } 1930 1931 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1932 { 1933 struct amdgpu_ring *ring; 1934 int r; 1935 1936 ring = &adev->gfx.kiq[xcc_id].ring; 1937 1938 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1939 if (unlikely(r != 0)) 1940 return r; 1941 1942 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1943 if (unlikely(r != 0)) { 1944 amdgpu_bo_unreserve(ring->mqd_obj); 1945 return r; 1946 } 1947 1948 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1949 amdgpu_bo_kunmap(ring->mqd_obj); 1950 ring->mqd_ptr = NULL; 1951 amdgpu_bo_unreserve(ring->mqd_obj); 1952 return 0; 1953 } 1954 1955 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1956 { 1957 struct amdgpu_ring *ring = NULL; 1958 int r = 0, i; 1959 1960 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1961 1962 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1963 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1964 1965 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1966 if (unlikely(r != 0)) 1967 goto done; 1968 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1969 if (!r) { 1970 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1971 amdgpu_bo_kunmap(ring->mqd_obj); 1972 ring->mqd_ptr = NULL; 1973 } 1974 amdgpu_bo_unreserve(ring->mqd_obj); 1975 if (r) 1976 goto done; 1977 } 1978 1979 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1980 done: 1981 return r; 1982 } 1983 1984 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1985 { 1986 struct amdgpu_ring *ring; 1987 int r, j; 1988 1989 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1990 1991 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1992 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1993 1994 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1995 if (r) 1996 return r; 1997 } 1998 1999 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2000 if (r) 2001 return r; 2002 2003 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2004 if (r) 2005 return r; 2006 2007 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2008 ring = &adev->gfx.compute_ring 2009 [j + xcc_id * adev->gfx.num_compute_rings]; 2010 r = amdgpu_ring_test_helper(ring); 2011 if (r) 2012 return r; 2013 } 2014 2015 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2016 2017 return 0; 2018 } 2019 2020 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2021 { 2022 int r = 0, i, num_xcc; 2023 2024 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2025 AMDGPU_XCP_FL_NONE) == 2026 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2027 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 2028 amdgpu_user_partt_mode); 2029 2030 if (r) 2031 return r; 2032 2033 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2034 for (i = 0; i < num_xcc; i++) { 2035 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2036 if (r) 2037 return r; 2038 } 2039 2040 return 0; 2041 } 2042 2043 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 2044 int xcc_id) 2045 { 2046 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 2047 } 2048 2049 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2050 { 2051 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2052 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2053 2054 if (amdgpu_sriov_vf(adev)) { 2055 /* must disable polling for SRIOV when hw finished, otherwise 2056 * CPC engine may still keep fetching WB address which is already 2057 * invalid after sw finished and trigger DMAR reading error in 2058 * hypervisor side. 2059 */ 2060 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2061 return; 2062 } 2063 2064 /* Use deinitialize sequence from CAIL when unbinding device 2065 * from driver, otherwise KIQ is hanging when binding back 2066 */ 2067 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2068 mutex_lock(&adev->srbm_mutex); 2069 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2070 adev->gfx.kiq[xcc_id].ring.pipe, 2071 adev->gfx.kiq[xcc_id].ring.queue, 0, 2072 GET_INST(GC, xcc_id)); 2073 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2074 xcc_id); 2075 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2076 mutex_unlock(&adev->srbm_mutex); 2077 } 2078 2079 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2080 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 2081 } 2082 2083 static int gfx_v9_4_3_hw_init(void *handle) 2084 { 2085 int r; 2086 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2087 2088 if (!amdgpu_sriov_vf(adev)) 2089 gfx_v9_4_3_init_golden_registers(adev); 2090 2091 gfx_v9_4_3_constants_init(adev); 2092 2093 r = adev->gfx.rlc.funcs->resume(adev); 2094 if (r) 2095 return r; 2096 2097 r = gfx_v9_4_3_cp_resume(adev); 2098 if (r) 2099 return r; 2100 2101 return r; 2102 } 2103 2104 static int gfx_v9_4_3_hw_fini(void *handle) 2105 { 2106 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2107 int i, num_xcc; 2108 2109 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2110 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2111 2112 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2113 for (i = 0; i < num_xcc; i++) { 2114 gfx_v9_4_3_xcc_fini(adev, i); 2115 } 2116 2117 return 0; 2118 } 2119 2120 static int gfx_v9_4_3_suspend(void *handle) 2121 { 2122 return gfx_v9_4_3_hw_fini(handle); 2123 } 2124 2125 static int gfx_v9_4_3_resume(void *handle) 2126 { 2127 return gfx_v9_4_3_hw_init(handle); 2128 } 2129 2130 static bool gfx_v9_4_3_is_idle(void *handle) 2131 { 2132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2133 int i, num_xcc; 2134 2135 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2136 for (i = 0; i < num_xcc; i++) { 2137 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2138 GRBM_STATUS, GUI_ACTIVE)) 2139 return false; 2140 } 2141 return true; 2142 } 2143 2144 static int gfx_v9_4_3_wait_for_idle(void *handle) 2145 { 2146 unsigned i; 2147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2148 2149 for (i = 0; i < adev->usec_timeout; i++) { 2150 if (gfx_v9_4_3_is_idle(handle)) 2151 return 0; 2152 udelay(1); 2153 } 2154 return -ETIMEDOUT; 2155 } 2156 2157 static int gfx_v9_4_3_soft_reset(void *handle) 2158 { 2159 u32 grbm_soft_reset = 0; 2160 u32 tmp; 2161 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2162 2163 /* GRBM_STATUS */ 2164 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2165 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2166 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2167 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2168 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2169 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2170 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2171 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2172 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2173 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2174 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2175 } 2176 2177 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2178 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2179 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2180 } 2181 2182 /* GRBM_STATUS2 */ 2183 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2184 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2185 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2186 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2187 2188 2189 if (grbm_soft_reset) { 2190 /* stop the rlc */ 2191 adev->gfx.rlc.funcs->stop(adev); 2192 2193 /* Disable MEC parsing/prefetching */ 2194 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2195 2196 if (grbm_soft_reset) { 2197 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2198 tmp |= grbm_soft_reset; 2199 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2200 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2201 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2202 2203 udelay(50); 2204 2205 tmp &= ~grbm_soft_reset; 2206 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2207 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2208 } 2209 2210 /* Wait a little for things to settle down */ 2211 udelay(50); 2212 } 2213 return 0; 2214 } 2215 2216 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2217 uint32_t vmid, 2218 uint32_t gds_base, uint32_t gds_size, 2219 uint32_t gws_base, uint32_t gws_size, 2220 uint32_t oa_base, uint32_t oa_size) 2221 { 2222 struct amdgpu_device *adev = ring->adev; 2223 2224 /* GDS Base */ 2225 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2226 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2227 gds_base); 2228 2229 /* GDS Size */ 2230 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2231 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2232 gds_size); 2233 2234 /* GWS */ 2235 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2236 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2237 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2238 2239 /* OA */ 2240 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2241 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2242 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2243 } 2244 2245 static int gfx_v9_4_3_early_init(void *handle) 2246 { 2247 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2248 2249 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2250 AMDGPU_MAX_COMPUTE_RINGS); 2251 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2252 gfx_v9_4_3_set_ring_funcs(adev); 2253 gfx_v9_4_3_set_irq_funcs(adev); 2254 gfx_v9_4_3_set_gds_init(adev); 2255 gfx_v9_4_3_set_rlc_funcs(adev); 2256 2257 /* init rlcg reg access ctrl */ 2258 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2259 2260 return gfx_v9_4_3_init_microcode(adev); 2261 } 2262 2263 static int gfx_v9_4_3_late_init(void *handle) 2264 { 2265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2266 int r; 2267 2268 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2269 if (r) 2270 return r; 2271 2272 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2273 if (r) 2274 return r; 2275 2276 if (adev->gfx.ras && 2277 adev->gfx.ras->enable_watchdog_timer) 2278 adev->gfx.ras->enable_watchdog_timer(adev); 2279 2280 return 0; 2281 } 2282 2283 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2284 bool enable, int xcc_id) 2285 { 2286 uint32_t def, data; 2287 2288 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2289 return; 2290 2291 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2292 regRLC_CGTT_MGCG_OVERRIDE); 2293 2294 if (enable) 2295 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2296 else 2297 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2298 2299 if (def != data) 2300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2301 regRLC_CGTT_MGCG_OVERRIDE, data); 2302 2303 } 2304 2305 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2306 bool enable, int xcc_id) 2307 { 2308 uint32_t def, data; 2309 2310 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2311 return; 2312 2313 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2314 regRLC_CGTT_MGCG_OVERRIDE); 2315 2316 if (enable) 2317 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2318 else 2319 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2320 2321 if (def != data) 2322 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2323 regRLC_CGTT_MGCG_OVERRIDE, data); 2324 } 2325 2326 static void 2327 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2328 bool enable, int xcc_id) 2329 { 2330 uint32_t data, def; 2331 2332 /* It is disabled by HW by default */ 2333 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2334 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2335 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2336 2337 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2338 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2339 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2340 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2341 2342 if (def != data) 2343 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2344 2345 /* MGLS is a global flag to control all MGLS in GFX */ 2346 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2347 /* 2 - RLC memory Light sleep */ 2348 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2349 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2350 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2351 if (def != data) 2352 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2353 } 2354 /* 3 - CP memory Light sleep */ 2355 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2356 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2357 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2358 if (def != data) 2359 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2360 } 2361 } 2362 } else { 2363 /* 1 - MGCG_OVERRIDE */ 2364 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2365 2366 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2367 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2368 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2369 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2370 2371 if (def != data) 2372 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2373 2374 /* 2 - disable MGLS in RLC */ 2375 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2376 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2377 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2378 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2379 } 2380 2381 /* 3 - disable MGLS in CP */ 2382 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2383 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2384 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2385 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2386 } 2387 } 2388 2389 } 2390 2391 static void 2392 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2393 bool enable, int xcc_id) 2394 { 2395 uint32_t def, data; 2396 2397 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2398 2399 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2400 /* unset CGCG override */ 2401 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2402 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2403 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2404 else 2405 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2406 /* update CGCG and CGLS override bits */ 2407 if (def != data) 2408 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2409 2410 /* CGCG Hysteresis: 400us */ 2411 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2412 2413 data = (0x2710 2414 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2415 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2416 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2417 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2418 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2419 if (def != data) 2420 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2421 2422 /* set IDLE_POLL_COUNT(0x33450100)*/ 2423 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2424 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2425 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2426 if (def != data) 2427 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2428 } else { 2429 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2430 /* reset CGCG/CGLS bits */ 2431 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2432 /* disable cgcg and cgls in FSM */ 2433 if (def != data) 2434 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2435 } 2436 2437 } 2438 2439 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2440 bool enable, int xcc_id) 2441 { 2442 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2443 2444 if (enable) { 2445 /* FGCG */ 2446 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2447 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2448 2449 /* CGCG/CGLS should be enabled after MGCG/MGLS 2450 * === MGCG + MGLS === 2451 */ 2452 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2453 xcc_id); 2454 /* === CGCG + CGLS === */ 2455 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2456 xcc_id); 2457 } else { 2458 /* CGCG/CGLS should be disabled before MGCG/MGLS 2459 * === CGCG + CGLS === 2460 */ 2461 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2462 xcc_id); 2463 /* === MGCG + MGLS === */ 2464 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2465 xcc_id); 2466 2467 /* FGCG */ 2468 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2469 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2470 } 2471 2472 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2473 2474 return 0; 2475 } 2476 2477 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2478 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2479 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2480 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2481 .init = gfx_v9_4_3_rlc_init, 2482 .resume = gfx_v9_4_3_rlc_resume, 2483 .stop = gfx_v9_4_3_rlc_stop, 2484 .reset = gfx_v9_4_3_rlc_reset, 2485 .start = gfx_v9_4_3_rlc_start, 2486 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2487 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2488 }; 2489 2490 static int gfx_v9_4_3_set_powergating_state(void *handle, 2491 enum amd_powergating_state state) 2492 { 2493 return 0; 2494 } 2495 2496 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2497 enum amd_clockgating_state state) 2498 { 2499 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2500 int i, num_xcc; 2501 2502 if (amdgpu_sriov_vf(adev)) 2503 return 0; 2504 2505 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2506 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2507 case IP_VERSION(9, 4, 3): 2508 case IP_VERSION(9, 4, 4): 2509 for (i = 0; i < num_xcc; i++) 2510 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2511 adev, state == AMD_CG_STATE_GATE, i); 2512 break; 2513 default: 2514 break; 2515 } 2516 return 0; 2517 } 2518 2519 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2520 { 2521 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2522 int data; 2523 2524 if (amdgpu_sriov_vf(adev)) 2525 *flags = 0; 2526 2527 /* AMD_CG_SUPPORT_GFX_MGCG */ 2528 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2529 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2530 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2531 2532 /* AMD_CG_SUPPORT_GFX_CGCG */ 2533 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2534 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2535 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2536 2537 /* AMD_CG_SUPPORT_GFX_CGLS */ 2538 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2539 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2540 2541 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2542 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2543 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2544 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2545 2546 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2547 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2548 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2549 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2550 } 2551 2552 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2553 { 2554 struct amdgpu_device *adev = ring->adev; 2555 u32 ref_and_mask, reg_mem_engine; 2556 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2557 2558 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2559 switch (ring->me) { 2560 case 1: 2561 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2562 break; 2563 case 2: 2564 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2565 break; 2566 default: 2567 return; 2568 } 2569 reg_mem_engine = 0; 2570 } else { 2571 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2572 reg_mem_engine = 1; /* pfp */ 2573 } 2574 2575 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2576 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2577 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2578 ref_and_mask, ref_and_mask, 0x20); 2579 } 2580 2581 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2582 struct amdgpu_job *job, 2583 struct amdgpu_ib *ib, 2584 uint32_t flags) 2585 { 2586 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2587 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2588 2589 /* Currently, there is a high possibility to get wave ID mismatch 2590 * between ME and GDS, leading to a hw deadlock, because ME generates 2591 * different wave IDs than the GDS expects. This situation happens 2592 * randomly when at least 5 compute pipes use GDS ordered append. 2593 * The wave IDs generated by ME are also wrong after suspend/resume. 2594 * Those are probably bugs somewhere else in the kernel driver. 2595 * 2596 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2597 * GDS to 0 for this ring (me/pipe). 2598 */ 2599 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2600 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2601 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2602 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2603 } 2604 2605 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2606 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2607 amdgpu_ring_write(ring, 2608 #ifdef __BIG_ENDIAN 2609 (2 << 0) | 2610 #endif 2611 lower_32_bits(ib->gpu_addr)); 2612 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2613 amdgpu_ring_write(ring, control); 2614 } 2615 2616 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2617 u64 seq, unsigned flags) 2618 { 2619 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2620 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2621 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2622 2623 /* RELEASE_MEM - flush caches, send int */ 2624 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2625 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2626 EOP_TC_NC_ACTION_EN) : 2627 (EOP_TCL1_ACTION_EN | 2628 EOP_TC_ACTION_EN | 2629 EOP_TC_WB_ACTION_EN | 2630 EOP_TC_MD_ACTION_EN)) | 2631 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2632 EVENT_INDEX(5))); 2633 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2634 2635 /* 2636 * the address should be Qword aligned if 64bit write, Dword 2637 * aligned if only send 32bit data low (discard data high) 2638 */ 2639 if (write64bit) 2640 BUG_ON(addr & 0x7); 2641 else 2642 BUG_ON(addr & 0x3); 2643 amdgpu_ring_write(ring, lower_32_bits(addr)); 2644 amdgpu_ring_write(ring, upper_32_bits(addr)); 2645 amdgpu_ring_write(ring, lower_32_bits(seq)); 2646 amdgpu_ring_write(ring, upper_32_bits(seq)); 2647 amdgpu_ring_write(ring, 0); 2648 } 2649 2650 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2651 { 2652 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2653 uint32_t seq = ring->fence_drv.sync_seq; 2654 uint64_t addr = ring->fence_drv.gpu_addr; 2655 2656 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2657 lower_32_bits(addr), upper_32_bits(addr), 2658 seq, 0xffffffff, 4); 2659 } 2660 2661 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2662 unsigned vmid, uint64_t pd_addr) 2663 { 2664 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2665 } 2666 2667 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2668 { 2669 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2670 } 2671 2672 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2673 { 2674 u64 wptr; 2675 2676 /* XXX check if swapping is necessary on BE */ 2677 if (ring->use_doorbell) 2678 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2679 else 2680 BUG(); 2681 return wptr; 2682 } 2683 2684 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2685 { 2686 struct amdgpu_device *adev = ring->adev; 2687 2688 /* XXX check if swapping is necessary on BE */ 2689 if (ring->use_doorbell) { 2690 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2691 WDOORBELL64(ring->doorbell_index, ring->wptr); 2692 } else { 2693 BUG(); /* only DOORBELL method supported on gfx9 now */ 2694 } 2695 } 2696 2697 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2698 u64 seq, unsigned int flags) 2699 { 2700 struct amdgpu_device *adev = ring->adev; 2701 2702 /* we only allocate 32bit for each seq wb address */ 2703 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2704 2705 /* write fence seq to the "addr" */ 2706 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2707 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2708 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2709 amdgpu_ring_write(ring, lower_32_bits(addr)); 2710 amdgpu_ring_write(ring, upper_32_bits(addr)); 2711 amdgpu_ring_write(ring, lower_32_bits(seq)); 2712 2713 if (flags & AMDGPU_FENCE_FLAG_INT) { 2714 /* set register to trigger INT */ 2715 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2716 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2717 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2718 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2719 amdgpu_ring_write(ring, 0); 2720 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2721 } 2722 } 2723 2724 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2725 uint32_t reg_val_offs) 2726 { 2727 struct amdgpu_device *adev = ring->adev; 2728 2729 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2730 amdgpu_ring_write(ring, 0 | /* src: register*/ 2731 (5 << 8) | /* dst: memory */ 2732 (1 << 20)); /* write confirm */ 2733 amdgpu_ring_write(ring, reg); 2734 amdgpu_ring_write(ring, 0); 2735 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2736 reg_val_offs * 4)); 2737 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2738 reg_val_offs * 4)); 2739 } 2740 2741 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2742 uint32_t val) 2743 { 2744 uint32_t cmd = 0; 2745 2746 switch (ring->funcs->type) { 2747 case AMDGPU_RING_TYPE_GFX: 2748 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2749 break; 2750 case AMDGPU_RING_TYPE_KIQ: 2751 cmd = (1 << 16); /* no inc addr */ 2752 break; 2753 default: 2754 cmd = WR_CONFIRM; 2755 break; 2756 } 2757 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2758 amdgpu_ring_write(ring, cmd); 2759 amdgpu_ring_write(ring, reg); 2760 amdgpu_ring_write(ring, 0); 2761 amdgpu_ring_write(ring, val); 2762 } 2763 2764 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2765 uint32_t val, uint32_t mask) 2766 { 2767 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2768 } 2769 2770 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2771 uint32_t reg0, uint32_t reg1, 2772 uint32_t ref, uint32_t mask) 2773 { 2774 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2775 ref, mask); 2776 } 2777 2778 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2779 struct amdgpu_device *adev, int me, int pipe, 2780 enum amdgpu_interrupt_state state, int xcc_id) 2781 { 2782 u32 mec_int_cntl, mec_int_cntl_reg; 2783 2784 /* 2785 * amdgpu controls only the first MEC. That's why this function only 2786 * handles the setting of interrupts for this specific MEC. All other 2787 * pipes' interrupts are set by amdkfd. 2788 */ 2789 2790 if (me == 1) { 2791 switch (pipe) { 2792 case 0: 2793 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2794 break; 2795 case 1: 2796 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2797 break; 2798 case 2: 2799 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2800 break; 2801 case 3: 2802 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2803 break; 2804 default: 2805 DRM_DEBUG("invalid pipe %d\n", pipe); 2806 return; 2807 } 2808 } else { 2809 DRM_DEBUG("invalid me %d\n", me); 2810 return; 2811 } 2812 2813 switch (state) { 2814 case AMDGPU_IRQ_STATE_DISABLE: 2815 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2816 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2817 TIME_STAMP_INT_ENABLE, 0); 2818 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2819 break; 2820 case AMDGPU_IRQ_STATE_ENABLE: 2821 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2822 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2823 TIME_STAMP_INT_ENABLE, 1); 2824 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2825 break; 2826 default: 2827 break; 2828 } 2829 } 2830 2831 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2832 struct amdgpu_irq_src *source, 2833 unsigned type, 2834 enum amdgpu_interrupt_state state) 2835 { 2836 int i, num_xcc; 2837 2838 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2839 switch (state) { 2840 case AMDGPU_IRQ_STATE_DISABLE: 2841 case AMDGPU_IRQ_STATE_ENABLE: 2842 for (i = 0; i < num_xcc; i++) 2843 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2844 PRIV_REG_INT_ENABLE, 2845 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2846 break; 2847 default: 2848 break; 2849 } 2850 2851 return 0; 2852 } 2853 2854 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2855 struct amdgpu_irq_src *source, 2856 unsigned type, 2857 enum amdgpu_interrupt_state state) 2858 { 2859 int i, num_xcc; 2860 2861 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2862 switch (state) { 2863 case AMDGPU_IRQ_STATE_DISABLE: 2864 case AMDGPU_IRQ_STATE_ENABLE: 2865 for (i = 0; i < num_xcc; i++) 2866 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2867 PRIV_INSTR_INT_ENABLE, 2868 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2869 break; 2870 default: 2871 break; 2872 } 2873 2874 return 0; 2875 } 2876 2877 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2878 struct amdgpu_irq_src *src, 2879 unsigned type, 2880 enum amdgpu_interrupt_state state) 2881 { 2882 int i, num_xcc; 2883 2884 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2885 for (i = 0; i < num_xcc; i++) { 2886 switch (type) { 2887 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2888 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2889 adev, 1, 0, state, i); 2890 break; 2891 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2892 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2893 adev, 1, 1, state, i); 2894 break; 2895 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2896 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2897 adev, 1, 2, state, i); 2898 break; 2899 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2900 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2901 adev, 1, 3, state, i); 2902 break; 2903 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2904 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2905 adev, 2, 0, state, i); 2906 break; 2907 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2908 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2909 adev, 2, 1, state, i); 2910 break; 2911 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2912 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2913 adev, 2, 2, state, i); 2914 break; 2915 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2916 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2917 adev, 2, 3, state, i); 2918 break; 2919 default: 2920 break; 2921 } 2922 } 2923 2924 return 0; 2925 } 2926 2927 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2928 struct amdgpu_irq_src *source, 2929 struct amdgpu_iv_entry *entry) 2930 { 2931 int i, xcc_id; 2932 u8 me_id, pipe_id, queue_id; 2933 struct amdgpu_ring *ring; 2934 2935 DRM_DEBUG("IH: CP EOP\n"); 2936 me_id = (entry->ring_id & 0x0c) >> 2; 2937 pipe_id = (entry->ring_id & 0x03) >> 0; 2938 queue_id = (entry->ring_id & 0x70) >> 4; 2939 2940 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2941 2942 if (xcc_id == -EINVAL) 2943 return -EINVAL; 2944 2945 switch (me_id) { 2946 case 0: 2947 case 1: 2948 case 2: 2949 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2950 ring = &adev->gfx.compute_ring 2951 [i + 2952 xcc_id * adev->gfx.num_compute_rings]; 2953 /* Per-queue interrupt is supported for MEC starting from VI. 2954 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2955 */ 2956 2957 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2958 amdgpu_fence_process(ring); 2959 } 2960 break; 2961 } 2962 return 0; 2963 } 2964 2965 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2966 struct amdgpu_iv_entry *entry) 2967 { 2968 u8 me_id, pipe_id, queue_id; 2969 struct amdgpu_ring *ring; 2970 int i, xcc_id; 2971 2972 me_id = (entry->ring_id & 0x0c) >> 2; 2973 pipe_id = (entry->ring_id & 0x03) >> 0; 2974 queue_id = (entry->ring_id & 0x70) >> 4; 2975 2976 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2977 2978 if (xcc_id == -EINVAL) 2979 return; 2980 2981 switch (me_id) { 2982 case 0: 2983 case 1: 2984 case 2: 2985 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2986 ring = &adev->gfx.compute_ring 2987 [i + 2988 xcc_id * adev->gfx.num_compute_rings]; 2989 if (ring->me == me_id && ring->pipe == pipe_id && 2990 ring->queue == queue_id) 2991 drm_sched_fault(&ring->sched); 2992 } 2993 break; 2994 } 2995 } 2996 2997 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2998 struct amdgpu_irq_src *source, 2999 struct amdgpu_iv_entry *entry) 3000 { 3001 DRM_ERROR("Illegal register access in command stream\n"); 3002 gfx_v9_4_3_fault(adev, entry); 3003 return 0; 3004 } 3005 3006 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3007 struct amdgpu_irq_src *source, 3008 struct amdgpu_iv_entry *entry) 3009 { 3010 DRM_ERROR("Illegal instruction in command stream\n"); 3011 gfx_v9_4_3_fault(adev, entry); 3012 return 0; 3013 } 3014 3015 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3016 { 3017 const unsigned int cp_coher_cntl = 3018 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3019 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3020 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3021 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3022 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3023 3024 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3025 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3026 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3027 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3028 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3029 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3030 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3031 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3032 } 3033 3034 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3035 uint32_t pipe, bool enable) 3036 { 3037 struct amdgpu_device *adev = ring->adev; 3038 uint32_t val; 3039 uint32_t wcl_cs_reg; 3040 3041 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3042 val = enable ? 0x1 : 0x7f; 3043 3044 switch (pipe) { 3045 case 0: 3046 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3047 break; 3048 case 1: 3049 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3050 break; 3051 case 2: 3052 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3053 break; 3054 case 3: 3055 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3056 break; 3057 default: 3058 DRM_DEBUG("invalid pipe %d\n", pipe); 3059 return; 3060 } 3061 3062 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3063 3064 } 3065 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3066 { 3067 struct amdgpu_device *adev = ring->adev; 3068 uint32_t val; 3069 int i; 3070 3071 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3072 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3073 * around 25% of gpu resources. 3074 */ 3075 val = enable ? 0x1f : 0x07ffffff; 3076 amdgpu_ring_emit_wreg(ring, 3077 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3078 val); 3079 3080 /* Restrict waves for normal/low priority compute queues as well 3081 * to get best QoS for high priority compute jobs. 3082 * 3083 * amdgpu controls only 1st ME(0-3 CS pipes). 3084 */ 3085 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3086 if (i != ring->pipe) 3087 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3088 3089 } 3090 } 3091 3092 enum amdgpu_gfx_cp_ras_mem_id { 3093 AMDGPU_GFX_CP_MEM1 = 1, 3094 AMDGPU_GFX_CP_MEM2, 3095 AMDGPU_GFX_CP_MEM3, 3096 AMDGPU_GFX_CP_MEM4, 3097 AMDGPU_GFX_CP_MEM5, 3098 }; 3099 3100 enum amdgpu_gfx_gcea_ras_mem_id { 3101 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3102 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3103 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3104 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3105 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3106 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3107 AMDGPU_GFX_GCEA_MAM_DMEM0, 3108 AMDGPU_GFX_GCEA_MAM_DMEM1, 3109 AMDGPU_GFX_GCEA_MAM_DMEM2, 3110 AMDGPU_GFX_GCEA_MAM_DMEM3, 3111 AMDGPU_GFX_GCEA_MAM_AMEM0, 3112 AMDGPU_GFX_GCEA_MAM_AMEM1, 3113 AMDGPU_GFX_GCEA_MAM_AMEM2, 3114 AMDGPU_GFX_GCEA_MAM_AMEM3, 3115 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3116 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3117 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3118 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3119 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3120 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3121 }; 3122 3123 enum amdgpu_gfx_gc_cane_ras_mem_id { 3124 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3125 }; 3126 3127 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3128 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3129 }; 3130 3131 enum amdgpu_gfx_gds_ras_mem_id { 3132 AMDGPU_GFX_GDS_MEM0 = 0, 3133 }; 3134 3135 enum amdgpu_gfx_lds_ras_mem_id { 3136 AMDGPU_GFX_LDS_BANK0 = 0, 3137 AMDGPU_GFX_LDS_BANK1, 3138 AMDGPU_GFX_LDS_BANK2, 3139 AMDGPU_GFX_LDS_BANK3, 3140 AMDGPU_GFX_LDS_BANK4, 3141 AMDGPU_GFX_LDS_BANK5, 3142 AMDGPU_GFX_LDS_BANK6, 3143 AMDGPU_GFX_LDS_BANK7, 3144 AMDGPU_GFX_LDS_BANK8, 3145 AMDGPU_GFX_LDS_BANK9, 3146 AMDGPU_GFX_LDS_BANK10, 3147 AMDGPU_GFX_LDS_BANK11, 3148 AMDGPU_GFX_LDS_BANK12, 3149 AMDGPU_GFX_LDS_BANK13, 3150 AMDGPU_GFX_LDS_BANK14, 3151 AMDGPU_GFX_LDS_BANK15, 3152 AMDGPU_GFX_LDS_BANK16, 3153 AMDGPU_GFX_LDS_BANK17, 3154 AMDGPU_GFX_LDS_BANK18, 3155 AMDGPU_GFX_LDS_BANK19, 3156 AMDGPU_GFX_LDS_BANK20, 3157 AMDGPU_GFX_LDS_BANK21, 3158 AMDGPU_GFX_LDS_BANK22, 3159 AMDGPU_GFX_LDS_BANK23, 3160 AMDGPU_GFX_LDS_BANK24, 3161 AMDGPU_GFX_LDS_BANK25, 3162 AMDGPU_GFX_LDS_BANK26, 3163 AMDGPU_GFX_LDS_BANK27, 3164 AMDGPU_GFX_LDS_BANK28, 3165 AMDGPU_GFX_LDS_BANK29, 3166 AMDGPU_GFX_LDS_BANK30, 3167 AMDGPU_GFX_LDS_BANK31, 3168 AMDGPU_GFX_LDS_SP_BUFFER_A, 3169 AMDGPU_GFX_LDS_SP_BUFFER_B, 3170 }; 3171 3172 enum amdgpu_gfx_rlc_ras_mem_id { 3173 AMDGPU_GFX_RLC_GPMF32 = 1, 3174 AMDGPU_GFX_RLC_RLCVF32, 3175 AMDGPU_GFX_RLC_SCRATCH, 3176 AMDGPU_GFX_RLC_SRM_ARAM, 3177 AMDGPU_GFX_RLC_SRM_DRAM, 3178 AMDGPU_GFX_RLC_TCTAG, 3179 AMDGPU_GFX_RLC_SPM_SE, 3180 AMDGPU_GFX_RLC_SPM_GRBMT, 3181 }; 3182 3183 enum amdgpu_gfx_sp_ras_mem_id { 3184 AMDGPU_GFX_SP_SIMDID0 = 0, 3185 }; 3186 3187 enum amdgpu_gfx_spi_ras_mem_id { 3188 AMDGPU_GFX_SPI_MEM0 = 0, 3189 AMDGPU_GFX_SPI_MEM1, 3190 AMDGPU_GFX_SPI_MEM2, 3191 AMDGPU_GFX_SPI_MEM3, 3192 }; 3193 3194 enum amdgpu_gfx_sqc_ras_mem_id { 3195 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3196 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3197 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3198 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3199 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3200 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3201 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3202 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3203 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3204 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3205 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3206 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3207 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3208 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3209 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3210 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3211 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3212 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3213 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3214 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3215 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3216 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3217 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3218 }; 3219 3220 enum amdgpu_gfx_sq_ras_mem_id { 3221 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3222 AMDGPU_GFX_SQ_SGPR_MEM1, 3223 AMDGPU_GFX_SQ_SGPR_MEM2, 3224 AMDGPU_GFX_SQ_SGPR_MEM3, 3225 }; 3226 3227 enum amdgpu_gfx_ta_ras_mem_id { 3228 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3229 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3230 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3231 AMDGPU_GFX_TA_FSX_LFIFO, 3232 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3233 }; 3234 3235 enum amdgpu_gfx_tcc_ras_mem_id { 3236 AMDGPU_GFX_TCC_MEM1 = 1, 3237 }; 3238 3239 enum amdgpu_gfx_tca_ras_mem_id { 3240 AMDGPU_GFX_TCA_MEM1 = 1, 3241 }; 3242 3243 enum amdgpu_gfx_tci_ras_mem_id { 3244 AMDGPU_GFX_TCIW_MEM = 1, 3245 }; 3246 3247 enum amdgpu_gfx_tcp_ras_mem_id { 3248 AMDGPU_GFX_TCP_LFIFO0 = 1, 3249 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3250 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3251 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3252 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3253 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3254 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3255 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3256 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3257 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3258 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3259 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3260 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3261 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3262 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3263 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3264 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3265 AMDGPU_GFX_TCP_VM_FIFO, 3266 AMDGPU_GFX_TCP_DB_TAGRAM0, 3267 AMDGPU_GFX_TCP_DB_TAGRAM1, 3268 AMDGPU_GFX_TCP_DB_TAGRAM2, 3269 AMDGPU_GFX_TCP_DB_TAGRAM3, 3270 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3271 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3272 AMDGPU_GFX_TCP_CMD_FIFO, 3273 }; 3274 3275 enum amdgpu_gfx_td_ras_mem_id { 3276 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3277 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3278 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3279 }; 3280 3281 enum amdgpu_gfx_tcx_ras_mem_id { 3282 AMDGPU_GFX_TCX_FIFOD0 = 0, 3283 AMDGPU_GFX_TCX_FIFOD1, 3284 AMDGPU_GFX_TCX_FIFOD2, 3285 AMDGPU_GFX_TCX_FIFOD3, 3286 AMDGPU_GFX_TCX_FIFOD4, 3287 AMDGPU_GFX_TCX_FIFOD5, 3288 AMDGPU_GFX_TCX_FIFOD6, 3289 AMDGPU_GFX_TCX_FIFOD7, 3290 AMDGPU_GFX_TCX_FIFOB0, 3291 AMDGPU_GFX_TCX_FIFOB1, 3292 AMDGPU_GFX_TCX_FIFOB2, 3293 AMDGPU_GFX_TCX_FIFOB3, 3294 AMDGPU_GFX_TCX_FIFOB4, 3295 AMDGPU_GFX_TCX_FIFOB5, 3296 AMDGPU_GFX_TCX_FIFOB6, 3297 AMDGPU_GFX_TCX_FIFOB7, 3298 AMDGPU_GFX_TCX_FIFOA0, 3299 AMDGPU_GFX_TCX_FIFOA1, 3300 AMDGPU_GFX_TCX_FIFOA2, 3301 AMDGPU_GFX_TCX_FIFOA3, 3302 AMDGPU_GFX_TCX_FIFOA4, 3303 AMDGPU_GFX_TCX_FIFOA5, 3304 AMDGPU_GFX_TCX_FIFOA6, 3305 AMDGPU_GFX_TCX_FIFOA7, 3306 AMDGPU_GFX_TCX_CFIFO0, 3307 AMDGPU_GFX_TCX_CFIFO1, 3308 AMDGPU_GFX_TCX_CFIFO2, 3309 AMDGPU_GFX_TCX_CFIFO3, 3310 AMDGPU_GFX_TCX_CFIFO4, 3311 AMDGPU_GFX_TCX_CFIFO5, 3312 AMDGPU_GFX_TCX_CFIFO6, 3313 AMDGPU_GFX_TCX_CFIFO7, 3314 AMDGPU_GFX_TCX_FIFO_ACKB0, 3315 AMDGPU_GFX_TCX_FIFO_ACKB1, 3316 AMDGPU_GFX_TCX_FIFO_ACKB2, 3317 AMDGPU_GFX_TCX_FIFO_ACKB3, 3318 AMDGPU_GFX_TCX_FIFO_ACKB4, 3319 AMDGPU_GFX_TCX_FIFO_ACKB5, 3320 AMDGPU_GFX_TCX_FIFO_ACKB6, 3321 AMDGPU_GFX_TCX_FIFO_ACKB7, 3322 AMDGPU_GFX_TCX_FIFO_ACKD0, 3323 AMDGPU_GFX_TCX_FIFO_ACKD1, 3324 AMDGPU_GFX_TCX_FIFO_ACKD2, 3325 AMDGPU_GFX_TCX_FIFO_ACKD3, 3326 AMDGPU_GFX_TCX_FIFO_ACKD4, 3327 AMDGPU_GFX_TCX_FIFO_ACKD5, 3328 AMDGPU_GFX_TCX_FIFO_ACKD6, 3329 AMDGPU_GFX_TCX_FIFO_ACKD7, 3330 AMDGPU_GFX_TCX_DST_FIFOA0, 3331 AMDGPU_GFX_TCX_DST_FIFOA1, 3332 AMDGPU_GFX_TCX_DST_FIFOA2, 3333 AMDGPU_GFX_TCX_DST_FIFOA3, 3334 AMDGPU_GFX_TCX_DST_FIFOA4, 3335 AMDGPU_GFX_TCX_DST_FIFOA5, 3336 AMDGPU_GFX_TCX_DST_FIFOA6, 3337 AMDGPU_GFX_TCX_DST_FIFOA7, 3338 AMDGPU_GFX_TCX_DST_FIFOB0, 3339 AMDGPU_GFX_TCX_DST_FIFOB1, 3340 AMDGPU_GFX_TCX_DST_FIFOB2, 3341 AMDGPU_GFX_TCX_DST_FIFOB3, 3342 AMDGPU_GFX_TCX_DST_FIFOB4, 3343 AMDGPU_GFX_TCX_DST_FIFOB5, 3344 AMDGPU_GFX_TCX_DST_FIFOB6, 3345 AMDGPU_GFX_TCX_DST_FIFOB7, 3346 AMDGPU_GFX_TCX_DST_FIFOD0, 3347 AMDGPU_GFX_TCX_DST_FIFOD1, 3348 AMDGPU_GFX_TCX_DST_FIFOD2, 3349 AMDGPU_GFX_TCX_DST_FIFOD3, 3350 AMDGPU_GFX_TCX_DST_FIFOD4, 3351 AMDGPU_GFX_TCX_DST_FIFOD5, 3352 AMDGPU_GFX_TCX_DST_FIFOD6, 3353 AMDGPU_GFX_TCX_DST_FIFOD7, 3354 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3355 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3356 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3357 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3358 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3359 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3360 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3361 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3362 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3363 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3364 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3365 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3366 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3367 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3368 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3369 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3370 }; 3371 3372 enum amdgpu_gfx_atc_l2_ras_mem_id { 3373 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3374 }; 3375 3376 enum amdgpu_gfx_utcl2_ras_mem_id { 3377 AMDGPU_GFX_UTCL2_MEM0 = 0, 3378 }; 3379 3380 enum amdgpu_gfx_vml2_ras_mem_id { 3381 AMDGPU_GFX_VML2_MEM0 = 0, 3382 }; 3383 3384 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3385 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3386 }; 3387 3388 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3389 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3390 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3391 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3392 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3393 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3394 }; 3395 3396 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3397 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3398 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3399 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3400 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3401 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3402 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3403 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3404 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3405 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3406 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3407 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3408 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3409 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3410 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3411 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3412 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3413 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3414 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3415 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3416 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3417 }; 3418 3419 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3420 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3421 }; 3422 3423 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3424 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3425 }; 3426 3427 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3428 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3429 }; 3430 3431 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3432 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3433 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3434 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3435 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3436 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3437 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3438 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3439 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3440 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3441 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3442 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3443 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3444 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3445 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3446 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3447 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3448 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3449 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3450 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3451 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3452 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3453 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3454 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3455 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3456 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3457 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3458 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3459 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3460 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3461 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3462 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3463 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3464 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3465 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3466 }; 3467 3468 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3469 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3470 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3471 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3472 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3473 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3474 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3475 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3476 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3477 }; 3478 3479 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3480 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3481 }; 3482 3483 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3484 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3485 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3486 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3487 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3488 }; 3489 3490 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3491 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3492 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3493 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3494 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3495 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3496 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3497 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3498 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3499 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3500 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3501 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3502 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3503 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3504 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3505 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3506 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3507 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3508 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3509 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3510 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3511 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3512 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3513 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3514 }; 3515 3516 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3517 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3518 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3519 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3520 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3521 }; 3522 3523 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3524 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3525 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3526 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3527 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3528 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3529 }; 3530 3531 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3532 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3533 }; 3534 3535 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3536 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3537 }; 3538 3539 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3540 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3541 }; 3542 3543 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3544 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3545 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3546 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3547 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3548 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3549 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3550 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3551 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3552 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3553 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3554 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3555 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3556 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3557 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3558 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3559 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3560 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3561 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3562 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3563 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3564 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3565 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3566 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3567 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3568 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3569 }; 3570 3571 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3572 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3573 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3574 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3575 }; 3576 3577 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3578 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3579 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3580 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3581 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3582 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3583 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3584 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3585 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3586 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3587 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3588 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3589 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3590 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3591 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3592 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3593 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3594 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3595 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3596 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3597 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3598 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3599 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3600 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3601 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3602 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3603 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3604 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3605 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3606 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3607 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3608 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3609 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3610 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3611 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3612 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3613 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3614 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3615 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3616 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3617 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3618 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3619 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3620 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3621 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3622 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3623 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3624 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3625 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3626 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3627 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3628 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3629 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3630 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3631 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3632 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3633 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3634 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3635 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3636 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3637 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3638 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3639 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3640 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3641 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3642 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3643 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3644 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3645 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3646 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3647 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3648 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3649 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3650 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3651 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3652 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3653 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3654 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3655 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3656 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3657 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3658 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3659 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3660 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3661 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3662 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3663 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3664 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3665 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3666 }; 3667 3668 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3669 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3670 }; 3671 3672 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3673 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3674 }; 3675 3676 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3677 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3678 }; 3679 3680 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3681 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3682 }; 3683 3684 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3685 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3686 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3687 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3688 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3689 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3690 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3691 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3692 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3693 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3694 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3695 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3696 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3697 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3698 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3699 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3700 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3701 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3702 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3703 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3704 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3705 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3706 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3707 }; 3708 3709 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3710 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3711 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3712 AMDGPU_GFX_RLC_MEM, 1}, 3713 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3714 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3715 AMDGPU_GFX_CP_MEM, 1}, 3716 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3717 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3718 AMDGPU_GFX_CP_MEM, 1}, 3719 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3720 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3721 AMDGPU_GFX_CP_MEM, 1}, 3722 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3723 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3724 AMDGPU_GFX_GDS_MEM, 1}, 3725 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3726 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3727 AMDGPU_GFX_GC_CANE_MEM, 1}, 3728 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3729 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3730 AMDGPU_GFX_SPI_MEM, 1}, 3731 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3732 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3733 AMDGPU_GFX_SP_MEM, 4}, 3734 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3735 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3736 AMDGPU_GFX_SP_MEM, 4}, 3737 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3738 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3739 AMDGPU_GFX_SQ_MEM, 4}, 3740 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3741 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3742 AMDGPU_GFX_SQC_MEM, 4}, 3743 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3744 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3745 AMDGPU_GFX_TCX_MEM, 1}, 3746 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3747 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3748 AMDGPU_GFX_TCC_MEM, 1}, 3749 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3750 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3751 AMDGPU_GFX_TA_MEM, 4}, 3752 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3753 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3754 AMDGPU_GFX_TCI_MEM, 1}, 3755 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3756 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3757 AMDGPU_GFX_TCP_MEM, 4}, 3758 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3759 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3760 AMDGPU_GFX_TD_MEM, 4}, 3761 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3762 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3763 AMDGPU_GFX_GCEA_MEM, 1}, 3764 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3765 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3766 AMDGPU_GFX_LDS_MEM, 4}, 3767 }; 3768 3769 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3770 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3771 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3772 AMDGPU_GFX_RLC_MEM, 1}, 3773 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3774 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3775 AMDGPU_GFX_CP_MEM, 1}, 3776 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3777 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3778 AMDGPU_GFX_CP_MEM, 1}, 3779 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3780 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3781 AMDGPU_GFX_CP_MEM, 1}, 3782 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3783 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3784 AMDGPU_GFX_GDS_MEM, 1}, 3785 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3786 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3787 AMDGPU_GFX_GC_CANE_MEM, 1}, 3788 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3789 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3790 AMDGPU_GFX_SPI_MEM, 1}, 3791 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3792 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3793 AMDGPU_GFX_SP_MEM, 4}, 3794 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3795 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3796 AMDGPU_GFX_SP_MEM, 4}, 3797 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3798 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3799 AMDGPU_GFX_SQ_MEM, 4}, 3800 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3801 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3802 AMDGPU_GFX_SQC_MEM, 4}, 3803 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3804 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3805 AMDGPU_GFX_TCX_MEM, 1}, 3806 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3807 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3808 AMDGPU_GFX_TCC_MEM, 1}, 3809 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3810 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3811 AMDGPU_GFX_TA_MEM, 4}, 3812 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3813 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3814 AMDGPU_GFX_TCI_MEM, 1}, 3815 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3816 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3817 AMDGPU_GFX_TCP_MEM, 4}, 3818 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3819 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3820 AMDGPU_GFX_TD_MEM, 4}, 3821 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3822 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3823 AMDGPU_GFX_TCA_MEM, 1}, 3824 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3825 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3826 AMDGPU_GFX_GCEA_MEM, 1}, 3827 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3828 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3829 AMDGPU_GFX_LDS_MEM, 4}, 3830 }; 3831 3832 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3833 void *ras_error_status, int xcc_id) 3834 { 3835 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3836 unsigned long ce_count = 0, ue_count = 0; 3837 uint32_t i, j, k; 3838 3839 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 3840 struct amdgpu_smuio_mcm_config_info mcm_info = { 3841 .socket_id = adev->smuio.funcs->get_socket_id(adev), 3842 .die_id = xcc_id & 0x01 ? 1 : 0, 3843 }; 3844 3845 mutex_lock(&adev->grbm_idx_mutex); 3846 3847 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3848 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3849 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3850 /* no need to select if instance number is 1 */ 3851 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3852 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3853 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3854 3855 amdgpu_ras_inst_query_ras_error_count(adev, 3856 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3857 1, 3858 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3859 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3860 GET_INST(GC, xcc_id), 3861 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3862 &ce_count); 3863 3864 amdgpu_ras_inst_query_ras_error_count(adev, 3865 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3866 1, 3867 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3868 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3869 GET_INST(GC, xcc_id), 3870 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3871 &ue_count); 3872 } 3873 } 3874 } 3875 3876 /* handle extra register entries of UE */ 3877 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3878 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3879 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3880 /* no need to select if instance number is 1 */ 3881 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3882 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3883 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3884 3885 amdgpu_ras_inst_query_ras_error_count(adev, 3886 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3887 1, 3888 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3889 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3890 GET_INST(GC, xcc_id), 3891 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3892 &ue_count); 3893 } 3894 } 3895 } 3896 3897 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3898 xcc_id); 3899 mutex_unlock(&adev->grbm_idx_mutex); 3900 3901 /* the caller should make sure initialize value of 3902 * err_data->ue_count and err_data->ce_count 3903 */ 3904 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count); 3905 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, ce_count); 3906 } 3907 3908 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3909 void *ras_error_status, int xcc_id) 3910 { 3911 uint32_t i, j, k; 3912 3913 mutex_lock(&adev->grbm_idx_mutex); 3914 3915 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3916 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3917 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3918 /* no need to select if instance number is 1 */ 3919 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3920 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3921 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3922 3923 amdgpu_ras_inst_reset_ras_error_count(adev, 3924 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3925 1, 3926 GET_INST(GC, xcc_id)); 3927 3928 amdgpu_ras_inst_reset_ras_error_count(adev, 3929 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3930 1, 3931 GET_INST(GC, xcc_id)); 3932 } 3933 } 3934 } 3935 3936 /* handle extra register entries of UE */ 3937 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3938 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3939 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3940 /* no need to select if instance number is 1 */ 3941 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3942 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3943 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3944 3945 amdgpu_ras_inst_reset_ras_error_count(adev, 3946 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3947 1, 3948 GET_INST(GC, xcc_id)); 3949 } 3950 } 3951 } 3952 3953 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3954 xcc_id); 3955 mutex_unlock(&adev->grbm_idx_mutex); 3956 } 3957 3958 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 3959 void *ras_error_status, int xcc_id) 3960 { 3961 uint32_t i; 3962 uint32_t data; 3963 3964 if (amdgpu_sriov_vf(adev)) 3965 return; 3966 3967 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 3968 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 3969 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 3970 3971 if (amdgpu_watchdog_timer.timeout_fatal_disable && 3972 (amdgpu_watchdog_timer.period < 1 || 3973 amdgpu_watchdog_timer.period > 0x23)) { 3974 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 3975 amdgpu_watchdog_timer.period = 0x23; 3976 } 3977 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 3978 amdgpu_watchdog_timer.period); 3979 3980 mutex_lock(&adev->grbm_idx_mutex); 3981 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3982 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 3983 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 3984 } 3985 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3986 xcc_id); 3987 mutex_unlock(&adev->grbm_idx_mutex); 3988 } 3989 3990 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 3991 void *ras_error_status) 3992 { 3993 amdgpu_gfx_ras_error_func(adev, ras_error_status, 3994 gfx_v9_4_3_inst_query_ras_err_count); 3995 } 3996 3997 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 3998 { 3999 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4000 } 4001 4002 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4003 { 4004 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4005 } 4006 4007 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4008 .name = "gfx_v9_4_3", 4009 .early_init = gfx_v9_4_3_early_init, 4010 .late_init = gfx_v9_4_3_late_init, 4011 .sw_init = gfx_v9_4_3_sw_init, 4012 .sw_fini = gfx_v9_4_3_sw_fini, 4013 .hw_init = gfx_v9_4_3_hw_init, 4014 .hw_fini = gfx_v9_4_3_hw_fini, 4015 .suspend = gfx_v9_4_3_suspend, 4016 .resume = gfx_v9_4_3_resume, 4017 .is_idle = gfx_v9_4_3_is_idle, 4018 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4019 .soft_reset = gfx_v9_4_3_soft_reset, 4020 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4021 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4022 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4023 .dump_ip_state = NULL, 4024 .print_ip_state = NULL, 4025 }; 4026 4027 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4028 .type = AMDGPU_RING_TYPE_COMPUTE, 4029 .align_mask = 0xff, 4030 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4031 .support_64bit_ptrs = true, 4032 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4033 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4034 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4035 .emit_frame_size = 4036 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4037 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4038 5 + /* hdp invalidate */ 4039 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4040 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4041 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4042 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4043 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4044 7 + /* gfx_v9_4_3_emit_mem_sync */ 4045 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4046 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4047 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4048 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4049 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4050 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4051 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4052 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4053 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4054 .test_ring = gfx_v9_4_3_ring_test_ring, 4055 .test_ib = gfx_v9_4_3_ring_test_ib, 4056 .insert_nop = amdgpu_ring_insert_nop, 4057 .pad_ib = amdgpu_ring_generic_pad_ib, 4058 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4059 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4060 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4061 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4062 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4063 }; 4064 4065 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4066 .type = AMDGPU_RING_TYPE_KIQ, 4067 .align_mask = 0xff, 4068 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4069 .support_64bit_ptrs = true, 4070 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4071 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4072 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4073 .emit_frame_size = 4074 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4075 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4076 5 + /* hdp invalidate */ 4077 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4078 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4079 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4080 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4081 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4082 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4083 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4084 .test_ring = gfx_v9_4_3_ring_test_ring, 4085 .insert_nop = amdgpu_ring_insert_nop, 4086 .pad_ib = amdgpu_ring_generic_pad_ib, 4087 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4088 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4089 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4090 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4091 }; 4092 4093 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4094 { 4095 int i, j, num_xcc; 4096 4097 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4098 for (i = 0; i < num_xcc; i++) { 4099 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4100 4101 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4102 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4103 = &gfx_v9_4_3_ring_funcs_compute; 4104 } 4105 } 4106 4107 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4108 .set = gfx_v9_4_3_set_eop_interrupt_state, 4109 .process = gfx_v9_4_3_eop_irq, 4110 }; 4111 4112 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4113 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4114 .process = gfx_v9_4_3_priv_reg_irq, 4115 }; 4116 4117 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4118 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4119 .process = gfx_v9_4_3_priv_inst_irq, 4120 }; 4121 4122 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4123 { 4124 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4125 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4126 4127 adev->gfx.priv_reg_irq.num_types = 1; 4128 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4129 4130 adev->gfx.priv_inst_irq.num_types = 1; 4131 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4132 } 4133 4134 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4135 { 4136 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4137 } 4138 4139 4140 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4141 { 4142 /* init asci gds info */ 4143 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4144 case IP_VERSION(9, 4, 3): 4145 case IP_VERSION(9, 4, 4): 4146 /* 9.4.3 removed all the GDS internal memory, 4147 * only support GWS opcode in kernel, like barrier 4148 * semaphore.etc */ 4149 adev->gds.gds_size = 0; 4150 break; 4151 default: 4152 adev->gds.gds_size = 0x10000; 4153 break; 4154 } 4155 4156 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4157 case IP_VERSION(9, 4, 3): 4158 case IP_VERSION(9, 4, 4): 4159 /* deprecated for 9.4.3, no usage at all */ 4160 adev->gds.gds_compute_max_wave_id = 0; 4161 break; 4162 default: 4163 /* this really depends on the chip */ 4164 adev->gds.gds_compute_max_wave_id = 0x7ff; 4165 break; 4166 } 4167 4168 adev->gds.gws_size = 64; 4169 adev->gds.oa_size = 16; 4170 } 4171 4172 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4173 u32 bitmap, int xcc_id) 4174 { 4175 u32 data; 4176 4177 if (!bitmap) 4178 return; 4179 4180 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4181 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4182 4183 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4184 } 4185 4186 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4187 { 4188 u32 data, mask; 4189 4190 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4191 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4192 4193 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4194 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4195 4196 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4197 4198 return (~data) & mask; 4199 } 4200 4201 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4202 struct amdgpu_cu_info *cu_info) 4203 { 4204 int i, j, k, counter, xcc_id, active_cu_number = 0; 4205 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4206 unsigned disable_masks[4 * 4]; 4207 4208 if (!adev || !cu_info) 4209 return -EINVAL; 4210 4211 /* 4212 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4213 */ 4214 if (adev->gfx.config.max_shader_engines * 4215 adev->gfx.config.max_sh_per_se > 16) 4216 return -EINVAL; 4217 4218 amdgpu_gfx_parse_disable_cu(disable_masks, 4219 adev->gfx.config.max_shader_engines, 4220 adev->gfx.config.max_sh_per_se); 4221 4222 mutex_lock(&adev->grbm_idx_mutex); 4223 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4224 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4225 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4226 mask = 1; 4227 ao_bitmap = 0; 4228 counter = 0; 4229 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4230 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4231 adev, 4232 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4233 xcc_id); 4234 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4235 4236 cu_info->bitmap[xcc_id][i][j] = bitmap; 4237 4238 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4239 if (bitmap & mask) { 4240 if (counter < adev->gfx.config.max_cu_per_sh) 4241 ao_bitmap |= mask; 4242 counter++; 4243 } 4244 mask <<= 1; 4245 } 4246 active_cu_number += counter; 4247 if (i < 2 && j < 2) 4248 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4249 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4250 } 4251 } 4252 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4253 xcc_id); 4254 } 4255 mutex_unlock(&adev->grbm_idx_mutex); 4256 4257 cu_info->number = active_cu_number; 4258 cu_info->ao_cu_mask = ao_cu_mask; 4259 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4260 4261 return 0; 4262 } 4263 4264 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4265 .type = AMD_IP_BLOCK_TYPE_GFX, 4266 .major = 9, 4267 .minor = 4, 4268 .rev = 3, 4269 .funcs = &gfx_v9_4_3_ip_funcs, 4270 }; 4271 4272 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4273 { 4274 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4275 uint32_t tmp_mask; 4276 int i, r; 4277 4278 /* TODO : Initialize golden regs */ 4279 /* gfx_v9_4_3_init_golden_registers(adev); */ 4280 4281 tmp_mask = inst_mask; 4282 for_each_inst(i, tmp_mask) 4283 gfx_v9_4_3_xcc_constants_init(adev, i); 4284 4285 if (!amdgpu_sriov_vf(adev)) { 4286 tmp_mask = inst_mask; 4287 for_each_inst(i, tmp_mask) { 4288 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4289 if (r) 4290 return r; 4291 } 4292 } 4293 4294 tmp_mask = inst_mask; 4295 for_each_inst(i, tmp_mask) { 4296 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4297 if (r) 4298 return r; 4299 } 4300 4301 return 0; 4302 } 4303 4304 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4305 { 4306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4307 int i; 4308 4309 for_each_inst(i, inst_mask) 4310 gfx_v9_4_3_xcc_fini(adev, i); 4311 4312 return 0; 4313 } 4314 4315 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4316 .suspend = &gfx_v9_4_3_xcp_suspend, 4317 .resume = &gfx_v9_4_3_xcp_resume 4318 }; 4319 4320 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4321 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4322 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4323 }; 4324 4325 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 4326 { 4327 int r; 4328 4329 r = amdgpu_ras_block_late_init(adev, ras_block); 4330 if (r) 4331 return r; 4332 4333 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 4334 &gfx_v9_4_3_aca_info, 4335 NULL); 4336 if (r) 4337 goto late_fini; 4338 4339 return 0; 4340 4341 late_fini: 4342 amdgpu_ras_block_late_fini(adev, ras_block); 4343 4344 return r; 4345 } 4346 4347 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4348 .ras_block = { 4349 .hw_ops = &gfx_v9_4_3_ras_ops, 4350 .ras_late_init = &gfx_v9_4_3_ras_late_init, 4351 }, 4352 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4353 }; 4354