1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 42 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 44 45 #define GFX9_MEC_HPD_SIZE 4096 46 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 47 48 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 49 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 50 51 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 52 53 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 54 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 55 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 56 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 57 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 58 struct amdgpu_cu_info *cu_info); 59 60 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 61 uint64_t queue_mask) 62 { 63 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 64 amdgpu_ring_write(kiq_ring, 65 PACKET3_SET_RESOURCES_VMID_MASK(0) | 66 /* vmid_mask:0* queue_type:0 (KIQ) */ 67 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 68 amdgpu_ring_write(kiq_ring, 69 lower_32_bits(queue_mask)); /* queue mask lo */ 70 amdgpu_ring_write(kiq_ring, 71 upper_32_bits(queue_mask)); /* queue mask hi */ 72 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 73 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 74 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 75 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 76 } 77 78 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 79 struct amdgpu_ring *ring) 80 { 81 struct amdgpu_device *adev = kiq_ring->adev; 82 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 83 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 84 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 85 86 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 87 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 88 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 89 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 90 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 91 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 92 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 93 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 94 /*queue_type: normal compute queue */ 95 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 96 /* alloc format: all_on_one_pipe */ 97 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 98 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 99 /* num_queues: must be 1 */ 100 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 101 amdgpu_ring_write(kiq_ring, 102 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 103 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 104 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 105 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 106 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 107 } 108 109 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 110 struct amdgpu_ring *ring, 111 enum amdgpu_unmap_queues_action action, 112 u64 gpu_addr, u64 seq) 113 { 114 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 115 116 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 117 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 118 PACKET3_UNMAP_QUEUES_ACTION(action) | 119 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 120 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 121 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 122 amdgpu_ring_write(kiq_ring, 123 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 124 125 if (action == PREEMPT_QUEUES_NO_UNMAP) { 126 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 127 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 128 amdgpu_ring_write(kiq_ring, seq); 129 } else { 130 amdgpu_ring_write(kiq_ring, 0); 131 amdgpu_ring_write(kiq_ring, 0); 132 amdgpu_ring_write(kiq_ring, 0); 133 } 134 } 135 136 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 137 struct amdgpu_ring *ring, 138 u64 addr, 139 u64 seq) 140 { 141 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 142 143 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 144 amdgpu_ring_write(kiq_ring, 145 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 146 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 147 PACKET3_QUERY_STATUS_COMMAND(2)); 148 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 149 amdgpu_ring_write(kiq_ring, 150 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 151 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 152 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 153 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 154 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 155 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 156 } 157 158 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 159 uint16_t pasid, uint32_t flush_type, 160 bool all_hub) 161 { 162 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 163 amdgpu_ring_write(kiq_ring, 164 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 165 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 166 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 167 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 168 } 169 170 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 171 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 172 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 173 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 174 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 175 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 176 .set_resources_size = 8, 177 .map_queues_size = 7, 178 .unmap_queues_size = 6, 179 .query_status_size = 7, 180 .invalidate_tlbs_size = 2, 181 }; 182 183 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 184 { 185 int i, num_xcc; 186 187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 188 for (i = 0; i < num_xcc; i++) 189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 190 } 191 192 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 193 { 194 int i, num_xcc, dev_inst; 195 196 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 197 for (i = 0; i < num_xcc; i++) { 198 dev_inst = GET_INST(GC, i); 199 200 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 201 GOLDEN_GB_ADDR_CONFIG); 202 /* Golden settings applied by driver for ASIC with rev_id 0 */ 203 if (adev->rev_id == 0) { 204 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 205 REDUCE_FIFO_DEPTH_BY_2, 2); 206 } else { 207 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 208 SPARE, 0x1); 209 } 210 } 211 } 212 213 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 214 bool wc, uint32_t reg, uint32_t val) 215 { 216 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 217 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 218 WRITE_DATA_DST_SEL(0) | 219 (wc ? WR_CONFIRM : 0)); 220 amdgpu_ring_write(ring, reg); 221 amdgpu_ring_write(ring, 0); 222 amdgpu_ring_write(ring, val); 223 } 224 225 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 226 int mem_space, int opt, uint32_t addr0, 227 uint32_t addr1, uint32_t ref, uint32_t mask, 228 uint32_t inv) 229 { 230 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 231 amdgpu_ring_write(ring, 232 /* memory (1) or register (0) */ 233 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 234 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 235 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 236 WAIT_REG_MEM_ENGINE(eng_sel))); 237 238 if (mem_space) 239 BUG_ON(addr0 & 0x3); /* Dword align */ 240 amdgpu_ring_write(ring, addr0); 241 amdgpu_ring_write(ring, addr1); 242 amdgpu_ring_write(ring, ref); 243 amdgpu_ring_write(ring, mask); 244 amdgpu_ring_write(ring, inv); /* poll interval */ 245 } 246 247 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 248 { 249 uint32_t scratch_reg0_offset, xcc_offset; 250 struct amdgpu_device *adev = ring->adev; 251 uint32_t tmp = 0; 252 unsigned i; 253 int r; 254 255 /* Use register offset which is local to XCC in the packet */ 256 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 257 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 258 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 259 260 r = amdgpu_ring_alloc(ring, 3); 261 if (r) 262 return r; 263 264 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 265 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 266 amdgpu_ring_write(ring, 0xDEADBEEF); 267 amdgpu_ring_commit(ring); 268 269 for (i = 0; i < adev->usec_timeout; i++) { 270 tmp = RREG32(scratch_reg0_offset); 271 if (tmp == 0xDEADBEEF) 272 break; 273 udelay(1); 274 } 275 276 if (i >= adev->usec_timeout) 277 r = -ETIMEDOUT; 278 return r; 279 } 280 281 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 282 { 283 struct amdgpu_device *adev = ring->adev; 284 struct amdgpu_ib ib; 285 struct dma_fence *f = NULL; 286 287 unsigned index; 288 uint64_t gpu_addr; 289 uint32_t tmp; 290 long r; 291 292 r = amdgpu_device_wb_get(adev, &index); 293 if (r) 294 return r; 295 296 gpu_addr = adev->wb.gpu_addr + (index * 4); 297 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 298 memset(&ib, 0, sizeof(ib)); 299 r = amdgpu_ib_get(adev, NULL, 16, 300 AMDGPU_IB_POOL_DIRECT, &ib); 301 if (r) 302 goto err1; 303 304 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 305 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 306 ib.ptr[2] = lower_32_bits(gpu_addr); 307 ib.ptr[3] = upper_32_bits(gpu_addr); 308 ib.ptr[4] = 0xDEADBEEF; 309 ib.length_dw = 5; 310 311 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 312 if (r) 313 goto err2; 314 315 r = dma_fence_wait_timeout(f, false, timeout); 316 if (r == 0) { 317 r = -ETIMEDOUT; 318 goto err2; 319 } else if (r < 0) { 320 goto err2; 321 } 322 323 tmp = adev->wb.wb[index]; 324 if (tmp == 0xDEADBEEF) 325 r = 0; 326 else 327 r = -EINVAL; 328 329 err2: 330 amdgpu_ib_free(adev, &ib, NULL); 331 dma_fence_put(f); 332 err1: 333 amdgpu_device_wb_free(adev, index); 334 return r; 335 } 336 337 338 /* This value might differs per partition */ 339 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 340 { 341 uint64_t clock; 342 343 mutex_lock(&adev->gfx.gpu_clock_mutex); 344 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 345 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 346 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 347 mutex_unlock(&adev->gfx.gpu_clock_mutex); 348 349 return clock; 350 } 351 352 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 353 { 354 amdgpu_ucode_release(&adev->gfx.pfp_fw); 355 amdgpu_ucode_release(&adev->gfx.me_fw); 356 amdgpu_ucode_release(&adev->gfx.ce_fw); 357 amdgpu_ucode_release(&adev->gfx.rlc_fw); 358 amdgpu_ucode_release(&adev->gfx.mec_fw); 359 amdgpu_ucode_release(&adev->gfx.mec2_fw); 360 361 kfree(adev->gfx.rlc.register_list_format); 362 } 363 364 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 365 const char *chip_name) 366 { 367 char fw_name[30]; 368 int err; 369 const struct rlc_firmware_header_v2_0 *rlc_hdr; 370 uint16_t version_major; 371 uint16_t version_minor; 372 373 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 374 375 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 376 if (err) 377 goto out; 378 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 379 380 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 381 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 382 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 383 out: 384 if (err) 385 amdgpu_ucode_release(&adev->gfx.rlc_fw); 386 387 return err; 388 } 389 390 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 391 { 392 return true; 393 } 394 395 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 396 { 397 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 398 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 399 } 400 401 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 402 const char *chip_name) 403 { 404 char fw_name[30]; 405 int err; 406 407 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 408 409 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 410 if (err) 411 goto out; 412 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 413 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 414 415 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 416 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 417 418 gfx_v9_4_3_check_if_need_gfxoff(adev); 419 420 out: 421 if (err) 422 amdgpu_ucode_release(&adev->gfx.mec_fw); 423 return err; 424 } 425 426 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 427 { 428 const char *chip_name; 429 int r; 430 431 chip_name = "gc_9_4_3"; 432 433 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 434 if (r) 435 return r; 436 437 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 438 if (r) 439 return r; 440 441 return r; 442 } 443 444 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 445 { 446 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 447 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 448 } 449 450 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 451 { 452 int r, i, num_xcc; 453 u32 *hpd; 454 const __le32 *fw_data; 455 unsigned fw_size; 456 u32 *fw; 457 size_t mec_hpd_size; 458 459 const struct gfx_firmware_header_v1_0 *mec_hdr; 460 461 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 462 for (i = 0; i < num_xcc; i++) 463 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 464 AMDGPU_MAX_COMPUTE_QUEUES); 465 466 /* take ownership of the relevant compute queues */ 467 amdgpu_gfx_compute_queue_acquire(adev); 468 mec_hpd_size = 469 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 470 if (mec_hpd_size) { 471 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 472 AMDGPU_GEM_DOMAIN_VRAM | 473 AMDGPU_GEM_DOMAIN_GTT, 474 &adev->gfx.mec.hpd_eop_obj, 475 &adev->gfx.mec.hpd_eop_gpu_addr, 476 (void **)&hpd); 477 if (r) { 478 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 479 gfx_v9_4_3_mec_fini(adev); 480 return r; 481 } 482 483 if (amdgpu_emu_mode == 1) { 484 for (i = 0; i < mec_hpd_size / 4; i++) { 485 memset((void *)(hpd + i), 0, 4); 486 if (i % 50 == 0) 487 msleep(1); 488 } 489 } else { 490 memset(hpd, 0, mec_hpd_size); 491 } 492 493 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 494 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 495 } 496 497 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 498 499 fw_data = (const __le32 *) 500 (adev->gfx.mec_fw->data + 501 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 502 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 503 504 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 505 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 506 &adev->gfx.mec.mec_fw_obj, 507 &adev->gfx.mec.mec_fw_gpu_addr, 508 (void **)&fw); 509 if (r) { 510 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 511 gfx_v9_4_3_mec_fini(adev); 512 return r; 513 } 514 515 memcpy(fw, fw_data, fw_size); 516 517 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 518 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 519 520 return 0; 521 } 522 523 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 524 u32 sh_num, u32 instance, int xcc_id) 525 { 526 u32 data; 527 528 if (instance == 0xffffffff) 529 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 530 INSTANCE_BROADCAST_WRITES, 1); 531 else 532 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 533 INSTANCE_INDEX, instance); 534 535 if (se_num == 0xffffffff) 536 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 537 SE_BROADCAST_WRITES, 1); 538 else 539 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 540 541 if (sh_num == 0xffffffff) 542 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 543 SH_BROADCAST_WRITES, 1); 544 else 545 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 546 547 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 548 } 549 550 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 551 { 552 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 553 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 554 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 555 (address << SQ_IND_INDEX__INDEX__SHIFT) | 556 (SQ_IND_INDEX__FORCE_READ_MASK)); 557 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 558 } 559 560 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 561 uint32_t wave, uint32_t thread, 562 uint32_t regno, uint32_t num, uint32_t *out) 563 { 564 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 565 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 566 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 567 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 568 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 569 (SQ_IND_INDEX__FORCE_READ_MASK) | 570 (SQ_IND_INDEX__AUTO_INCR_MASK)); 571 while (num--) 572 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 573 } 574 575 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 576 uint32_t xcc_id, uint32_t simd, uint32_t wave, 577 uint32_t *dst, int *no_fields) 578 { 579 /* type 1 wave data */ 580 dst[(*no_fields)++] = 1; 581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 586 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 594 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 595 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 596 } 597 598 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 599 uint32_t wave, uint32_t start, 600 uint32_t size, uint32_t *dst) 601 { 602 wave_read_regs(adev, xcc_id, simd, wave, 0, 603 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 604 } 605 606 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 607 uint32_t wave, uint32_t thread, 608 uint32_t start, uint32_t size, 609 uint32_t *dst) 610 { 611 wave_read_regs(adev, xcc_id, simd, wave, thread, 612 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 613 } 614 615 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 616 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 617 { 618 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 619 } 620 621 622 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 623 int num_xccs_per_xcp) 624 { 625 int ret, i, num_xcc; 626 u32 tmp = 0, regval; 627 628 if (adev->psp.funcs) { 629 ret = psp_spatial_partition(&adev->psp, 630 NUM_XCC(adev->gfx.xcc_mask) / 631 num_xccs_per_xcp); 632 if (ret) 633 return ret; 634 } 635 636 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 637 638 for (i = 0; i < num_xcc; i++) { 639 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 640 num_xccs_per_xcp); 641 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 642 i % num_xccs_per_xcp); 643 regval = RREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL); 644 if (regval != tmp) 645 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 646 tmp); 647 } 648 649 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 650 651 return 0; 652 } 653 654 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 655 { 656 int xcc; 657 658 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 659 if (!xcc) { 660 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 661 return -EINVAL; 662 } 663 664 return xcc - 1; 665 } 666 667 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 668 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 669 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 670 .read_wave_data = &gfx_v9_4_3_read_wave_data, 671 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 672 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 673 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 674 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 675 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 676 }; 677 678 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 679 { 680 u32 gb_addr_config; 681 682 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 683 adev->gfx.ras = &gfx_v9_4_3_ras; 684 685 switch (adev->ip_versions[GC_HWIP][0]) { 686 case IP_VERSION(9, 4, 3): 687 adev->gfx.config.max_hw_contexts = 8; 688 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 689 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 690 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 691 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 692 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 693 break; 694 default: 695 BUG(); 696 break; 697 } 698 699 adev->gfx.config.gb_addr_config = gb_addr_config; 700 701 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 702 REG_GET_FIELD( 703 adev->gfx.config.gb_addr_config, 704 GB_ADDR_CONFIG, 705 NUM_PIPES); 706 707 adev->gfx.config.max_tile_pipes = 708 adev->gfx.config.gb_addr_config_fields.num_pipes; 709 710 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 711 REG_GET_FIELD( 712 adev->gfx.config.gb_addr_config, 713 GB_ADDR_CONFIG, 714 NUM_BANKS); 715 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 716 REG_GET_FIELD( 717 adev->gfx.config.gb_addr_config, 718 GB_ADDR_CONFIG, 719 MAX_COMPRESSED_FRAGS); 720 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 721 REG_GET_FIELD( 722 adev->gfx.config.gb_addr_config, 723 GB_ADDR_CONFIG, 724 NUM_RB_PER_SE); 725 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 726 REG_GET_FIELD( 727 adev->gfx.config.gb_addr_config, 728 GB_ADDR_CONFIG, 729 NUM_SHADER_ENGINES); 730 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 731 REG_GET_FIELD( 732 adev->gfx.config.gb_addr_config, 733 GB_ADDR_CONFIG, 734 PIPE_INTERLEAVE_SIZE)); 735 736 return 0; 737 } 738 739 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 740 int xcc_id, int mec, int pipe, int queue) 741 { 742 unsigned irq_type; 743 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 744 unsigned int hw_prio; 745 uint32_t xcc_doorbell_start; 746 747 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 748 ring_id]; 749 750 /* mec0 is me1 */ 751 ring->xcc_id = xcc_id; 752 ring->me = mec + 1; 753 ring->pipe = pipe; 754 ring->queue = queue; 755 756 ring->ring_obj = NULL; 757 ring->use_doorbell = true; 758 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 759 xcc_id * adev->doorbell_index.xcc_doorbell_range; 760 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 761 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 762 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 763 GFX9_MEC_HPD_SIZE; 764 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 765 sprintf(ring->name, "comp_%d.%d.%d.%d", 766 ring->xcc_id, ring->me, ring->pipe, ring->queue); 767 768 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 769 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 770 + ring->pipe; 771 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 772 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 773 /* type-2 packets are deprecated on MEC, use type-3 instead */ 774 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 775 hw_prio, NULL); 776 } 777 778 static int gfx_v9_4_3_sw_init(void *handle) 779 { 780 int i, j, k, r, ring_id, xcc_id, num_xcc; 781 struct amdgpu_kiq *kiq; 782 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 783 784 adev->gfx.mec.num_mec = 2; 785 adev->gfx.mec.num_pipe_per_mec = 4; 786 adev->gfx.mec.num_queue_per_pipe = 8; 787 788 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 789 790 /* EOP Event */ 791 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 792 if (r) 793 return r; 794 795 /* Privileged reg */ 796 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 797 &adev->gfx.priv_reg_irq); 798 if (r) 799 return r; 800 801 /* Privileged inst */ 802 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 803 &adev->gfx.priv_inst_irq); 804 if (r) 805 return r; 806 807 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 808 809 r = adev->gfx.rlc.funcs->init(adev); 810 if (r) { 811 DRM_ERROR("Failed to init rlc BOs!\n"); 812 return r; 813 } 814 815 r = gfx_v9_4_3_mec_init(adev); 816 if (r) { 817 DRM_ERROR("Failed to init MEC BOs!\n"); 818 return r; 819 } 820 821 /* set up the compute queues - allocate horizontally across pipes */ 822 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 823 ring_id = 0; 824 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 825 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 826 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 827 k++) { 828 if (!amdgpu_gfx_is_mec_queue_enabled( 829 adev, xcc_id, i, k, j)) 830 continue; 831 832 r = gfx_v9_4_3_compute_ring_init(adev, 833 ring_id, 834 xcc_id, 835 i, k, j); 836 if (r) 837 return r; 838 839 ring_id++; 840 } 841 } 842 } 843 844 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 845 if (r) { 846 DRM_ERROR("Failed to init KIQ BOs!\n"); 847 return r; 848 } 849 850 kiq = &adev->gfx.kiq[xcc_id]; 851 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 852 if (r) 853 return r; 854 855 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 856 r = amdgpu_gfx_mqd_sw_init(adev, 857 sizeof(struct v9_mqd_allocation), xcc_id); 858 if (r) 859 return r; 860 } 861 862 r = gfx_v9_4_3_gpu_early_init(adev); 863 if (r) 864 return r; 865 866 r = amdgpu_gfx_sysfs_init(adev); 867 if (r) 868 return r; 869 870 return amdgpu_gfx_ras_sw_init(adev); 871 } 872 873 static int gfx_v9_4_3_sw_fini(void *handle) 874 { 875 int i, num_xcc; 876 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 877 878 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 879 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 880 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 881 882 for (i = 0; i < num_xcc; i++) { 883 amdgpu_gfx_mqd_sw_fini(adev, i); 884 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 885 amdgpu_gfx_kiq_fini(adev, i); 886 } 887 888 gfx_v9_4_3_mec_fini(adev); 889 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 890 gfx_v9_4_3_free_microcode(adev); 891 amdgpu_gfx_sysfs_fini(adev); 892 893 return 0; 894 } 895 896 #define DEFAULT_SH_MEM_BASES (0x6000) 897 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 898 int xcc_id) 899 { 900 int i; 901 uint32_t sh_mem_config; 902 uint32_t sh_mem_bases; 903 uint32_t data; 904 905 /* 906 * Configure apertures: 907 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 908 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 909 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 910 */ 911 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 912 913 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 914 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 915 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 916 917 mutex_lock(&adev->srbm_mutex); 918 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 919 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 920 /* CP and shaders */ 921 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 922 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 923 924 /* Enable trap for each kfd vmid. */ 925 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 926 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 927 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 928 } 929 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 930 mutex_unlock(&adev->srbm_mutex); 931 932 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 933 acccess. These should be enabled by FW for target VMIDs. */ 934 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 935 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 936 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 937 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 938 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 939 } 940 } 941 942 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 943 { 944 int vmid; 945 946 /* 947 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 948 * access. Compute VMIDs should be enabled by FW for target VMIDs, 949 * the driver can enable them for graphics. VMID0 should maintain 950 * access so that HWS firmware can save/restore entries. 951 */ 952 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 953 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 954 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 955 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 956 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 957 } 958 } 959 960 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 961 int xcc_id) 962 { 963 u32 tmp; 964 int i; 965 966 /* XXX SH_MEM regs */ 967 /* where to put LDS, scratch, GPUVM in FSA64 space */ 968 mutex_lock(&adev->srbm_mutex); 969 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 970 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 971 /* CP and shaders */ 972 if (i == 0) { 973 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 974 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 975 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 976 !!adev->gmc.noretry); 977 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 978 regSH_MEM_CONFIG, tmp); 979 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 980 regSH_MEM_BASES, 0); 981 } else { 982 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 983 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 984 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 985 !!adev->gmc.noretry); 986 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 987 regSH_MEM_CONFIG, tmp); 988 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 989 (adev->gmc.private_aperture_start >> 990 48)); 991 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 992 (adev->gmc.shared_aperture_start >> 993 48)); 994 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 995 regSH_MEM_BASES, tmp); 996 } 997 } 998 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 999 1000 mutex_unlock(&adev->srbm_mutex); 1001 1002 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1003 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1004 } 1005 1006 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1007 { 1008 int i, num_xcc; 1009 1010 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1011 1012 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1013 adev->gfx.config.db_debug2 = 1014 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1015 1016 for (i = 0; i < num_xcc; i++) 1017 gfx_v9_4_3_xcc_constants_init(adev, i); 1018 } 1019 1020 static void 1021 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1022 int xcc_id) 1023 { 1024 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1025 } 1026 1027 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1028 { 1029 /* 1030 * Rlc save restore list is workable since v2_1. 1031 * And it's needed by gfxoff feature. 1032 */ 1033 if (adev->gfx.rlc.is_rlc_v2_1) 1034 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1035 } 1036 1037 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1038 { 1039 uint32_t data; 1040 1041 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1042 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1043 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1044 } 1045 1046 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1047 { 1048 uint32_t rlc_setting; 1049 1050 /* if RLC is not enabled, do nothing */ 1051 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1052 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1053 return false; 1054 1055 return true; 1056 } 1057 1058 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1059 { 1060 uint32_t data; 1061 unsigned i; 1062 1063 data = RLC_SAFE_MODE__CMD_MASK; 1064 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1065 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1066 1067 /* wait for RLC_SAFE_MODE */ 1068 for (i = 0; i < adev->usec_timeout; i++) { 1069 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1070 break; 1071 udelay(1); 1072 } 1073 } 1074 1075 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1076 int xcc_id) 1077 { 1078 uint32_t data; 1079 1080 data = RLC_SAFE_MODE__CMD_MASK; 1081 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1082 } 1083 1084 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1085 { 1086 int xcc_id, num_xcc; 1087 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1088 1089 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1090 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1091 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1092 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1093 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1094 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1095 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1096 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1097 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1098 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1099 } 1100 } 1101 1102 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1103 { 1104 /* init spm vmid with 0xf */ 1105 if (adev->gfx.rlc.funcs->update_spm_vmid) 1106 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1107 1108 return 0; 1109 } 1110 1111 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1112 int xcc_id) 1113 { 1114 u32 i, j, k; 1115 u32 mask; 1116 1117 mutex_lock(&adev->grbm_idx_mutex); 1118 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1119 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1120 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1121 xcc_id); 1122 for (k = 0; k < adev->usec_timeout; k++) { 1123 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1124 break; 1125 udelay(1); 1126 } 1127 if (k == adev->usec_timeout) { 1128 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1129 0xffffffff, 1130 0xffffffff, xcc_id); 1131 mutex_unlock(&adev->grbm_idx_mutex); 1132 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1133 i, j); 1134 return; 1135 } 1136 } 1137 } 1138 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1139 xcc_id); 1140 mutex_unlock(&adev->grbm_idx_mutex); 1141 1142 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1143 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1144 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1145 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1146 for (k = 0; k < adev->usec_timeout; k++) { 1147 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1148 break; 1149 udelay(1); 1150 } 1151 } 1152 1153 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1154 bool enable, int xcc_id) 1155 { 1156 u32 tmp; 1157 1158 /* These interrupts should be enabled to drive DS clock */ 1159 1160 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1161 1162 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1163 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1164 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1165 1166 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1167 } 1168 1169 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1170 { 1171 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1172 RLC_ENABLE_F32, 0); 1173 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1174 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1175 } 1176 1177 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1178 { 1179 int i, num_xcc; 1180 1181 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1182 for (i = 0; i < num_xcc; i++) 1183 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1184 } 1185 1186 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1187 { 1188 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1189 SOFT_RESET_RLC, 1); 1190 udelay(50); 1191 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1192 SOFT_RESET_RLC, 0); 1193 udelay(50); 1194 } 1195 1196 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1197 { 1198 int i, num_xcc; 1199 1200 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1201 for (i = 0; i < num_xcc; i++) 1202 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1203 } 1204 1205 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1206 { 1207 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1208 RLC_ENABLE_F32, 1); 1209 udelay(50); 1210 1211 /* carrizo do enable cp interrupt after cp inited */ 1212 if (!(adev->flags & AMD_IS_APU)) { 1213 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1214 udelay(50); 1215 } 1216 } 1217 1218 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1219 { 1220 #ifdef AMDGPU_RLC_DEBUG_RETRY 1221 u32 rlc_ucode_ver; 1222 #endif 1223 int i, num_xcc; 1224 1225 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1226 for (i = 0; i < num_xcc; i++) { 1227 gfx_v9_4_3_xcc_rlc_start(adev, i); 1228 #ifdef AMDGPU_RLC_DEBUG_RETRY 1229 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1230 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1231 if (rlc_ucode_ver == 0x108) { 1232 dev_info(adev->dev, 1233 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1234 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1235 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1236 * default is 0x9C4 to create a 100us interval */ 1237 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1238 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1239 * to disable the page fault retry interrupts, default is 1240 * 0x100 (256) */ 1241 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1242 } 1243 #endif 1244 } 1245 } 1246 1247 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1248 int xcc_id) 1249 { 1250 const struct rlc_firmware_header_v2_0 *hdr; 1251 const __le32 *fw_data; 1252 unsigned i, fw_size; 1253 1254 if (!adev->gfx.rlc_fw) 1255 return -EINVAL; 1256 1257 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1258 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1259 1260 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1261 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1262 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1263 1264 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1265 RLCG_UCODE_LOADING_START_ADDRESS); 1266 for (i = 0; i < fw_size; i++) { 1267 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1268 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1269 msleep(1); 1270 } 1271 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1272 } 1273 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1274 1275 return 0; 1276 } 1277 1278 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1279 { 1280 int r; 1281 1282 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1283 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1284 /* legacy rlc firmware loading */ 1285 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1286 if (r) 1287 return r; 1288 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1289 } 1290 1291 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1292 /* disable CG */ 1293 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1294 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1295 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1296 1297 return 0; 1298 } 1299 1300 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1301 { 1302 int r, i, num_xcc; 1303 1304 if (amdgpu_sriov_vf(adev)) 1305 return 0; 1306 1307 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1308 for (i = 0; i < num_xcc; i++) { 1309 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1310 if (r) 1311 return r; 1312 } 1313 1314 return 0; 1315 } 1316 1317 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1318 unsigned vmid) 1319 { 1320 u32 reg, data; 1321 1322 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1323 if (amdgpu_sriov_is_pp_one_vf(adev)) 1324 data = RREG32_NO_KIQ(reg); 1325 else 1326 data = RREG32(reg); 1327 1328 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1329 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1330 1331 if (amdgpu_sriov_is_pp_one_vf(adev)) 1332 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1333 else 1334 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1335 } 1336 1337 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1338 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1339 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1340 }; 1341 1342 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1343 uint32_t offset, 1344 struct soc15_reg_rlcg *entries, int arr_size) 1345 { 1346 int i, inst; 1347 uint32_t reg; 1348 1349 if (!entries) 1350 return false; 1351 1352 for (i = 0; i < arr_size; i++) { 1353 const struct soc15_reg_rlcg *entry; 1354 1355 entry = &entries[i]; 1356 inst = adev->ip_map.logical_to_dev_inst ? 1357 adev->ip_map.logical_to_dev_inst( 1358 adev, entry->hwip, entry->instance) : 1359 entry->instance; 1360 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1361 entry->reg; 1362 if (offset == reg) 1363 return true; 1364 } 1365 1366 return false; 1367 } 1368 1369 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1370 { 1371 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1372 (void *)rlcg_access_gc_9_4_3, 1373 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1374 } 1375 1376 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1377 bool enable, int xcc_id) 1378 { 1379 if (enable) { 1380 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1381 } else { 1382 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1383 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1384 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1385 } 1386 udelay(50); 1387 } 1388 1389 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1390 int xcc_id) 1391 { 1392 const struct gfx_firmware_header_v1_0 *mec_hdr; 1393 const __le32 *fw_data; 1394 unsigned i; 1395 u32 tmp; 1396 u32 mec_ucode_addr_offset; 1397 u32 mec_ucode_data_offset; 1398 1399 if (!adev->gfx.mec_fw) 1400 return -EINVAL; 1401 1402 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1403 1404 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1405 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1406 1407 fw_data = (const __le32 *) 1408 (adev->gfx.mec_fw->data + 1409 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1410 tmp = 0; 1411 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1412 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1413 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1414 1415 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1416 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1417 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1418 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1419 1420 mec_ucode_addr_offset = 1421 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1422 mec_ucode_data_offset = 1423 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1424 1425 /* MEC1 */ 1426 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1427 for (i = 0; i < mec_hdr->jt_size; i++) 1428 WREG32(mec_ucode_data_offset, 1429 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1430 1431 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1432 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1433 1434 return 0; 1435 } 1436 1437 /* KIQ functions */ 1438 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1439 { 1440 uint32_t tmp; 1441 struct amdgpu_device *adev = ring->adev; 1442 1443 /* tell RLC which is KIQ queue */ 1444 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1445 tmp &= 0xffffff00; 1446 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1447 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1448 tmp |= 0x80; 1449 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1450 } 1451 1452 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1453 { 1454 struct amdgpu_device *adev = ring->adev; 1455 1456 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1457 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1458 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1459 mqd->cp_hqd_queue_priority = 1460 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1461 } 1462 } 1463 } 1464 1465 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1466 { 1467 struct amdgpu_device *adev = ring->adev; 1468 struct v9_mqd *mqd = ring->mqd_ptr; 1469 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1470 uint32_t tmp; 1471 1472 mqd->header = 0xC0310800; 1473 mqd->compute_pipelinestat_enable = 0x00000001; 1474 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1475 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1476 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1477 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1478 mqd->compute_misc_reserved = 0x00000003; 1479 1480 mqd->dynamic_cu_mask_addr_lo = 1481 lower_32_bits(ring->mqd_gpu_addr 1482 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1483 mqd->dynamic_cu_mask_addr_hi = 1484 upper_32_bits(ring->mqd_gpu_addr 1485 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1486 1487 eop_base_addr = ring->eop_gpu_addr >> 8; 1488 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1489 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1490 1491 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1492 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1493 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1494 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1495 1496 mqd->cp_hqd_eop_control = tmp; 1497 1498 /* enable doorbell? */ 1499 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1500 1501 if (ring->use_doorbell) { 1502 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1503 DOORBELL_OFFSET, ring->doorbell_index); 1504 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1505 DOORBELL_EN, 1); 1506 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1507 DOORBELL_SOURCE, 0); 1508 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1509 DOORBELL_HIT, 0); 1510 } else { 1511 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1512 DOORBELL_EN, 0); 1513 } 1514 1515 mqd->cp_hqd_pq_doorbell_control = tmp; 1516 1517 /* disable the queue if it's active */ 1518 ring->wptr = 0; 1519 mqd->cp_hqd_dequeue_request = 0; 1520 mqd->cp_hqd_pq_rptr = 0; 1521 mqd->cp_hqd_pq_wptr_lo = 0; 1522 mqd->cp_hqd_pq_wptr_hi = 0; 1523 1524 /* set the pointer to the MQD */ 1525 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1526 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1527 1528 /* set MQD vmid to 0 */ 1529 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1530 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1531 mqd->cp_mqd_control = tmp; 1532 1533 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1534 hqd_gpu_addr = ring->gpu_addr >> 8; 1535 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1536 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1537 1538 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1539 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1540 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1541 (order_base_2(ring->ring_size / 4) - 1)); 1542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1543 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1544 #ifdef __BIG_ENDIAN 1545 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1546 #endif 1547 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1548 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1549 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1550 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1551 mqd->cp_hqd_pq_control = tmp; 1552 1553 /* set the wb address whether it's enabled or not */ 1554 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1555 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1556 mqd->cp_hqd_pq_rptr_report_addr_hi = 1557 upper_32_bits(wb_gpu_addr) & 0xffff; 1558 1559 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1560 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1561 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1562 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1563 1564 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1565 ring->wptr = 0; 1566 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1567 1568 /* set the vmid for the queue */ 1569 mqd->cp_hqd_vmid = 0; 1570 1571 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1572 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1573 mqd->cp_hqd_persistent_state = tmp; 1574 1575 /* set MIN_IB_AVAIL_SIZE */ 1576 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1577 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1578 mqd->cp_hqd_ib_control = tmp; 1579 1580 /* set static priority for a queue/ring */ 1581 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1582 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1583 1584 /* map_queues packet doesn't need activate the queue, 1585 * so only kiq need set this field. 1586 */ 1587 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1588 mqd->cp_hqd_active = 1; 1589 1590 return 0; 1591 } 1592 1593 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1594 int xcc_id) 1595 { 1596 struct amdgpu_device *adev = ring->adev; 1597 struct v9_mqd *mqd = ring->mqd_ptr; 1598 int j; 1599 1600 /* disable wptr polling */ 1601 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1602 1603 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1604 mqd->cp_hqd_eop_base_addr_lo); 1605 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1606 mqd->cp_hqd_eop_base_addr_hi); 1607 1608 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1609 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1610 mqd->cp_hqd_eop_control); 1611 1612 /* enable doorbell? */ 1613 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1614 mqd->cp_hqd_pq_doorbell_control); 1615 1616 /* disable the queue if it's active */ 1617 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1618 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1619 for (j = 0; j < adev->usec_timeout; j++) { 1620 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1621 break; 1622 udelay(1); 1623 } 1624 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1625 mqd->cp_hqd_dequeue_request); 1626 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1627 mqd->cp_hqd_pq_rptr); 1628 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1629 mqd->cp_hqd_pq_wptr_lo); 1630 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1631 mqd->cp_hqd_pq_wptr_hi); 1632 } 1633 1634 /* set the pointer to the MQD */ 1635 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1636 mqd->cp_mqd_base_addr_lo); 1637 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1638 mqd->cp_mqd_base_addr_hi); 1639 1640 /* set MQD vmid to 0 */ 1641 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1642 mqd->cp_mqd_control); 1643 1644 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1645 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1646 mqd->cp_hqd_pq_base_lo); 1647 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1648 mqd->cp_hqd_pq_base_hi); 1649 1650 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1651 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1652 mqd->cp_hqd_pq_control); 1653 1654 /* set the wb address whether it's enabled or not */ 1655 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1656 mqd->cp_hqd_pq_rptr_report_addr_lo); 1657 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1658 mqd->cp_hqd_pq_rptr_report_addr_hi); 1659 1660 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1661 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1662 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1663 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1664 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1665 1666 /* enable the doorbell if requested */ 1667 if (ring->use_doorbell) { 1668 WREG32_SOC15( 1669 GC, GET_INST(GC, xcc_id), 1670 regCP_MEC_DOORBELL_RANGE_LOWER, 1671 ((adev->doorbell_index.kiq + 1672 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1673 2) << 2); 1674 WREG32_SOC15( 1675 GC, GET_INST(GC, xcc_id), 1676 regCP_MEC_DOORBELL_RANGE_UPPER, 1677 ((adev->doorbell_index.userqueue_end + 1678 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1679 2) << 2); 1680 } 1681 1682 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1683 mqd->cp_hqd_pq_doorbell_control); 1684 1685 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1686 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1687 mqd->cp_hqd_pq_wptr_lo); 1688 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1689 mqd->cp_hqd_pq_wptr_hi); 1690 1691 /* set the vmid for the queue */ 1692 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1693 1694 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1695 mqd->cp_hqd_persistent_state); 1696 1697 /* activate the queue */ 1698 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1699 mqd->cp_hqd_active); 1700 1701 if (ring->use_doorbell) 1702 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1703 1704 return 0; 1705 } 1706 1707 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1708 int xcc_id) 1709 { 1710 struct amdgpu_device *adev = ring->adev; 1711 int j; 1712 1713 /* disable the queue if it's active */ 1714 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1715 1716 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1717 1718 for (j = 0; j < adev->usec_timeout; j++) { 1719 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1720 break; 1721 udelay(1); 1722 } 1723 1724 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1725 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1726 1727 /* Manual disable if dequeue request times out */ 1728 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1729 } 1730 1731 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1732 0); 1733 } 1734 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1736 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1737 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 1738 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1739 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1740 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1741 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1742 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1743 1744 return 0; 1745 } 1746 1747 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1748 { 1749 struct amdgpu_device *adev = ring->adev; 1750 struct v9_mqd *mqd = ring->mqd_ptr; 1751 struct v9_mqd *tmp_mqd; 1752 1753 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1754 1755 /* GPU could be in bad state during probe, driver trigger the reset 1756 * after load the SMU, in this case , the mqd is not be initialized. 1757 * driver need to re-init the mqd. 1758 * check mqd->cp_hqd_pq_control since this value should not be 0 1759 */ 1760 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1761 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1762 /* for GPU_RESET case , reset MQD to a clean status */ 1763 if (adev->gfx.kiq[xcc_id].mqd_backup) 1764 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1765 1766 /* reset ring buffer */ 1767 ring->wptr = 0; 1768 amdgpu_ring_clear_ring(ring); 1769 mutex_lock(&adev->srbm_mutex); 1770 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1771 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1772 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1773 mutex_unlock(&adev->srbm_mutex); 1774 } else { 1775 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1776 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1777 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1778 mutex_lock(&adev->srbm_mutex); 1779 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1780 amdgpu_ring_clear_ring(ring); 1781 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1782 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1783 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1784 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1785 mutex_unlock(&adev->srbm_mutex); 1786 1787 if (adev->gfx.kiq[xcc_id].mqd_backup) 1788 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1789 } 1790 1791 return 0; 1792 } 1793 1794 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1795 { 1796 struct amdgpu_device *adev = ring->adev; 1797 struct v9_mqd *mqd = ring->mqd_ptr; 1798 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1799 struct v9_mqd *tmp_mqd; 1800 1801 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1802 * is not be initialized before 1803 */ 1804 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1805 1806 if (!tmp_mqd->cp_hqd_pq_control || 1807 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1808 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1809 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1810 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1811 mutex_lock(&adev->srbm_mutex); 1812 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1813 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1814 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1815 mutex_unlock(&adev->srbm_mutex); 1816 1817 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1818 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1819 } else { 1820 /* restore MQD to a clean status */ 1821 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1822 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1823 /* reset ring buffer */ 1824 ring->wptr = 0; 1825 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1826 amdgpu_ring_clear_ring(ring); 1827 } 1828 1829 return 0; 1830 } 1831 1832 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1833 { 1834 struct amdgpu_ring *ring; 1835 int j; 1836 1837 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1838 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1839 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1840 mutex_lock(&adev->srbm_mutex); 1841 soc15_grbm_select(adev, ring->me, 1842 ring->pipe, 1843 ring->queue, 0, GET_INST(GC, xcc_id)); 1844 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1845 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1846 mutex_unlock(&adev->srbm_mutex); 1847 } 1848 } 1849 1850 return 0; 1851 } 1852 1853 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1854 { 1855 struct amdgpu_ring *ring; 1856 int r; 1857 1858 ring = &adev->gfx.kiq[xcc_id].ring; 1859 1860 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1861 if (unlikely(r != 0)) 1862 return r; 1863 1864 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1865 if (unlikely(r != 0)) { 1866 amdgpu_bo_unreserve(ring->mqd_obj); 1867 return r; 1868 } 1869 1870 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1871 amdgpu_bo_kunmap(ring->mqd_obj); 1872 ring->mqd_ptr = NULL; 1873 amdgpu_bo_unreserve(ring->mqd_obj); 1874 return 0; 1875 } 1876 1877 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1878 { 1879 struct amdgpu_ring *ring = NULL; 1880 int r = 0, i; 1881 1882 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1883 1884 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1885 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1886 1887 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1888 if (unlikely(r != 0)) 1889 goto done; 1890 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1891 if (!r) { 1892 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1893 amdgpu_bo_kunmap(ring->mqd_obj); 1894 ring->mqd_ptr = NULL; 1895 } 1896 amdgpu_bo_unreserve(ring->mqd_obj); 1897 if (r) 1898 goto done; 1899 } 1900 1901 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1902 done: 1903 return r; 1904 } 1905 1906 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1907 { 1908 struct amdgpu_ring *ring; 1909 int r, j; 1910 1911 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1912 1913 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1914 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1915 1916 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1917 if (r) 1918 return r; 1919 } 1920 1921 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1922 if (r) 1923 return r; 1924 1925 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 1926 if (r) 1927 return r; 1928 1929 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1930 ring = &adev->gfx.compute_ring 1931 [j + xcc_id * adev->gfx.num_compute_rings]; 1932 r = amdgpu_ring_test_helper(ring); 1933 if (r) 1934 return r; 1935 } 1936 1937 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1938 1939 return 0; 1940 } 1941 1942 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 1943 { 1944 int r = 0, i, num_xcc; 1945 1946 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 1947 AMDGPU_XCP_FL_NONE) == 1948 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 1949 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 1950 amdgpu_user_partt_mode); 1951 1952 if (r) 1953 return r; 1954 1955 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1956 for (i = 0; i < num_xcc; i++) { 1957 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 1958 if (r) 1959 return r; 1960 } 1961 1962 return 0; 1963 } 1964 1965 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 1966 int xcc_id) 1967 { 1968 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 1969 } 1970 1971 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 1972 { 1973 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 1974 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 1975 1976 if (amdgpu_sriov_vf(adev)) { 1977 /* must disable polling for SRIOV when hw finished, otherwise 1978 * CPC engine may still keep fetching WB address which is already 1979 * invalid after sw finished and trigger DMAR reading error in 1980 * hypervisor side. 1981 */ 1982 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1983 return; 1984 } 1985 1986 /* Use deinitialize sequence from CAIL when unbinding device 1987 * from driver, otherwise KIQ is hanging when binding back 1988 */ 1989 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1990 mutex_lock(&adev->srbm_mutex); 1991 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 1992 adev->gfx.kiq[xcc_id].ring.pipe, 1993 adev->gfx.kiq[xcc_id].ring.queue, 0, 1994 GET_INST(GC, xcc_id)); 1995 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 1996 xcc_id); 1997 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1998 mutex_unlock(&adev->srbm_mutex); 1999 } 2000 2001 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2002 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 2003 } 2004 2005 static int gfx_v9_4_3_hw_init(void *handle) 2006 { 2007 int r; 2008 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2009 2010 if (!amdgpu_sriov_vf(adev)) 2011 gfx_v9_4_3_init_golden_registers(adev); 2012 2013 gfx_v9_4_3_constants_init(adev); 2014 2015 r = adev->gfx.rlc.funcs->resume(adev); 2016 if (r) 2017 return r; 2018 2019 r = gfx_v9_4_3_cp_resume(adev); 2020 if (r) 2021 return r; 2022 2023 return r; 2024 } 2025 2026 static int gfx_v9_4_3_hw_fini(void *handle) 2027 { 2028 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2029 int i, num_xcc; 2030 2031 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2032 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2033 2034 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2035 for (i = 0; i < num_xcc; i++) { 2036 gfx_v9_4_3_xcc_fini(adev, i); 2037 } 2038 2039 return 0; 2040 } 2041 2042 static int gfx_v9_4_3_suspend(void *handle) 2043 { 2044 return gfx_v9_4_3_hw_fini(handle); 2045 } 2046 2047 static int gfx_v9_4_3_resume(void *handle) 2048 { 2049 return gfx_v9_4_3_hw_init(handle); 2050 } 2051 2052 static bool gfx_v9_4_3_is_idle(void *handle) 2053 { 2054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2055 int i, num_xcc; 2056 2057 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2058 for (i = 0; i < num_xcc; i++) { 2059 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2060 GRBM_STATUS, GUI_ACTIVE)) 2061 return false; 2062 } 2063 return true; 2064 } 2065 2066 static int gfx_v9_4_3_wait_for_idle(void *handle) 2067 { 2068 unsigned i; 2069 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2070 2071 for (i = 0; i < adev->usec_timeout; i++) { 2072 if (gfx_v9_4_3_is_idle(handle)) 2073 return 0; 2074 udelay(1); 2075 } 2076 return -ETIMEDOUT; 2077 } 2078 2079 static int gfx_v9_4_3_soft_reset(void *handle) 2080 { 2081 u32 grbm_soft_reset = 0; 2082 u32 tmp; 2083 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2084 2085 /* GRBM_STATUS */ 2086 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2087 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2088 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2089 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2090 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2091 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2092 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2093 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2094 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2095 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2096 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2097 } 2098 2099 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2100 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2101 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2102 } 2103 2104 /* GRBM_STATUS2 */ 2105 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2106 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2107 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2108 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2109 2110 2111 if (grbm_soft_reset) { 2112 /* stop the rlc */ 2113 adev->gfx.rlc.funcs->stop(adev); 2114 2115 /* Disable MEC parsing/prefetching */ 2116 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2117 2118 if (grbm_soft_reset) { 2119 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2120 tmp |= grbm_soft_reset; 2121 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2122 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2123 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2124 2125 udelay(50); 2126 2127 tmp &= ~grbm_soft_reset; 2128 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2129 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2130 } 2131 2132 /* Wait a little for things to settle down */ 2133 udelay(50); 2134 } 2135 return 0; 2136 } 2137 2138 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2139 uint32_t vmid, 2140 uint32_t gds_base, uint32_t gds_size, 2141 uint32_t gws_base, uint32_t gws_size, 2142 uint32_t oa_base, uint32_t oa_size) 2143 { 2144 struct amdgpu_device *adev = ring->adev; 2145 2146 /* GDS Base */ 2147 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2148 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2149 gds_base); 2150 2151 /* GDS Size */ 2152 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2153 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2154 gds_size); 2155 2156 /* GWS */ 2157 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2158 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2159 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2160 2161 /* OA */ 2162 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2163 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2164 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2165 } 2166 2167 static int gfx_v9_4_3_early_init(void *handle) 2168 { 2169 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2170 2171 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2172 AMDGPU_MAX_COMPUTE_RINGS); 2173 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2174 gfx_v9_4_3_set_ring_funcs(adev); 2175 gfx_v9_4_3_set_irq_funcs(adev); 2176 gfx_v9_4_3_set_gds_init(adev); 2177 gfx_v9_4_3_set_rlc_funcs(adev); 2178 2179 /* init rlcg reg access ctrl */ 2180 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2181 2182 return gfx_v9_4_3_init_microcode(adev); 2183 } 2184 2185 static int gfx_v9_4_3_late_init(void *handle) 2186 { 2187 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2188 int r; 2189 2190 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2191 if (r) 2192 return r; 2193 2194 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2195 if (r) 2196 return r; 2197 2198 if (adev->gfx.ras && 2199 adev->gfx.ras->enable_watchdog_timer) 2200 adev->gfx.ras->enable_watchdog_timer(adev); 2201 2202 return 0; 2203 } 2204 2205 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2206 bool enable, int xcc_id) 2207 { 2208 uint32_t def, data; 2209 2210 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2211 return; 2212 2213 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2214 regRLC_CGTT_MGCG_OVERRIDE); 2215 2216 if (enable) 2217 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2218 else 2219 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2220 2221 if (def != data) 2222 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2223 regRLC_CGTT_MGCG_OVERRIDE, data); 2224 2225 } 2226 2227 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2228 bool enable, int xcc_id) 2229 { 2230 uint32_t def, data; 2231 2232 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2233 return; 2234 2235 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2236 regRLC_CGTT_MGCG_OVERRIDE); 2237 2238 if (enable) 2239 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2240 else 2241 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2242 2243 if (def != data) 2244 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2245 regRLC_CGTT_MGCG_OVERRIDE, data); 2246 } 2247 2248 static void 2249 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2250 bool enable, int xcc_id) 2251 { 2252 uint32_t data, def; 2253 2254 /* It is disabled by HW by default */ 2255 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2256 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2257 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2258 2259 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2260 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2261 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2262 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2263 2264 if (def != data) 2265 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2266 2267 /* MGLS is a global flag to control all MGLS in GFX */ 2268 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2269 /* 2 - RLC memory Light sleep */ 2270 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2271 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2272 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2273 if (def != data) 2274 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2275 } 2276 /* 3 - CP memory Light sleep */ 2277 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2278 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2279 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2280 if (def != data) 2281 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2282 } 2283 } 2284 } else { 2285 /* 1 - MGCG_OVERRIDE */ 2286 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2287 2288 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2289 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2290 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2291 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2292 2293 if (def != data) 2294 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2295 2296 /* 2 - disable MGLS in RLC */ 2297 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2298 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2299 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2301 } 2302 2303 /* 3 - disable MGLS in CP */ 2304 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2305 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2306 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2307 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2308 } 2309 } 2310 2311 } 2312 2313 static void 2314 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2315 bool enable, int xcc_id) 2316 { 2317 uint32_t def, data; 2318 2319 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2320 2321 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2322 /* unset CGCG override */ 2323 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2324 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2325 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2326 else 2327 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2328 /* update CGCG and CGLS override bits */ 2329 if (def != data) 2330 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2331 2332 /* enable cgcg FSM(0x0000363F) */ 2333 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2334 2335 data = (0x36 2336 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2337 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2338 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2339 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2340 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2341 if (def != data) 2342 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2343 2344 /* set IDLE_POLL_COUNT(0x00900100) */ 2345 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2346 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2347 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2348 if (def != data) 2349 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2350 } else { 2351 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2352 /* reset CGCG/CGLS bits */ 2353 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2354 /* disable cgcg and cgls in FSM */ 2355 if (def != data) 2356 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2357 } 2358 2359 } 2360 2361 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2362 bool enable, int xcc_id) 2363 { 2364 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2365 2366 if (enable) { 2367 /* FGCG */ 2368 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2369 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2370 2371 /* CGCG/CGLS should be enabled after MGCG/MGLS 2372 * === MGCG + MGLS === 2373 */ 2374 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2375 xcc_id); 2376 /* === CGCG + CGLS === */ 2377 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2378 xcc_id); 2379 } else { 2380 /* CGCG/CGLS should be disabled before MGCG/MGLS 2381 * === CGCG + CGLS === 2382 */ 2383 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2384 xcc_id); 2385 /* === MGCG + MGLS === */ 2386 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2387 xcc_id); 2388 2389 /* FGCG */ 2390 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2391 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2392 } 2393 2394 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2395 2396 return 0; 2397 } 2398 2399 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2400 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2401 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2402 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2403 .init = gfx_v9_4_3_rlc_init, 2404 .resume = gfx_v9_4_3_rlc_resume, 2405 .stop = gfx_v9_4_3_rlc_stop, 2406 .reset = gfx_v9_4_3_rlc_reset, 2407 .start = gfx_v9_4_3_rlc_start, 2408 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2409 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2410 }; 2411 2412 static int gfx_v9_4_3_set_powergating_state(void *handle, 2413 enum amd_powergating_state state) 2414 { 2415 return 0; 2416 } 2417 2418 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2419 enum amd_clockgating_state state) 2420 { 2421 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2422 int i, num_xcc; 2423 2424 if (amdgpu_sriov_vf(adev)) 2425 return 0; 2426 2427 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2428 switch (adev->ip_versions[GC_HWIP][0]) { 2429 case IP_VERSION(9, 4, 3): 2430 for (i = 0; i < num_xcc; i++) 2431 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2432 adev, state == AMD_CG_STATE_GATE, i); 2433 break; 2434 default: 2435 break; 2436 } 2437 return 0; 2438 } 2439 2440 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2441 { 2442 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2443 int data; 2444 2445 if (amdgpu_sriov_vf(adev)) 2446 *flags = 0; 2447 2448 /* AMD_CG_SUPPORT_GFX_MGCG */ 2449 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2450 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2451 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2452 2453 /* AMD_CG_SUPPORT_GFX_CGCG */ 2454 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2455 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2456 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2457 2458 /* AMD_CG_SUPPORT_GFX_CGLS */ 2459 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2460 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2461 2462 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2463 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2464 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2465 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2466 2467 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2468 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2469 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2470 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2471 } 2472 2473 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2474 { 2475 struct amdgpu_device *adev = ring->adev; 2476 u32 ref_and_mask, reg_mem_engine; 2477 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2478 2479 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2480 switch (ring->me) { 2481 case 1: 2482 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2483 break; 2484 case 2: 2485 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2486 break; 2487 default: 2488 return; 2489 } 2490 reg_mem_engine = 0; 2491 } else { 2492 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2493 reg_mem_engine = 1; /* pfp */ 2494 } 2495 2496 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2497 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2498 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2499 ref_and_mask, ref_and_mask, 0x20); 2500 } 2501 2502 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2503 struct amdgpu_job *job, 2504 struct amdgpu_ib *ib, 2505 uint32_t flags) 2506 { 2507 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2508 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2509 2510 /* Currently, there is a high possibility to get wave ID mismatch 2511 * between ME and GDS, leading to a hw deadlock, because ME generates 2512 * different wave IDs than the GDS expects. This situation happens 2513 * randomly when at least 5 compute pipes use GDS ordered append. 2514 * The wave IDs generated by ME are also wrong after suspend/resume. 2515 * Those are probably bugs somewhere else in the kernel driver. 2516 * 2517 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2518 * GDS to 0 for this ring (me/pipe). 2519 */ 2520 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2521 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2522 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2523 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2524 } 2525 2526 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2527 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2528 amdgpu_ring_write(ring, 2529 #ifdef __BIG_ENDIAN 2530 (2 << 0) | 2531 #endif 2532 lower_32_bits(ib->gpu_addr)); 2533 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2534 amdgpu_ring_write(ring, control); 2535 } 2536 2537 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2538 u64 seq, unsigned flags) 2539 { 2540 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2541 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2542 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2543 2544 /* RELEASE_MEM - flush caches, send int */ 2545 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2546 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2547 EOP_TC_NC_ACTION_EN) : 2548 (EOP_TCL1_ACTION_EN | 2549 EOP_TC_ACTION_EN | 2550 EOP_TC_WB_ACTION_EN | 2551 EOP_TC_MD_ACTION_EN)) | 2552 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2553 EVENT_INDEX(5))); 2554 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2555 2556 /* 2557 * the address should be Qword aligned if 64bit write, Dword 2558 * aligned if only send 32bit data low (discard data high) 2559 */ 2560 if (write64bit) 2561 BUG_ON(addr & 0x7); 2562 else 2563 BUG_ON(addr & 0x3); 2564 amdgpu_ring_write(ring, lower_32_bits(addr)); 2565 amdgpu_ring_write(ring, upper_32_bits(addr)); 2566 amdgpu_ring_write(ring, lower_32_bits(seq)); 2567 amdgpu_ring_write(ring, upper_32_bits(seq)); 2568 amdgpu_ring_write(ring, 0); 2569 } 2570 2571 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2572 { 2573 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2574 uint32_t seq = ring->fence_drv.sync_seq; 2575 uint64_t addr = ring->fence_drv.gpu_addr; 2576 2577 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2578 lower_32_bits(addr), upper_32_bits(addr), 2579 seq, 0xffffffff, 4); 2580 } 2581 2582 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2583 unsigned vmid, uint64_t pd_addr) 2584 { 2585 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2586 } 2587 2588 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2589 { 2590 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2591 } 2592 2593 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2594 { 2595 u64 wptr; 2596 2597 /* XXX check if swapping is necessary on BE */ 2598 if (ring->use_doorbell) 2599 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2600 else 2601 BUG(); 2602 return wptr; 2603 } 2604 2605 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2606 { 2607 struct amdgpu_device *adev = ring->adev; 2608 2609 /* XXX check if swapping is necessary on BE */ 2610 if (ring->use_doorbell) { 2611 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2612 WDOORBELL64(ring->doorbell_index, ring->wptr); 2613 } else { 2614 BUG(); /* only DOORBELL method supported on gfx9 now */ 2615 } 2616 } 2617 2618 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2619 u64 seq, unsigned int flags) 2620 { 2621 struct amdgpu_device *adev = ring->adev; 2622 2623 /* we only allocate 32bit for each seq wb address */ 2624 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2625 2626 /* write fence seq to the "addr" */ 2627 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2628 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2629 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2630 amdgpu_ring_write(ring, lower_32_bits(addr)); 2631 amdgpu_ring_write(ring, upper_32_bits(addr)); 2632 amdgpu_ring_write(ring, lower_32_bits(seq)); 2633 2634 if (flags & AMDGPU_FENCE_FLAG_INT) { 2635 /* set register to trigger INT */ 2636 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2637 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2638 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2639 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2640 amdgpu_ring_write(ring, 0); 2641 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2642 } 2643 } 2644 2645 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2646 uint32_t reg_val_offs) 2647 { 2648 struct amdgpu_device *adev = ring->adev; 2649 2650 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2651 amdgpu_ring_write(ring, 0 | /* src: register*/ 2652 (5 << 8) | /* dst: memory */ 2653 (1 << 20)); /* write confirm */ 2654 amdgpu_ring_write(ring, reg); 2655 amdgpu_ring_write(ring, 0); 2656 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2657 reg_val_offs * 4)); 2658 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2659 reg_val_offs * 4)); 2660 } 2661 2662 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2663 uint32_t val) 2664 { 2665 uint32_t cmd = 0; 2666 2667 switch (ring->funcs->type) { 2668 case AMDGPU_RING_TYPE_GFX: 2669 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2670 break; 2671 case AMDGPU_RING_TYPE_KIQ: 2672 cmd = (1 << 16); /* no inc addr */ 2673 break; 2674 default: 2675 cmd = WR_CONFIRM; 2676 break; 2677 } 2678 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2679 amdgpu_ring_write(ring, cmd); 2680 amdgpu_ring_write(ring, reg); 2681 amdgpu_ring_write(ring, 0); 2682 amdgpu_ring_write(ring, val); 2683 } 2684 2685 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2686 uint32_t val, uint32_t mask) 2687 { 2688 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2689 } 2690 2691 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2692 uint32_t reg0, uint32_t reg1, 2693 uint32_t ref, uint32_t mask) 2694 { 2695 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2696 ref, mask); 2697 } 2698 2699 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2700 struct amdgpu_device *adev, int me, int pipe, 2701 enum amdgpu_interrupt_state state, int xcc_id) 2702 { 2703 u32 mec_int_cntl, mec_int_cntl_reg; 2704 2705 /* 2706 * amdgpu controls only the first MEC. That's why this function only 2707 * handles the setting of interrupts for this specific MEC. All other 2708 * pipes' interrupts are set by amdkfd. 2709 */ 2710 2711 if (me == 1) { 2712 switch (pipe) { 2713 case 0: 2714 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2715 break; 2716 case 1: 2717 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2718 break; 2719 case 2: 2720 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2721 break; 2722 case 3: 2723 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2724 break; 2725 default: 2726 DRM_DEBUG("invalid pipe %d\n", pipe); 2727 return; 2728 } 2729 } else { 2730 DRM_DEBUG("invalid me %d\n", me); 2731 return; 2732 } 2733 2734 switch (state) { 2735 case AMDGPU_IRQ_STATE_DISABLE: 2736 mec_int_cntl = RREG32(mec_int_cntl_reg); 2737 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2738 TIME_STAMP_INT_ENABLE, 0); 2739 WREG32(mec_int_cntl_reg, mec_int_cntl); 2740 break; 2741 case AMDGPU_IRQ_STATE_ENABLE: 2742 mec_int_cntl = RREG32(mec_int_cntl_reg); 2743 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2744 TIME_STAMP_INT_ENABLE, 1); 2745 WREG32(mec_int_cntl_reg, mec_int_cntl); 2746 break; 2747 default: 2748 break; 2749 } 2750 } 2751 2752 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2753 struct amdgpu_irq_src *source, 2754 unsigned type, 2755 enum amdgpu_interrupt_state state) 2756 { 2757 int i, num_xcc; 2758 2759 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2760 switch (state) { 2761 case AMDGPU_IRQ_STATE_DISABLE: 2762 case AMDGPU_IRQ_STATE_ENABLE: 2763 for (i = 0; i < num_xcc; i++) 2764 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2765 PRIV_REG_INT_ENABLE, 2766 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2767 break; 2768 default: 2769 break; 2770 } 2771 2772 return 0; 2773 } 2774 2775 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2776 struct amdgpu_irq_src *source, 2777 unsigned type, 2778 enum amdgpu_interrupt_state state) 2779 { 2780 int i, num_xcc; 2781 2782 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2783 switch (state) { 2784 case AMDGPU_IRQ_STATE_DISABLE: 2785 case AMDGPU_IRQ_STATE_ENABLE: 2786 for (i = 0; i < num_xcc; i++) 2787 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2788 PRIV_INSTR_INT_ENABLE, 2789 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2790 break; 2791 default: 2792 break; 2793 } 2794 2795 return 0; 2796 } 2797 2798 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2799 struct amdgpu_irq_src *src, 2800 unsigned type, 2801 enum amdgpu_interrupt_state state) 2802 { 2803 int i, num_xcc; 2804 2805 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2806 for (i = 0; i < num_xcc; i++) { 2807 switch (type) { 2808 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2809 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2810 adev, 1, 0, state, i); 2811 break; 2812 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2813 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2814 adev, 1, 1, state, i); 2815 break; 2816 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2817 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2818 adev, 1, 2, state, i); 2819 break; 2820 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2821 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2822 adev, 1, 3, state, i); 2823 break; 2824 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2825 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2826 adev, 2, 0, state, i); 2827 break; 2828 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2829 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2830 adev, 2, 1, state, i); 2831 break; 2832 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2833 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2834 adev, 2, 2, state, i); 2835 break; 2836 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2837 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2838 adev, 2, 3, state, i); 2839 break; 2840 default: 2841 break; 2842 } 2843 } 2844 2845 return 0; 2846 } 2847 2848 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2849 struct amdgpu_irq_src *source, 2850 struct amdgpu_iv_entry *entry) 2851 { 2852 int i, xcc_id; 2853 u8 me_id, pipe_id, queue_id; 2854 struct amdgpu_ring *ring; 2855 2856 DRM_DEBUG("IH: CP EOP\n"); 2857 me_id = (entry->ring_id & 0x0c) >> 2; 2858 pipe_id = (entry->ring_id & 0x03) >> 0; 2859 queue_id = (entry->ring_id & 0x70) >> 4; 2860 2861 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2862 2863 if (xcc_id == -EINVAL) 2864 return -EINVAL; 2865 2866 switch (me_id) { 2867 case 0: 2868 case 1: 2869 case 2: 2870 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2871 ring = &adev->gfx.compute_ring 2872 [i + 2873 xcc_id * adev->gfx.num_compute_rings]; 2874 /* Per-queue interrupt is supported for MEC starting from VI. 2875 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2876 */ 2877 2878 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2879 amdgpu_fence_process(ring); 2880 } 2881 break; 2882 } 2883 return 0; 2884 } 2885 2886 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2887 struct amdgpu_iv_entry *entry) 2888 { 2889 u8 me_id, pipe_id, queue_id; 2890 struct amdgpu_ring *ring; 2891 int i, xcc_id; 2892 2893 me_id = (entry->ring_id & 0x0c) >> 2; 2894 pipe_id = (entry->ring_id & 0x03) >> 0; 2895 queue_id = (entry->ring_id & 0x70) >> 4; 2896 2897 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2898 2899 if (xcc_id == -EINVAL) 2900 return; 2901 2902 switch (me_id) { 2903 case 0: 2904 case 1: 2905 case 2: 2906 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2907 ring = &adev->gfx.compute_ring 2908 [i + 2909 xcc_id * adev->gfx.num_compute_rings]; 2910 if (ring->me == me_id && ring->pipe == pipe_id && 2911 ring->queue == queue_id) 2912 drm_sched_fault(&ring->sched); 2913 } 2914 break; 2915 } 2916 } 2917 2918 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2919 struct amdgpu_irq_src *source, 2920 struct amdgpu_iv_entry *entry) 2921 { 2922 DRM_ERROR("Illegal register access in command stream\n"); 2923 gfx_v9_4_3_fault(adev, entry); 2924 return 0; 2925 } 2926 2927 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2928 struct amdgpu_irq_src *source, 2929 struct amdgpu_iv_entry *entry) 2930 { 2931 DRM_ERROR("Illegal instruction in command stream\n"); 2932 gfx_v9_4_3_fault(adev, entry); 2933 return 0; 2934 } 2935 2936 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 2937 { 2938 const unsigned int cp_coher_cntl = 2939 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 2940 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 2941 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 2942 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 2943 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 2944 2945 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 2946 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 2947 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 2948 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 2949 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 2950 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 2951 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 2952 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 2953 } 2954 2955 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 2956 uint32_t pipe, bool enable) 2957 { 2958 struct amdgpu_device *adev = ring->adev; 2959 uint32_t val; 2960 uint32_t wcl_cs_reg; 2961 2962 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 2963 val = enable ? 0x1 : 0x7f; 2964 2965 switch (pipe) { 2966 case 0: 2967 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 2968 break; 2969 case 1: 2970 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 2971 break; 2972 case 2: 2973 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 2974 break; 2975 case 3: 2976 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 2977 break; 2978 default: 2979 DRM_DEBUG("invalid pipe %d\n", pipe); 2980 return; 2981 } 2982 2983 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 2984 2985 } 2986 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 2987 { 2988 struct amdgpu_device *adev = ring->adev; 2989 uint32_t val; 2990 int i; 2991 2992 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 2993 * number of gfx waves. Setting 5 bit will make sure gfx only gets 2994 * around 25% of gpu resources. 2995 */ 2996 val = enable ? 0x1f : 0x07ffffff; 2997 amdgpu_ring_emit_wreg(ring, 2998 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 2999 val); 3000 3001 /* Restrict waves for normal/low priority compute queues as well 3002 * to get best QoS for high priority compute jobs. 3003 * 3004 * amdgpu controls only 1st ME(0-3 CS pipes). 3005 */ 3006 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3007 if (i != ring->pipe) 3008 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3009 3010 } 3011 } 3012 3013 enum amdgpu_gfx_cp_ras_mem_id { 3014 AMDGPU_GFX_CP_MEM1 = 1, 3015 AMDGPU_GFX_CP_MEM2, 3016 AMDGPU_GFX_CP_MEM3, 3017 AMDGPU_GFX_CP_MEM4, 3018 AMDGPU_GFX_CP_MEM5, 3019 }; 3020 3021 enum amdgpu_gfx_gcea_ras_mem_id { 3022 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3023 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3024 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3025 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3026 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3027 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3028 AMDGPU_GFX_GCEA_MAM_DMEM0, 3029 AMDGPU_GFX_GCEA_MAM_DMEM1, 3030 AMDGPU_GFX_GCEA_MAM_DMEM2, 3031 AMDGPU_GFX_GCEA_MAM_DMEM3, 3032 AMDGPU_GFX_GCEA_MAM_AMEM0, 3033 AMDGPU_GFX_GCEA_MAM_AMEM1, 3034 AMDGPU_GFX_GCEA_MAM_AMEM2, 3035 AMDGPU_GFX_GCEA_MAM_AMEM3, 3036 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3037 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3038 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3039 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3040 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3041 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3042 }; 3043 3044 enum amdgpu_gfx_gc_cane_ras_mem_id { 3045 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3046 }; 3047 3048 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3049 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3050 }; 3051 3052 enum amdgpu_gfx_gds_ras_mem_id { 3053 AMDGPU_GFX_GDS_MEM0 = 0, 3054 }; 3055 3056 enum amdgpu_gfx_lds_ras_mem_id { 3057 AMDGPU_GFX_LDS_BANK0 = 0, 3058 AMDGPU_GFX_LDS_BANK1, 3059 AMDGPU_GFX_LDS_BANK2, 3060 AMDGPU_GFX_LDS_BANK3, 3061 AMDGPU_GFX_LDS_BANK4, 3062 AMDGPU_GFX_LDS_BANK5, 3063 AMDGPU_GFX_LDS_BANK6, 3064 AMDGPU_GFX_LDS_BANK7, 3065 AMDGPU_GFX_LDS_BANK8, 3066 AMDGPU_GFX_LDS_BANK9, 3067 AMDGPU_GFX_LDS_BANK10, 3068 AMDGPU_GFX_LDS_BANK11, 3069 AMDGPU_GFX_LDS_BANK12, 3070 AMDGPU_GFX_LDS_BANK13, 3071 AMDGPU_GFX_LDS_BANK14, 3072 AMDGPU_GFX_LDS_BANK15, 3073 AMDGPU_GFX_LDS_BANK16, 3074 AMDGPU_GFX_LDS_BANK17, 3075 AMDGPU_GFX_LDS_BANK18, 3076 AMDGPU_GFX_LDS_BANK19, 3077 AMDGPU_GFX_LDS_BANK20, 3078 AMDGPU_GFX_LDS_BANK21, 3079 AMDGPU_GFX_LDS_BANK22, 3080 AMDGPU_GFX_LDS_BANK23, 3081 AMDGPU_GFX_LDS_BANK24, 3082 AMDGPU_GFX_LDS_BANK25, 3083 AMDGPU_GFX_LDS_BANK26, 3084 AMDGPU_GFX_LDS_BANK27, 3085 AMDGPU_GFX_LDS_BANK28, 3086 AMDGPU_GFX_LDS_BANK29, 3087 AMDGPU_GFX_LDS_BANK30, 3088 AMDGPU_GFX_LDS_BANK31, 3089 AMDGPU_GFX_LDS_SP_BUFFER_A, 3090 AMDGPU_GFX_LDS_SP_BUFFER_B, 3091 }; 3092 3093 enum amdgpu_gfx_rlc_ras_mem_id { 3094 AMDGPU_GFX_RLC_GPMF32 = 1, 3095 AMDGPU_GFX_RLC_RLCVF32, 3096 AMDGPU_GFX_RLC_SCRATCH, 3097 AMDGPU_GFX_RLC_SRM_ARAM, 3098 AMDGPU_GFX_RLC_SRM_DRAM, 3099 AMDGPU_GFX_RLC_TCTAG, 3100 AMDGPU_GFX_RLC_SPM_SE, 3101 AMDGPU_GFX_RLC_SPM_GRBMT, 3102 }; 3103 3104 enum amdgpu_gfx_sp_ras_mem_id { 3105 AMDGPU_GFX_SP_SIMDID0 = 0, 3106 }; 3107 3108 enum amdgpu_gfx_spi_ras_mem_id { 3109 AMDGPU_GFX_SPI_MEM0 = 0, 3110 AMDGPU_GFX_SPI_MEM1, 3111 AMDGPU_GFX_SPI_MEM2, 3112 AMDGPU_GFX_SPI_MEM3, 3113 }; 3114 3115 enum amdgpu_gfx_sqc_ras_mem_id { 3116 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3117 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3118 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3119 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3120 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3121 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3122 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3123 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3124 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3125 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3126 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3127 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3128 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3129 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3130 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3131 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3132 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3133 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3134 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3135 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3136 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3137 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3138 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3139 }; 3140 3141 enum amdgpu_gfx_sq_ras_mem_id { 3142 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3143 AMDGPU_GFX_SQ_SGPR_MEM1, 3144 AMDGPU_GFX_SQ_SGPR_MEM2, 3145 AMDGPU_GFX_SQ_SGPR_MEM3, 3146 }; 3147 3148 enum amdgpu_gfx_ta_ras_mem_id { 3149 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3150 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3151 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3152 AMDGPU_GFX_TA_FSX_LFIFO, 3153 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3154 }; 3155 3156 enum amdgpu_gfx_tcc_ras_mem_id { 3157 AMDGPU_GFX_TCC_MEM1 = 1, 3158 }; 3159 3160 enum amdgpu_gfx_tca_ras_mem_id { 3161 AMDGPU_GFX_TCA_MEM1 = 1, 3162 }; 3163 3164 enum amdgpu_gfx_tci_ras_mem_id { 3165 AMDGPU_GFX_TCIW_MEM = 1, 3166 }; 3167 3168 enum amdgpu_gfx_tcp_ras_mem_id { 3169 AMDGPU_GFX_TCP_LFIFO0 = 1, 3170 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3171 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3172 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3173 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3174 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3175 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3176 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3177 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3178 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3179 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3180 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3181 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3182 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3183 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3184 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3185 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3186 AMDGPU_GFX_TCP_VM_FIFO, 3187 AMDGPU_GFX_TCP_DB_TAGRAM0, 3188 AMDGPU_GFX_TCP_DB_TAGRAM1, 3189 AMDGPU_GFX_TCP_DB_TAGRAM2, 3190 AMDGPU_GFX_TCP_DB_TAGRAM3, 3191 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3192 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3193 AMDGPU_GFX_TCP_CMD_FIFO, 3194 }; 3195 3196 enum amdgpu_gfx_td_ras_mem_id { 3197 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3198 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3199 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3200 }; 3201 3202 enum amdgpu_gfx_tcx_ras_mem_id { 3203 AMDGPU_GFX_TCX_FIFOD0 = 0, 3204 AMDGPU_GFX_TCX_FIFOD1, 3205 AMDGPU_GFX_TCX_FIFOD2, 3206 AMDGPU_GFX_TCX_FIFOD3, 3207 AMDGPU_GFX_TCX_FIFOD4, 3208 AMDGPU_GFX_TCX_FIFOD5, 3209 AMDGPU_GFX_TCX_FIFOD6, 3210 AMDGPU_GFX_TCX_FIFOD7, 3211 AMDGPU_GFX_TCX_FIFOB0, 3212 AMDGPU_GFX_TCX_FIFOB1, 3213 AMDGPU_GFX_TCX_FIFOB2, 3214 AMDGPU_GFX_TCX_FIFOB3, 3215 AMDGPU_GFX_TCX_FIFOB4, 3216 AMDGPU_GFX_TCX_FIFOB5, 3217 AMDGPU_GFX_TCX_FIFOB6, 3218 AMDGPU_GFX_TCX_FIFOB7, 3219 AMDGPU_GFX_TCX_FIFOA0, 3220 AMDGPU_GFX_TCX_FIFOA1, 3221 AMDGPU_GFX_TCX_FIFOA2, 3222 AMDGPU_GFX_TCX_FIFOA3, 3223 AMDGPU_GFX_TCX_FIFOA4, 3224 AMDGPU_GFX_TCX_FIFOA5, 3225 AMDGPU_GFX_TCX_FIFOA6, 3226 AMDGPU_GFX_TCX_FIFOA7, 3227 AMDGPU_GFX_TCX_CFIFO0, 3228 AMDGPU_GFX_TCX_CFIFO1, 3229 AMDGPU_GFX_TCX_CFIFO2, 3230 AMDGPU_GFX_TCX_CFIFO3, 3231 AMDGPU_GFX_TCX_CFIFO4, 3232 AMDGPU_GFX_TCX_CFIFO5, 3233 AMDGPU_GFX_TCX_CFIFO6, 3234 AMDGPU_GFX_TCX_CFIFO7, 3235 AMDGPU_GFX_TCX_FIFO_ACKB0, 3236 AMDGPU_GFX_TCX_FIFO_ACKB1, 3237 AMDGPU_GFX_TCX_FIFO_ACKB2, 3238 AMDGPU_GFX_TCX_FIFO_ACKB3, 3239 AMDGPU_GFX_TCX_FIFO_ACKB4, 3240 AMDGPU_GFX_TCX_FIFO_ACKB5, 3241 AMDGPU_GFX_TCX_FIFO_ACKB6, 3242 AMDGPU_GFX_TCX_FIFO_ACKB7, 3243 AMDGPU_GFX_TCX_FIFO_ACKD0, 3244 AMDGPU_GFX_TCX_FIFO_ACKD1, 3245 AMDGPU_GFX_TCX_FIFO_ACKD2, 3246 AMDGPU_GFX_TCX_FIFO_ACKD3, 3247 AMDGPU_GFX_TCX_FIFO_ACKD4, 3248 AMDGPU_GFX_TCX_FIFO_ACKD5, 3249 AMDGPU_GFX_TCX_FIFO_ACKD6, 3250 AMDGPU_GFX_TCX_FIFO_ACKD7, 3251 AMDGPU_GFX_TCX_DST_FIFOA0, 3252 AMDGPU_GFX_TCX_DST_FIFOA1, 3253 AMDGPU_GFX_TCX_DST_FIFOA2, 3254 AMDGPU_GFX_TCX_DST_FIFOA3, 3255 AMDGPU_GFX_TCX_DST_FIFOA4, 3256 AMDGPU_GFX_TCX_DST_FIFOA5, 3257 AMDGPU_GFX_TCX_DST_FIFOA6, 3258 AMDGPU_GFX_TCX_DST_FIFOA7, 3259 AMDGPU_GFX_TCX_DST_FIFOB0, 3260 AMDGPU_GFX_TCX_DST_FIFOB1, 3261 AMDGPU_GFX_TCX_DST_FIFOB2, 3262 AMDGPU_GFX_TCX_DST_FIFOB3, 3263 AMDGPU_GFX_TCX_DST_FIFOB4, 3264 AMDGPU_GFX_TCX_DST_FIFOB5, 3265 AMDGPU_GFX_TCX_DST_FIFOB6, 3266 AMDGPU_GFX_TCX_DST_FIFOB7, 3267 AMDGPU_GFX_TCX_DST_FIFOD0, 3268 AMDGPU_GFX_TCX_DST_FIFOD1, 3269 AMDGPU_GFX_TCX_DST_FIFOD2, 3270 AMDGPU_GFX_TCX_DST_FIFOD3, 3271 AMDGPU_GFX_TCX_DST_FIFOD4, 3272 AMDGPU_GFX_TCX_DST_FIFOD5, 3273 AMDGPU_GFX_TCX_DST_FIFOD6, 3274 AMDGPU_GFX_TCX_DST_FIFOD7, 3275 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3276 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3277 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3278 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3279 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3280 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3281 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3282 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3283 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3284 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3285 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3286 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3287 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3288 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3289 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3290 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3291 }; 3292 3293 enum amdgpu_gfx_atc_l2_ras_mem_id { 3294 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3295 }; 3296 3297 enum amdgpu_gfx_utcl2_ras_mem_id { 3298 AMDGPU_GFX_UTCL2_MEM0 = 0, 3299 }; 3300 3301 enum amdgpu_gfx_vml2_ras_mem_id { 3302 AMDGPU_GFX_VML2_MEM0 = 0, 3303 }; 3304 3305 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3306 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3307 }; 3308 3309 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3310 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3311 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3312 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3313 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3314 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3315 }; 3316 3317 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3318 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3319 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3320 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3321 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3322 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3323 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3324 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3325 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3326 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3327 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3328 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3329 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3330 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3331 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3332 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3333 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3334 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3335 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3336 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3337 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3338 }; 3339 3340 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3341 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3342 }; 3343 3344 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3345 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3346 }; 3347 3348 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3349 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3350 }; 3351 3352 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3353 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3354 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3355 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3356 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3357 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3358 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3359 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3360 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3361 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3362 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3363 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3364 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3365 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3366 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3367 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3368 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3369 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3370 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3371 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3372 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3373 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3374 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3375 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3376 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3377 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3378 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3379 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3380 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3381 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3382 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3383 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3384 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3385 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3386 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3387 }; 3388 3389 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3390 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3391 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3392 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3393 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3394 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3395 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3396 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3397 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3398 }; 3399 3400 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3401 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3402 }; 3403 3404 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3405 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3406 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3407 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3408 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3409 }; 3410 3411 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3412 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3413 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3414 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3415 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3416 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3417 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3418 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3419 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3420 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3421 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3422 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3423 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3424 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3425 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3426 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3427 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3428 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3429 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3430 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3431 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3432 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3433 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3434 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3435 }; 3436 3437 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3438 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3439 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3440 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3441 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3442 }; 3443 3444 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3445 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3446 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3447 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3448 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3449 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3450 }; 3451 3452 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3453 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3454 }; 3455 3456 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3457 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3458 }; 3459 3460 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3461 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3462 }; 3463 3464 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3465 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3466 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3467 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3468 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3469 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3470 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3471 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3472 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3473 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3474 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3475 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3476 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3477 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3478 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3479 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3480 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3481 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3482 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3483 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3484 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3485 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3486 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3487 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3488 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3489 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3490 }; 3491 3492 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3493 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3494 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3495 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3496 }; 3497 3498 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3499 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3500 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3501 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3502 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3503 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3504 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3505 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3506 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3507 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3508 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3509 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3510 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3511 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3512 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3513 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3514 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3515 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3516 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3517 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3518 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3519 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3520 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3521 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3522 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3523 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3524 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3525 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3526 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3527 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3528 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3529 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3530 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3531 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3532 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3533 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3534 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3535 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3536 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3537 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3538 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3539 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3540 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3541 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3542 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3543 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3544 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3545 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3546 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3547 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3548 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3549 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3550 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3551 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3552 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3553 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3554 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3555 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3556 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3557 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3558 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3559 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3560 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3561 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3562 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3563 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3564 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3565 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3566 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3567 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3568 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3569 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3570 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3571 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3572 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3573 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3574 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3575 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3576 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3577 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3578 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3579 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3580 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3581 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3582 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3583 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3584 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3585 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3586 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3587 }; 3588 3589 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3590 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3591 }; 3592 3593 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3594 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3595 }; 3596 3597 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3598 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3599 }; 3600 3601 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3602 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3603 }; 3604 3605 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3606 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3607 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3608 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3609 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3610 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3611 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3612 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3613 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3614 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3615 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3616 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3617 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3618 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3619 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3620 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3621 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3622 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3623 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3624 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3625 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3626 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3627 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3628 }; 3629 3630 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3631 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3632 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3633 AMDGPU_GFX_RLC_MEM, 1}, 3634 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3635 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3636 AMDGPU_GFX_CP_MEM, 1}, 3637 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3638 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3639 AMDGPU_GFX_CP_MEM, 1}, 3640 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3641 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3642 AMDGPU_GFX_CP_MEM, 1}, 3643 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3644 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3645 AMDGPU_GFX_GDS_MEM, 1}, 3646 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3647 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3648 AMDGPU_GFX_GC_CANE_MEM, 1}, 3649 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3650 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3651 AMDGPU_GFX_SPI_MEM, 8}, 3652 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3653 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3654 AMDGPU_GFX_SP_MEM, 1}, 3655 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3656 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3657 AMDGPU_GFX_SP_MEM, 1}, 3658 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3659 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3660 AMDGPU_GFX_SQ_MEM, 8}, 3661 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3662 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3663 AMDGPU_GFX_SQC_MEM, 8}, 3664 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3665 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3666 AMDGPU_GFX_TCX_MEM, 1}, 3667 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3668 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3669 AMDGPU_GFX_TCC_MEM, 1}, 3670 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3671 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3672 AMDGPU_GFX_TA_MEM, 8}, 3673 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3674 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3675 AMDGPU_GFX_TCI_MEM, 1}, 3676 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3677 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3678 AMDGPU_GFX_TCP_MEM, 8}, 3679 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3680 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3681 AMDGPU_GFX_TD_MEM, 8}, 3682 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3683 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3684 AMDGPU_GFX_GCEA_MEM, 1}, 3685 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3686 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3687 AMDGPU_GFX_LDS_MEM, 1}, 3688 }; 3689 3690 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3691 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3692 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3693 AMDGPU_GFX_RLC_MEM, 1}, 3694 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3695 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3696 AMDGPU_GFX_CP_MEM, 1}, 3697 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3698 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3699 AMDGPU_GFX_CP_MEM, 1}, 3700 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3701 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3702 AMDGPU_GFX_CP_MEM, 1}, 3703 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3704 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3705 AMDGPU_GFX_GDS_MEM, 1}, 3706 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3707 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3708 AMDGPU_GFX_GC_CANE_MEM, 1}, 3709 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3710 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3711 AMDGPU_GFX_SPI_MEM, 8}, 3712 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3713 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3714 AMDGPU_GFX_SP_MEM, 1}, 3715 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3716 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3717 AMDGPU_GFX_SP_MEM, 1}, 3718 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3719 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3720 AMDGPU_GFX_SQ_MEM, 8}, 3721 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3722 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3723 AMDGPU_GFX_SQC_MEM, 8}, 3724 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3725 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3726 AMDGPU_GFX_TCX_MEM, 1}, 3727 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3728 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3729 AMDGPU_GFX_TCC_MEM, 1}, 3730 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3731 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3732 AMDGPU_GFX_TA_MEM, 8}, 3733 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3734 31, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3735 AMDGPU_GFX_TCI_MEM, 1}, 3736 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3737 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3738 AMDGPU_GFX_TCP_MEM, 8}, 3739 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3740 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3741 AMDGPU_GFX_TD_MEM, 8}, 3742 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3743 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3744 AMDGPU_GFX_TCA_MEM, 1}, 3745 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3746 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3747 AMDGPU_GFX_GCEA_MEM, 1}, 3748 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3749 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3750 AMDGPU_GFX_LDS_MEM, 1}, 3751 }; 3752 3753 static const struct soc15_reg_entry gfx_v9_4_3_ea_err_status_regs = { 3754 SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16 3755 }; 3756 3757 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3758 void *ras_error_status, int xcc_id) 3759 { 3760 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3761 unsigned long ce_count = 0, ue_count = 0; 3762 uint32_t i, j, k; 3763 3764 mutex_lock(&adev->grbm_idx_mutex); 3765 3766 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3767 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3768 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3769 /* no need to select if instance number is 1 */ 3770 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3771 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3772 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3773 3774 amdgpu_ras_inst_query_ras_error_count(adev, 3775 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3776 1, 3777 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3778 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3779 GET_INST(GC, xcc_id), 3780 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3781 &ce_count); 3782 3783 amdgpu_ras_inst_query_ras_error_count(adev, 3784 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3785 1, 3786 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3787 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3788 GET_INST(GC, xcc_id), 3789 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3790 &ue_count); 3791 } 3792 } 3793 } 3794 3795 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3796 xcc_id); 3797 mutex_unlock(&adev->grbm_idx_mutex); 3798 3799 /* the caller should make sure initialize value of 3800 * err_data->ue_count and err_data->ce_count 3801 */ 3802 err_data->ce_count += ce_count; 3803 err_data->ue_count += ue_count; 3804 } 3805 3806 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3807 void *ras_error_status, int xcc_id) 3808 { 3809 uint32_t i, j, k; 3810 3811 mutex_lock(&adev->grbm_idx_mutex); 3812 3813 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3814 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3815 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3816 /* no need to select if instance number is 1 */ 3817 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3818 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3819 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3820 3821 amdgpu_ras_inst_reset_ras_error_count(adev, 3822 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3823 1, 3824 GET_INST(GC, xcc_id)); 3825 3826 amdgpu_ras_inst_reset_ras_error_count(adev, 3827 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3828 1, 3829 GET_INST(GC, xcc_id)); 3830 } 3831 } 3832 } 3833 3834 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3835 xcc_id); 3836 mutex_unlock(&adev->grbm_idx_mutex); 3837 } 3838 3839 static void gfx_v9_4_3_inst_query_ea_err_status(struct amdgpu_device *adev, 3840 int xcc_id) 3841 { 3842 uint32_t i, j; 3843 uint32_t reg_value; 3844 3845 mutex_lock(&adev->grbm_idx_mutex); 3846 3847 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3848 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 3849 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 3850 reg_value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3851 regGCEA_ERR_STATUS); 3852 if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) || 3853 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) || 3854 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) { 3855 dev_warn(adev->dev, 3856 "GCEA err detected at instance: %d, status: 0x%x!\n", 3857 j, reg_value); 3858 } 3859 /* clear after read */ 3860 reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS, 3861 CLEAR_ERROR_STATUS, 0x1); 3862 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, 3863 reg_value); 3864 } 3865 } 3866 3867 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3868 xcc_id); 3869 mutex_unlock(&adev->grbm_idx_mutex); 3870 } 3871 3872 static void gfx_v9_4_3_inst_query_utc_err_status(struct amdgpu_device *adev, 3873 int xcc_id) 3874 { 3875 uint32_t data; 3876 3877 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS); 3878 if (data) { 3879 dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data); 3880 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3881 } 3882 3883 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS); 3884 if (data) { 3885 dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data); 3886 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3887 } 3888 3889 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3890 regVML2_WALKER_MEM_ECC_STATUS); 3891 if (data) { 3892 dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data); 3893 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 3894 0x3); 3895 } 3896 } 3897 3898 static void gfx_v9_4_3_log_cu_timeout_status(struct amdgpu_device *adev, 3899 uint32_t status, int xcc_id) 3900 { 3901 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 3902 uint32_t i, simd, wave; 3903 uint32_t wave_status; 3904 uint32_t wave_pc_lo, wave_pc_hi; 3905 uint32_t wave_exec_lo, wave_exec_hi; 3906 uint32_t wave_inst_dw0, wave_inst_dw1; 3907 uint32_t wave_ib_sts; 3908 3909 for (i = 0; i < 32; i++) { 3910 if (!((i << 1) & status)) 3911 continue; 3912 3913 simd = i / cu_info->max_waves_per_simd; 3914 wave = i % cu_info->max_waves_per_simd; 3915 3916 wave_status = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 3917 wave_pc_lo = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 3918 wave_pc_hi = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 3919 wave_exec_lo = 3920 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 3921 wave_exec_hi = 3922 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 3923 wave_inst_dw0 = 3924 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 3925 wave_inst_dw1 = 3926 wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 3927 wave_ib_sts = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 3928 3929 dev_info( 3930 adev->dev, 3931 "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n", 3932 simd, wave, wave_status, 3933 ((uint64_t)wave_pc_hi << 32 | wave_pc_lo), 3934 ((uint64_t)wave_exec_hi << 32 | wave_exec_lo), 3935 ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0), 3936 wave_ib_sts); 3937 } 3938 } 3939 3940 static void gfx_v9_4_3_inst_query_sq_timeout_status(struct amdgpu_device *adev, 3941 int xcc_id) 3942 { 3943 uint32_t se_idx, sh_idx, cu_idx; 3944 uint32_t status; 3945 3946 mutex_lock(&adev->grbm_idx_mutex); 3947 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 3948 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 3949 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 3950 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 3951 cu_idx, xcc_id); 3952 status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3953 regSQ_TIMEOUT_STATUS); 3954 if (status != 0) { 3955 dev_info( 3956 adev->dev, 3957 "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n", 3958 se_idx, sh_idx, cu_idx); 3959 gfx_v9_4_3_log_cu_timeout_status( 3960 adev, status, xcc_id); 3961 } 3962 /* clear old status */ 3963 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3964 regSQ_TIMEOUT_STATUS, 0); 3965 } 3966 } 3967 } 3968 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3969 xcc_id); 3970 mutex_unlock(&adev->grbm_idx_mutex); 3971 } 3972 3973 static void gfx_v9_4_3_inst_query_ras_err_status(struct amdgpu_device *adev, 3974 void *ras_error_status, int xcc_id) 3975 { 3976 gfx_v9_4_3_inst_query_ea_err_status(adev, xcc_id); 3977 gfx_v9_4_3_inst_query_utc_err_status(adev, xcc_id); 3978 gfx_v9_4_3_inst_query_sq_timeout_status(adev, xcc_id); 3979 } 3980 3981 static void gfx_v9_4_3_inst_reset_utc_err_status(struct amdgpu_device *adev, 3982 int xcc_id) 3983 { 3984 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regUTCL2_MEM_ECC_STATUS, 0x3); 3985 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_MEM_ECC_STATUS, 0x3); 3986 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regVML2_WALKER_MEM_ECC_STATUS, 0x3); 3987 } 3988 3989 static void gfx_v9_4_3_inst_reset_ea_err_status(struct amdgpu_device *adev, 3990 int xcc_id) 3991 { 3992 uint32_t i, j; 3993 uint32_t value; 3994 3995 mutex_lock(&adev->grbm_idx_mutex); 3996 for (i = 0; i < gfx_v9_4_3_ea_err_status_regs.se_num; i++) { 3997 for (j = 0; j < gfx_v9_4_3_ea_err_status_regs.instance; j++) { 3998 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0, j, xcc_id); 3999 value = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS); 4000 value = REG_SET_FIELD(value, GCEA_ERR_STATUS, 4001 CLEAR_ERROR_STATUS, 0x1); 4002 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGCEA_ERR_STATUS, value); 4003 } 4004 } 4005 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4006 xcc_id); 4007 mutex_unlock(&adev->grbm_idx_mutex); 4008 } 4009 4010 static void gfx_v9_4_3_inst_reset_sq_timeout_status(struct amdgpu_device *adev, 4011 int xcc_id) 4012 { 4013 uint32_t se_idx, sh_idx, cu_idx; 4014 4015 mutex_lock(&adev->grbm_idx_mutex); 4016 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) { 4017 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { 4018 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) { 4019 gfx_v9_4_3_xcc_select_se_sh(adev, se_idx, sh_idx, 4020 cu_idx, xcc_id); 4021 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 4022 regSQ_TIMEOUT_STATUS, 0); 4023 } 4024 } 4025 } 4026 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4027 xcc_id); 4028 mutex_unlock(&adev->grbm_idx_mutex); 4029 } 4030 4031 static void gfx_v9_4_3_inst_reset_ras_err_status(struct amdgpu_device *adev, 4032 void *ras_error_status, int xcc_id) 4033 { 4034 gfx_v9_4_3_inst_reset_utc_err_status(adev, xcc_id); 4035 gfx_v9_4_3_inst_reset_ea_err_status(adev, xcc_id); 4036 gfx_v9_4_3_inst_reset_sq_timeout_status(adev, xcc_id); 4037 } 4038 4039 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4040 void *ras_error_status, int xcc_id) 4041 { 4042 uint32_t i; 4043 uint32_t data; 4044 4045 data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4046 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4047 4048 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4049 (amdgpu_watchdog_timer.period < 1 || 4050 amdgpu_watchdog_timer.period > 0x23)) { 4051 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4052 amdgpu_watchdog_timer.period = 0x23; 4053 } 4054 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4055 amdgpu_watchdog_timer.period); 4056 4057 mutex_lock(&adev->grbm_idx_mutex); 4058 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4059 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4060 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4061 } 4062 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4063 xcc_id); 4064 mutex_unlock(&adev->grbm_idx_mutex); 4065 } 4066 4067 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4068 void *ras_error_status) 4069 { 4070 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4071 gfx_v9_4_3_inst_query_ras_err_count); 4072 } 4073 4074 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4075 { 4076 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4077 } 4078 4079 static void gfx_v9_4_3_query_ras_error_status(struct amdgpu_device *adev) 4080 { 4081 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_query_ras_err_status); 4082 } 4083 4084 static void gfx_v9_4_3_reset_ras_error_status(struct amdgpu_device *adev) 4085 { 4086 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_status); 4087 } 4088 4089 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4090 { 4091 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4092 } 4093 4094 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4095 .name = "gfx_v9_4_3", 4096 .early_init = gfx_v9_4_3_early_init, 4097 .late_init = gfx_v9_4_3_late_init, 4098 .sw_init = gfx_v9_4_3_sw_init, 4099 .sw_fini = gfx_v9_4_3_sw_fini, 4100 .hw_init = gfx_v9_4_3_hw_init, 4101 .hw_fini = gfx_v9_4_3_hw_fini, 4102 .suspend = gfx_v9_4_3_suspend, 4103 .resume = gfx_v9_4_3_resume, 4104 .is_idle = gfx_v9_4_3_is_idle, 4105 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4106 .soft_reset = gfx_v9_4_3_soft_reset, 4107 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4108 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4109 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4110 }; 4111 4112 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4113 .type = AMDGPU_RING_TYPE_COMPUTE, 4114 .align_mask = 0xff, 4115 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4116 .support_64bit_ptrs = true, 4117 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4118 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4119 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4120 .emit_frame_size = 4121 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4122 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4123 5 + /* hdp invalidate */ 4124 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4125 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4126 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4127 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4128 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4129 7 + /* gfx_v9_4_3_emit_mem_sync */ 4130 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4131 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4132 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4133 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4134 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4135 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4136 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4137 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4138 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4139 .test_ring = gfx_v9_4_3_ring_test_ring, 4140 .test_ib = gfx_v9_4_3_ring_test_ib, 4141 .insert_nop = amdgpu_ring_insert_nop, 4142 .pad_ib = amdgpu_ring_generic_pad_ib, 4143 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4144 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4145 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4146 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4147 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4148 }; 4149 4150 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4151 .type = AMDGPU_RING_TYPE_KIQ, 4152 .align_mask = 0xff, 4153 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4154 .support_64bit_ptrs = true, 4155 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4156 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4157 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4158 .emit_frame_size = 4159 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4160 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4161 5 + /* hdp invalidate */ 4162 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4163 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4164 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4165 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4166 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4167 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4168 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4169 .test_ring = gfx_v9_4_3_ring_test_ring, 4170 .insert_nop = amdgpu_ring_insert_nop, 4171 .pad_ib = amdgpu_ring_generic_pad_ib, 4172 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4173 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4174 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4175 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4176 }; 4177 4178 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4179 { 4180 int i, j, num_xcc; 4181 4182 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4183 for (i = 0; i < num_xcc; i++) { 4184 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4185 4186 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4187 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4188 = &gfx_v9_4_3_ring_funcs_compute; 4189 } 4190 } 4191 4192 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4193 .set = gfx_v9_4_3_set_eop_interrupt_state, 4194 .process = gfx_v9_4_3_eop_irq, 4195 }; 4196 4197 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4198 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4199 .process = gfx_v9_4_3_priv_reg_irq, 4200 }; 4201 4202 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4203 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4204 .process = gfx_v9_4_3_priv_inst_irq, 4205 }; 4206 4207 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4208 { 4209 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4210 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4211 4212 adev->gfx.priv_reg_irq.num_types = 1; 4213 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4214 4215 adev->gfx.priv_inst_irq.num_types = 1; 4216 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4217 } 4218 4219 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4220 { 4221 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4222 } 4223 4224 4225 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4226 { 4227 /* init asci gds info */ 4228 switch (adev->ip_versions[GC_HWIP][0]) { 4229 case IP_VERSION(9, 4, 3): 4230 /* 9.4.3 removed all the GDS internal memory, 4231 * only support GWS opcode in kernel, like barrier 4232 * semaphore.etc */ 4233 adev->gds.gds_size = 0; 4234 break; 4235 default: 4236 adev->gds.gds_size = 0x10000; 4237 break; 4238 } 4239 4240 switch (adev->ip_versions[GC_HWIP][0]) { 4241 case IP_VERSION(9, 4, 3): 4242 /* deprecated for 9.4.3, no usage at all */ 4243 adev->gds.gds_compute_max_wave_id = 0; 4244 break; 4245 default: 4246 /* this really depends on the chip */ 4247 adev->gds.gds_compute_max_wave_id = 0x7ff; 4248 break; 4249 } 4250 4251 adev->gds.gws_size = 64; 4252 adev->gds.oa_size = 16; 4253 } 4254 4255 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4256 u32 bitmap) 4257 { 4258 u32 data; 4259 4260 if (!bitmap) 4261 return; 4262 4263 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4264 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4265 4266 WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data); 4267 } 4268 4269 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) 4270 { 4271 u32 data, mask; 4272 4273 data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG); 4274 data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG); 4275 4276 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4277 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4278 4279 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4280 4281 return (~data) & mask; 4282 } 4283 4284 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4285 struct amdgpu_cu_info *cu_info) 4286 { 4287 int i, j, k, counter, active_cu_number = 0; 4288 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4289 unsigned disable_masks[4 * 4]; 4290 4291 if (!adev || !cu_info) 4292 return -EINVAL; 4293 4294 /* 4295 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4296 */ 4297 if (adev->gfx.config.max_shader_engines * 4298 adev->gfx.config.max_sh_per_se > 16) 4299 return -EINVAL; 4300 4301 amdgpu_gfx_parse_disable_cu(disable_masks, 4302 adev->gfx.config.max_shader_engines, 4303 adev->gfx.config.max_sh_per_se); 4304 4305 mutex_lock(&adev->grbm_idx_mutex); 4306 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4307 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4308 mask = 1; 4309 ao_bitmap = 0; 4310 counter = 0; 4311 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0); 4312 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4313 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 4314 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); 4315 4316 /* 4317 * The bitmap(and ao_cu_bitmap) in cu_info structure is 4318 * 4x4 size array, and it's usually suitable for Vega 4319 * ASICs which has 4*2 SE/SH layout. 4320 * But for Arcturus, SE/SH layout is changed to 8*1. 4321 * To mostly reduce the impact, we make it compatible 4322 * with current bitmap array as below: 4323 * SE4,SH0 --> bitmap[0][1] 4324 * SE5,SH0 --> bitmap[1][1] 4325 * SE6,SH0 --> bitmap[2][1] 4326 * SE7,SH0 --> bitmap[3][1] 4327 */ 4328 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 4329 4330 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4331 if (bitmap & mask) { 4332 if (counter < adev->gfx.config.max_cu_per_sh) 4333 ao_bitmap |= mask; 4334 counter++; 4335 } 4336 mask <<= 1; 4337 } 4338 active_cu_number += counter; 4339 if (i < 2 && j < 2) 4340 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4341 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 4342 } 4343 } 4344 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4345 0); 4346 mutex_unlock(&adev->grbm_idx_mutex); 4347 4348 cu_info->number = active_cu_number; 4349 cu_info->ao_cu_mask = ao_cu_mask; 4350 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4351 4352 return 0; 4353 } 4354 4355 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4356 .type = AMD_IP_BLOCK_TYPE_GFX, 4357 .major = 9, 4358 .minor = 4, 4359 .rev = 0, 4360 .funcs = &gfx_v9_4_3_ip_funcs, 4361 }; 4362 4363 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4364 { 4365 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4366 uint32_t tmp_mask; 4367 int i, r; 4368 4369 /* TODO : Initialize golden regs */ 4370 /* gfx_v9_4_3_init_golden_registers(adev); */ 4371 4372 tmp_mask = inst_mask; 4373 for_each_inst(i, tmp_mask) 4374 gfx_v9_4_3_xcc_constants_init(adev, i); 4375 4376 if (!amdgpu_sriov_vf(adev)) { 4377 tmp_mask = inst_mask; 4378 for_each_inst(i, tmp_mask) { 4379 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4380 if (r) 4381 return r; 4382 } 4383 } 4384 4385 tmp_mask = inst_mask; 4386 for_each_inst(i, tmp_mask) { 4387 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4388 if (r) 4389 return r; 4390 } 4391 4392 return 0; 4393 } 4394 4395 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4396 { 4397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4398 int i; 4399 4400 for_each_inst(i, inst_mask) 4401 gfx_v9_4_3_xcc_fini(adev, i); 4402 4403 return 0; 4404 } 4405 4406 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4407 .suspend = &gfx_v9_4_3_xcp_suspend, 4408 .resume = &gfx_v9_4_3_xcp_resume 4409 }; 4410 4411 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4412 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4413 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4414 .query_ras_error_status = &gfx_v9_4_3_query_ras_error_status, 4415 .reset_ras_error_status = &gfx_v9_4_3_reset_ras_error_status, 4416 }; 4417 4418 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4419 .ras_block = { 4420 .hw_ops = &gfx_v9_4_3_ras_ops, 4421 }, 4422 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4423 }; 4424