1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* SE status registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 110 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 111 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 113 }; 114 115 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 116 /* compute queue registers */ 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 162 }; 163 164 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 165 166 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 167 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 168 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 169 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 170 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 171 struct amdgpu_cu_info *cu_info); 172 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 173 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 174 175 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 176 uint64_t queue_mask) 177 { 178 struct amdgpu_device *adev = kiq_ring->adev; 179 u64 shader_mc_addr; 180 181 /* Cleaner shader MC address */ 182 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 183 184 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 185 amdgpu_ring_write(kiq_ring, 186 PACKET3_SET_RESOURCES_VMID_MASK(0) | 187 /* vmid_mask:0* queue_type:0 (KIQ) */ 188 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 189 amdgpu_ring_write(kiq_ring, 190 lower_32_bits(queue_mask)); /* queue mask lo */ 191 amdgpu_ring_write(kiq_ring, 192 upper_32_bits(queue_mask)); /* queue mask hi */ 193 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 194 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 195 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 196 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 197 } 198 199 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 200 struct amdgpu_ring *ring) 201 { 202 struct amdgpu_device *adev = kiq_ring->adev; 203 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 204 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 205 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 206 207 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 208 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 209 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 210 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 211 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 212 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 213 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 214 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 215 /*queue_type: normal compute queue */ 216 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 217 /* alloc format: all_on_one_pipe */ 218 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 219 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 220 /* num_queues: must be 1 */ 221 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 222 amdgpu_ring_write(kiq_ring, 223 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 224 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 225 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 226 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 227 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 228 } 229 230 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 231 struct amdgpu_ring *ring, 232 enum amdgpu_unmap_queues_action action, 233 u64 gpu_addr, u64 seq) 234 { 235 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 236 237 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 238 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 239 PACKET3_UNMAP_QUEUES_ACTION(action) | 240 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 241 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 242 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 243 amdgpu_ring_write(kiq_ring, 244 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 245 246 if (action == PREEMPT_QUEUES_NO_UNMAP) { 247 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 248 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 249 amdgpu_ring_write(kiq_ring, seq); 250 } else { 251 amdgpu_ring_write(kiq_ring, 0); 252 amdgpu_ring_write(kiq_ring, 0); 253 amdgpu_ring_write(kiq_ring, 0); 254 } 255 } 256 257 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 258 struct amdgpu_ring *ring, 259 u64 addr, 260 u64 seq) 261 { 262 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 263 264 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 267 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 268 PACKET3_QUERY_STATUS_COMMAND(2)); 269 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 270 amdgpu_ring_write(kiq_ring, 271 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 272 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 273 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 274 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 275 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 276 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 277 } 278 279 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 280 uint16_t pasid, uint32_t flush_type, 281 bool all_hub) 282 { 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 284 amdgpu_ring_write(kiq_ring, 285 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 286 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 287 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 288 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 289 } 290 291 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 292 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 293 uint32_t xcc_id, uint32_t vmid) 294 { 295 struct amdgpu_device *adev = kiq_ring->adev; 296 unsigned i; 297 298 /* enter save mode */ 299 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 300 mutex_lock(&adev->srbm_mutex); 301 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 302 303 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 305 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 306 /* wait till dequeue take effects */ 307 for (i = 0; i < adev->usec_timeout; i++) { 308 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 309 break; 310 udelay(1); 311 } 312 if (i >= adev->usec_timeout) 313 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 314 } else { 315 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 316 } 317 318 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 319 mutex_unlock(&adev->srbm_mutex); 320 /* exit safe mode */ 321 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 322 } 323 324 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 325 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 326 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 327 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 328 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 329 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 330 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 331 .set_resources_size = 8, 332 .map_queues_size = 7, 333 .unmap_queues_size = 6, 334 .query_status_size = 7, 335 .invalidate_tlbs_size = 2, 336 }; 337 338 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 339 { 340 int i, num_xcc; 341 342 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 343 for (i = 0; i < num_xcc; i++) 344 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 345 } 346 347 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 348 { 349 int i, num_xcc, dev_inst; 350 351 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 352 for (i = 0; i < num_xcc; i++) { 353 dev_inst = GET_INST(GC, i); 354 355 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 356 GOLDEN_GB_ADDR_CONFIG); 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 358 } 359 } 360 361 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 362 { 363 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 364 365 /* If it is an XCC reg, normalize the reg to keep 366 lower 16 bits in local xcc */ 367 368 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 369 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 370 return normalized_reg; 371 else 372 return reg; 373 } 374 375 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 376 bool wc, uint32_t reg, uint32_t val) 377 { 378 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 379 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 380 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 381 WRITE_DATA_DST_SEL(0) | 382 (wc ? WR_CONFIRM : 0)); 383 amdgpu_ring_write(ring, reg); 384 amdgpu_ring_write(ring, 0); 385 amdgpu_ring_write(ring, val); 386 } 387 388 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 389 int mem_space, int opt, uint32_t addr0, 390 uint32_t addr1, uint32_t ref, uint32_t mask, 391 uint32_t inv) 392 { 393 /* Only do the normalization on regspace */ 394 if (mem_space == 0) { 395 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 396 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 397 } 398 399 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 400 amdgpu_ring_write(ring, 401 /* memory (1) or register (0) */ 402 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 403 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 404 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 405 WAIT_REG_MEM_ENGINE(eng_sel))); 406 407 if (mem_space) 408 BUG_ON(addr0 & 0x3); /* Dword align */ 409 amdgpu_ring_write(ring, addr0); 410 amdgpu_ring_write(ring, addr1); 411 amdgpu_ring_write(ring, ref); 412 amdgpu_ring_write(ring, mask); 413 amdgpu_ring_write(ring, inv); /* poll interval */ 414 } 415 416 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 417 { 418 uint32_t scratch_reg0_offset, xcc_offset; 419 struct amdgpu_device *adev = ring->adev; 420 uint32_t tmp = 0; 421 unsigned i; 422 int r; 423 424 /* Use register offset which is local to XCC in the packet */ 425 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 426 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 427 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 428 tmp = RREG32(scratch_reg0_offset); 429 430 r = amdgpu_ring_alloc(ring, 3); 431 if (r) 432 return r; 433 434 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 435 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 436 amdgpu_ring_write(ring, 0xDEADBEEF); 437 amdgpu_ring_commit(ring); 438 439 for (i = 0; i < adev->usec_timeout; i++) { 440 tmp = RREG32(scratch_reg0_offset); 441 if (tmp == 0xDEADBEEF) 442 break; 443 udelay(1); 444 } 445 446 if (i >= adev->usec_timeout) 447 r = -ETIMEDOUT; 448 return r; 449 } 450 451 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 struct amdgpu_ib ib; 455 struct dma_fence *f = NULL; 456 457 unsigned index; 458 uint64_t gpu_addr; 459 uint32_t tmp; 460 long r; 461 462 r = amdgpu_device_wb_get(adev, &index); 463 if (r) 464 return r; 465 466 gpu_addr = adev->wb.gpu_addr + (index * 4); 467 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 468 memset(&ib, 0, sizeof(ib)); 469 470 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 471 if (r) 472 goto err1; 473 474 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 475 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 476 ib.ptr[2] = lower_32_bits(gpu_addr); 477 ib.ptr[3] = upper_32_bits(gpu_addr); 478 ib.ptr[4] = 0xDEADBEEF; 479 ib.length_dw = 5; 480 481 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 482 if (r) 483 goto err2; 484 485 r = dma_fence_wait_timeout(f, false, timeout); 486 if (r == 0) { 487 r = -ETIMEDOUT; 488 goto err2; 489 } else if (r < 0) { 490 goto err2; 491 } 492 493 tmp = adev->wb.wb[index]; 494 if (tmp == 0xDEADBEEF) 495 r = 0; 496 else 497 r = -EINVAL; 498 499 err2: 500 amdgpu_ib_free(&ib, NULL); 501 dma_fence_put(f); 502 err1: 503 amdgpu_device_wb_free(adev, index); 504 return r; 505 } 506 507 508 /* This value might differs per partition */ 509 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 510 { 511 uint64_t clock; 512 513 mutex_lock(&adev->gfx.gpu_clock_mutex); 514 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 515 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 516 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 517 mutex_unlock(&adev->gfx.gpu_clock_mutex); 518 519 return clock; 520 } 521 522 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 523 { 524 amdgpu_ucode_release(&adev->gfx.pfp_fw); 525 amdgpu_ucode_release(&adev->gfx.me_fw); 526 amdgpu_ucode_release(&adev->gfx.ce_fw); 527 amdgpu_ucode_release(&adev->gfx.rlc_fw); 528 amdgpu_ucode_release(&adev->gfx.mec_fw); 529 amdgpu_ucode_release(&adev->gfx.mec2_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 535 const char *chip_name) 536 { 537 int err; 538 const struct rlc_firmware_header_v2_0 *rlc_hdr; 539 uint16_t version_major; 540 uint16_t version_minor; 541 542 543 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 544 AMDGPU_UCODE_REQUIRED, 545 "amdgpu/%s_rlc.bin", chip_name); 546 if (err) 547 goto out; 548 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 549 550 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 551 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 552 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 553 out: 554 if (err) 555 amdgpu_ucode_release(&adev->gfx.rlc_fw); 556 557 return err; 558 } 559 560 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 561 const char *chip_name) 562 { 563 int err; 564 565 if (amdgpu_sriov_vf(adev)) { 566 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 567 AMDGPU_UCODE_REQUIRED, 568 "amdgpu/%s_sjt_mec.bin", chip_name); 569 570 if (err) 571 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 572 AMDGPU_UCODE_REQUIRED, 573 "amdgpu/%s_mec.bin", chip_name); 574 } else 575 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 576 AMDGPU_UCODE_REQUIRED, 577 "amdgpu/%s_mec.bin", chip_name); 578 if (err) 579 goto out; 580 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 581 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 582 583 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 584 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 585 586 out: 587 if (err) 588 amdgpu_ucode_release(&adev->gfx.mec_fw); 589 return err; 590 } 591 592 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 593 { 594 char ucode_prefix[15]; 595 int r; 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 600 if (r) 601 return r; 602 603 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 604 if (r) 605 return r; 606 607 return r; 608 } 609 610 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 611 { 612 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 613 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 614 } 615 616 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 617 { 618 int r, i, num_xcc; 619 u32 *hpd; 620 const __le32 *fw_data; 621 unsigned fw_size; 622 u32 *fw; 623 size_t mec_hpd_size; 624 625 const struct gfx_firmware_header_v1_0 *mec_hdr; 626 627 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 628 for (i = 0; i < num_xcc; i++) 629 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 630 AMDGPU_MAX_COMPUTE_QUEUES); 631 632 /* take ownership of the relevant compute queues */ 633 amdgpu_gfx_compute_queue_acquire(adev); 634 mec_hpd_size = 635 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 636 if (mec_hpd_size) { 637 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 638 AMDGPU_GEM_DOMAIN_VRAM | 639 AMDGPU_GEM_DOMAIN_GTT, 640 &adev->gfx.mec.hpd_eop_obj, 641 &adev->gfx.mec.hpd_eop_gpu_addr, 642 (void **)&hpd); 643 if (r) { 644 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 645 gfx_v9_4_3_mec_fini(adev); 646 return r; 647 } 648 649 if (amdgpu_emu_mode == 1) { 650 for (i = 0; i < mec_hpd_size / 4; i++) { 651 memset((void *)(hpd + i), 0, 4); 652 if (i % 50 == 0) 653 msleep(1); 654 } 655 } else { 656 memset(hpd, 0, mec_hpd_size); 657 } 658 659 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 660 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 661 } 662 663 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 664 665 fw_data = (const __le32 *) 666 (adev->gfx.mec_fw->data + 667 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 668 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 669 670 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 671 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 672 &adev->gfx.mec.mec_fw_obj, 673 &adev->gfx.mec.mec_fw_gpu_addr, 674 (void **)&fw); 675 if (r) { 676 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 677 gfx_v9_4_3_mec_fini(adev); 678 return r; 679 } 680 681 memcpy(fw, fw_data, fw_size); 682 683 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 684 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 685 686 return 0; 687 } 688 689 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 690 u32 sh_num, u32 instance, int xcc_id) 691 { 692 u32 data; 693 694 if (instance == 0xffffffff) 695 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 696 INSTANCE_BROADCAST_WRITES, 1); 697 else 698 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 699 INSTANCE_INDEX, instance); 700 701 if (se_num == 0xffffffff) 702 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 703 SE_BROADCAST_WRITES, 1); 704 else 705 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 706 707 if (sh_num == 0xffffffff) 708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 709 SH_BROADCAST_WRITES, 1); 710 else 711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 712 713 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 714 } 715 716 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 717 { 718 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 719 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 720 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 721 (address << SQ_IND_INDEX__INDEX__SHIFT) | 722 (SQ_IND_INDEX__FORCE_READ_MASK)); 723 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 724 } 725 726 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 727 uint32_t wave, uint32_t thread, 728 uint32_t regno, uint32_t num, uint32_t *out) 729 { 730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 731 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 732 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 733 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 734 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 735 (SQ_IND_INDEX__FORCE_READ_MASK) | 736 (SQ_IND_INDEX__AUTO_INCR_MASK)); 737 while (num--) 738 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 739 } 740 741 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 742 uint32_t xcc_id, uint32_t simd, uint32_t wave, 743 uint32_t *dst, int *no_fields) 744 { 745 /* type 1 wave data */ 746 dst[(*no_fields)++] = 1; 747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 761 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 762 } 763 764 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 765 uint32_t wave, uint32_t start, 766 uint32_t size, uint32_t *dst) 767 { 768 wave_read_regs(adev, xcc_id, simd, wave, 0, 769 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 770 } 771 772 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 773 uint32_t wave, uint32_t thread, 774 uint32_t start, uint32_t size, 775 uint32_t *dst) 776 { 777 wave_read_regs(adev, xcc_id, simd, wave, thread, 778 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 779 } 780 781 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 782 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 783 { 784 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 785 } 786 787 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 788 { 789 u32 xcp_ctl; 790 791 /* Value is expected to be the same on all, fetch from first instance */ 792 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 793 794 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 795 } 796 797 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 798 int num_xccs_per_xcp) 799 { 800 int ret, i, num_xcc; 801 u32 tmp = 0; 802 803 if (adev->psp.funcs) { 804 ret = psp_spatial_partition(&adev->psp, 805 NUM_XCC(adev->gfx.xcc_mask) / 806 num_xccs_per_xcp); 807 if (ret) 808 return ret; 809 } else { 810 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 811 812 for (i = 0; i < num_xcc; i++) { 813 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 814 num_xccs_per_xcp); 815 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 816 i % num_xccs_per_xcp); 817 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 818 tmp); 819 } 820 ret = 0; 821 } 822 823 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 824 825 return ret; 826 } 827 828 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 829 { 830 int xcc; 831 832 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 833 if (!xcc) { 834 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 835 return -EINVAL; 836 } 837 838 return xcc - 1; 839 } 840 841 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 842 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 843 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 844 .read_wave_data = &gfx_v9_4_3_read_wave_data, 845 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 846 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 847 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 848 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 849 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 850 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 851 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 852 }; 853 854 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 855 struct aca_bank *bank, enum aca_smu_type type, 856 void *data) 857 { 858 struct aca_bank_info info; 859 u64 misc0; 860 u32 instlo; 861 int ret; 862 863 ret = aca_bank_info_decode(bank, &info); 864 if (ret) 865 return ret; 866 867 /* NOTE: overwrite info.die_id with xcd id for gfx */ 868 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 869 instlo &= GENMASK(31, 1); 870 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 871 872 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 873 874 switch (type) { 875 case ACA_SMU_TYPE_UE: 876 bank->aca_err_type = ACA_ERROR_TYPE_UE; 877 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL); 878 break; 879 case ACA_SMU_TYPE_CE: 880 bank->aca_err_type = ACA_ERROR_TYPE_CE; 881 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 882 ACA_REG__MISC0__ERRCNT(misc0)); 883 break; 884 default: 885 return -EINVAL; 886 } 887 888 return ret; 889 } 890 891 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 892 enum aca_smu_type type, void *data) 893 { 894 u32 instlo; 895 896 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 897 instlo &= GENMASK(31, 1); 898 switch (instlo) { 899 case mmSMNAID_XCD0_MCA_SMU: 900 case mmSMNAID_XCD1_MCA_SMU: 901 case mmSMNXCD_XCD0_MCA_SMU: 902 return true; 903 default: 904 break; 905 } 906 907 return false; 908 } 909 910 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 911 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 912 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 913 }; 914 915 static const struct aca_info gfx_v9_4_3_aca_info = { 916 .hwip = ACA_HWIP_TYPE_SMU, 917 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 918 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 919 }; 920 921 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 922 { 923 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 924 adev->gfx.ras = &gfx_v9_4_3_ras; 925 926 adev->gfx.config.max_hw_contexts = 8; 927 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 928 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 929 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 930 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 931 adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG; 932 933 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 934 REG_GET_FIELD( 935 adev->gfx.config.gb_addr_config, 936 GB_ADDR_CONFIG, 937 NUM_PIPES); 938 939 adev->gfx.config.max_tile_pipes = 940 adev->gfx.config.gb_addr_config_fields.num_pipes; 941 942 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 943 REG_GET_FIELD( 944 adev->gfx.config.gb_addr_config, 945 GB_ADDR_CONFIG, 946 NUM_BANKS); 947 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 948 REG_GET_FIELD( 949 adev->gfx.config.gb_addr_config, 950 GB_ADDR_CONFIG, 951 MAX_COMPRESSED_FRAGS); 952 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 953 REG_GET_FIELD( 954 adev->gfx.config.gb_addr_config, 955 GB_ADDR_CONFIG, 956 NUM_RB_PER_SE); 957 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 958 REG_GET_FIELD( 959 adev->gfx.config.gb_addr_config, 960 GB_ADDR_CONFIG, 961 NUM_SHADER_ENGINES); 962 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 963 REG_GET_FIELD( 964 adev->gfx.config.gb_addr_config, 965 GB_ADDR_CONFIG, 966 PIPE_INTERLEAVE_SIZE)); 967 968 return 0; 969 } 970 971 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 972 int xcc_id, int mec, int pipe, int queue) 973 { 974 unsigned irq_type; 975 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 976 unsigned int hw_prio; 977 uint32_t xcc_doorbell_start; 978 979 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 980 ring_id]; 981 982 /* mec0 is me1 */ 983 ring->xcc_id = xcc_id; 984 ring->me = mec + 1; 985 ring->pipe = pipe; 986 ring->queue = queue; 987 988 ring->ring_obj = NULL; 989 ring->use_doorbell = true; 990 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 991 xcc_id * adev->doorbell_index.xcc_doorbell_range; 992 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 993 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 994 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 995 GFX9_MEC_HPD_SIZE; 996 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 997 sprintf(ring->name, "comp_%d.%d.%d.%d", 998 ring->xcc_id, ring->me, ring->pipe, ring->queue); 999 1000 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1001 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1002 + ring->pipe; 1003 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1004 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1005 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1006 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1007 hw_prio, NULL); 1008 } 1009 1010 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1011 { 1012 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1013 uint32_t *ptr, num_xcc, inst; 1014 1015 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1016 1017 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1018 if (!ptr) { 1019 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1020 adev->gfx.ip_dump_core = NULL; 1021 } else { 1022 adev->gfx.ip_dump_core = ptr; 1023 } 1024 1025 /* Allocate memory for compute queue registers for all the instances */ 1026 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1027 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1028 adev->gfx.mec.num_queue_per_pipe; 1029 1030 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1031 if (!ptr) { 1032 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1033 adev->gfx.ip_dump_compute_queues = NULL; 1034 } else { 1035 adev->gfx.ip_dump_compute_queues = ptr; 1036 } 1037 } 1038 1039 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1040 { 1041 int i, j, k, r, ring_id, xcc_id, num_xcc; 1042 struct amdgpu_device *adev = ip_block->adev; 1043 1044 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1045 case IP_VERSION(9, 4, 3): 1046 case IP_VERSION(9, 4, 4): 1047 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1048 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1049 if (adev->gfx.mec_fw_version >= 153) { 1050 adev->gfx.enable_cleaner_shader = true; 1051 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1052 if (r) { 1053 adev->gfx.enable_cleaner_shader = false; 1054 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1055 } 1056 } 1057 break; 1058 default: 1059 adev->gfx.enable_cleaner_shader = false; 1060 break; 1061 } 1062 1063 adev->gfx.mec.num_mec = 2; 1064 adev->gfx.mec.num_pipe_per_mec = 4; 1065 adev->gfx.mec.num_queue_per_pipe = 8; 1066 1067 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1068 1069 /* EOP Event */ 1070 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1071 if (r) 1072 return r; 1073 1074 /* Bad opcode Event */ 1075 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1076 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1077 &adev->gfx.bad_op_irq); 1078 if (r) 1079 return r; 1080 1081 /* Privileged reg */ 1082 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1083 &adev->gfx.priv_reg_irq); 1084 if (r) 1085 return r; 1086 1087 /* Privileged inst */ 1088 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1089 &adev->gfx.priv_inst_irq); 1090 if (r) 1091 return r; 1092 1093 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1094 1095 r = adev->gfx.rlc.funcs->init(adev); 1096 if (r) { 1097 DRM_ERROR("Failed to init rlc BOs!\n"); 1098 return r; 1099 } 1100 1101 r = gfx_v9_4_3_mec_init(adev); 1102 if (r) { 1103 DRM_ERROR("Failed to init MEC BOs!\n"); 1104 return r; 1105 } 1106 1107 /* set up the compute queues - allocate horizontally across pipes */ 1108 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1109 ring_id = 0; 1110 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1111 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1112 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1113 k++) { 1114 if (!amdgpu_gfx_is_mec_queue_enabled( 1115 adev, xcc_id, i, k, j)) 1116 continue; 1117 1118 r = gfx_v9_4_3_compute_ring_init(adev, 1119 ring_id, 1120 xcc_id, 1121 i, k, j); 1122 if (r) 1123 return r; 1124 1125 ring_id++; 1126 } 1127 } 1128 } 1129 1130 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1131 if (r) { 1132 DRM_ERROR("Failed to init KIQ BOs!\n"); 1133 return r; 1134 } 1135 1136 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1137 if (r) 1138 return r; 1139 1140 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1141 r = amdgpu_gfx_mqd_sw_init(adev, 1142 sizeof(struct v9_mqd_allocation), xcc_id); 1143 if (r) 1144 return r; 1145 } 1146 1147 adev->gfx.compute_supported_reset = 1148 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1149 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1150 case IP_VERSION(9, 4, 3): 1151 case IP_VERSION(9, 4, 4): 1152 if ((adev->gfx.mec_fw_version >= 155) && 1153 !amdgpu_sriov_vf(adev) && 1154 !adev->debug_disable_gpu_ring_reset) { 1155 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1156 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1157 } 1158 break; 1159 case IP_VERSION(9, 5, 0): 1160 if ((adev->gfx.mec_fw_version >= 21) && 1161 !amdgpu_sriov_vf(adev) && 1162 !adev->debug_disable_gpu_ring_reset) { 1163 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1164 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1165 } 1166 break; 1167 default: 1168 break; 1169 } 1170 r = gfx_v9_4_3_gpu_early_init(adev); 1171 if (r) 1172 return r; 1173 1174 r = amdgpu_gfx_ras_sw_init(adev); 1175 if (r) 1176 return r; 1177 1178 r = amdgpu_gfx_sysfs_init(adev); 1179 if (r) 1180 return r; 1181 1182 gfx_v9_4_3_alloc_ip_dump(adev); 1183 1184 return 0; 1185 } 1186 1187 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1188 { 1189 int i, num_xcc; 1190 struct amdgpu_device *adev = ip_block->adev; 1191 1192 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1193 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1194 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1195 1196 for (i = 0; i < num_xcc; i++) { 1197 amdgpu_gfx_mqd_sw_fini(adev, i); 1198 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1199 amdgpu_gfx_kiq_fini(adev, i); 1200 } 1201 1202 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1203 1204 gfx_v9_4_3_mec_fini(adev); 1205 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1206 gfx_v9_4_3_free_microcode(adev); 1207 amdgpu_gfx_sysfs_fini(adev); 1208 1209 kfree(adev->gfx.ip_dump_core); 1210 kfree(adev->gfx.ip_dump_compute_queues); 1211 1212 return 0; 1213 } 1214 1215 #define DEFAULT_SH_MEM_BASES (0x6000) 1216 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1217 int xcc_id) 1218 { 1219 int i; 1220 uint32_t sh_mem_config; 1221 uint32_t sh_mem_bases; 1222 uint32_t data; 1223 1224 /* 1225 * Configure apertures: 1226 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1227 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1228 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1229 */ 1230 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1231 1232 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1233 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1234 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1235 1236 mutex_lock(&adev->srbm_mutex); 1237 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1238 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1239 /* CP and shaders */ 1240 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1241 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1242 1243 /* Enable trap for each kfd vmid. */ 1244 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1245 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1246 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1247 } 1248 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1249 mutex_unlock(&adev->srbm_mutex); 1250 1251 /* 1252 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1253 * access. These should be enabled by FW for target VMIDs. 1254 */ 1255 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1256 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1257 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1258 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1259 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1260 } 1261 } 1262 1263 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1264 { 1265 int vmid; 1266 1267 /* 1268 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1269 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1270 * the driver can enable them for graphics. VMID0 should maintain 1271 * access so that HWS firmware can save/restore entries. 1272 */ 1273 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1274 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1275 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1276 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1277 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1278 } 1279 } 1280 1281 /* For ASICs that needs xnack chain and MEC version supports, set SG_CONFIG1 1282 * DISABLE_XNACK_CHECK_IN_RETRY_DISABLE bit and inform KFD to set xnack_chain 1283 * bit in SET_RESOURCES 1284 */ 1285 static void gfx_v9_4_3_xcc_init_sq(struct amdgpu_device *adev, int xcc_id) 1286 { 1287 uint32_t data; 1288 1289 if (!(adev->gmc.xnack_flags & AMDGPU_GMC_XNACK_FLAG_CHAIN)) 1290 return; 1291 1292 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1); 1293 data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1); 1294 WREG32_SOC15(GC, xcc_id, regSQ_CONFIG1, data); 1295 } 1296 1297 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1298 int xcc_id) 1299 { 1300 u32 tmp; 1301 int i; 1302 1303 /* XXX SH_MEM regs */ 1304 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1305 mutex_lock(&adev->srbm_mutex); 1306 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1307 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1308 /* CP and shaders */ 1309 if (i == 0) { 1310 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1311 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1312 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1313 !!adev->gmc.noretry); 1314 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1315 regSH_MEM_CONFIG, tmp); 1316 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1317 regSH_MEM_BASES, 0); 1318 } else { 1319 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1320 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1321 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1322 !!adev->gmc.noretry); 1323 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1324 regSH_MEM_CONFIG, tmp); 1325 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1326 (adev->gmc.private_aperture_start >> 1327 48)); 1328 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1329 (adev->gmc.shared_aperture_start >> 1330 48)); 1331 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1332 regSH_MEM_BASES, tmp); 1333 } 1334 } 1335 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1336 1337 mutex_unlock(&adev->srbm_mutex); 1338 1339 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1340 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1341 gfx_v9_4_3_xcc_init_sq(adev, xcc_id); 1342 } 1343 1344 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1345 { 1346 int i, num_xcc; 1347 1348 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1349 1350 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1351 adev->gfx.config.db_debug2 = 1352 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1353 1354 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1355 /* ToDo: GC 9.4.4 */ 1356 case IP_VERSION(9, 4, 3): 1357 if (adev->gfx.mec_fw_version >= 184 && 1358 (amdgpu_sriov_reg_access_sq_config(adev) || 1359 !amdgpu_sriov_vf(adev))) 1360 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1361 break; 1362 case IP_VERSION(9, 5, 0): 1363 if (adev->gfx.mec_fw_version >= 23) 1364 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1365 break; 1366 default: 1367 break; 1368 } 1369 1370 for (i = 0; i < num_xcc; i++) 1371 gfx_v9_4_3_xcc_constants_init(adev, i); 1372 } 1373 1374 static void 1375 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1376 int xcc_id) 1377 { 1378 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1379 } 1380 1381 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1382 { 1383 /* 1384 * Rlc save restore list is workable since v2_1. 1385 */ 1386 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1387 } 1388 1389 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1390 { 1391 uint32_t data; 1392 1393 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1394 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1395 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1396 } 1397 1398 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1399 { 1400 uint32_t rlc_setting; 1401 1402 /* if RLC is not enabled, do nothing */ 1403 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1404 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1405 return false; 1406 1407 return true; 1408 } 1409 1410 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1411 { 1412 uint32_t data; 1413 unsigned i; 1414 1415 data = RLC_SAFE_MODE__CMD_MASK; 1416 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1417 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1418 1419 /* wait for RLC_SAFE_MODE */ 1420 for (i = 0; i < adev->usec_timeout; i++) { 1421 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1422 break; 1423 udelay(1); 1424 } 1425 } 1426 1427 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1428 int xcc_id) 1429 { 1430 uint32_t data; 1431 1432 data = RLC_SAFE_MODE__CMD_MASK; 1433 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1434 } 1435 1436 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1437 { 1438 int xcc_id, num_xcc; 1439 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1440 1441 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1442 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1443 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1444 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1445 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1446 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1447 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1448 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1449 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1450 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1451 } 1452 adev->gfx.rlc.rlcg_reg_access_supported = true; 1453 } 1454 1455 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1456 { 1457 /* init spm vmid with 0xf */ 1458 if (adev->gfx.rlc.funcs->update_spm_vmid) 1459 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 1460 1461 return 0; 1462 } 1463 1464 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1465 int xcc_id) 1466 { 1467 u32 i, j, k; 1468 u32 mask; 1469 1470 mutex_lock(&adev->grbm_idx_mutex); 1471 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1472 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1473 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1474 xcc_id); 1475 for (k = 0; k < adev->usec_timeout; k++) { 1476 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1477 break; 1478 udelay(1); 1479 } 1480 if (k == adev->usec_timeout) { 1481 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1482 0xffffffff, 1483 0xffffffff, xcc_id); 1484 mutex_unlock(&adev->grbm_idx_mutex); 1485 drm_info(adev_to_drm(adev), "Timeout wait for RLC serdes %u,%u\n", 1486 i, j); 1487 return; 1488 } 1489 } 1490 } 1491 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1492 xcc_id); 1493 mutex_unlock(&adev->grbm_idx_mutex); 1494 1495 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1496 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1497 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1498 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1499 for (k = 0; k < adev->usec_timeout; k++) { 1500 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1501 break; 1502 udelay(1); 1503 } 1504 } 1505 1506 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1507 bool enable, int xcc_id) 1508 { 1509 u32 tmp; 1510 1511 /* These interrupts should be enabled to drive DS clock */ 1512 1513 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1514 1515 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1516 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1517 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1518 1519 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1520 } 1521 1522 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1523 { 1524 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1525 RLC_ENABLE_F32, 0); 1526 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1527 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1528 } 1529 1530 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1531 { 1532 int i, num_xcc; 1533 1534 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1535 for (i = 0; i < num_xcc; i++) 1536 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1537 } 1538 1539 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1540 { 1541 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1542 SOFT_RESET_RLC, 1); 1543 udelay(50); 1544 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1545 SOFT_RESET_RLC, 0); 1546 udelay(50); 1547 } 1548 1549 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1550 { 1551 int i, num_xcc; 1552 1553 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1554 for (i = 0; i < num_xcc; i++) 1555 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1556 } 1557 1558 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1559 { 1560 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1561 RLC_ENABLE_F32, 1); 1562 udelay(50); 1563 1564 /* carrizo do enable cp interrupt after cp inited */ 1565 if (!(adev->flags & AMD_IS_APU)) { 1566 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1567 udelay(50); 1568 } 1569 } 1570 1571 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1572 { 1573 #ifdef AMDGPU_RLC_DEBUG_RETRY 1574 u32 rlc_ucode_ver; 1575 #endif 1576 int i, num_xcc; 1577 1578 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1579 for (i = 0; i < num_xcc; i++) { 1580 gfx_v9_4_3_xcc_rlc_start(adev, i); 1581 #ifdef AMDGPU_RLC_DEBUG_RETRY 1582 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1583 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1584 if (rlc_ucode_ver == 0x108) { 1585 dev_info(adev->dev, 1586 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i\n", 1587 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1588 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1589 * default is 0x9C4 to create a 100us interval */ 1590 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1591 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1592 * to disable the page fault retry interrupts, default is 1593 * 0x100 (256) */ 1594 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1595 } 1596 #endif 1597 } 1598 } 1599 1600 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1601 int xcc_id) 1602 { 1603 const struct rlc_firmware_header_v2_0 *hdr; 1604 const __le32 *fw_data; 1605 unsigned i, fw_size; 1606 1607 if (!adev->gfx.rlc_fw) 1608 return -EINVAL; 1609 1610 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1611 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1612 1613 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1614 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1615 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1616 1617 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1618 RLCG_UCODE_LOADING_START_ADDRESS); 1619 for (i = 0; i < fw_size; i++) { 1620 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1621 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1622 msleep(1); 1623 } 1624 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1625 } 1626 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1627 1628 return 0; 1629 } 1630 1631 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1632 { 1633 int r; 1634 1635 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1636 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1637 /* legacy rlc firmware loading */ 1638 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1639 if (r) 1640 return r; 1641 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1642 } 1643 1644 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1645 /* disable CG */ 1646 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1647 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1648 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1649 1650 return 0; 1651 } 1652 1653 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1654 { 1655 int r, i, num_xcc; 1656 1657 if (amdgpu_sriov_vf(adev)) 1658 return 0; 1659 1660 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1661 for (i = 0; i < num_xcc; i++) { 1662 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1663 if (r) 1664 return r; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1671 int inst, struct amdgpu_ring *ring, unsigned int vmid) 1672 { 1673 u32 reg, pre_data, data; 1674 1675 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL); 1676 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1677 pre_data = RREG32_NO_KIQ(reg); 1678 else 1679 pre_data = RREG32(reg); 1680 1681 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1682 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1683 1684 if (pre_data != data) { 1685 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1686 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1687 } else 1688 WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1689 } 1690 } 1691 1692 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1693 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1694 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1695 }; 1696 1697 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1698 uint32_t offset, 1699 struct soc15_reg_rlcg *entries, int arr_size) 1700 { 1701 int i, inst; 1702 uint32_t reg; 1703 1704 if (!entries) 1705 return false; 1706 1707 for (i = 0; i < arr_size; i++) { 1708 const struct soc15_reg_rlcg *entry; 1709 1710 entry = &entries[i]; 1711 inst = adev->ip_map.logical_to_dev_inst ? 1712 adev->ip_map.logical_to_dev_inst( 1713 adev, entry->hwip, entry->instance) : 1714 entry->instance; 1715 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1716 entry->reg; 1717 if (offset == reg) 1718 return true; 1719 } 1720 1721 return false; 1722 } 1723 1724 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1725 { 1726 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1727 (void *)rlcg_access_gc_9_4_3, 1728 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1729 } 1730 1731 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1732 bool enable, int xcc_id) 1733 { 1734 if (enable) { 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1736 } else { 1737 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1738 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1739 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1740 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1741 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1742 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1743 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1744 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1745 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1746 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1747 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1748 } 1749 udelay(50); 1750 } 1751 1752 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1753 int xcc_id) 1754 { 1755 const struct gfx_firmware_header_v1_0 *mec_hdr; 1756 const __le32 *fw_data; 1757 unsigned i; 1758 u32 tmp; 1759 u32 mec_ucode_addr_offset; 1760 u32 mec_ucode_data_offset; 1761 1762 if (!adev->gfx.mec_fw) 1763 return -EINVAL; 1764 1765 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1766 1767 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1768 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1769 1770 fw_data = (const __le32 *) 1771 (adev->gfx.mec_fw->data + 1772 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1773 tmp = 0; 1774 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1775 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1776 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1777 1778 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1779 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1780 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1781 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1782 1783 mec_ucode_addr_offset = 1784 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1785 mec_ucode_data_offset = 1786 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1787 1788 /* MEC1 */ 1789 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1790 for (i = 0; i < mec_hdr->jt_size; i++) 1791 WREG32(mec_ucode_data_offset, 1792 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1793 1794 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1795 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1796 1797 return 0; 1798 } 1799 1800 /* KIQ functions */ 1801 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1802 { 1803 uint32_t tmp; 1804 struct amdgpu_device *adev = ring->adev; 1805 1806 /* tell RLC which is KIQ queue */ 1807 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1808 tmp &= 0xffffff00; 1809 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1810 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1811 } 1812 1813 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1814 { 1815 struct amdgpu_device *adev = ring->adev; 1816 1817 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1818 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1819 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1820 mqd->cp_hqd_queue_priority = 1821 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1822 } 1823 } 1824 } 1825 1826 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1827 { 1828 struct amdgpu_device *adev = ring->adev; 1829 struct v9_mqd *mqd = ring->mqd_ptr; 1830 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1831 uint32_t tmp; 1832 1833 mqd->header = 0xC0310800; 1834 mqd->compute_pipelinestat_enable = 0x00000001; 1835 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1836 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1837 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1838 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1839 mqd->compute_misc_reserved = 0x00000003; 1840 1841 mqd->dynamic_cu_mask_addr_lo = 1842 lower_32_bits(ring->mqd_gpu_addr 1843 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1844 mqd->dynamic_cu_mask_addr_hi = 1845 upper_32_bits(ring->mqd_gpu_addr 1846 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1847 1848 eop_base_addr = ring->eop_gpu_addr >> 8; 1849 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1850 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1851 1852 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1853 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1854 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1855 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1856 1857 mqd->cp_hqd_eop_control = tmp; 1858 1859 /* enable doorbell? */ 1860 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1861 1862 if (ring->use_doorbell) { 1863 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1864 DOORBELL_OFFSET, ring->doorbell_index); 1865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1866 DOORBELL_EN, 1); 1867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1868 DOORBELL_SOURCE, 0); 1869 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1870 DOORBELL_HIT, 0); 1871 if (amdgpu_sriov_multi_vf_mode(adev)) 1872 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1873 DOORBELL_MODE, 1); 1874 } else { 1875 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1876 DOORBELL_EN, 0); 1877 } 1878 1879 mqd->cp_hqd_pq_doorbell_control = tmp; 1880 1881 /* disable the queue if it's active */ 1882 ring->wptr = 0; 1883 mqd->cp_hqd_dequeue_request = 0; 1884 mqd->cp_hqd_pq_rptr = 0; 1885 mqd->cp_hqd_pq_wptr_lo = 0; 1886 mqd->cp_hqd_pq_wptr_hi = 0; 1887 1888 /* set the pointer to the MQD */ 1889 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1890 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1891 1892 /* set MQD vmid to 0 */ 1893 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1894 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1895 mqd->cp_mqd_control = tmp; 1896 1897 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1898 hqd_gpu_addr = ring->gpu_addr >> 8; 1899 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1900 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1901 1902 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1903 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1904 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1905 (order_base_2(ring->ring_size / 4) - 1)); 1906 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1907 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1908 #ifdef __BIG_ENDIAN 1909 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1910 #endif 1911 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1912 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1913 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1914 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1915 mqd->cp_hqd_pq_control = tmp; 1916 1917 /* set the wb address whether it's enabled or not */ 1918 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1919 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1920 mqd->cp_hqd_pq_rptr_report_addr_hi = 1921 upper_32_bits(wb_gpu_addr) & 0xffff; 1922 1923 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1924 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1925 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1926 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1927 1928 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1929 ring->wptr = 0; 1930 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1931 1932 /* set the vmid for the queue */ 1933 mqd->cp_hqd_vmid = 0; 1934 1935 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1936 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1937 mqd->cp_hqd_persistent_state = tmp; 1938 1939 /* set MIN_IB_AVAIL_SIZE */ 1940 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1941 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1942 mqd->cp_hqd_ib_control = tmp; 1943 1944 /* set static priority for a queue/ring */ 1945 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1946 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1947 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); 1948 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 1949 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 1950 mqd->cp_hqd_quantum = tmp; 1951 1952 /* map_queues packet doesn't need activate the queue, 1953 * so only kiq need set this field. 1954 */ 1955 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1956 mqd->cp_hqd_active = 1; 1957 1958 return 0; 1959 } 1960 1961 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1962 int xcc_id) 1963 { 1964 struct amdgpu_device *adev = ring->adev; 1965 struct v9_mqd *mqd = ring->mqd_ptr; 1966 int j; 1967 1968 /* disable wptr polling */ 1969 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1970 1971 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1972 mqd->cp_hqd_eop_base_addr_lo); 1973 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1974 mqd->cp_hqd_eop_base_addr_hi); 1975 1976 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1977 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1978 mqd->cp_hqd_eop_control); 1979 1980 /* enable doorbell? */ 1981 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1982 mqd->cp_hqd_pq_doorbell_control); 1983 1984 /* disable the queue if it's active */ 1985 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1986 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1987 for (j = 0; j < adev->usec_timeout; j++) { 1988 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1989 break; 1990 udelay(1); 1991 } 1992 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1993 mqd->cp_hqd_dequeue_request); 1994 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1995 mqd->cp_hqd_pq_rptr); 1996 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1997 mqd->cp_hqd_pq_wptr_lo); 1998 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1999 mqd->cp_hqd_pq_wptr_hi); 2000 } 2001 2002 /* set the pointer to the MQD */ 2003 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 2004 mqd->cp_mqd_base_addr_lo); 2005 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 2006 mqd->cp_mqd_base_addr_hi); 2007 2008 /* set MQD vmid to 0 */ 2009 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 2010 mqd->cp_mqd_control); 2011 2012 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2013 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 2014 mqd->cp_hqd_pq_base_lo); 2015 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 2016 mqd->cp_hqd_pq_base_hi); 2017 2018 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2019 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 2020 mqd->cp_hqd_pq_control); 2021 2022 /* set the wb address whether it's enabled or not */ 2023 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2024 mqd->cp_hqd_pq_rptr_report_addr_lo); 2025 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2026 mqd->cp_hqd_pq_rptr_report_addr_hi); 2027 2028 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2029 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2030 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2031 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2032 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2033 2034 /* enable the doorbell if requested */ 2035 if (ring->use_doorbell) { 2036 WREG32_SOC15( 2037 GC, GET_INST(GC, xcc_id), 2038 regCP_MEC_DOORBELL_RANGE_LOWER, 2039 ((adev->doorbell_index.kiq + 2040 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2041 2) << 2); 2042 WREG32_SOC15( 2043 GC, GET_INST(GC, xcc_id), 2044 regCP_MEC_DOORBELL_RANGE_UPPER, 2045 ((adev->doorbell_index.userqueue_end + 2046 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2047 2) << 2); 2048 } 2049 2050 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2051 mqd->cp_hqd_pq_doorbell_control); 2052 2053 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2054 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2055 mqd->cp_hqd_pq_wptr_lo); 2056 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2057 mqd->cp_hqd_pq_wptr_hi); 2058 2059 /* set the vmid for the queue */ 2060 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2061 2062 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2063 mqd->cp_hqd_persistent_state); 2064 2065 /* activate the queue */ 2066 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2067 mqd->cp_hqd_active); 2068 2069 if (ring->use_doorbell) 2070 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2071 2072 return 0; 2073 } 2074 2075 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2076 int xcc_id) 2077 { 2078 struct amdgpu_device *adev = ring->adev; 2079 int j; 2080 2081 /* disable the queue if it's active */ 2082 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2083 2084 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2085 2086 for (j = 0; j < adev->usec_timeout; j++) { 2087 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2088 break; 2089 udelay(1); 2090 } 2091 2092 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2093 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2094 2095 /* Manual disable if dequeue request times out */ 2096 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2097 } 2098 2099 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2100 0); 2101 } 2102 2103 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2104 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2105 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2106 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2107 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2108 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2109 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2110 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2111 2112 return 0; 2113 } 2114 2115 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2116 { 2117 struct amdgpu_device *adev = ring->adev; 2118 struct v9_mqd *mqd = ring->mqd_ptr; 2119 struct v9_mqd *tmp_mqd; 2120 2121 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2122 2123 /* GPU could be in bad state during probe, driver trigger the reset 2124 * after load the SMU, in this case , the mqd is not be initialized. 2125 * driver need to re-init the mqd. 2126 * check mqd->cp_hqd_pq_control since this value should not be 0 2127 */ 2128 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2129 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2130 /* for GPU_RESET case , reset MQD to a clean status */ 2131 if (adev->gfx.kiq[xcc_id].mqd_backup) 2132 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2133 2134 /* reset ring buffer */ 2135 ring->wptr = 0; 2136 amdgpu_ring_clear_ring(ring); 2137 mutex_lock(&adev->srbm_mutex); 2138 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2139 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2140 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2141 mutex_unlock(&adev->srbm_mutex); 2142 } else { 2143 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2144 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2145 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2146 mutex_lock(&adev->srbm_mutex); 2147 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2148 amdgpu_ring_clear_ring(ring); 2149 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2150 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2151 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2152 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2153 mutex_unlock(&adev->srbm_mutex); 2154 2155 if (adev->gfx.kiq[xcc_id].mqd_backup) 2156 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2157 } 2158 2159 return 0; 2160 } 2161 2162 static void gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, 2163 bool restore) 2164 { 2165 struct amdgpu_device *adev = ring->adev; 2166 struct v9_mqd *mqd = ring->mqd_ptr; 2167 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2168 struct v9_mqd *tmp_mqd; 2169 2170 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2171 * is not be initialized before 2172 */ 2173 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2174 2175 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2176 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2177 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2178 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2179 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2180 mutex_lock(&adev->srbm_mutex); 2181 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2182 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2183 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2184 mutex_unlock(&adev->srbm_mutex); 2185 2186 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2187 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2188 } else { 2189 /* restore MQD to a clean status */ 2190 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2191 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2192 /* reset ring buffer */ 2193 ring->wptr = 0; 2194 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2195 amdgpu_ring_clear_ring(ring); 2196 } 2197 } 2198 2199 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2200 { 2201 struct amdgpu_ring *ring; 2202 int j; 2203 2204 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2205 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2206 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2207 mutex_lock(&adev->srbm_mutex); 2208 soc15_grbm_select(adev, ring->me, 2209 ring->pipe, 2210 ring->queue, 0, GET_INST(GC, xcc_id)); 2211 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2212 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2213 mutex_unlock(&adev->srbm_mutex); 2214 } 2215 } 2216 2217 return 0; 2218 } 2219 2220 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2221 { 2222 gfx_v9_4_3_xcc_kiq_init_queue(&adev->gfx.kiq[xcc_id].ring, xcc_id); 2223 return 0; 2224 } 2225 2226 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2227 { 2228 struct amdgpu_ring *ring; 2229 int i; 2230 2231 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2232 2233 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2234 ring = &adev->gfx.compute_ring[i + xcc_id * 2235 adev->gfx.num_compute_rings]; 2236 2237 gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2238 } 2239 2240 return amdgpu_gfx_enable_kcq(adev, xcc_id); 2241 } 2242 2243 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2244 { 2245 struct amdgpu_ring *ring; 2246 int r, j; 2247 2248 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2249 2250 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2251 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2252 2253 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2254 if (r) 2255 return r; 2256 } else { 2257 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2258 } 2259 2260 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2261 if (r) 2262 return r; 2263 2264 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2265 if (r) 2266 return r; 2267 2268 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2269 ring = &adev->gfx.compute_ring 2270 [j + xcc_id * adev->gfx.num_compute_rings]; 2271 r = amdgpu_ring_test_helper(ring); 2272 if (r) 2273 return r; 2274 } 2275 2276 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2277 2278 return 0; 2279 } 2280 2281 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2282 { 2283 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2284 2285 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2286 if (amdgpu_sriov_vf(adev)) { 2287 enum amdgpu_gfx_partition mode; 2288 2289 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2290 AMDGPU_XCP_FL_NONE); 2291 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2292 return -EINVAL; 2293 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2294 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2295 num_xcp = num_xcc / num_xcc_per_xcp; 2296 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2297 2298 } else { 2299 if (adev->in_suspend) 2300 amdgpu_xcp_restore_partition_mode(adev->xcp_mgr); 2301 else if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2302 AMDGPU_XCP_FL_NONE) == 2303 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2304 r = amdgpu_xcp_switch_partition_mode( 2305 adev->xcp_mgr, amdgpu_user_partt_mode); 2306 } 2307 if (r) 2308 return r; 2309 2310 for (i = 0; i < num_xcc; i++) { 2311 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2312 if (r) 2313 return r; 2314 } 2315 2316 return 0; 2317 } 2318 2319 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2320 { 2321 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2322 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2323 2324 if (amdgpu_sriov_vf(adev)) { 2325 /* must disable polling for SRIOV when hw finished, otherwise 2326 * CPC engine may still keep fetching WB address which is already 2327 * invalid after sw finished and trigger DMAR reading error in 2328 * hypervisor side. 2329 */ 2330 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2331 return; 2332 } 2333 2334 /* Use deinitialize sequence from CAIL when unbinding device 2335 * from driver, otherwise KIQ is hanging when binding back 2336 */ 2337 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2338 mutex_lock(&adev->srbm_mutex); 2339 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2340 adev->gfx.kiq[xcc_id].ring.pipe, 2341 adev->gfx.kiq[xcc_id].ring.queue, 0, 2342 GET_INST(GC, xcc_id)); 2343 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2344 xcc_id); 2345 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2346 mutex_unlock(&adev->srbm_mutex); 2347 } 2348 2349 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2350 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2351 } 2352 2353 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2354 { 2355 int r; 2356 struct amdgpu_device *adev = ip_block->adev; 2357 2358 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2359 adev->gfx.cleaner_shader_ptr); 2360 2361 if (!amdgpu_sriov_vf(adev)) 2362 gfx_v9_4_3_init_golden_registers(adev); 2363 2364 gfx_v9_4_3_constants_init(adev); 2365 2366 r = adev->gfx.rlc.funcs->resume(adev); 2367 if (r) 2368 return r; 2369 2370 r = gfx_v9_4_3_cp_resume(adev); 2371 if (r) 2372 return r; 2373 2374 return r; 2375 } 2376 2377 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2378 { 2379 struct amdgpu_device *adev = ip_block->adev; 2380 int i, num_xcc; 2381 2382 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2383 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2384 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2385 2386 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2387 for (i = 0; i < num_xcc; i++) { 2388 gfx_v9_4_3_xcc_fini(adev, i); 2389 } 2390 2391 return 0; 2392 } 2393 2394 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2395 { 2396 return gfx_v9_4_3_hw_fini(ip_block); 2397 } 2398 2399 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2400 { 2401 return gfx_v9_4_3_hw_init(ip_block); 2402 } 2403 2404 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2405 { 2406 struct amdgpu_device *adev = ip_block->adev; 2407 int i, num_xcc; 2408 2409 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2410 for (i = 0; i < num_xcc; i++) { 2411 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2412 GRBM_STATUS, GUI_ACTIVE)) 2413 return false; 2414 } 2415 return true; 2416 } 2417 2418 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2419 { 2420 unsigned i; 2421 struct amdgpu_device *adev = ip_block->adev; 2422 2423 for (i = 0; i < adev->usec_timeout; i++) { 2424 if (gfx_v9_4_3_is_idle(ip_block)) 2425 return 0; 2426 udelay(1); 2427 } 2428 return -ETIMEDOUT; 2429 } 2430 2431 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2432 { 2433 u32 grbm_soft_reset = 0; 2434 u32 tmp; 2435 struct amdgpu_device *adev = ip_block->adev; 2436 2437 /* GRBM_STATUS */ 2438 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2439 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2440 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2441 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2442 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2443 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2444 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2445 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2446 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2447 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2448 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2449 } 2450 2451 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2452 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2453 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2454 } 2455 2456 /* GRBM_STATUS2 */ 2457 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2458 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2459 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2460 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2461 2462 2463 if (grbm_soft_reset) { 2464 /* stop the rlc */ 2465 adev->gfx.rlc.funcs->stop(adev); 2466 2467 /* Disable MEC parsing/prefetching */ 2468 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2469 2470 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2471 tmp |= grbm_soft_reset; 2472 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2473 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2474 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2475 2476 udelay(50); 2477 2478 tmp &= ~grbm_soft_reset; 2479 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2480 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2481 2482 /* Wait a little for things to settle down */ 2483 udelay(50); 2484 } 2485 return 0; 2486 } 2487 2488 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2489 uint32_t vmid, 2490 uint32_t gds_base, uint32_t gds_size, 2491 uint32_t gws_base, uint32_t gws_size, 2492 uint32_t oa_base, uint32_t oa_size) 2493 { 2494 struct amdgpu_device *adev = ring->adev; 2495 2496 /* GDS Base */ 2497 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2498 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2499 gds_base); 2500 2501 /* GDS Size */ 2502 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2503 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2504 gds_size); 2505 2506 /* GWS */ 2507 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2508 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2509 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2510 2511 /* OA */ 2512 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2513 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2514 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2515 } 2516 2517 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2518 { 2519 struct amdgpu_device *adev = ip_block->adev; 2520 2521 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2522 AMDGPU_MAX_COMPUTE_RINGS); 2523 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2524 gfx_v9_4_3_set_ring_funcs(adev); 2525 gfx_v9_4_3_set_irq_funcs(adev); 2526 gfx_v9_4_3_set_gds_init(adev); 2527 gfx_v9_4_3_set_rlc_funcs(adev); 2528 2529 /* init rlcg reg access ctrl */ 2530 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2531 2532 return gfx_v9_4_3_init_microcode(adev); 2533 } 2534 2535 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2536 { 2537 struct amdgpu_device *adev = ip_block->adev; 2538 int r; 2539 2540 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2541 if (r) 2542 return r; 2543 2544 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2545 if (r) 2546 return r; 2547 2548 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2549 if (r) 2550 return r; 2551 2552 if (adev->gfx.ras && 2553 adev->gfx.ras->enable_watchdog_timer) 2554 adev->gfx.ras->enable_watchdog_timer(adev); 2555 2556 return 0; 2557 } 2558 2559 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2560 bool enable, int xcc_id) 2561 { 2562 uint32_t def, data; 2563 2564 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2565 return; 2566 2567 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2568 regRLC_CGTT_MGCG_OVERRIDE); 2569 2570 if (enable) 2571 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2572 else 2573 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2574 2575 if (def != data) 2576 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2577 regRLC_CGTT_MGCG_OVERRIDE, data); 2578 2579 } 2580 2581 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2582 bool enable, int xcc_id) 2583 { 2584 uint32_t def, data; 2585 2586 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2587 return; 2588 2589 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2590 regRLC_CGTT_MGCG_OVERRIDE); 2591 2592 if (enable) 2593 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2594 else 2595 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2596 2597 if (def != data) 2598 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2599 regRLC_CGTT_MGCG_OVERRIDE, data); 2600 } 2601 2602 static void 2603 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2604 bool enable, int xcc_id) 2605 { 2606 uint32_t data, def; 2607 2608 /* It is disabled by HW by default */ 2609 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2610 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2611 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2612 2613 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2614 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2615 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2616 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2617 2618 if (def != data) 2619 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2620 2621 /* MGLS is a global flag to control all MGLS in GFX */ 2622 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2623 /* 2 - RLC memory Light sleep */ 2624 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2625 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2626 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2627 if (def != data) 2628 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2629 } 2630 /* 3 - CP memory Light sleep */ 2631 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2632 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2633 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2634 if (def != data) 2635 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2636 } 2637 } 2638 } else { 2639 /* 1 - MGCG_OVERRIDE */ 2640 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2641 2642 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2643 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2644 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2645 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2646 2647 if (def != data) 2648 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2649 2650 /* 2 - disable MGLS in RLC */ 2651 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2652 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2653 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2654 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2655 } 2656 2657 /* 3 - disable MGLS in CP */ 2658 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2659 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2660 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2661 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2662 } 2663 } 2664 2665 } 2666 2667 static void 2668 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2669 bool enable, int xcc_id) 2670 { 2671 uint32_t def, data; 2672 2673 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2674 2675 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2676 /* unset CGCG override */ 2677 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2678 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2679 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2680 else 2681 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2682 /* update CGCG and CGLS override bits */ 2683 if (def != data) 2684 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2685 2686 /* CGCG Hysteresis: 400us */ 2687 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2688 2689 data = (0x2710 2690 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2691 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2692 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2693 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2694 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2695 if (def != data) 2696 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2697 2698 /* set IDLE_POLL_COUNT(0x33450100)*/ 2699 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2700 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2701 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2702 if (def != data) 2703 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2704 } else { 2705 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2706 /* reset CGCG/CGLS bits */ 2707 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2708 /* disable cgcg and cgls in FSM */ 2709 if (def != data) 2710 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2711 } 2712 2713 } 2714 2715 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2716 bool enable, int xcc_id) 2717 { 2718 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2719 2720 if (enable) { 2721 /* FGCG */ 2722 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2723 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2724 2725 /* CGCG/CGLS should be enabled after MGCG/MGLS 2726 * === MGCG + MGLS === 2727 */ 2728 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2729 xcc_id); 2730 /* === CGCG + CGLS === */ 2731 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2732 xcc_id); 2733 } else { 2734 /* CGCG/CGLS should be disabled before MGCG/MGLS 2735 * === CGCG + CGLS === 2736 */ 2737 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2738 xcc_id); 2739 /* === MGCG + MGLS === */ 2740 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2741 xcc_id); 2742 2743 /* FGCG */ 2744 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2745 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2746 } 2747 2748 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2749 2750 return 0; 2751 } 2752 2753 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2754 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2755 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2756 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2757 .init = gfx_v9_4_3_rlc_init, 2758 .resume = gfx_v9_4_3_rlc_resume, 2759 .stop = gfx_v9_4_3_rlc_stop, 2760 .reset = gfx_v9_4_3_rlc_reset, 2761 .start = gfx_v9_4_3_rlc_start, 2762 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2763 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2764 }; 2765 2766 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2767 enum amd_powergating_state state) 2768 { 2769 return 0; 2770 } 2771 2772 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2773 enum amd_clockgating_state state) 2774 { 2775 struct amdgpu_device *adev = ip_block->adev; 2776 int i, num_xcc; 2777 2778 if (amdgpu_sriov_vf(adev)) 2779 return 0; 2780 2781 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2782 for (i = 0; i < num_xcc; i++) 2783 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2784 adev, state == AMD_CG_STATE_GATE, i); 2785 2786 return 0; 2787 } 2788 2789 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2790 { 2791 struct amdgpu_device *adev = ip_block->adev; 2792 int data; 2793 2794 if (amdgpu_sriov_vf(adev)) 2795 *flags = 0; 2796 2797 /* AMD_CG_SUPPORT_GFX_MGCG */ 2798 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2799 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2800 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2801 2802 /* AMD_CG_SUPPORT_GFX_CGCG */ 2803 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2804 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2805 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2806 2807 /* AMD_CG_SUPPORT_GFX_CGLS */ 2808 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2809 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2810 2811 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2812 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2813 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2814 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2815 2816 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2817 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2818 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2819 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2820 } 2821 2822 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2823 { 2824 struct amdgpu_device *adev = ring->adev; 2825 u32 ref_and_mask, reg_mem_engine; 2826 2827 if (!adev->gfx.funcs->get_hdp_flush_mask) { 2828 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 2829 return; 2830 } 2831 2832 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 2833 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2834 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2835 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2836 ref_and_mask, ref_and_mask, 0x20); 2837 } 2838 2839 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2840 struct amdgpu_job *job, 2841 struct amdgpu_ib *ib, 2842 uint32_t flags) 2843 { 2844 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2845 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2846 2847 /* Currently, there is a high possibility to get wave ID mismatch 2848 * between ME and GDS, leading to a hw deadlock, because ME generates 2849 * different wave IDs than the GDS expects. This situation happens 2850 * randomly when at least 5 compute pipes use GDS ordered append. 2851 * The wave IDs generated by ME are also wrong after suspend/resume. 2852 * Those are probably bugs somewhere else in the kernel driver. 2853 * 2854 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2855 * GDS to 0 for this ring (me/pipe). 2856 */ 2857 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2858 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2859 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2860 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2861 } 2862 2863 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2864 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2865 amdgpu_ring_write(ring, 2866 #ifdef __BIG_ENDIAN 2867 (2 << 0) | 2868 #endif 2869 lower_32_bits(ib->gpu_addr)); 2870 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2871 amdgpu_ring_write(ring, control); 2872 } 2873 2874 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2875 u64 seq, unsigned flags) 2876 { 2877 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2878 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2879 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2880 2881 /* RELEASE_MEM - flush caches, send int */ 2882 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2883 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2884 EOP_TC_NC_ACTION_EN) : 2885 (EOP_TCL1_ACTION_EN | 2886 EOP_TC_ACTION_EN | 2887 EOP_TC_WB_ACTION_EN | 2888 EOP_TC_MD_ACTION_EN)) | 2889 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2890 EVENT_INDEX(5))); 2891 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2892 2893 /* 2894 * the address should be Qword aligned if 64bit write, Dword 2895 * aligned if only send 32bit data low (discard data high) 2896 */ 2897 if (write64bit) 2898 BUG_ON(addr & 0x7); 2899 else 2900 BUG_ON(addr & 0x3); 2901 amdgpu_ring_write(ring, lower_32_bits(addr)); 2902 amdgpu_ring_write(ring, upper_32_bits(addr)); 2903 amdgpu_ring_write(ring, lower_32_bits(seq)); 2904 amdgpu_ring_write(ring, upper_32_bits(seq)); 2905 amdgpu_ring_write(ring, 0); 2906 } 2907 2908 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2909 { 2910 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2911 uint32_t seq = ring->fence_drv.sync_seq; 2912 uint64_t addr = ring->fence_drv.gpu_addr; 2913 2914 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2915 lower_32_bits(addr), upper_32_bits(addr), 2916 seq, 0xffffffff, 4); 2917 } 2918 2919 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2920 unsigned vmid, uint64_t pd_addr) 2921 { 2922 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2923 } 2924 2925 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2926 { 2927 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2928 } 2929 2930 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2931 { 2932 u64 wptr; 2933 2934 /* XXX check if swapping is necessary on BE */ 2935 if (ring->use_doorbell) 2936 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2937 else 2938 BUG(); 2939 return wptr; 2940 } 2941 2942 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2943 { 2944 struct amdgpu_device *adev = ring->adev; 2945 2946 /* XXX check if swapping is necessary on BE */ 2947 if (ring->use_doorbell) { 2948 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2949 WDOORBELL64(ring->doorbell_index, ring->wptr); 2950 } else { 2951 BUG(); /* only DOORBELL method supported on gfx9 now */ 2952 } 2953 } 2954 2955 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2956 u64 seq, unsigned int flags) 2957 { 2958 struct amdgpu_device *adev = ring->adev; 2959 2960 /* we only allocate 32bit for each seq wb address */ 2961 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2962 2963 /* write fence seq to the "addr" */ 2964 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2965 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2966 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2967 amdgpu_ring_write(ring, lower_32_bits(addr)); 2968 amdgpu_ring_write(ring, upper_32_bits(addr)); 2969 amdgpu_ring_write(ring, lower_32_bits(seq)); 2970 2971 if (flags & AMDGPU_FENCE_FLAG_INT) { 2972 /* set register to trigger INT */ 2973 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2974 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2975 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2976 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2977 amdgpu_ring_write(ring, 0); 2978 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2979 } 2980 } 2981 2982 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2983 uint32_t reg_val_offs) 2984 { 2985 struct amdgpu_device *adev = ring->adev; 2986 2987 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2988 2989 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2990 amdgpu_ring_write(ring, 0 | /* src: register*/ 2991 (5 << 8) | /* dst: memory */ 2992 (1 << 20)); /* write confirm */ 2993 amdgpu_ring_write(ring, reg); 2994 amdgpu_ring_write(ring, 0); 2995 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2996 reg_val_offs * 4)); 2997 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2998 reg_val_offs * 4)); 2999 } 3000 3001 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3002 uint32_t val) 3003 { 3004 uint32_t cmd = 0; 3005 3006 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3007 3008 switch (ring->funcs->type) { 3009 case AMDGPU_RING_TYPE_GFX: 3010 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3011 break; 3012 case AMDGPU_RING_TYPE_KIQ: 3013 cmd = (1 << 16); /* no inc addr */ 3014 break; 3015 default: 3016 cmd = WR_CONFIRM; 3017 break; 3018 } 3019 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3020 amdgpu_ring_write(ring, cmd); 3021 amdgpu_ring_write(ring, reg); 3022 amdgpu_ring_write(ring, 0); 3023 amdgpu_ring_write(ring, val); 3024 } 3025 3026 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3027 uint32_t val, uint32_t mask) 3028 { 3029 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3030 } 3031 3032 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3033 uint32_t reg0, uint32_t reg1, 3034 uint32_t ref, uint32_t mask) 3035 { 3036 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3037 ref, mask); 3038 } 3039 3040 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3041 unsigned vmid) 3042 { 3043 struct amdgpu_device *adev = ring->adev; 3044 uint32_t value = 0; 3045 3046 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3047 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3048 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3049 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3050 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3051 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3052 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3053 } 3054 3055 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3056 struct amdgpu_device *adev, int me, int pipe, 3057 enum amdgpu_interrupt_state state, int xcc_id) 3058 { 3059 u32 mec_int_cntl, mec_int_cntl_reg; 3060 3061 /* 3062 * amdgpu controls only the first MEC. That's why this function only 3063 * handles the setting of interrupts for this specific MEC. All other 3064 * pipes' interrupts are set by amdkfd. 3065 */ 3066 3067 if (me == 1) { 3068 switch (pipe) { 3069 case 0: 3070 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3071 break; 3072 case 1: 3073 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3074 break; 3075 case 2: 3076 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3077 break; 3078 case 3: 3079 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3080 break; 3081 default: 3082 DRM_DEBUG("invalid pipe %d\n", pipe); 3083 return; 3084 } 3085 } else { 3086 DRM_DEBUG("invalid me %d\n", me); 3087 return; 3088 } 3089 3090 switch (state) { 3091 case AMDGPU_IRQ_STATE_DISABLE: 3092 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3093 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3094 TIME_STAMP_INT_ENABLE, 0); 3095 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3096 break; 3097 case AMDGPU_IRQ_STATE_ENABLE: 3098 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3099 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3100 TIME_STAMP_INT_ENABLE, 1); 3101 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3102 break; 3103 default: 3104 break; 3105 } 3106 } 3107 3108 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3109 int xcc_id, int me, int pipe) 3110 { 3111 /* 3112 * amdgpu controls only the first MEC. That's why this function only 3113 * handles the setting of interrupts for this specific MEC. All other 3114 * pipes' interrupts are set by amdkfd. 3115 */ 3116 if (me != 1) 3117 return 0; 3118 3119 switch (pipe) { 3120 case 0: 3121 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3122 case 1: 3123 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3124 case 2: 3125 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3126 case 3: 3127 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3128 default: 3129 return 0; 3130 } 3131 } 3132 3133 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3134 struct amdgpu_irq_src *source, 3135 unsigned type, 3136 enum amdgpu_interrupt_state state) 3137 { 3138 u32 mec_int_cntl_reg, mec_int_cntl; 3139 int i, j, k, num_xcc; 3140 3141 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3142 switch (state) { 3143 case AMDGPU_IRQ_STATE_DISABLE: 3144 case AMDGPU_IRQ_STATE_ENABLE: 3145 for (i = 0; i < num_xcc; i++) { 3146 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3147 PRIV_REG_INT_ENABLE, 3148 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3149 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3150 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3151 /* MECs start at 1 */ 3152 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3153 3154 if (mec_int_cntl_reg) { 3155 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3156 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3157 PRIV_REG_INT_ENABLE, 3158 state == AMDGPU_IRQ_STATE_ENABLE ? 3159 1 : 0); 3160 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3161 } 3162 } 3163 } 3164 } 3165 break; 3166 default: 3167 break; 3168 } 3169 3170 return 0; 3171 } 3172 3173 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3174 struct amdgpu_irq_src *source, 3175 unsigned type, 3176 enum amdgpu_interrupt_state state) 3177 { 3178 u32 mec_int_cntl_reg, mec_int_cntl; 3179 int i, j, k, num_xcc; 3180 3181 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3182 switch (state) { 3183 case AMDGPU_IRQ_STATE_DISABLE: 3184 case AMDGPU_IRQ_STATE_ENABLE: 3185 for (i = 0; i < num_xcc; i++) { 3186 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3187 OPCODE_ERROR_INT_ENABLE, 3188 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3189 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3190 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3191 /* MECs start at 1 */ 3192 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3193 3194 if (mec_int_cntl_reg) { 3195 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3196 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3197 OPCODE_ERROR_INT_ENABLE, 3198 state == AMDGPU_IRQ_STATE_ENABLE ? 3199 1 : 0); 3200 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3201 } 3202 } 3203 } 3204 } 3205 break; 3206 default: 3207 break; 3208 } 3209 3210 return 0; 3211 } 3212 3213 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3214 struct amdgpu_irq_src *source, 3215 unsigned type, 3216 enum amdgpu_interrupt_state state) 3217 { 3218 int i, num_xcc; 3219 3220 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3221 switch (state) { 3222 case AMDGPU_IRQ_STATE_DISABLE: 3223 case AMDGPU_IRQ_STATE_ENABLE: 3224 for (i = 0; i < num_xcc; i++) 3225 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3226 PRIV_INSTR_INT_ENABLE, 3227 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3228 break; 3229 default: 3230 break; 3231 } 3232 3233 return 0; 3234 } 3235 3236 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3237 struct amdgpu_irq_src *src, 3238 unsigned type, 3239 enum amdgpu_interrupt_state state) 3240 { 3241 int i, num_xcc; 3242 3243 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3244 for (i = 0; i < num_xcc; i++) { 3245 switch (type) { 3246 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3247 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3248 adev, 1, 0, state, i); 3249 break; 3250 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3251 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3252 adev, 1, 1, state, i); 3253 break; 3254 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3255 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3256 adev, 1, 2, state, i); 3257 break; 3258 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3259 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3260 adev, 1, 3, state, i); 3261 break; 3262 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3263 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3264 adev, 2, 0, state, i); 3265 break; 3266 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3267 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3268 adev, 2, 1, state, i); 3269 break; 3270 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3271 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3272 adev, 2, 2, state, i); 3273 break; 3274 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3275 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3276 adev, 2, 3, state, i); 3277 break; 3278 default: 3279 break; 3280 } 3281 } 3282 3283 return 0; 3284 } 3285 3286 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3287 struct amdgpu_irq_src *source, 3288 struct amdgpu_iv_entry *entry) 3289 { 3290 int i, xcc_id; 3291 u8 me_id, pipe_id, queue_id; 3292 struct amdgpu_ring *ring; 3293 3294 DRM_DEBUG("IH: CP EOP\n"); 3295 me_id = (entry->ring_id & 0x0c) >> 2; 3296 pipe_id = (entry->ring_id & 0x03) >> 0; 3297 queue_id = (entry->ring_id & 0x70) >> 4; 3298 3299 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3300 3301 if (xcc_id == -EINVAL) 3302 return -EINVAL; 3303 3304 switch (me_id) { 3305 case 0: 3306 case 1: 3307 case 2: 3308 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3309 ring = &adev->gfx.compute_ring 3310 [i + 3311 xcc_id * adev->gfx.num_compute_rings]; 3312 /* Per-queue interrupt is supported for MEC starting from VI. 3313 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3314 */ 3315 3316 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3317 amdgpu_fence_process(ring); 3318 } 3319 break; 3320 } 3321 return 0; 3322 } 3323 3324 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3325 struct amdgpu_iv_entry *entry) 3326 { 3327 u8 me_id, pipe_id, queue_id; 3328 struct amdgpu_ring *ring; 3329 int i, xcc_id; 3330 3331 me_id = (entry->ring_id & 0x0c) >> 2; 3332 pipe_id = (entry->ring_id & 0x03) >> 0; 3333 queue_id = (entry->ring_id & 0x70) >> 4; 3334 3335 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3336 3337 if (xcc_id == -EINVAL) 3338 return; 3339 3340 switch (me_id) { 3341 case 0: 3342 case 1: 3343 case 2: 3344 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3345 ring = &adev->gfx.compute_ring 3346 [i + 3347 xcc_id * adev->gfx.num_compute_rings]; 3348 if (ring->me == me_id && ring->pipe == pipe_id && 3349 ring->queue == queue_id) 3350 drm_sched_fault(&ring->sched); 3351 } 3352 break; 3353 } 3354 } 3355 3356 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3357 struct amdgpu_irq_src *source, 3358 struct amdgpu_iv_entry *entry) 3359 { 3360 DRM_ERROR("Illegal register access in command stream\n"); 3361 gfx_v9_4_3_fault(adev, entry); 3362 return 0; 3363 } 3364 3365 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3366 struct amdgpu_irq_src *source, 3367 struct amdgpu_iv_entry *entry) 3368 { 3369 DRM_ERROR("Illegal opcode in command stream\n"); 3370 gfx_v9_4_3_fault(adev, entry); 3371 return 0; 3372 } 3373 3374 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3375 struct amdgpu_irq_src *source, 3376 struct amdgpu_iv_entry *entry) 3377 { 3378 DRM_ERROR("Illegal instruction in command stream\n"); 3379 gfx_v9_4_3_fault(adev, entry); 3380 return 0; 3381 } 3382 3383 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3384 { 3385 const unsigned int cp_coher_cntl = 3386 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3387 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3388 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3389 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3390 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3391 3392 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3393 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3394 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3395 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3396 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3397 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3398 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3399 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3400 } 3401 3402 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3403 uint32_t pipe, bool enable) 3404 { 3405 struct amdgpu_device *adev = ring->adev; 3406 uint32_t val; 3407 uint32_t wcl_cs_reg; 3408 3409 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3410 val = enable ? 0x1 : 0x7f; 3411 3412 switch (pipe) { 3413 case 0: 3414 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3415 break; 3416 case 1: 3417 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3418 break; 3419 case 2: 3420 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3421 break; 3422 case 3: 3423 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3424 break; 3425 default: 3426 DRM_DEBUG("invalid pipe %d\n", pipe); 3427 return; 3428 } 3429 3430 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3431 3432 } 3433 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3434 { 3435 struct amdgpu_device *adev = ring->adev; 3436 uint32_t val; 3437 int i; 3438 3439 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3440 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3441 * around 25% of gpu resources. 3442 */ 3443 val = enable ? 0x1f : 0x07ffffff; 3444 amdgpu_ring_emit_wreg(ring, 3445 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3446 val); 3447 3448 /* Restrict waves for normal/low priority compute queues as well 3449 * to get best QoS for high priority compute jobs. 3450 * 3451 * amdgpu controls only 1st ME(0-3 CS pipes). 3452 */ 3453 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3454 if (i != ring->pipe) 3455 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3456 3457 } 3458 } 3459 3460 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3461 uint32_t pipe, uint32_t queue, 3462 uint32_t xcc_id) 3463 { 3464 int i, r; 3465 /* make sure dequeue is complete*/ 3466 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3467 mutex_lock(&adev->srbm_mutex); 3468 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3469 for (i = 0; i < adev->usec_timeout; i++) { 3470 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3471 break; 3472 udelay(1); 3473 } 3474 if (i >= adev->usec_timeout) 3475 r = -ETIMEDOUT; 3476 else 3477 r = 0; 3478 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3479 mutex_unlock(&adev->srbm_mutex); 3480 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3481 3482 return r; 3483 3484 } 3485 3486 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3487 { 3488 if (!!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3489 return true; 3490 else 3491 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3492 3493 return false; 3494 } 3495 3496 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3497 { 3498 struct amdgpu_device *adev = ring->adev; 3499 uint32_t reset_pipe, clean_pipe; 3500 int r; 3501 3502 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3503 return -EINVAL; 3504 3505 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3506 mutex_lock(&adev->srbm_mutex); 3507 3508 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3509 clean_pipe = reset_pipe; 3510 3511 if (ring->me == 1) { 3512 switch (ring->pipe) { 3513 case 0: 3514 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3515 MEC_ME1_PIPE0_RESET, 1); 3516 break; 3517 case 1: 3518 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3519 MEC_ME1_PIPE1_RESET, 1); 3520 break; 3521 case 2: 3522 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3523 MEC_ME1_PIPE2_RESET, 1); 3524 break; 3525 case 3: 3526 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3527 MEC_ME1_PIPE3_RESET, 1); 3528 break; 3529 default: 3530 break; 3531 } 3532 } else { 3533 if (ring->pipe) 3534 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3535 MEC_ME2_PIPE1_RESET, 1); 3536 else 3537 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3538 MEC_ME2_PIPE0_RESET, 1); 3539 } 3540 3541 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3542 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3543 mutex_unlock(&adev->srbm_mutex); 3544 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3545 3546 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3547 return r; 3548 } 3549 3550 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3551 unsigned int vmid, 3552 struct amdgpu_fence *timedout_fence) 3553 { 3554 struct amdgpu_device *adev = ring->adev; 3555 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3556 struct amdgpu_ring *kiq_ring = &kiq->ring; 3557 int reset_mode = AMDGPU_RESET_TYPE_PER_QUEUE; 3558 unsigned long flags; 3559 int r; 3560 3561 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3562 return -EINVAL; 3563 3564 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 3565 3566 spin_lock_irqsave(&kiq->ring_lock, flags); 3567 3568 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3569 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3570 return -ENOMEM; 3571 } 3572 3573 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3574 0, 0); 3575 amdgpu_ring_commit(kiq_ring); 3576 3577 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3578 3579 r = amdgpu_ring_test_ring(kiq_ring); 3580 if (r) { 3581 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3582 ring->name); 3583 goto pipe_reset; 3584 } 3585 3586 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3587 if (r) 3588 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3589 3590 pipe_reset: 3591 if (r) { 3592 if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3593 return -EOPNOTSUPP; 3594 r = gfx_v9_4_3_reset_hw_pipe(ring); 3595 reset_mode = AMDGPU_RESET_TYPE_PER_PIPE; 3596 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3597 r ? "failed" : "successfully"); 3598 if (r) 3599 return r; 3600 } 3601 3602 gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3603 3604 spin_lock_irqsave(&kiq->ring_lock, flags); 3605 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3606 if (r) { 3607 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3608 return -ENOMEM; 3609 } 3610 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3611 amdgpu_ring_commit(kiq_ring); 3612 r = amdgpu_ring_test_ring(kiq_ring); 3613 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3614 if (r) { 3615 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) 3616 goto pipe_reset; 3617 3618 dev_err(adev->dev, "fail to remap queue\n"); 3619 return r; 3620 } 3621 3622 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) { 3623 r = amdgpu_ring_test_ring(ring); 3624 if (r) 3625 goto pipe_reset; 3626 } 3627 3628 3629 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 3630 } 3631 3632 enum amdgpu_gfx_cp_ras_mem_id { 3633 AMDGPU_GFX_CP_MEM1 = 1, 3634 AMDGPU_GFX_CP_MEM2, 3635 AMDGPU_GFX_CP_MEM3, 3636 AMDGPU_GFX_CP_MEM4, 3637 AMDGPU_GFX_CP_MEM5, 3638 }; 3639 3640 enum amdgpu_gfx_gcea_ras_mem_id { 3641 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3642 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3643 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3644 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3645 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3646 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3647 AMDGPU_GFX_GCEA_MAM_DMEM0, 3648 AMDGPU_GFX_GCEA_MAM_DMEM1, 3649 AMDGPU_GFX_GCEA_MAM_DMEM2, 3650 AMDGPU_GFX_GCEA_MAM_DMEM3, 3651 AMDGPU_GFX_GCEA_MAM_AMEM0, 3652 AMDGPU_GFX_GCEA_MAM_AMEM1, 3653 AMDGPU_GFX_GCEA_MAM_AMEM2, 3654 AMDGPU_GFX_GCEA_MAM_AMEM3, 3655 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3656 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3657 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3658 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3659 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3660 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3661 }; 3662 3663 enum amdgpu_gfx_gc_cane_ras_mem_id { 3664 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3665 }; 3666 3667 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3668 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3669 }; 3670 3671 enum amdgpu_gfx_gds_ras_mem_id { 3672 AMDGPU_GFX_GDS_MEM0 = 0, 3673 }; 3674 3675 enum amdgpu_gfx_lds_ras_mem_id { 3676 AMDGPU_GFX_LDS_BANK0 = 0, 3677 AMDGPU_GFX_LDS_BANK1, 3678 AMDGPU_GFX_LDS_BANK2, 3679 AMDGPU_GFX_LDS_BANK3, 3680 AMDGPU_GFX_LDS_BANK4, 3681 AMDGPU_GFX_LDS_BANK5, 3682 AMDGPU_GFX_LDS_BANK6, 3683 AMDGPU_GFX_LDS_BANK7, 3684 AMDGPU_GFX_LDS_BANK8, 3685 AMDGPU_GFX_LDS_BANK9, 3686 AMDGPU_GFX_LDS_BANK10, 3687 AMDGPU_GFX_LDS_BANK11, 3688 AMDGPU_GFX_LDS_BANK12, 3689 AMDGPU_GFX_LDS_BANK13, 3690 AMDGPU_GFX_LDS_BANK14, 3691 AMDGPU_GFX_LDS_BANK15, 3692 AMDGPU_GFX_LDS_BANK16, 3693 AMDGPU_GFX_LDS_BANK17, 3694 AMDGPU_GFX_LDS_BANK18, 3695 AMDGPU_GFX_LDS_BANK19, 3696 AMDGPU_GFX_LDS_BANK20, 3697 AMDGPU_GFX_LDS_BANK21, 3698 AMDGPU_GFX_LDS_BANK22, 3699 AMDGPU_GFX_LDS_BANK23, 3700 AMDGPU_GFX_LDS_BANK24, 3701 AMDGPU_GFX_LDS_BANK25, 3702 AMDGPU_GFX_LDS_BANK26, 3703 AMDGPU_GFX_LDS_BANK27, 3704 AMDGPU_GFX_LDS_BANK28, 3705 AMDGPU_GFX_LDS_BANK29, 3706 AMDGPU_GFX_LDS_BANK30, 3707 AMDGPU_GFX_LDS_BANK31, 3708 AMDGPU_GFX_LDS_SP_BUFFER_A, 3709 AMDGPU_GFX_LDS_SP_BUFFER_B, 3710 }; 3711 3712 enum amdgpu_gfx_rlc_ras_mem_id { 3713 AMDGPU_GFX_RLC_GPMF32 = 1, 3714 AMDGPU_GFX_RLC_RLCVF32, 3715 AMDGPU_GFX_RLC_SCRATCH, 3716 AMDGPU_GFX_RLC_SRM_ARAM, 3717 AMDGPU_GFX_RLC_SRM_DRAM, 3718 AMDGPU_GFX_RLC_TCTAG, 3719 AMDGPU_GFX_RLC_SPM_SE, 3720 AMDGPU_GFX_RLC_SPM_GRBMT, 3721 }; 3722 3723 enum amdgpu_gfx_sp_ras_mem_id { 3724 AMDGPU_GFX_SP_SIMDID0 = 0, 3725 }; 3726 3727 enum amdgpu_gfx_spi_ras_mem_id { 3728 AMDGPU_GFX_SPI_MEM0 = 0, 3729 AMDGPU_GFX_SPI_MEM1, 3730 AMDGPU_GFX_SPI_MEM2, 3731 AMDGPU_GFX_SPI_MEM3, 3732 }; 3733 3734 enum amdgpu_gfx_sqc_ras_mem_id { 3735 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3736 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3737 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3738 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3739 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3740 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3741 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3742 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3743 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3744 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3745 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3746 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3747 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3748 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3749 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3750 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3751 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3752 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3753 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3754 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3755 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3756 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3757 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3758 }; 3759 3760 enum amdgpu_gfx_sq_ras_mem_id { 3761 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3762 AMDGPU_GFX_SQ_SGPR_MEM1, 3763 AMDGPU_GFX_SQ_SGPR_MEM2, 3764 AMDGPU_GFX_SQ_SGPR_MEM3, 3765 }; 3766 3767 enum amdgpu_gfx_ta_ras_mem_id { 3768 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3769 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3770 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3771 AMDGPU_GFX_TA_FSX_LFIFO, 3772 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3773 }; 3774 3775 enum amdgpu_gfx_tcc_ras_mem_id { 3776 AMDGPU_GFX_TCC_MEM1 = 1, 3777 }; 3778 3779 enum amdgpu_gfx_tca_ras_mem_id { 3780 AMDGPU_GFX_TCA_MEM1 = 1, 3781 }; 3782 3783 enum amdgpu_gfx_tci_ras_mem_id { 3784 AMDGPU_GFX_TCIW_MEM = 1, 3785 }; 3786 3787 enum amdgpu_gfx_tcp_ras_mem_id { 3788 AMDGPU_GFX_TCP_LFIFO0 = 1, 3789 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3790 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3791 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3792 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3793 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3794 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3795 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3796 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3797 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3798 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3799 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3800 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3801 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3802 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3803 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3804 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3805 AMDGPU_GFX_TCP_VM_FIFO, 3806 AMDGPU_GFX_TCP_DB_TAGRAM0, 3807 AMDGPU_GFX_TCP_DB_TAGRAM1, 3808 AMDGPU_GFX_TCP_DB_TAGRAM2, 3809 AMDGPU_GFX_TCP_DB_TAGRAM3, 3810 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3811 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3812 AMDGPU_GFX_TCP_CMD_FIFO, 3813 }; 3814 3815 enum amdgpu_gfx_td_ras_mem_id { 3816 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3817 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3818 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3819 }; 3820 3821 enum amdgpu_gfx_tcx_ras_mem_id { 3822 AMDGPU_GFX_TCX_FIFOD0 = 0, 3823 AMDGPU_GFX_TCX_FIFOD1, 3824 AMDGPU_GFX_TCX_FIFOD2, 3825 AMDGPU_GFX_TCX_FIFOD3, 3826 AMDGPU_GFX_TCX_FIFOD4, 3827 AMDGPU_GFX_TCX_FIFOD5, 3828 AMDGPU_GFX_TCX_FIFOD6, 3829 AMDGPU_GFX_TCX_FIFOD7, 3830 AMDGPU_GFX_TCX_FIFOB0, 3831 AMDGPU_GFX_TCX_FIFOB1, 3832 AMDGPU_GFX_TCX_FIFOB2, 3833 AMDGPU_GFX_TCX_FIFOB3, 3834 AMDGPU_GFX_TCX_FIFOB4, 3835 AMDGPU_GFX_TCX_FIFOB5, 3836 AMDGPU_GFX_TCX_FIFOB6, 3837 AMDGPU_GFX_TCX_FIFOB7, 3838 AMDGPU_GFX_TCX_FIFOA0, 3839 AMDGPU_GFX_TCX_FIFOA1, 3840 AMDGPU_GFX_TCX_FIFOA2, 3841 AMDGPU_GFX_TCX_FIFOA3, 3842 AMDGPU_GFX_TCX_FIFOA4, 3843 AMDGPU_GFX_TCX_FIFOA5, 3844 AMDGPU_GFX_TCX_FIFOA6, 3845 AMDGPU_GFX_TCX_FIFOA7, 3846 AMDGPU_GFX_TCX_CFIFO0, 3847 AMDGPU_GFX_TCX_CFIFO1, 3848 AMDGPU_GFX_TCX_CFIFO2, 3849 AMDGPU_GFX_TCX_CFIFO3, 3850 AMDGPU_GFX_TCX_CFIFO4, 3851 AMDGPU_GFX_TCX_CFIFO5, 3852 AMDGPU_GFX_TCX_CFIFO6, 3853 AMDGPU_GFX_TCX_CFIFO7, 3854 AMDGPU_GFX_TCX_FIFO_ACKB0, 3855 AMDGPU_GFX_TCX_FIFO_ACKB1, 3856 AMDGPU_GFX_TCX_FIFO_ACKB2, 3857 AMDGPU_GFX_TCX_FIFO_ACKB3, 3858 AMDGPU_GFX_TCX_FIFO_ACKB4, 3859 AMDGPU_GFX_TCX_FIFO_ACKB5, 3860 AMDGPU_GFX_TCX_FIFO_ACKB6, 3861 AMDGPU_GFX_TCX_FIFO_ACKB7, 3862 AMDGPU_GFX_TCX_FIFO_ACKD0, 3863 AMDGPU_GFX_TCX_FIFO_ACKD1, 3864 AMDGPU_GFX_TCX_FIFO_ACKD2, 3865 AMDGPU_GFX_TCX_FIFO_ACKD3, 3866 AMDGPU_GFX_TCX_FIFO_ACKD4, 3867 AMDGPU_GFX_TCX_FIFO_ACKD5, 3868 AMDGPU_GFX_TCX_FIFO_ACKD6, 3869 AMDGPU_GFX_TCX_FIFO_ACKD7, 3870 AMDGPU_GFX_TCX_DST_FIFOA0, 3871 AMDGPU_GFX_TCX_DST_FIFOA1, 3872 AMDGPU_GFX_TCX_DST_FIFOA2, 3873 AMDGPU_GFX_TCX_DST_FIFOA3, 3874 AMDGPU_GFX_TCX_DST_FIFOA4, 3875 AMDGPU_GFX_TCX_DST_FIFOA5, 3876 AMDGPU_GFX_TCX_DST_FIFOA6, 3877 AMDGPU_GFX_TCX_DST_FIFOA7, 3878 AMDGPU_GFX_TCX_DST_FIFOB0, 3879 AMDGPU_GFX_TCX_DST_FIFOB1, 3880 AMDGPU_GFX_TCX_DST_FIFOB2, 3881 AMDGPU_GFX_TCX_DST_FIFOB3, 3882 AMDGPU_GFX_TCX_DST_FIFOB4, 3883 AMDGPU_GFX_TCX_DST_FIFOB5, 3884 AMDGPU_GFX_TCX_DST_FIFOB6, 3885 AMDGPU_GFX_TCX_DST_FIFOB7, 3886 AMDGPU_GFX_TCX_DST_FIFOD0, 3887 AMDGPU_GFX_TCX_DST_FIFOD1, 3888 AMDGPU_GFX_TCX_DST_FIFOD2, 3889 AMDGPU_GFX_TCX_DST_FIFOD3, 3890 AMDGPU_GFX_TCX_DST_FIFOD4, 3891 AMDGPU_GFX_TCX_DST_FIFOD5, 3892 AMDGPU_GFX_TCX_DST_FIFOD6, 3893 AMDGPU_GFX_TCX_DST_FIFOD7, 3894 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3895 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3896 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3897 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3898 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3899 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3900 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3901 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3902 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3903 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3904 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3905 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3906 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3907 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3908 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3909 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3910 }; 3911 3912 enum amdgpu_gfx_atc_l2_ras_mem_id { 3913 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3914 }; 3915 3916 enum amdgpu_gfx_utcl2_ras_mem_id { 3917 AMDGPU_GFX_UTCL2_MEM0 = 0, 3918 }; 3919 3920 enum amdgpu_gfx_vml2_ras_mem_id { 3921 AMDGPU_GFX_VML2_MEM0 = 0, 3922 }; 3923 3924 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3925 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3926 }; 3927 3928 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3929 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3930 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3931 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3932 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3933 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3934 }; 3935 3936 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3937 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3938 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3939 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3940 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3941 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3942 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3943 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3944 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3945 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3946 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3947 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3948 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3949 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3950 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3951 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3952 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3953 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3954 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3955 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3956 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3957 }; 3958 3959 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3960 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3961 }; 3962 3963 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3964 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3965 }; 3966 3967 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3968 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3969 }; 3970 3971 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3972 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3973 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3974 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3975 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3976 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3977 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3978 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3979 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3980 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3981 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3982 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3983 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3984 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3985 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3986 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3987 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3988 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3989 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3990 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3991 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3992 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3993 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3994 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3995 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3996 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3997 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3998 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3999 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 4000 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 4001 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 4002 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 4003 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 4004 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 4005 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4006 }; 4007 4008 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4009 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4010 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4011 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4012 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4013 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4014 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4015 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4016 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4017 }; 4018 4019 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4020 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4021 }; 4022 4023 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4024 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4025 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4026 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4027 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4028 }; 4029 4030 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4031 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4032 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4033 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4034 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4035 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4036 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4037 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4038 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4039 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4040 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4041 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4042 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4043 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4044 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4045 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4046 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4047 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4048 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4049 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4050 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4051 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4052 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4053 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4054 }; 4055 4056 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4057 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4058 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4059 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4060 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4061 }; 4062 4063 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4064 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4065 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4066 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4067 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4068 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4069 }; 4070 4071 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4072 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4073 }; 4074 4075 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4076 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4077 }; 4078 4079 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4080 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4081 }; 4082 4083 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4084 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4085 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4086 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4087 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4088 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4089 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4090 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4091 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4092 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4093 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4094 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4095 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4096 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4097 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4098 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4099 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4100 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4101 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4102 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4103 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4104 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4105 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4106 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4107 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4108 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4109 }; 4110 4111 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4112 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4113 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4114 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4115 }; 4116 4117 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4118 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4119 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4120 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4121 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4122 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4123 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4124 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4125 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4126 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4127 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4128 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4129 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4130 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4131 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4132 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4133 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4134 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4135 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4136 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4137 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4138 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4139 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4140 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4141 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4142 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4143 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4144 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4145 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4146 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4147 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4148 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4149 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4150 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4151 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4152 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4153 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4154 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4155 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4156 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4157 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4158 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4159 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4160 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4161 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4162 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4163 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4164 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4165 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4166 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4167 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4168 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4169 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4170 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4171 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4172 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4173 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4174 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4175 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4176 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4177 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4178 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4179 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4180 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4181 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4182 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4183 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4184 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4185 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4186 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4187 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4188 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4189 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4190 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4191 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4192 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4193 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4194 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4195 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4196 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4197 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4198 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4199 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4200 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4201 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4202 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4203 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4204 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4205 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4206 }; 4207 4208 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4209 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4210 }; 4211 4212 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4213 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4214 }; 4215 4216 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4217 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4218 }; 4219 4220 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4221 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4222 }; 4223 4224 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4225 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4226 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4227 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4228 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4229 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4230 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4231 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4232 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4233 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4234 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4235 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4236 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4237 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4238 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4239 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4240 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4241 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4242 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4243 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4244 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4245 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4246 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4247 }; 4248 4249 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4250 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4251 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4252 AMDGPU_GFX_RLC_MEM, 1}, 4253 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4254 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4255 AMDGPU_GFX_CP_MEM, 1}, 4256 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4257 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4258 AMDGPU_GFX_CP_MEM, 1}, 4259 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4260 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4261 AMDGPU_GFX_CP_MEM, 1}, 4262 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4263 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4264 AMDGPU_GFX_GDS_MEM, 1}, 4265 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4266 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4267 AMDGPU_GFX_GC_CANE_MEM, 1}, 4268 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4269 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4270 AMDGPU_GFX_SPI_MEM, 1}, 4271 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4272 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4273 AMDGPU_GFX_SP_MEM, 4}, 4274 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4275 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4276 AMDGPU_GFX_SP_MEM, 4}, 4277 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4278 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4279 AMDGPU_GFX_SQ_MEM, 4}, 4280 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4281 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4282 AMDGPU_GFX_SQC_MEM, 4}, 4283 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4284 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4285 AMDGPU_GFX_TCX_MEM, 1}, 4286 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4287 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4288 AMDGPU_GFX_TCC_MEM, 1}, 4289 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4290 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4291 AMDGPU_GFX_TA_MEM, 4}, 4292 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4293 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4294 AMDGPU_GFX_TCI_MEM, 1}, 4295 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4296 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4297 AMDGPU_GFX_TCP_MEM, 4}, 4298 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4299 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4300 AMDGPU_GFX_TD_MEM, 4}, 4301 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4302 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4303 AMDGPU_GFX_GCEA_MEM, 1}, 4304 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4305 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4306 AMDGPU_GFX_LDS_MEM, 4}, 4307 }; 4308 4309 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4310 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4311 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4312 AMDGPU_GFX_RLC_MEM, 1}, 4313 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4314 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4315 AMDGPU_GFX_CP_MEM, 1}, 4316 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4317 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4318 AMDGPU_GFX_CP_MEM, 1}, 4319 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4320 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4321 AMDGPU_GFX_CP_MEM, 1}, 4322 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4323 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4324 AMDGPU_GFX_GDS_MEM, 1}, 4325 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4326 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4327 AMDGPU_GFX_GC_CANE_MEM, 1}, 4328 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4329 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4330 AMDGPU_GFX_SPI_MEM, 1}, 4331 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4332 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4333 AMDGPU_GFX_SP_MEM, 4}, 4334 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4335 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4336 AMDGPU_GFX_SP_MEM, 4}, 4337 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4338 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4339 AMDGPU_GFX_SQ_MEM, 4}, 4340 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4341 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4342 AMDGPU_GFX_SQC_MEM, 4}, 4343 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4344 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4345 AMDGPU_GFX_TCX_MEM, 1}, 4346 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4347 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4348 AMDGPU_GFX_TCC_MEM, 1}, 4349 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4350 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4351 AMDGPU_GFX_TA_MEM, 4}, 4352 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4353 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4354 AMDGPU_GFX_TCI_MEM, 1}, 4355 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4356 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4357 AMDGPU_GFX_TCP_MEM, 4}, 4358 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4359 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4360 AMDGPU_GFX_TD_MEM, 4}, 4361 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4362 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4363 AMDGPU_GFX_TCA_MEM, 1}, 4364 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4365 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4366 AMDGPU_GFX_GCEA_MEM, 1}, 4367 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4368 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4369 AMDGPU_GFX_LDS_MEM, 4}, 4370 }; 4371 4372 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4373 void *ras_error_status, int xcc_id) 4374 { 4375 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4376 unsigned long ce_count = 0, ue_count = 0; 4377 uint32_t i, j, k; 4378 4379 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4380 struct amdgpu_smuio_mcm_config_info mcm_info = { 4381 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4382 .die_id = xcc_id & 0x01 ? 1 : 0, 4383 }; 4384 4385 mutex_lock(&adev->grbm_idx_mutex); 4386 4387 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4388 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4389 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4390 /* no need to select if instance number is 1 */ 4391 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4392 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4393 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4394 4395 amdgpu_ras_inst_query_ras_error_count(adev, 4396 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4397 1, 4398 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4399 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4400 GET_INST(GC, xcc_id), 4401 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4402 &ce_count); 4403 4404 amdgpu_ras_inst_query_ras_error_count(adev, 4405 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4406 1, 4407 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4408 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4409 GET_INST(GC, xcc_id), 4410 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4411 &ue_count); 4412 } 4413 } 4414 } 4415 4416 /* handle extra register entries of UE */ 4417 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4418 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4419 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4420 /* no need to select if instance number is 1 */ 4421 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4422 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4423 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4424 4425 amdgpu_ras_inst_query_ras_error_count(adev, 4426 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4427 1, 4428 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4429 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4430 GET_INST(GC, xcc_id), 4431 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4432 &ue_count); 4433 } 4434 } 4435 } 4436 4437 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4438 xcc_id); 4439 mutex_unlock(&adev->grbm_idx_mutex); 4440 4441 /* the caller should make sure initialize value of 4442 * err_data->ue_count and err_data->ce_count 4443 */ 4444 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4445 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4446 } 4447 4448 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4449 void *ras_error_status, int xcc_id) 4450 { 4451 uint32_t i, j, k; 4452 4453 mutex_lock(&adev->grbm_idx_mutex); 4454 4455 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4456 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4457 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4458 /* no need to select if instance number is 1 */ 4459 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4460 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4461 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4462 4463 amdgpu_ras_inst_reset_ras_error_count(adev, 4464 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4465 1, 4466 GET_INST(GC, xcc_id)); 4467 4468 amdgpu_ras_inst_reset_ras_error_count(adev, 4469 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4470 1, 4471 GET_INST(GC, xcc_id)); 4472 } 4473 } 4474 } 4475 4476 /* handle extra register entries of UE */ 4477 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4478 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4479 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4480 /* no need to select if instance number is 1 */ 4481 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4482 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4483 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4484 4485 amdgpu_ras_inst_reset_ras_error_count(adev, 4486 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4487 1, 4488 GET_INST(GC, xcc_id)); 4489 } 4490 } 4491 } 4492 4493 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4494 xcc_id); 4495 mutex_unlock(&adev->grbm_idx_mutex); 4496 } 4497 4498 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4499 void *ras_error_status, int xcc_id) 4500 { 4501 uint32_t i; 4502 uint32_t data; 4503 4504 if (amdgpu_sriov_vf(adev)) 4505 return; 4506 4507 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4508 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4509 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4510 4511 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4512 (amdgpu_watchdog_timer.period < 1 || 4513 amdgpu_watchdog_timer.period > 0x23)) { 4514 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4515 amdgpu_watchdog_timer.period = 0x23; 4516 } 4517 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4518 amdgpu_watchdog_timer.period); 4519 4520 mutex_lock(&adev->grbm_idx_mutex); 4521 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4522 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4523 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4524 } 4525 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4526 xcc_id); 4527 mutex_unlock(&adev->grbm_idx_mutex); 4528 } 4529 4530 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4531 void *ras_error_status) 4532 { 4533 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4534 gfx_v9_4_3_inst_query_ras_err_count); 4535 } 4536 4537 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4538 { 4539 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4540 } 4541 4542 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4543 { 4544 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4545 } 4546 4547 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4548 { 4549 /* Header itself is a NOP packet */ 4550 if (num_nop == 1) { 4551 amdgpu_ring_write(ring, ring->funcs->nop); 4552 return; 4553 } 4554 4555 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4556 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4557 4558 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4559 amdgpu_ring_insert_nop(ring, num_nop - 1); 4560 } 4561 4562 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4563 { 4564 struct amdgpu_device *adev = ip_block->adev; 4565 uint32_t i, j, k; 4566 uint32_t xcc_id, xcc_offset, inst_offset; 4567 uint32_t num_xcc, reg, num_inst; 4568 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4569 4570 if (!adev->gfx.ip_dump_core) 4571 return; 4572 4573 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4574 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4575 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4576 xcc_offset = xcc_id * reg_count; 4577 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4578 for (i = 0; i < reg_count; i++) 4579 drm_printf(p, "%-50s \t 0x%08x\n", 4580 gc_reg_list_9_4_3[i].reg_name, 4581 adev->gfx.ip_dump_core[xcc_offset + i]); 4582 } 4583 4584 /* print compute queue registers for all instances */ 4585 if (!adev->gfx.ip_dump_compute_queues) 4586 return; 4587 4588 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4589 adev->gfx.mec.num_queue_per_pipe; 4590 4591 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4592 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4593 num_xcc, 4594 adev->gfx.mec.num_mec, 4595 adev->gfx.mec.num_pipe_per_mec, 4596 adev->gfx.mec.num_queue_per_pipe); 4597 4598 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4599 xcc_offset = xcc_id * reg_count * num_inst; 4600 inst_offset = 0; 4601 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4602 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4603 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4604 drm_printf(p, 4605 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4606 xcc_id, i, j, k); 4607 for (reg = 0; reg < reg_count; reg++) { 4608 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4609 regCP_MEC_ME1_HEADER_DUMP) 4610 drm_printf(p, 4611 "%-50s \t 0x%08x\n", 4612 "regCP_MEC_ME2_HEADER_DUMP", 4613 adev->gfx.ip_dump_compute_queues 4614 [xcc_offset + inst_offset + 4615 reg]); 4616 else 4617 drm_printf(p, 4618 "%-50s \t 0x%08x\n", 4619 gc_cp_reg_list_9_4_3[reg].reg_name, 4620 adev->gfx.ip_dump_compute_queues 4621 [xcc_offset + inst_offset + 4622 reg]); 4623 } 4624 inst_offset += reg_count; 4625 } 4626 } 4627 } 4628 } 4629 } 4630 4631 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4632 { 4633 struct amdgpu_device *adev = ip_block->adev; 4634 uint32_t i, j, k; 4635 uint32_t num_xcc, reg, num_inst; 4636 uint32_t xcc_id, xcc_offset, inst_offset; 4637 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4638 4639 if (!adev->gfx.ip_dump_core) 4640 return; 4641 4642 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4643 4644 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4645 xcc_offset = xcc_id * reg_count; 4646 for (i = 0; i < reg_count; i++) 4647 adev->gfx.ip_dump_core[xcc_offset + i] = 4648 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4649 GET_INST(GC, xcc_id))); 4650 } 4651 4652 /* dump compute queue registers for all instances */ 4653 if (!adev->gfx.ip_dump_compute_queues) 4654 return; 4655 4656 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4657 adev->gfx.mec.num_queue_per_pipe; 4658 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4659 mutex_lock(&adev->srbm_mutex); 4660 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4661 xcc_offset = xcc_id * reg_count * num_inst; 4662 inst_offset = 0; 4663 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4664 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4665 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4666 /* ME0 is for GFX so start from 1 for CP */ 4667 soc15_grbm_select(adev, 1 + i, j, k, 0, 4668 GET_INST(GC, xcc_id)); 4669 4670 for (reg = 0; reg < reg_count; reg++) { 4671 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4672 regCP_MEC_ME1_HEADER_DUMP) 4673 adev->gfx.ip_dump_compute_queues 4674 [xcc_offset + 4675 inst_offset + reg] = 4676 RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), 4677 regCP_MEC_ME2_HEADER_DUMP)); 4678 else 4679 adev->gfx.ip_dump_compute_queues 4680 [xcc_offset + 4681 inst_offset + reg] = 4682 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4683 gc_cp_reg_list_9_4_3[reg], 4684 GET_INST(GC, xcc_id))); 4685 } 4686 inst_offset += reg_count; 4687 } 4688 } 4689 } 4690 } 4691 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4692 mutex_unlock(&adev->srbm_mutex); 4693 } 4694 4695 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4696 { 4697 /* Emit the cleaner shader */ 4698 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4699 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4700 } 4701 4702 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4703 .name = "gfx_v9_4_3", 4704 .early_init = gfx_v9_4_3_early_init, 4705 .late_init = gfx_v9_4_3_late_init, 4706 .sw_init = gfx_v9_4_3_sw_init, 4707 .sw_fini = gfx_v9_4_3_sw_fini, 4708 .hw_init = gfx_v9_4_3_hw_init, 4709 .hw_fini = gfx_v9_4_3_hw_fini, 4710 .suspend = gfx_v9_4_3_suspend, 4711 .resume = gfx_v9_4_3_resume, 4712 .is_idle = gfx_v9_4_3_is_idle, 4713 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4714 .soft_reset = gfx_v9_4_3_soft_reset, 4715 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4716 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4717 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4718 .dump_ip_state = gfx_v9_4_3_ip_dump, 4719 .print_ip_state = gfx_v9_4_3_ip_print, 4720 }; 4721 4722 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4723 .type = AMDGPU_RING_TYPE_COMPUTE, 4724 .align_mask = 0xff, 4725 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4726 .support_64bit_ptrs = true, 4727 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4728 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4729 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4730 .emit_frame_size = 4731 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4732 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4733 5 + /* hdp invalidate */ 4734 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4735 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4736 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4737 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4738 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4739 7 + /* gfx_v9_4_3_emit_mem_sync */ 4740 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4741 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4742 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4743 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4744 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4745 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4746 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4747 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4748 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4749 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4750 .test_ring = gfx_v9_4_3_ring_test_ring, 4751 .test_ib = gfx_v9_4_3_ring_test_ib, 4752 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4753 .pad_ib = amdgpu_ring_generic_pad_ib, 4754 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4755 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4756 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4757 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4758 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4759 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4760 .reset = gfx_v9_4_3_reset_kcq, 4761 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4762 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4763 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4764 }; 4765 4766 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4767 .type = AMDGPU_RING_TYPE_KIQ, 4768 .align_mask = 0xff, 4769 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4770 .support_64bit_ptrs = true, 4771 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4772 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4773 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4774 .emit_frame_size = 4775 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4776 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4777 5 + /* hdp invalidate */ 4778 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4779 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4780 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4781 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4782 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4783 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4784 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4785 .test_ring = gfx_v9_4_3_ring_test_ring, 4786 .insert_nop = amdgpu_ring_insert_nop, 4787 .pad_ib = amdgpu_ring_generic_pad_ib, 4788 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4789 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4790 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4791 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4792 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4793 }; 4794 4795 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4796 { 4797 int i, j, num_xcc; 4798 4799 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4800 for (i = 0; i < num_xcc; i++) { 4801 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4802 4803 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4804 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4805 = &gfx_v9_4_3_ring_funcs_compute; 4806 } 4807 } 4808 4809 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4810 .set = gfx_v9_4_3_set_eop_interrupt_state, 4811 .process = gfx_v9_4_3_eop_irq, 4812 }; 4813 4814 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4815 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4816 .process = gfx_v9_4_3_priv_reg_irq, 4817 }; 4818 4819 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4820 .set = gfx_v9_4_3_set_bad_op_fault_state, 4821 .process = gfx_v9_4_3_bad_op_irq, 4822 }; 4823 4824 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4825 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4826 .process = gfx_v9_4_3_priv_inst_irq, 4827 }; 4828 4829 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4830 { 4831 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4832 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4833 4834 adev->gfx.priv_reg_irq.num_types = 1; 4835 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4836 4837 adev->gfx.bad_op_irq.num_types = 1; 4838 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4839 4840 adev->gfx.priv_inst_irq.num_types = 1; 4841 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4842 } 4843 4844 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4845 { 4846 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4847 } 4848 4849 4850 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4851 { 4852 /* 9.4.3 variants removed all the GDS internal memory, 4853 * only support GWS opcode in kernel, like barrier 4854 * semaphore.etc */ 4855 4856 /* init asic gds info */ 4857 adev->gds.gds_size = 0; 4858 adev->gds.gds_compute_max_wave_id = 0; 4859 adev->gds.gws_size = 64; 4860 adev->gds.oa_size = 16; 4861 } 4862 4863 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4864 u32 bitmap, int xcc_id) 4865 { 4866 u32 data; 4867 4868 if (!bitmap) 4869 return; 4870 4871 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4872 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4873 4874 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4875 } 4876 4877 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4878 { 4879 u32 data, mask; 4880 4881 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4882 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4883 4884 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4885 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4886 4887 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4888 4889 return (~data) & mask; 4890 } 4891 4892 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4893 struct amdgpu_cu_info *cu_info) 4894 { 4895 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4896 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4897 unsigned disable_masks[4 * 4]; 4898 bool is_symmetric_cus; 4899 4900 if (!adev || !cu_info) 4901 return -EINVAL; 4902 4903 /* 4904 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4905 */ 4906 if (adev->gfx.config.max_shader_engines * 4907 adev->gfx.config.max_sh_per_se > 16) 4908 return -EINVAL; 4909 4910 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4911 adev->gfx.config.max_shader_engines, 4912 adev->gfx.config.max_sh_per_se); 4913 4914 mutex_lock(&adev->grbm_idx_mutex); 4915 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4916 is_symmetric_cus = true; 4917 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4918 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4919 mask = 1; 4920 ao_bitmap = 0; 4921 counter = 0; 4922 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4923 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4924 adev, 4925 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4926 xcc_id); 4927 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4928 4929 cu_info->bitmap[xcc_id][i][j] = bitmap; 4930 4931 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4932 if (bitmap & mask) { 4933 if (counter < adev->gfx.config.max_cu_per_sh) 4934 ao_bitmap |= mask; 4935 counter++; 4936 } 4937 mask <<= 1; 4938 } 4939 active_cu_number += counter; 4940 if (i < 2 && j < 2) 4941 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4942 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4943 } 4944 if (i && is_symmetric_cus && prev_counter != counter) 4945 is_symmetric_cus = false; 4946 prev_counter = counter; 4947 } 4948 if (is_symmetric_cus) { 4949 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4950 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4951 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4952 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4953 } 4954 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4955 xcc_id); 4956 } 4957 mutex_unlock(&adev->grbm_idx_mutex); 4958 4959 cu_info->number = active_cu_number; 4960 cu_info->ao_cu_mask = ao_cu_mask; 4961 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4962 4963 return 0; 4964 } 4965 4966 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4967 .type = AMD_IP_BLOCK_TYPE_GFX, 4968 .major = 9, 4969 .minor = 4, 4970 .rev = 3, 4971 .funcs = &gfx_v9_4_3_ip_funcs, 4972 }; 4973 4974 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4975 { 4976 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4977 uint32_t tmp_mask; 4978 int i, r; 4979 4980 /* TODO : Initialize golden regs */ 4981 /* gfx_v9_4_3_init_golden_registers(adev); */ 4982 4983 tmp_mask = inst_mask; 4984 for_each_inst(i, tmp_mask) 4985 gfx_v9_4_3_xcc_constants_init(adev, i); 4986 4987 if (!amdgpu_sriov_vf(adev)) { 4988 tmp_mask = inst_mask; 4989 for_each_inst(i, tmp_mask) { 4990 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4991 if (r) 4992 return r; 4993 } 4994 } 4995 4996 tmp_mask = inst_mask; 4997 for_each_inst(i, tmp_mask) { 4998 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4999 if (r) 5000 return r; 5001 } 5002 5003 return 0; 5004 } 5005 5006 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 5007 { 5008 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5009 int i; 5010 5011 for_each_inst(i, inst_mask) 5012 gfx_v9_4_3_xcc_fini(adev, i); 5013 5014 return 0; 5015 } 5016 5017 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5018 .suspend = &gfx_v9_4_3_xcp_suspend, 5019 .resume = &gfx_v9_4_3_xcp_resume 5020 }; 5021 5022 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5023 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5024 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5025 }; 5026 5027 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5028 { 5029 int r; 5030 5031 r = amdgpu_ras_block_late_init(adev, ras_block); 5032 if (r) 5033 return r; 5034 5035 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5036 &gfx_v9_4_3_aca_info, 5037 NULL); 5038 if (r) 5039 goto late_fini; 5040 5041 return 0; 5042 5043 late_fini: 5044 amdgpu_ras_block_late_fini(adev, ras_block); 5045 5046 return r; 5047 } 5048 5049 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5050 .ras_block = { 5051 .hw_ops = &gfx_v9_4_3_ras_ops, 5052 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5053 }, 5054 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5055 }; 5056