1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* SE status registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 110 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 111 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 113 }; 114 115 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 116 /* compute queue registers */ 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 162 }; 163 164 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 165 166 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 167 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 168 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 169 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 170 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 171 struct amdgpu_cu_info *cu_info); 172 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 173 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 174 175 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 176 uint64_t queue_mask) 177 { 178 struct amdgpu_device *adev = kiq_ring->adev; 179 u64 shader_mc_addr; 180 181 /* Cleaner shader MC address */ 182 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 183 184 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 185 amdgpu_ring_write(kiq_ring, 186 PACKET3_SET_RESOURCES_VMID_MASK(0) | 187 /* vmid_mask:0* queue_type:0 (KIQ) */ 188 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 189 amdgpu_ring_write(kiq_ring, 190 lower_32_bits(queue_mask)); /* queue mask lo */ 191 amdgpu_ring_write(kiq_ring, 192 upper_32_bits(queue_mask)); /* queue mask hi */ 193 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 194 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 195 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 196 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 197 } 198 199 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 200 struct amdgpu_ring *ring) 201 { 202 struct amdgpu_device *adev = kiq_ring->adev; 203 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 204 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 205 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 206 207 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 208 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 209 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 210 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 211 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 212 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 213 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 214 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 215 /*queue_type: normal compute queue */ 216 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 217 /* alloc format: all_on_one_pipe */ 218 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 219 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 220 /* num_queues: must be 1 */ 221 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 222 amdgpu_ring_write(kiq_ring, 223 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 224 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 225 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 226 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 227 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 228 } 229 230 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 231 struct amdgpu_ring *ring, 232 enum amdgpu_unmap_queues_action action, 233 u64 gpu_addr, u64 seq) 234 { 235 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 236 237 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 238 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 239 PACKET3_UNMAP_QUEUES_ACTION(action) | 240 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 241 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 242 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 243 amdgpu_ring_write(kiq_ring, 244 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 245 246 if (action == PREEMPT_QUEUES_NO_UNMAP) { 247 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 248 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 249 amdgpu_ring_write(kiq_ring, seq); 250 } else { 251 amdgpu_ring_write(kiq_ring, 0); 252 amdgpu_ring_write(kiq_ring, 0); 253 amdgpu_ring_write(kiq_ring, 0); 254 } 255 } 256 257 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 258 struct amdgpu_ring *ring, 259 u64 addr, 260 u64 seq) 261 { 262 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 263 264 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 267 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 268 PACKET3_QUERY_STATUS_COMMAND(2)); 269 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 270 amdgpu_ring_write(kiq_ring, 271 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 272 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 273 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 274 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 275 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 276 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 277 } 278 279 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 280 uint16_t pasid, uint32_t flush_type, 281 bool all_hub) 282 { 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 284 amdgpu_ring_write(kiq_ring, 285 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 286 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 287 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 288 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 289 } 290 291 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 292 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 293 uint32_t xcc_id, uint32_t vmid) 294 { 295 struct amdgpu_device *adev = kiq_ring->adev; 296 unsigned i; 297 298 /* enter save mode */ 299 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 300 mutex_lock(&adev->srbm_mutex); 301 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 302 303 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 305 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 306 /* wait till dequeue take effects */ 307 for (i = 0; i < adev->usec_timeout; i++) { 308 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 309 break; 310 udelay(1); 311 } 312 if (i >= adev->usec_timeout) 313 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 314 } else { 315 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 316 } 317 318 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 319 mutex_unlock(&adev->srbm_mutex); 320 /* exit safe mode */ 321 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 322 } 323 324 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 325 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 326 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 327 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 328 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 329 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 330 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 331 .set_resources_size = 8, 332 .map_queues_size = 7, 333 .unmap_queues_size = 6, 334 .query_status_size = 7, 335 .invalidate_tlbs_size = 2, 336 }; 337 338 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 339 { 340 int i, num_xcc; 341 342 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 343 for (i = 0; i < num_xcc; i++) 344 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 345 } 346 347 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 348 { 349 int i, num_xcc, dev_inst; 350 351 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 352 for (i = 0; i < num_xcc; i++) { 353 dev_inst = GET_INST(GC, i); 354 355 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 356 GOLDEN_GB_ADDR_CONFIG); 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 358 } 359 } 360 361 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 362 { 363 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 364 365 /* If it is an XCC reg, normalize the reg to keep 366 lower 16 bits in local xcc */ 367 368 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 369 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 370 return normalized_reg; 371 else 372 return reg; 373 } 374 375 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 376 bool wc, uint32_t reg, uint32_t val) 377 { 378 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 379 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 380 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 381 WRITE_DATA_DST_SEL(0) | 382 (wc ? WR_CONFIRM : 0)); 383 amdgpu_ring_write(ring, reg); 384 amdgpu_ring_write(ring, 0); 385 amdgpu_ring_write(ring, val); 386 } 387 388 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 389 int mem_space, int opt, uint32_t addr0, 390 uint32_t addr1, uint32_t ref, uint32_t mask, 391 uint32_t inv) 392 { 393 /* Only do the normalization on regspace */ 394 if (mem_space == 0) { 395 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 396 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 397 } 398 399 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 400 amdgpu_ring_write(ring, 401 /* memory (1) or register (0) */ 402 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 403 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 404 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 405 WAIT_REG_MEM_ENGINE(eng_sel))); 406 407 if (mem_space) 408 BUG_ON(addr0 & 0x3); /* Dword align */ 409 amdgpu_ring_write(ring, addr0); 410 amdgpu_ring_write(ring, addr1); 411 amdgpu_ring_write(ring, ref); 412 amdgpu_ring_write(ring, mask); 413 amdgpu_ring_write(ring, inv); /* poll interval */ 414 } 415 416 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 417 { 418 uint32_t scratch_reg0_offset, xcc_offset; 419 struct amdgpu_device *adev = ring->adev; 420 uint32_t tmp = 0; 421 unsigned i; 422 int r; 423 424 /* Use register offset which is local to XCC in the packet */ 425 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 426 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 427 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 428 tmp = RREG32(scratch_reg0_offset); 429 430 r = amdgpu_ring_alloc(ring, 3); 431 if (r) 432 return r; 433 434 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 435 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 436 amdgpu_ring_write(ring, 0xDEADBEEF); 437 amdgpu_ring_commit(ring); 438 439 for (i = 0; i < adev->usec_timeout; i++) { 440 tmp = RREG32(scratch_reg0_offset); 441 if (tmp == 0xDEADBEEF) 442 break; 443 udelay(1); 444 } 445 446 if (i >= adev->usec_timeout) 447 r = -ETIMEDOUT; 448 return r; 449 } 450 451 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 struct amdgpu_ib ib; 455 struct dma_fence *f = NULL; 456 457 unsigned index; 458 uint64_t gpu_addr; 459 uint32_t tmp; 460 long r; 461 462 r = amdgpu_device_wb_get(adev, &index); 463 if (r) 464 return r; 465 466 gpu_addr = adev->wb.gpu_addr + (index * 4); 467 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 468 memset(&ib, 0, sizeof(ib)); 469 470 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 471 if (r) 472 goto err1; 473 474 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 475 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 476 ib.ptr[2] = lower_32_bits(gpu_addr); 477 ib.ptr[3] = upper_32_bits(gpu_addr); 478 ib.ptr[4] = 0xDEADBEEF; 479 ib.length_dw = 5; 480 481 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 482 if (r) 483 goto err2; 484 485 r = dma_fence_wait_timeout(f, false, timeout); 486 if (r == 0) { 487 r = -ETIMEDOUT; 488 goto err2; 489 } else if (r < 0) { 490 goto err2; 491 } 492 493 tmp = adev->wb.wb[index]; 494 if (tmp == 0xDEADBEEF) 495 r = 0; 496 else 497 r = -EINVAL; 498 499 err2: 500 amdgpu_ib_free(&ib, NULL); 501 dma_fence_put(f); 502 err1: 503 amdgpu_device_wb_free(adev, index); 504 return r; 505 } 506 507 508 /* This value might differs per partition */ 509 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 510 { 511 uint64_t clock; 512 513 mutex_lock(&adev->gfx.gpu_clock_mutex); 514 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 515 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 516 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 517 mutex_unlock(&adev->gfx.gpu_clock_mutex); 518 519 return clock; 520 } 521 522 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 523 { 524 amdgpu_ucode_release(&adev->gfx.pfp_fw); 525 amdgpu_ucode_release(&adev->gfx.me_fw); 526 amdgpu_ucode_release(&adev->gfx.ce_fw); 527 amdgpu_ucode_release(&adev->gfx.rlc_fw); 528 amdgpu_ucode_release(&adev->gfx.mec_fw); 529 amdgpu_ucode_release(&adev->gfx.mec2_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 535 const char *chip_name) 536 { 537 int err; 538 const struct rlc_firmware_header_v2_0 *rlc_hdr; 539 uint16_t version_major; 540 uint16_t version_minor; 541 542 543 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 544 AMDGPU_UCODE_REQUIRED, 545 "amdgpu/%s_rlc.bin", chip_name); 546 if (err) 547 goto out; 548 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 549 550 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 551 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 552 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 553 out: 554 if (err) 555 amdgpu_ucode_release(&adev->gfx.rlc_fw); 556 557 return err; 558 } 559 560 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 561 const char *chip_name) 562 { 563 int err; 564 565 if (amdgpu_sriov_vf(adev)) { 566 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 567 AMDGPU_UCODE_REQUIRED, 568 "amdgpu/%s_sjt_mec.bin", chip_name); 569 570 if (err) 571 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 572 AMDGPU_UCODE_REQUIRED, 573 "amdgpu/%s_mec.bin", chip_name); 574 } else 575 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 576 AMDGPU_UCODE_REQUIRED, 577 "amdgpu/%s_mec.bin", chip_name); 578 if (err) 579 goto out; 580 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 581 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 582 583 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 584 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 585 586 out: 587 if (err) 588 amdgpu_ucode_release(&adev->gfx.mec_fw); 589 return err; 590 } 591 592 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 593 { 594 char ucode_prefix[15]; 595 int r; 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 600 if (r) 601 return r; 602 603 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 604 if (r) 605 return r; 606 607 return r; 608 } 609 610 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 611 { 612 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 613 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 614 } 615 616 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 617 { 618 int r, i, num_xcc; 619 u32 *hpd; 620 const __le32 *fw_data; 621 unsigned fw_size; 622 u32 *fw; 623 size_t mec_hpd_size; 624 625 const struct gfx_firmware_header_v1_0 *mec_hdr; 626 627 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 628 for (i = 0; i < num_xcc; i++) 629 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 630 AMDGPU_MAX_COMPUTE_QUEUES); 631 632 /* take ownership of the relevant compute queues */ 633 amdgpu_gfx_compute_queue_acquire(adev); 634 mec_hpd_size = 635 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 636 if (mec_hpd_size) { 637 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 638 AMDGPU_GEM_DOMAIN_VRAM | 639 AMDGPU_GEM_DOMAIN_GTT, 640 &adev->gfx.mec.hpd_eop_obj, 641 &adev->gfx.mec.hpd_eop_gpu_addr, 642 (void **)&hpd); 643 if (r) { 644 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 645 gfx_v9_4_3_mec_fini(adev); 646 return r; 647 } 648 649 if (amdgpu_emu_mode == 1) { 650 for (i = 0; i < mec_hpd_size / 4; i++) { 651 memset((void *)(hpd + i), 0, 4); 652 if (i % 50 == 0) 653 msleep(1); 654 } 655 } else { 656 memset(hpd, 0, mec_hpd_size); 657 } 658 659 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 660 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 661 } 662 663 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 664 665 fw_data = (const __le32 *) 666 (adev->gfx.mec_fw->data + 667 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 668 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 669 670 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 671 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 672 &adev->gfx.mec.mec_fw_obj, 673 &adev->gfx.mec.mec_fw_gpu_addr, 674 (void **)&fw); 675 if (r) { 676 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 677 gfx_v9_4_3_mec_fini(adev); 678 return r; 679 } 680 681 memcpy(fw, fw_data, fw_size); 682 683 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 684 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 685 686 return 0; 687 } 688 689 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 690 u32 sh_num, u32 instance, int xcc_id) 691 { 692 u32 data; 693 694 if (instance == 0xffffffff) 695 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 696 INSTANCE_BROADCAST_WRITES, 1); 697 else 698 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 699 INSTANCE_INDEX, instance); 700 701 if (se_num == 0xffffffff) 702 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 703 SE_BROADCAST_WRITES, 1); 704 else 705 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 706 707 if (sh_num == 0xffffffff) 708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 709 SH_BROADCAST_WRITES, 1); 710 else 711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 712 713 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 714 } 715 716 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 717 { 718 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 719 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 720 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 721 (address << SQ_IND_INDEX__INDEX__SHIFT) | 722 (SQ_IND_INDEX__FORCE_READ_MASK)); 723 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 724 } 725 726 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 727 uint32_t wave, uint32_t thread, 728 uint32_t regno, uint32_t num, uint32_t *out) 729 { 730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 731 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 732 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 733 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 734 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 735 (SQ_IND_INDEX__FORCE_READ_MASK) | 736 (SQ_IND_INDEX__AUTO_INCR_MASK)); 737 while (num--) 738 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 739 } 740 741 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 742 uint32_t xcc_id, uint32_t simd, uint32_t wave, 743 uint32_t *dst, int *no_fields) 744 { 745 /* type 1 wave data */ 746 dst[(*no_fields)++] = 1; 747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 761 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 762 } 763 764 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 765 uint32_t wave, uint32_t start, 766 uint32_t size, uint32_t *dst) 767 { 768 wave_read_regs(adev, xcc_id, simd, wave, 0, 769 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 770 } 771 772 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 773 uint32_t wave, uint32_t thread, 774 uint32_t start, uint32_t size, 775 uint32_t *dst) 776 { 777 wave_read_regs(adev, xcc_id, simd, wave, thread, 778 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 779 } 780 781 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 782 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 783 { 784 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 785 } 786 787 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 788 { 789 u32 xcp_ctl; 790 791 /* Value is expected to be the same on all, fetch from first instance */ 792 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 793 794 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 795 } 796 797 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 798 int num_xccs_per_xcp) 799 { 800 int ret, i, num_xcc; 801 u32 tmp = 0; 802 803 if (adev->psp.funcs) { 804 ret = psp_spatial_partition(&adev->psp, 805 NUM_XCC(adev->gfx.xcc_mask) / 806 num_xccs_per_xcp); 807 if (ret) 808 return ret; 809 } else { 810 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 811 812 for (i = 0; i < num_xcc; i++) { 813 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 814 num_xccs_per_xcp); 815 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 816 i % num_xccs_per_xcp); 817 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 818 tmp); 819 } 820 ret = 0; 821 } 822 823 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 824 825 return ret; 826 } 827 828 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 829 { 830 int xcc; 831 832 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 833 if (!xcc) { 834 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 835 return -EINVAL; 836 } 837 838 return xcc - 1; 839 } 840 841 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 842 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 843 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 844 .read_wave_data = &gfx_v9_4_3_read_wave_data, 845 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 846 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 847 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 848 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 849 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 850 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 851 }; 852 853 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 854 struct aca_bank *bank, enum aca_smu_type type, 855 void *data) 856 { 857 struct aca_bank_info info; 858 u64 misc0; 859 u32 instlo; 860 int ret; 861 862 ret = aca_bank_info_decode(bank, &info); 863 if (ret) 864 return ret; 865 866 /* NOTE: overwrite info.die_id with xcd id for gfx */ 867 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 868 instlo &= GENMASK(31, 1); 869 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 870 871 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 872 873 switch (type) { 874 case ACA_SMU_TYPE_UE: 875 bank->aca_err_type = ACA_ERROR_TYPE_UE; 876 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL); 877 break; 878 case ACA_SMU_TYPE_CE: 879 bank->aca_err_type = ACA_ERROR_TYPE_CE; 880 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 881 ACA_REG__MISC0__ERRCNT(misc0)); 882 break; 883 default: 884 return -EINVAL; 885 } 886 887 return ret; 888 } 889 890 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 891 enum aca_smu_type type, void *data) 892 { 893 u32 instlo; 894 895 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 896 instlo &= GENMASK(31, 1); 897 switch (instlo) { 898 case mmSMNAID_XCD0_MCA_SMU: 899 case mmSMNAID_XCD1_MCA_SMU: 900 case mmSMNXCD_XCD0_MCA_SMU: 901 return true; 902 default: 903 break; 904 } 905 906 return false; 907 } 908 909 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 910 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 911 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 912 }; 913 914 static const struct aca_info gfx_v9_4_3_aca_info = { 915 .hwip = ACA_HWIP_TYPE_SMU, 916 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 917 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 918 }; 919 920 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 921 { 922 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 923 adev->gfx.ras = &gfx_v9_4_3_ras; 924 925 adev->gfx.config.max_hw_contexts = 8; 926 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 927 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 928 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 929 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 930 adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG; 931 932 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 933 REG_GET_FIELD( 934 adev->gfx.config.gb_addr_config, 935 GB_ADDR_CONFIG, 936 NUM_PIPES); 937 938 adev->gfx.config.max_tile_pipes = 939 adev->gfx.config.gb_addr_config_fields.num_pipes; 940 941 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 942 REG_GET_FIELD( 943 adev->gfx.config.gb_addr_config, 944 GB_ADDR_CONFIG, 945 NUM_BANKS); 946 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 947 REG_GET_FIELD( 948 adev->gfx.config.gb_addr_config, 949 GB_ADDR_CONFIG, 950 MAX_COMPRESSED_FRAGS); 951 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 952 REG_GET_FIELD( 953 adev->gfx.config.gb_addr_config, 954 GB_ADDR_CONFIG, 955 NUM_RB_PER_SE); 956 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 957 REG_GET_FIELD( 958 adev->gfx.config.gb_addr_config, 959 GB_ADDR_CONFIG, 960 NUM_SHADER_ENGINES); 961 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 962 REG_GET_FIELD( 963 adev->gfx.config.gb_addr_config, 964 GB_ADDR_CONFIG, 965 PIPE_INTERLEAVE_SIZE)); 966 967 return 0; 968 } 969 970 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 971 int xcc_id, int mec, int pipe, int queue) 972 { 973 unsigned irq_type; 974 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 975 unsigned int hw_prio; 976 uint32_t xcc_doorbell_start; 977 978 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 979 ring_id]; 980 981 /* mec0 is me1 */ 982 ring->xcc_id = xcc_id; 983 ring->me = mec + 1; 984 ring->pipe = pipe; 985 ring->queue = queue; 986 987 ring->ring_obj = NULL; 988 ring->use_doorbell = true; 989 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 990 xcc_id * adev->doorbell_index.xcc_doorbell_range; 991 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 992 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 993 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 994 GFX9_MEC_HPD_SIZE; 995 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 996 sprintf(ring->name, "comp_%d.%d.%d.%d", 997 ring->xcc_id, ring->me, ring->pipe, ring->queue); 998 999 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1000 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1001 + ring->pipe; 1002 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1003 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1004 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1005 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1006 hw_prio, NULL); 1007 } 1008 1009 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1010 { 1011 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1012 uint32_t *ptr, num_xcc, inst; 1013 1014 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1015 1016 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1017 if (!ptr) { 1018 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1019 adev->gfx.ip_dump_core = NULL; 1020 } else { 1021 adev->gfx.ip_dump_core = ptr; 1022 } 1023 1024 /* Allocate memory for compute queue registers for all the instances */ 1025 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1026 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1027 adev->gfx.mec.num_queue_per_pipe; 1028 1029 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1030 if (!ptr) { 1031 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1032 adev->gfx.ip_dump_compute_queues = NULL; 1033 } else { 1034 adev->gfx.ip_dump_compute_queues = ptr; 1035 } 1036 } 1037 1038 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1039 { 1040 int i, j, k, r, ring_id, xcc_id, num_xcc; 1041 struct amdgpu_device *adev = ip_block->adev; 1042 1043 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1044 case IP_VERSION(9, 4, 3): 1045 case IP_VERSION(9, 4, 4): 1046 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1047 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1048 if (adev->gfx.mec_fw_version >= 153) { 1049 adev->gfx.enable_cleaner_shader = true; 1050 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1051 if (r) { 1052 adev->gfx.enable_cleaner_shader = false; 1053 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1054 } 1055 } 1056 break; 1057 default: 1058 adev->gfx.enable_cleaner_shader = false; 1059 break; 1060 } 1061 1062 adev->gfx.mec.num_mec = 2; 1063 adev->gfx.mec.num_pipe_per_mec = 4; 1064 adev->gfx.mec.num_queue_per_pipe = 8; 1065 1066 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1067 1068 /* EOP Event */ 1069 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1070 if (r) 1071 return r; 1072 1073 /* Bad opcode Event */ 1074 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1075 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1076 &adev->gfx.bad_op_irq); 1077 if (r) 1078 return r; 1079 1080 /* Privileged reg */ 1081 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1082 &adev->gfx.priv_reg_irq); 1083 if (r) 1084 return r; 1085 1086 /* Privileged inst */ 1087 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1088 &adev->gfx.priv_inst_irq); 1089 if (r) 1090 return r; 1091 1092 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1093 1094 r = adev->gfx.rlc.funcs->init(adev); 1095 if (r) { 1096 DRM_ERROR("Failed to init rlc BOs!\n"); 1097 return r; 1098 } 1099 1100 r = gfx_v9_4_3_mec_init(adev); 1101 if (r) { 1102 DRM_ERROR("Failed to init MEC BOs!\n"); 1103 return r; 1104 } 1105 1106 /* set up the compute queues - allocate horizontally across pipes */ 1107 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1108 ring_id = 0; 1109 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1110 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1111 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1112 k++) { 1113 if (!amdgpu_gfx_is_mec_queue_enabled( 1114 adev, xcc_id, i, k, j)) 1115 continue; 1116 1117 r = gfx_v9_4_3_compute_ring_init(adev, 1118 ring_id, 1119 xcc_id, 1120 i, k, j); 1121 if (r) 1122 return r; 1123 1124 ring_id++; 1125 } 1126 } 1127 } 1128 1129 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1130 if (r) { 1131 DRM_ERROR("Failed to init KIQ BOs!\n"); 1132 return r; 1133 } 1134 1135 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1136 if (r) 1137 return r; 1138 1139 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1140 r = amdgpu_gfx_mqd_sw_init(adev, 1141 sizeof(struct v9_mqd_allocation), xcc_id); 1142 if (r) 1143 return r; 1144 } 1145 1146 adev->gfx.compute_supported_reset = 1147 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1148 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1149 case IP_VERSION(9, 4, 3): 1150 case IP_VERSION(9, 4, 4): 1151 if (adev->gfx.mec_fw_version >= 155) { 1152 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1153 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1154 } 1155 break; 1156 default: 1157 break; 1158 } 1159 r = gfx_v9_4_3_gpu_early_init(adev); 1160 if (r) 1161 return r; 1162 1163 r = amdgpu_gfx_ras_sw_init(adev); 1164 if (r) 1165 return r; 1166 1167 r = amdgpu_gfx_sysfs_init(adev); 1168 if (r) 1169 return r; 1170 1171 gfx_v9_4_3_alloc_ip_dump(adev); 1172 1173 return 0; 1174 } 1175 1176 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1177 { 1178 int i, num_xcc; 1179 struct amdgpu_device *adev = ip_block->adev; 1180 1181 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1182 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1183 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1184 1185 for (i = 0; i < num_xcc; i++) { 1186 amdgpu_gfx_mqd_sw_fini(adev, i); 1187 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1188 amdgpu_gfx_kiq_fini(adev, i); 1189 } 1190 1191 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1192 1193 gfx_v9_4_3_mec_fini(adev); 1194 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1195 gfx_v9_4_3_free_microcode(adev); 1196 amdgpu_gfx_sysfs_fini(adev); 1197 1198 kfree(adev->gfx.ip_dump_core); 1199 kfree(adev->gfx.ip_dump_compute_queues); 1200 1201 return 0; 1202 } 1203 1204 #define DEFAULT_SH_MEM_BASES (0x6000) 1205 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1206 int xcc_id) 1207 { 1208 int i; 1209 uint32_t sh_mem_config; 1210 uint32_t sh_mem_bases; 1211 uint32_t data; 1212 1213 /* 1214 * Configure apertures: 1215 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1216 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1217 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1218 */ 1219 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1220 1221 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1222 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1223 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1224 1225 mutex_lock(&adev->srbm_mutex); 1226 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1227 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1228 /* CP and shaders */ 1229 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1230 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1231 1232 /* Enable trap for each kfd vmid. */ 1233 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1234 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1235 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1236 } 1237 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1238 mutex_unlock(&adev->srbm_mutex); 1239 1240 /* 1241 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1242 * access. These should be enabled by FW for target VMIDs. 1243 */ 1244 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1245 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1246 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1247 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1248 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1249 } 1250 } 1251 1252 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1253 { 1254 int vmid; 1255 1256 /* 1257 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1258 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1259 * the driver can enable them for graphics. VMID0 should maintain 1260 * access so that HWS firmware can save/restore entries. 1261 */ 1262 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1263 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1264 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1265 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1266 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1267 } 1268 } 1269 1270 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1271 int xcc_id) 1272 { 1273 u32 tmp; 1274 int i; 1275 1276 /* XXX SH_MEM regs */ 1277 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1278 mutex_lock(&adev->srbm_mutex); 1279 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1280 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1281 /* CP and shaders */ 1282 if (i == 0) { 1283 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1284 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1285 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1286 !!adev->gmc.noretry); 1287 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1288 regSH_MEM_CONFIG, tmp); 1289 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1290 regSH_MEM_BASES, 0); 1291 } else { 1292 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1293 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1294 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1295 !!adev->gmc.noretry); 1296 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1297 regSH_MEM_CONFIG, tmp); 1298 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1299 (adev->gmc.private_aperture_start >> 1300 48)); 1301 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1302 (adev->gmc.shared_aperture_start >> 1303 48)); 1304 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1305 regSH_MEM_BASES, tmp); 1306 } 1307 } 1308 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1309 1310 mutex_unlock(&adev->srbm_mutex); 1311 1312 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1313 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1314 } 1315 1316 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1317 { 1318 int i, num_xcc; 1319 1320 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1321 1322 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1323 adev->gfx.config.db_debug2 = 1324 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1325 1326 for (i = 0; i < num_xcc; i++) 1327 gfx_v9_4_3_xcc_constants_init(adev, i); 1328 } 1329 1330 static void 1331 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1332 int xcc_id) 1333 { 1334 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1335 } 1336 1337 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1338 { 1339 /* 1340 * Rlc save restore list is workable since v2_1. 1341 */ 1342 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1343 } 1344 1345 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1346 { 1347 uint32_t data; 1348 1349 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1350 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1351 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1352 } 1353 1354 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1355 { 1356 uint32_t rlc_setting; 1357 1358 /* if RLC is not enabled, do nothing */ 1359 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1360 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1361 return false; 1362 1363 return true; 1364 } 1365 1366 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1367 { 1368 uint32_t data; 1369 unsigned i; 1370 1371 data = RLC_SAFE_MODE__CMD_MASK; 1372 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1373 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1374 1375 /* wait for RLC_SAFE_MODE */ 1376 for (i = 0; i < adev->usec_timeout; i++) { 1377 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1378 break; 1379 udelay(1); 1380 } 1381 } 1382 1383 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1384 int xcc_id) 1385 { 1386 uint32_t data; 1387 1388 data = RLC_SAFE_MODE__CMD_MASK; 1389 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1390 } 1391 1392 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1393 { 1394 int xcc_id, num_xcc; 1395 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1396 1397 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1398 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1399 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1400 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1401 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1402 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1403 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1404 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1405 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1406 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1407 } 1408 adev->gfx.rlc.rlcg_reg_access_supported = true; 1409 } 1410 1411 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1412 { 1413 /* init spm vmid with 0xf */ 1414 if (adev->gfx.rlc.funcs->update_spm_vmid) 1415 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1416 1417 return 0; 1418 } 1419 1420 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1421 int xcc_id) 1422 { 1423 u32 i, j, k; 1424 u32 mask; 1425 1426 mutex_lock(&adev->grbm_idx_mutex); 1427 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1428 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1429 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1430 xcc_id); 1431 for (k = 0; k < adev->usec_timeout; k++) { 1432 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1433 break; 1434 udelay(1); 1435 } 1436 if (k == adev->usec_timeout) { 1437 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1438 0xffffffff, 1439 0xffffffff, xcc_id); 1440 mutex_unlock(&adev->grbm_idx_mutex); 1441 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1442 i, j); 1443 return; 1444 } 1445 } 1446 } 1447 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1448 xcc_id); 1449 mutex_unlock(&adev->grbm_idx_mutex); 1450 1451 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1452 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1453 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1454 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1455 for (k = 0; k < adev->usec_timeout; k++) { 1456 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1457 break; 1458 udelay(1); 1459 } 1460 } 1461 1462 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1463 bool enable, int xcc_id) 1464 { 1465 u32 tmp; 1466 1467 /* These interrupts should be enabled to drive DS clock */ 1468 1469 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1470 1471 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1472 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1473 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1474 1475 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1476 } 1477 1478 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1479 { 1480 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1481 RLC_ENABLE_F32, 0); 1482 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1483 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1484 } 1485 1486 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1487 { 1488 int i, num_xcc; 1489 1490 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1491 for (i = 0; i < num_xcc; i++) 1492 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1493 } 1494 1495 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1496 { 1497 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1498 SOFT_RESET_RLC, 1); 1499 udelay(50); 1500 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1501 SOFT_RESET_RLC, 0); 1502 udelay(50); 1503 } 1504 1505 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1506 { 1507 int i, num_xcc; 1508 1509 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1510 for (i = 0; i < num_xcc; i++) 1511 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1512 } 1513 1514 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1515 { 1516 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1517 RLC_ENABLE_F32, 1); 1518 udelay(50); 1519 1520 /* carrizo do enable cp interrupt after cp inited */ 1521 if (!(adev->flags & AMD_IS_APU)) { 1522 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1523 udelay(50); 1524 } 1525 } 1526 1527 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1528 { 1529 #ifdef AMDGPU_RLC_DEBUG_RETRY 1530 u32 rlc_ucode_ver; 1531 #endif 1532 int i, num_xcc; 1533 1534 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1535 for (i = 0; i < num_xcc; i++) { 1536 gfx_v9_4_3_xcc_rlc_start(adev, i); 1537 #ifdef AMDGPU_RLC_DEBUG_RETRY 1538 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1539 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1540 if (rlc_ucode_ver == 0x108) { 1541 dev_info(adev->dev, 1542 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1543 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1544 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1545 * default is 0x9C4 to create a 100us interval */ 1546 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1547 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1548 * to disable the page fault retry interrupts, default is 1549 * 0x100 (256) */ 1550 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1551 } 1552 #endif 1553 } 1554 } 1555 1556 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1557 int xcc_id) 1558 { 1559 const struct rlc_firmware_header_v2_0 *hdr; 1560 const __le32 *fw_data; 1561 unsigned i, fw_size; 1562 1563 if (!adev->gfx.rlc_fw) 1564 return -EINVAL; 1565 1566 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1567 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1568 1569 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1570 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1571 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1572 1573 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1574 RLCG_UCODE_LOADING_START_ADDRESS); 1575 for (i = 0; i < fw_size; i++) { 1576 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1577 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1578 msleep(1); 1579 } 1580 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1581 } 1582 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1583 1584 return 0; 1585 } 1586 1587 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1588 { 1589 int r; 1590 1591 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1592 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1593 /* legacy rlc firmware loading */ 1594 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1595 if (r) 1596 return r; 1597 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1598 } 1599 1600 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1601 /* disable CG */ 1602 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1603 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1604 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1605 1606 return 0; 1607 } 1608 1609 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1610 { 1611 int r, i, num_xcc; 1612 1613 if (amdgpu_sriov_vf(adev)) 1614 return 0; 1615 1616 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1617 for (i = 0; i < num_xcc; i++) { 1618 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1619 if (r) 1620 return r; 1621 } 1622 1623 return 0; 1624 } 1625 1626 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1627 unsigned vmid) 1628 { 1629 u32 reg, pre_data, data; 1630 1631 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1632 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1633 pre_data = RREG32_NO_KIQ(reg); 1634 else 1635 pre_data = RREG32(reg); 1636 1637 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1638 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1639 1640 if (pre_data != data) { 1641 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1642 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1643 } else 1644 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1645 } 1646 } 1647 1648 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1649 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1650 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1651 }; 1652 1653 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1654 uint32_t offset, 1655 struct soc15_reg_rlcg *entries, int arr_size) 1656 { 1657 int i, inst; 1658 uint32_t reg; 1659 1660 if (!entries) 1661 return false; 1662 1663 for (i = 0; i < arr_size; i++) { 1664 const struct soc15_reg_rlcg *entry; 1665 1666 entry = &entries[i]; 1667 inst = adev->ip_map.logical_to_dev_inst ? 1668 adev->ip_map.logical_to_dev_inst( 1669 adev, entry->hwip, entry->instance) : 1670 entry->instance; 1671 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1672 entry->reg; 1673 if (offset == reg) 1674 return true; 1675 } 1676 1677 return false; 1678 } 1679 1680 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1681 { 1682 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1683 (void *)rlcg_access_gc_9_4_3, 1684 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1685 } 1686 1687 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1688 bool enable, int xcc_id) 1689 { 1690 if (enable) { 1691 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1692 } else { 1693 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1694 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1695 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1696 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1697 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1698 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1699 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1700 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1701 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1702 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1703 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1704 } 1705 udelay(50); 1706 } 1707 1708 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1709 int xcc_id) 1710 { 1711 const struct gfx_firmware_header_v1_0 *mec_hdr; 1712 const __le32 *fw_data; 1713 unsigned i; 1714 u32 tmp; 1715 u32 mec_ucode_addr_offset; 1716 u32 mec_ucode_data_offset; 1717 1718 if (!adev->gfx.mec_fw) 1719 return -EINVAL; 1720 1721 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1722 1723 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1724 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1725 1726 fw_data = (const __le32 *) 1727 (adev->gfx.mec_fw->data + 1728 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1729 tmp = 0; 1730 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1731 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1732 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1733 1734 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1735 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1736 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1737 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1738 1739 mec_ucode_addr_offset = 1740 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1741 mec_ucode_data_offset = 1742 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1743 1744 /* MEC1 */ 1745 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1746 for (i = 0; i < mec_hdr->jt_size; i++) 1747 WREG32(mec_ucode_data_offset, 1748 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1749 1750 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1751 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1752 1753 return 0; 1754 } 1755 1756 /* KIQ functions */ 1757 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1758 { 1759 uint32_t tmp; 1760 struct amdgpu_device *adev = ring->adev; 1761 1762 /* tell RLC which is KIQ queue */ 1763 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1764 tmp &= 0xffffff00; 1765 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1766 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1767 } 1768 1769 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1770 { 1771 struct amdgpu_device *adev = ring->adev; 1772 1773 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1774 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1775 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1776 mqd->cp_hqd_queue_priority = 1777 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1778 } 1779 } 1780 } 1781 1782 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1783 { 1784 struct amdgpu_device *adev = ring->adev; 1785 struct v9_mqd *mqd = ring->mqd_ptr; 1786 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1787 uint32_t tmp; 1788 1789 mqd->header = 0xC0310800; 1790 mqd->compute_pipelinestat_enable = 0x00000001; 1791 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1792 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1793 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1794 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1795 mqd->compute_misc_reserved = 0x00000003; 1796 1797 mqd->dynamic_cu_mask_addr_lo = 1798 lower_32_bits(ring->mqd_gpu_addr 1799 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1800 mqd->dynamic_cu_mask_addr_hi = 1801 upper_32_bits(ring->mqd_gpu_addr 1802 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1803 1804 eop_base_addr = ring->eop_gpu_addr >> 8; 1805 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1806 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1807 1808 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1809 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1810 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1811 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1812 1813 mqd->cp_hqd_eop_control = tmp; 1814 1815 /* enable doorbell? */ 1816 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1817 1818 if (ring->use_doorbell) { 1819 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1820 DOORBELL_OFFSET, ring->doorbell_index); 1821 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1822 DOORBELL_EN, 1); 1823 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1824 DOORBELL_SOURCE, 0); 1825 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1826 DOORBELL_HIT, 0); 1827 if (amdgpu_sriov_multi_vf_mode(adev)) 1828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1829 DOORBELL_MODE, 1); 1830 } else { 1831 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1832 DOORBELL_EN, 0); 1833 } 1834 1835 mqd->cp_hqd_pq_doorbell_control = tmp; 1836 1837 /* disable the queue if it's active */ 1838 ring->wptr = 0; 1839 mqd->cp_hqd_dequeue_request = 0; 1840 mqd->cp_hqd_pq_rptr = 0; 1841 mqd->cp_hqd_pq_wptr_lo = 0; 1842 mqd->cp_hqd_pq_wptr_hi = 0; 1843 1844 /* set the pointer to the MQD */ 1845 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1846 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1847 1848 /* set MQD vmid to 0 */ 1849 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1850 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1851 mqd->cp_mqd_control = tmp; 1852 1853 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1854 hqd_gpu_addr = ring->gpu_addr >> 8; 1855 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1856 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1857 1858 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1859 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1860 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1861 (order_base_2(ring->ring_size / 4) - 1)); 1862 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1863 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1864 #ifdef __BIG_ENDIAN 1865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1866 #endif 1867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1868 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1869 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1870 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1871 mqd->cp_hqd_pq_control = tmp; 1872 1873 /* set the wb address whether it's enabled or not */ 1874 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1875 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1876 mqd->cp_hqd_pq_rptr_report_addr_hi = 1877 upper_32_bits(wb_gpu_addr) & 0xffff; 1878 1879 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1880 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1881 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1882 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1883 1884 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1885 ring->wptr = 0; 1886 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1887 1888 /* set the vmid for the queue */ 1889 mqd->cp_hqd_vmid = 0; 1890 1891 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1892 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1893 mqd->cp_hqd_persistent_state = tmp; 1894 1895 /* set MIN_IB_AVAIL_SIZE */ 1896 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1897 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1898 mqd->cp_hqd_ib_control = tmp; 1899 1900 /* set static priority for a queue/ring */ 1901 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1902 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1903 1904 /* map_queues packet doesn't need activate the queue, 1905 * so only kiq need set this field. 1906 */ 1907 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1908 mqd->cp_hqd_active = 1; 1909 1910 return 0; 1911 } 1912 1913 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1914 int xcc_id) 1915 { 1916 struct amdgpu_device *adev = ring->adev; 1917 struct v9_mqd *mqd = ring->mqd_ptr; 1918 int j; 1919 1920 /* disable wptr polling */ 1921 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1922 1923 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1924 mqd->cp_hqd_eop_base_addr_lo); 1925 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1926 mqd->cp_hqd_eop_base_addr_hi); 1927 1928 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1929 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1930 mqd->cp_hqd_eop_control); 1931 1932 /* enable doorbell? */ 1933 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1934 mqd->cp_hqd_pq_doorbell_control); 1935 1936 /* disable the queue if it's active */ 1937 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1938 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1939 for (j = 0; j < adev->usec_timeout; j++) { 1940 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1941 break; 1942 udelay(1); 1943 } 1944 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1945 mqd->cp_hqd_dequeue_request); 1946 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1947 mqd->cp_hqd_pq_rptr); 1948 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1949 mqd->cp_hqd_pq_wptr_lo); 1950 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1951 mqd->cp_hqd_pq_wptr_hi); 1952 } 1953 1954 /* set the pointer to the MQD */ 1955 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1956 mqd->cp_mqd_base_addr_lo); 1957 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1958 mqd->cp_mqd_base_addr_hi); 1959 1960 /* set MQD vmid to 0 */ 1961 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1962 mqd->cp_mqd_control); 1963 1964 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1965 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1966 mqd->cp_hqd_pq_base_lo); 1967 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1968 mqd->cp_hqd_pq_base_hi); 1969 1970 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1971 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1972 mqd->cp_hqd_pq_control); 1973 1974 /* set the wb address whether it's enabled or not */ 1975 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1976 mqd->cp_hqd_pq_rptr_report_addr_lo); 1977 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1978 mqd->cp_hqd_pq_rptr_report_addr_hi); 1979 1980 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1981 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1982 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1983 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1984 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1985 1986 /* enable the doorbell if requested */ 1987 if (ring->use_doorbell) { 1988 WREG32_SOC15( 1989 GC, GET_INST(GC, xcc_id), 1990 regCP_MEC_DOORBELL_RANGE_LOWER, 1991 ((adev->doorbell_index.kiq + 1992 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1993 2) << 2); 1994 WREG32_SOC15( 1995 GC, GET_INST(GC, xcc_id), 1996 regCP_MEC_DOORBELL_RANGE_UPPER, 1997 ((adev->doorbell_index.userqueue_end + 1998 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1999 2) << 2); 2000 } 2001 2002 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2003 mqd->cp_hqd_pq_doorbell_control); 2004 2005 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2006 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2007 mqd->cp_hqd_pq_wptr_lo); 2008 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2009 mqd->cp_hqd_pq_wptr_hi); 2010 2011 /* set the vmid for the queue */ 2012 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2013 2014 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2015 mqd->cp_hqd_persistent_state); 2016 2017 /* activate the queue */ 2018 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2019 mqd->cp_hqd_active); 2020 2021 if (ring->use_doorbell) 2022 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2023 2024 return 0; 2025 } 2026 2027 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2028 int xcc_id) 2029 { 2030 struct amdgpu_device *adev = ring->adev; 2031 int j; 2032 2033 /* disable the queue if it's active */ 2034 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2035 2036 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2037 2038 for (j = 0; j < adev->usec_timeout; j++) { 2039 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2040 break; 2041 udelay(1); 2042 } 2043 2044 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2045 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2046 2047 /* Manual disable if dequeue request times out */ 2048 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2049 } 2050 2051 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2052 0); 2053 } 2054 2055 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2056 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2057 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2058 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2059 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2060 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2061 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2062 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2063 2064 return 0; 2065 } 2066 2067 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2068 { 2069 struct amdgpu_device *adev = ring->adev; 2070 struct v9_mqd *mqd = ring->mqd_ptr; 2071 struct v9_mqd *tmp_mqd; 2072 2073 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2074 2075 /* GPU could be in bad state during probe, driver trigger the reset 2076 * after load the SMU, in this case , the mqd is not be initialized. 2077 * driver need to re-init the mqd. 2078 * check mqd->cp_hqd_pq_control since this value should not be 0 2079 */ 2080 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2081 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2082 /* for GPU_RESET case , reset MQD to a clean status */ 2083 if (adev->gfx.kiq[xcc_id].mqd_backup) 2084 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2085 2086 /* reset ring buffer */ 2087 ring->wptr = 0; 2088 amdgpu_ring_clear_ring(ring); 2089 mutex_lock(&adev->srbm_mutex); 2090 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2091 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2092 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2093 mutex_unlock(&adev->srbm_mutex); 2094 } else { 2095 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2096 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2097 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2098 mutex_lock(&adev->srbm_mutex); 2099 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2100 amdgpu_ring_clear_ring(ring); 2101 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2102 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2103 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2104 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2105 mutex_unlock(&adev->srbm_mutex); 2106 2107 if (adev->gfx.kiq[xcc_id].mqd_backup) 2108 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2109 } 2110 2111 return 0; 2112 } 2113 2114 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) 2115 { 2116 struct amdgpu_device *adev = ring->adev; 2117 struct v9_mqd *mqd = ring->mqd_ptr; 2118 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2119 struct v9_mqd *tmp_mqd; 2120 2121 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2122 * is not be initialized before 2123 */ 2124 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2125 2126 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2127 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2128 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2129 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2130 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2131 mutex_lock(&adev->srbm_mutex); 2132 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2133 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2134 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2135 mutex_unlock(&adev->srbm_mutex); 2136 2137 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2138 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2139 } else { 2140 /* restore MQD to a clean status */ 2141 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2142 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2143 /* reset ring buffer */ 2144 ring->wptr = 0; 2145 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2146 amdgpu_ring_clear_ring(ring); 2147 } 2148 2149 return 0; 2150 } 2151 2152 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2153 { 2154 struct amdgpu_ring *ring; 2155 int j; 2156 2157 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2158 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2159 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2160 mutex_lock(&adev->srbm_mutex); 2161 soc15_grbm_select(adev, ring->me, 2162 ring->pipe, 2163 ring->queue, 0, GET_INST(GC, xcc_id)); 2164 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2165 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2166 mutex_unlock(&adev->srbm_mutex); 2167 } 2168 } 2169 2170 return 0; 2171 } 2172 2173 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2174 { 2175 gfx_v9_4_3_xcc_kiq_init_queue(&adev->gfx.kiq[xcc_id].ring, xcc_id); 2176 return 0; 2177 } 2178 2179 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2180 { 2181 struct amdgpu_ring *ring; 2182 int i, r; 2183 2184 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2185 2186 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2187 ring = &adev->gfx.compute_ring[i + xcc_id * 2188 adev->gfx.num_compute_rings]; 2189 2190 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2191 if (r) 2192 return r; 2193 } 2194 2195 return amdgpu_gfx_enable_kcq(adev, xcc_id); 2196 } 2197 2198 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2199 { 2200 struct amdgpu_ring *ring; 2201 int r, j; 2202 2203 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2204 2205 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2206 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2207 2208 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2209 if (r) 2210 return r; 2211 } else { 2212 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2213 } 2214 2215 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2216 if (r) 2217 return r; 2218 2219 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2220 if (r) 2221 return r; 2222 2223 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2224 ring = &adev->gfx.compute_ring 2225 [j + xcc_id * adev->gfx.num_compute_rings]; 2226 r = amdgpu_ring_test_helper(ring); 2227 if (r) 2228 return r; 2229 } 2230 2231 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2232 2233 return 0; 2234 } 2235 2236 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2237 { 2238 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2239 2240 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2241 if (amdgpu_sriov_vf(adev)) { 2242 enum amdgpu_gfx_partition mode; 2243 2244 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2245 AMDGPU_XCP_FL_NONE); 2246 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2247 return -EINVAL; 2248 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2249 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2250 num_xcp = num_xcc / num_xcc_per_xcp; 2251 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2252 2253 } else { 2254 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2255 AMDGPU_XCP_FL_NONE) == 2256 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2257 r = amdgpu_xcp_switch_partition_mode( 2258 adev->xcp_mgr, amdgpu_user_partt_mode); 2259 } 2260 if (r) 2261 return r; 2262 2263 for (i = 0; i < num_xcc; i++) { 2264 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2265 if (r) 2266 return r; 2267 } 2268 2269 return 0; 2270 } 2271 2272 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2273 { 2274 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2275 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2276 2277 if (amdgpu_sriov_vf(adev)) { 2278 /* must disable polling for SRIOV when hw finished, otherwise 2279 * CPC engine may still keep fetching WB address which is already 2280 * invalid after sw finished and trigger DMAR reading error in 2281 * hypervisor side. 2282 */ 2283 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2284 return; 2285 } 2286 2287 /* Use deinitialize sequence from CAIL when unbinding device 2288 * from driver, otherwise KIQ is hanging when binding back 2289 */ 2290 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2291 mutex_lock(&adev->srbm_mutex); 2292 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2293 adev->gfx.kiq[xcc_id].ring.pipe, 2294 adev->gfx.kiq[xcc_id].ring.queue, 0, 2295 GET_INST(GC, xcc_id)); 2296 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2297 xcc_id); 2298 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2299 mutex_unlock(&adev->srbm_mutex); 2300 } 2301 2302 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2303 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2304 } 2305 2306 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2307 { 2308 int r; 2309 struct amdgpu_device *adev = ip_block->adev; 2310 2311 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2312 adev->gfx.cleaner_shader_ptr); 2313 2314 if (!amdgpu_sriov_vf(adev)) 2315 gfx_v9_4_3_init_golden_registers(adev); 2316 2317 gfx_v9_4_3_constants_init(adev); 2318 2319 r = adev->gfx.rlc.funcs->resume(adev); 2320 if (r) 2321 return r; 2322 2323 r = gfx_v9_4_3_cp_resume(adev); 2324 if (r) 2325 return r; 2326 2327 return r; 2328 } 2329 2330 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2331 { 2332 struct amdgpu_device *adev = ip_block->adev; 2333 int i, num_xcc; 2334 2335 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2336 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2337 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2338 2339 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2340 for (i = 0; i < num_xcc; i++) { 2341 gfx_v9_4_3_xcc_fini(adev, i); 2342 } 2343 2344 return 0; 2345 } 2346 2347 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2348 { 2349 return gfx_v9_4_3_hw_fini(ip_block); 2350 } 2351 2352 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2353 { 2354 return gfx_v9_4_3_hw_init(ip_block); 2355 } 2356 2357 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2358 { 2359 struct amdgpu_device *adev = ip_block->adev; 2360 int i, num_xcc; 2361 2362 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2363 for (i = 0; i < num_xcc; i++) { 2364 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2365 GRBM_STATUS, GUI_ACTIVE)) 2366 return false; 2367 } 2368 return true; 2369 } 2370 2371 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2372 { 2373 unsigned i; 2374 struct amdgpu_device *adev = ip_block->adev; 2375 2376 for (i = 0; i < adev->usec_timeout; i++) { 2377 if (gfx_v9_4_3_is_idle(ip_block)) 2378 return 0; 2379 udelay(1); 2380 } 2381 return -ETIMEDOUT; 2382 } 2383 2384 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2385 { 2386 u32 grbm_soft_reset = 0; 2387 u32 tmp; 2388 struct amdgpu_device *adev = ip_block->adev; 2389 2390 /* GRBM_STATUS */ 2391 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2392 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2393 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2394 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2395 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2396 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2397 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2398 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2399 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2400 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2401 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2402 } 2403 2404 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2405 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2406 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2407 } 2408 2409 /* GRBM_STATUS2 */ 2410 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2411 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2412 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2413 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2414 2415 2416 if (grbm_soft_reset) { 2417 /* stop the rlc */ 2418 adev->gfx.rlc.funcs->stop(adev); 2419 2420 /* Disable MEC parsing/prefetching */ 2421 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2422 2423 if (grbm_soft_reset) { 2424 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2425 tmp |= grbm_soft_reset; 2426 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2427 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2428 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2429 2430 udelay(50); 2431 2432 tmp &= ~grbm_soft_reset; 2433 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2434 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2435 } 2436 2437 /* Wait a little for things to settle down */ 2438 udelay(50); 2439 } 2440 return 0; 2441 } 2442 2443 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2444 uint32_t vmid, 2445 uint32_t gds_base, uint32_t gds_size, 2446 uint32_t gws_base, uint32_t gws_size, 2447 uint32_t oa_base, uint32_t oa_size) 2448 { 2449 struct amdgpu_device *adev = ring->adev; 2450 2451 /* GDS Base */ 2452 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2453 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2454 gds_base); 2455 2456 /* GDS Size */ 2457 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2458 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2459 gds_size); 2460 2461 /* GWS */ 2462 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2463 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2464 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2465 2466 /* OA */ 2467 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2468 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2469 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2470 } 2471 2472 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2473 { 2474 struct amdgpu_device *adev = ip_block->adev; 2475 2476 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2477 AMDGPU_MAX_COMPUTE_RINGS); 2478 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2479 gfx_v9_4_3_set_ring_funcs(adev); 2480 gfx_v9_4_3_set_irq_funcs(adev); 2481 gfx_v9_4_3_set_gds_init(adev); 2482 gfx_v9_4_3_set_rlc_funcs(adev); 2483 2484 /* init rlcg reg access ctrl */ 2485 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2486 2487 return gfx_v9_4_3_init_microcode(adev); 2488 } 2489 2490 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2491 { 2492 struct amdgpu_device *adev = ip_block->adev; 2493 int r; 2494 2495 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2496 if (r) 2497 return r; 2498 2499 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2500 if (r) 2501 return r; 2502 2503 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2504 if (r) 2505 return r; 2506 2507 if (adev->gfx.ras && 2508 adev->gfx.ras->enable_watchdog_timer) 2509 adev->gfx.ras->enable_watchdog_timer(adev); 2510 2511 return 0; 2512 } 2513 2514 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2515 bool enable, int xcc_id) 2516 { 2517 uint32_t def, data; 2518 2519 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2520 return; 2521 2522 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2523 regRLC_CGTT_MGCG_OVERRIDE); 2524 2525 if (enable) 2526 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2527 else 2528 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2529 2530 if (def != data) 2531 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2532 regRLC_CGTT_MGCG_OVERRIDE, data); 2533 2534 } 2535 2536 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2537 bool enable, int xcc_id) 2538 { 2539 uint32_t def, data; 2540 2541 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2542 return; 2543 2544 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2545 regRLC_CGTT_MGCG_OVERRIDE); 2546 2547 if (enable) 2548 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2549 else 2550 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2551 2552 if (def != data) 2553 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2554 regRLC_CGTT_MGCG_OVERRIDE, data); 2555 } 2556 2557 static void 2558 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2559 bool enable, int xcc_id) 2560 { 2561 uint32_t data, def; 2562 2563 /* It is disabled by HW by default */ 2564 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2565 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2566 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2567 2568 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2569 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2570 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2571 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2572 2573 if (def != data) 2574 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2575 2576 /* MGLS is a global flag to control all MGLS in GFX */ 2577 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2578 /* 2 - RLC memory Light sleep */ 2579 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2580 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2581 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2582 if (def != data) 2583 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2584 } 2585 /* 3 - CP memory Light sleep */ 2586 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2587 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2588 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2589 if (def != data) 2590 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2591 } 2592 } 2593 } else { 2594 /* 1 - MGCG_OVERRIDE */ 2595 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2596 2597 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2598 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2599 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2600 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2601 2602 if (def != data) 2603 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2604 2605 /* 2 - disable MGLS in RLC */ 2606 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2607 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2608 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2609 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2610 } 2611 2612 /* 3 - disable MGLS in CP */ 2613 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2614 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2615 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2616 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2617 } 2618 } 2619 2620 } 2621 2622 static void 2623 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2624 bool enable, int xcc_id) 2625 { 2626 uint32_t def, data; 2627 2628 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2629 2630 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2631 /* unset CGCG override */ 2632 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2633 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2634 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2635 else 2636 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2637 /* update CGCG and CGLS override bits */ 2638 if (def != data) 2639 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2640 2641 /* CGCG Hysteresis: 400us */ 2642 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2643 2644 data = (0x2710 2645 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2646 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2647 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2648 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2649 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2650 if (def != data) 2651 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2652 2653 /* set IDLE_POLL_COUNT(0x33450100)*/ 2654 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2655 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2656 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2657 if (def != data) 2658 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2659 } else { 2660 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2661 /* reset CGCG/CGLS bits */ 2662 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2663 /* disable cgcg and cgls in FSM */ 2664 if (def != data) 2665 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2666 } 2667 2668 } 2669 2670 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2671 bool enable, int xcc_id) 2672 { 2673 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2674 2675 if (enable) { 2676 /* FGCG */ 2677 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2678 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2679 2680 /* CGCG/CGLS should be enabled after MGCG/MGLS 2681 * === MGCG + MGLS === 2682 */ 2683 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2684 xcc_id); 2685 /* === CGCG + CGLS === */ 2686 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2687 xcc_id); 2688 } else { 2689 /* CGCG/CGLS should be disabled before MGCG/MGLS 2690 * === CGCG + CGLS === 2691 */ 2692 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2693 xcc_id); 2694 /* === MGCG + MGLS === */ 2695 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2696 xcc_id); 2697 2698 /* FGCG */ 2699 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2700 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2701 } 2702 2703 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2704 2705 return 0; 2706 } 2707 2708 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2709 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2710 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2711 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2712 .init = gfx_v9_4_3_rlc_init, 2713 .resume = gfx_v9_4_3_rlc_resume, 2714 .stop = gfx_v9_4_3_rlc_stop, 2715 .reset = gfx_v9_4_3_rlc_reset, 2716 .start = gfx_v9_4_3_rlc_start, 2717 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2718 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2719 }; 2720 2721 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2722 enum amd_powergating_state state) 2723 { 2724 return 0; 2725 } 2726 2727 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2728 enum amd_clockgating_state state) 2729 { 2730 struct amdgpu_device *adev = ip_block->adev; 2731 int i, num_xcc; 2732 2733 if (amdgpu_sriov_vf(adev)) 2734 return 0; 2735 2736 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2737 for (i = 0; i < num_xcc; i++) 2738 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2739 adev, state == AMD_CG_STATE_GATE, i); 2740 2741 return 0; 2742 } 2743 2744 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2745 { 2746 struct amdgpu_device *adev = ip_block->adev; 2747 int data; 2748 2749 if (amdgpu_sriov_vf(adev)) 2750 *flags = 0; 2751 2752 /* AMD_CG_SUPPORT_GFX_MGCG */ 2753 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2754 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2755 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2756 2757 /* AMD_CG_SUPPORT_GFX_CGCG */ 2758 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2759 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2760 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2761 2762 /* AMD_CG_SUPPORT_GFX_CGLS */ 2763 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2764 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2765 2766 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2767 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2768 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2769 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2770 2771 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2772 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2773 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2774 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2775 } 2776 2777 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2778 { 2779 struct amdgpu_device *adev = ring->adev; 2780 u32 ref_and_mask, reg_mem_engine; 2781 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2782 2783 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2784 switch (ring->me) { 2785 case 1: 2786 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2787 break; 2788 case 2: 2789 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2790 break; 2791 default: 2792 return; 2793 } 2794 reg_mem_engine = 0; 2795 } else { 2796 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2797 reg_mem_engine = 1; /* pfp */ 2798 } 2799 2800 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2801 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2802 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2803 ref_and_mask, ref_and_mask, 0x20); 2804 } 2805 2806 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2807 struct amdgpu_job *job, 2808 struct amdgpu_ib *ib, 2809 uint32_t flags) 2810 { 2811 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2812 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2813 2814 /* Currently, there is a high possibility to get wave ID mismatch 2815 * between ME and GDS, leading to a hw deadlock, because ME generates 2816 * different wave IDs than the GDS expects. This situation happens 2817 * randomly when at least 5 compute pipes use GDS ordered append. 2818 * The wave IDs generated by ME are also wrong after suspend/resume. 2819 * Those are probably bugs somewhere else in the kernel driver. 2820 * 2821 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2822 * GDS to 0 for this ring (me/pipe). 2823 */ 2824 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2825 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2826 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2827 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2828 } 2829 2830 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2831 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2832 amdgpu_ring_write(ring, 2833 #ifdef __BIG_ENDIAN 2834 (2 << 0) | 2835 #endif 2836 lower_32_bits(ib->gpu_addr)); 2837 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2838 amdgpu_ring_write(ring, control); 2839 } 2840 2841 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2842 u64 seq, unsigned flags) 2843 { 2844 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2845 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2846 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2847 2848 /* RELEASE_MEM - flush caches, send int */ 2849 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2850 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2851 EOP_TC_NC_ACTION_EN) : 2852 (EOP_TCL1_ACTION_EN | 2853 EOP_TC_ACTION_EN | 2854 EOP_TC_WB_ACTION_EN | 2855 EOP_TC_MD_ACTION_EN)) | 2856 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2857 EVENT_INDEX(5))); 2858 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2859 2860 /* 2861 * the address should be Qword aligned if 64bit write, Dword 2862 * aligned if only send 32bit data low (discard data high) 2863 */ 2864 if (write64bit) 2865 BUG_ON(addr & 0x7); 2866 else 2867 BUG_ON(addr & 0x3); 2868 amdgpu_ring_write(ring, lower_32_bits(addr)); 2869 amdgpu_ring_write(ring, upper_32_bits(addr)); 2870 amdgpu_ring_write(ring, lower_32_bits(seq)); 2871 amdgpu_ring_write(ring, upper_32_bits(seq)); 2872 amdgpu_ring_write(ring, 0); 2873 } 2874 2875 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2876 { 2877 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2878 uint32_t seq = ring->fence_drv.sync_seq; 2879 uint64_t addr = ring->fence_drv.gpu_addr; 2880 2881 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2882 lower_32_bits(addr), upper_32_bits(addr), 2883 seq, 0xffffffff, 4); 2884 } 2885 2886 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2887 unsigned vmid, uint64_t pd_addr) 2888 { 2889 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2890 } 2891 2892 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2893 { 2894 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2895 } 2896 2897 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2898 { 2899 u64 wptr; 2900 2901 /* XXX check if swapping is necessary on BE */ 2902 if (ring->use_doorbell) 2903 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2904 else 2905 BUG(); 2906 return wptr; 2907 } 2908 2909 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2910 { 2911 struct amdgpu_device *adev = ring->adev; 2912 2913 /* XXX check if swapping is necessary on BE */ 2914 if (ring->use_doorbell) { 2915 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2916 WDOORBELL64(ring->doorbell_index, ring->wptr); 2917 } else { 2918 BUG(); /* only DOORBELL method supported on gfx9 now */ 2919 } 2920 } 2921 2922 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2923 u64 seq, unsigned int flags) 2924 { 2925 struct amdgpu_device *adev = ring->adev; 2926 2927 /* we only allocate 32bit for each seq wb address */ 2928 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2929 2930 /* write fence seq to the "addr" */ 2931 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2932 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2933 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2934 amdgpu_ring_write(ring, lower_32_bits(addr)); 2935 amdgpu_ring_write(ring, upper_32_bits(addr)); 2936 amdgpu_ring_write(ring, lower_32_bits(seq)); 2937 2938 if (flags & AMDGPU_FENCE_FLAG_INT) { 2939 /* set register to trigger INT */ 2940 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2941 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2942 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2943 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2944 amdgpu_ring_write(ring, 0); 2945 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2946 } 2947 } 2948 2949 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2950 uint32_t reg_val_offs) 2951 { 2952 struct amdgpu_device *adev = ring->adev; 2953 2954 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2955 2956 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2957 amdgpu_ring_write(ring, 0 | /* src: register*/ 2958 (5 << 8) | /* dst: memory */ 2959 (1 << 20)); /* write confirm */ 2960 amdgpu_ring_write(ring, reg); 2961 amdgpu_ring_write(ring, 0); 2962 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2963 reg_val_offs * 4)); 2964 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2965 reg_val_offs * 4)); 2966 } 2967 2968 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2969 uint32_t val) 2970 { 2971 uint32_t cmd = 0; 2972 2973 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2974 2975 switch (ring->funcs->type) { 2976 case AMDGPU_RING_TYPE_GFX: 2977 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2978 break; 2979 case AMDGPU_RING_TYPE_KIQ: 2980 cmd = (1 << 16); /* no inc addr */ 2981 break; 2982 default: 2983 cmd = WR_CONFIRM; 2984 break; 2985 } 2986 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2987 amdgpu_ring_write(ring, cmd); 2988 amdgpu_ring_write(ring, reg); 2989 amdgpu_ring_write(ring, 0); 2990 amdgpu_ring_write(ring, val); 2991 } 2992 2993 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2994 uint32_t val, uint32_t mask) 2995 { 2996 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2997 } 2998 2999 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3000 uint32_t reg0, uint32_t reg1, 3001 uint32_t ref, uint32_t mask) 3002 { 3003 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3004 ref, mask); 3005 } 3006 3007 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3008 unsigned vmid) 3009 { 3010 struct amdgpu_device *adev = ring->adev; 3011 uint32_t value = 0; 3012 3013 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3014 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3015 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3016 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3017 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3018 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3019 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3020 } 3021 3022 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3023 struct amdgpu_device *adev, int me, int pipe, 3024 enum amdgpu_interrupt_state state, int xcc_id) 3025 { 3026 u32 mec_int_cntl, mec_int_cntl_reg; 3027 3028 /* 3029 * amdgpu controls only the first MEC. That's why this function only 3030 * handles the setting of interrupts for this specific MEC. All other 3031 * pipes' interrupts are set by amdkfd. 3032 */ 3033 3034 if (me == 1) { 3035 switch (pipe) { 3036 case 0: 3037 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3038 break; 3039 case 1: 3040 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3041 break; 3042 case 2: 3043 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3044 break; 3045 case 3: 3046 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3047 break; 3048 default: 3049 DRM_DEBUG("invalid pipe %d\n", pipe); 3050 return; 3051 } 3052 } else { 3053 DRM_DEBUG("invalid me %d\n", me); 3054 return; 3055 } 3056 3057 switch (state) { 3058 case AMDGPU_IRQ_STATE_DISABLE: 3059 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3060 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3061 TIME_STAMP_INT_ENABLE, 0); 3062 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3063 break; 3064 case AMDGPU_IRQ_STATE_ENABLE: 3065 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3066 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3067 TIME_STAMP_INT_ENABLE, 1); 3068 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3069 break; 3070 default: 3071 break; 3072 } 3073 } 3074 3075 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3076 int xcc_id, int me, int pipe) 3077 { 3078 /* 3079 * amdgpu controls only the first MEC. That's why this function only 3080 * handles the setting of interrupts for this specific MEC. All other 3081 * pipes' interrupts are set by amdkfd. 3082 */ 3083 if (me != 1) 3084 return 0; 3085 3086 switch (pipe) { 3087 case 0: 3088 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3089 case 1: 3090 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3091 case 2: 3092 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3093 case 3: 3094 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3095 default: 3096 return 0; 3097 } 3098 } 3099 3100 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3101 struct amdgpu_irq_src *source, 3102 unsigned type, 3103 enum amdgpu_interrupt_state state) 3104 { 3105 u32 mec_int_cntl_reg, mec_int_cntl; 3106 int i, j, k, num_xcc; 3107 3108 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3109 switch (state) { 3110 case AMDGPU_IRQ_STATE_DISABLE: 3111 case AMDGPU_IRQ_STATE_ENABLE: 3112 for (i = 0; i < num_xcc; i++) { 3113 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3114 PRIV_REG_INT_ENABLE, 3115 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3116 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3117 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3118 /* MECs start at 1 */ 3119 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3120 3121 if (mec_int_cntl_reg) { 3122 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3123 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3124 PRIV_REG_INT_ENABLE, 3125 state == AMDGPU_IRQ_STATE_ENABLE ? 3126 1 : 0); 3127 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3128 } 3129 } 3130 } 3131 } 3132 break; 3133 default: 3134 break; 3135 } 3136 3137 return 0; 3138 } 3139 3140 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3141 struct amdgpu_irq_src *source, 3142 unsigned type, 3143 enum amdgpu_interrupt_state state) 3144 { 3145 u32 mec_int_cntl_reg, mec_int_cntl; 3146 int i, j, k, num_xcc; 3147 3148 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3149 switch (state) { 3150 case AMDGPU_IRQ_STATE_DISABLE: 3151 case AMDGPU_IRQ_STATE_ENABLE: 3152 for (i = 0; i < num_xcc; i++) { 3153 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3154 OPCODE_ERROR_INT_ENABLE, 3155 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3156 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3157 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3158 /* MECs start at 1 */ 3159 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3160 3161 if (mec_int_cntl_reg) { 3162 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3163 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3164 OPCODE_ERROR_INT_ENABLE, 3165 state == AMDGPU_IRQ_STATE_ENABLE ? 3166 1 : 0); 3167 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3168 } 3169 } 3170 } 3171 } 3172 break; 3173 default: 3174 break; 3175 } 3176 3177 return 0; 3178 } 3179 3180 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3181 struct amdgpu_irq_src *source, 3182 unsigned type, 3183 enum amdgpu_interrupt_state state) 3184 { 3185 int i, num_xcc; 3186 3187 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3188 switch (state) { 3189 case AMDGPU_IRQ_STATE_DISABLE: 3190 case AMDGPU_IRQ_STATE_ENABLE: 3191 for (i = 0; i < num_xcc; i++) 3192 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3193 PRIV_INSTR_INT_ENABLE, 3194 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3195 break; 3196 default: 3197 break; 3198 } 3199 3200 return 0; 3201 } 3202 3203 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3204 struct amdgpu_irq_src *src, 3205 unsigned type, 3206 enum amdgpu_interrupt_state state) 3207 { 3208 int i, num_xcc; 3209 3210 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3211 for (i = 0; i < num_xcc; i++) { 3212 switch (type) { 3213 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3214 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3215 adev, 1, 0, state, i); 3216 break; 3217 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3218 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3219 adev, 1, 1, state, i); 3220 break; 3221 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3222 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3223 adev, 1, 2, state, i); 3224 break; 3225 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3226 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3227 adev, 1, 3, state, i); 3228 break; 3229 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3230 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3231 adev, 2, 0, state, i); 3232 break; 3233 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3234 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3235 adev, 2, 1, state, i); 3236 break; 3237 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3238 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3239 adev, 2, 2, state, i); 3240 break; 3241 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3242 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3243 adev, 2, 3, state, i); 3244 break; 3245 default: 3246 break; 3247 } 3248 } 3249 3250 return 0; 3251 } 3252 3253 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3254 struct amdgpu_irq_src *source, 3255 struct amdgpu_iv_entry *entry) 3256 { 3257 int i, xcc_id; 3258 u8 me_id, pipe_id, queue_id; 3259 struct amdgpu_ring *ring; 3260 3261 DRM_DEBUG("IH: CP EOP\n"); 3262 me_id = (entry->ring_id & 0x0c) >> 2; 3263 pipe_id = (entry->ring_id & 0x03) >> 0; 3264 queue_id = (entry->ring_id & 0x70) >> 4; 3265 3266 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3267 3268 if (xcc_id == -EINVAL) 3269 return -EINVAL; 3270 3271 switch (me_id) { 3272 case 0: 3273 case 1: 3274 case 2: 3275 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3276 ring = &adev->gfx.compute_ring 3277 [i + 3278 xcc_id * adev->gfx.num_compute_rings]; 3279 /* Per-queue interrupt is supported for MEC starting from VI. 3280 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3281 */ 3282 3283 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3284 amdgpu_fence_process(ring); 3285 } 3286 break; 3287 } 3288 return 0; 3289 } 3290 3291 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3292 struct amdgpu_iv_entry *entry) 3293 { 3294 u8 me_id, pipe_id, queue_id; 3295 struct amdgpu_ring *ring; 3296 int i, xcc_id; 3297 3298 me_id = (entry->ring_id & 0x0c) >> 2; 3299 pipe_id = (entry->ring_id & 0x03) >> 0; 3300 queue_id = (entry->ring_id & 0x70) >> 4; 3301 3302 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3303 3304 if (xcc_id == -EINVAL) 3305 return; 3306 3307 switch (me_id) { 3308 case 0: 3309 case 1: 3310 case 2: 3311 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3312 ring = &adev->gfx.compute_ring 3313 [i + 3314 xcc_id * adev->gfx.num_compute_rings]; 3315 if (ring->me == me_id && ring->pipe == pipe_id && 3316 ring->queue == queue_id) 3317 drm_sched_fault(&ring->sched); 3318 } 3319 break; 3320 } 3321 } 3322 3323 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3324 struct amdgpu_irq_src *source, 3325 struct amdgpu_iv_entry *entry) 3326 { 3327 DRM_ERROR("Illegal register access in command stream\n"); 3328 gfx_v9_4_3_fault(adev, entry); 3329 return 0; 3330 } 3331 3332 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3333 struct amdgpu_irq_src *source, 3334 struct amdgpu_iv_entry *entry) 3335 { 3336 DRM_ERROR("Illegal opcode in command stream\n"); 3337 gfx_v9_4_3_fault(adev, entry); 3338 return 0; 3339 } 3340 3341 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3342 struct amdgpu_irq_src *source, 3343 struct amdgpu_iv_entry *entry) 3344 { 3345 DRM_ERROR("Illegal instruction in command stream\n"); 3346 gfx_v9_4_3_fault(adev, entry); 3347 return 0; 3348 } 3349 3350 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3351 { 3352 const unsigned int cp_coher_cntl = 3353 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3354 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3355 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3356 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3357 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3358 3359 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3360 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3361 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3362 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3363 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3364 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3365 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3366 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3367 } 3368 3369 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3370 uint32_t pipe, bool enable) 3371 { 3372 struct amdgpu_device *adev = ring->adev; 3373 uint32_t val; 3374 uint32_t wcl_cs_reg; 3375 3376 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3377 val = enable ? 0x1 : 0x7f; 3378 3379 switch (pipe) { 3380 case 0: 3381 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3382 break; 3383 case 1: 3384 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3385 break; 3386 case 2: 3387 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3388 break; 3389 case 3: 3390 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3391 break; 3392 default: 3393 DRM_DEBUG("invalid pipe %d\n", pipe); 3394 return; 3395 } 3396 3397 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3398 3399 } 3400 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3401 { 3402 struct amdgpu_device *adev = ring->adev; 3403 uint32_t val; 3404 int i; 3405 3406 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3407 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3408 * around 25% of gpu resources. 3409 */ 3410 val = enable ? 0x1f : 0x07ffffff; 3411 amdgpu_ring_emit_wreg(ring, 3412 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3413 val); 3414 3415 /* Restrict waves for normal/low priority compute queues as well 3416 * to get best QoS for high priority compute jobs. 3417 * 3418 * amdgpu controls only 1st ME(0-3 CS pipes). 3419 */ 3420 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3421 if (i != ring->pipe) 3422 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3423 3424 } 3425 } 3426 3427 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3428 uint32_t pipe, uint32_t queue, 3429 uint32_t xcc_id) 3430 { 3431 int i, r; 3432 /* make sure dequeue is complete*/ 3433 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3434 mutex_lock(&adev->srbm_mutex); 3435 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3436 for (i = 0; i < adev->usec_timeout; i++) { 3437 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3438 break; 3439 udelay(1); 3440 } 3441 if (i >= adev->usec_timeout) 3442 r = -ETIMEDOUT; 3443 else 3444 r = 0; 3445 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3446 mutex_unlock(&adev->srbm_mutex); 3447 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3448 3449 return r; 3450 3451 } 3452 3453 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3454 { 3455 /*TODO: Need check gfx9.4.4 mec fw whether supports pipe reset as well.*/ 3456 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 3457 adev->gfx.mec_fw_version >= 0x0000009b) 3458 return true; 3459 else 3460 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3461 3462 return false; 3463 } 3464 3465 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3466 { 3467 struct amdgpu_device *adev = ring->adev; 3468 uint32_t reset_pipe, clean_pipe; 3469 int r; 3470 3471 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3472 return -EINVAL; 3473 3474 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3475 mutex_lock(&adev->srbm_mutex); 3476 3477 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3478 clean_pipe = reset_pipe; 3479 3480 if (ring->me == 1) { 3481 switch (ring->pipe) { 3482 case 0: 3483 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3484 MEC_ME1_PIPE0_RESET, 1); 3485 break; 3486 case 1: 3487 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3488 MEC_ME1_PIPE1_RESET, 1); 3489 break; 3490 case 2: 3491 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3492 MEC_ME1_PIPE2_RESET, 1); 3493 break; 3494 case 3: 3495 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3496 MEC_ME1_PIPE3_RESET, 1); 3497 break; 3498 default: 3499 break; 3500 } 3501 } else { 3502 if (ring->pipe) 3503 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3504 MEC_ME2_PIPE1_RESET, 1); 3505 else 3506 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3507 MEC_ME2_PIPE0_RESET, 1); 3508 } 3509 3510 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3511 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3512 mutex_unlock(&adev->srbm_mutex); 3513 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3514 3515 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3516 return r; 3517 } 3518 3519 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3520 unsigned int vmid) 3521 { 3522 struct amdgpu_device *adev = ring->adev; 3523 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3524 struct amdgpu_ring *kiq_ring = &kiq->ring; 3525 unsigned long flags; 3526 int r; 3527 3528 if (amdgpu_sriov_vf(adev)) 3529 return -EINVAL; 3530 3531 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3532 return -EINVAL; 3533 3534 spin_lock_irqsave(&kiq->ring_lock, flags); 3535 3536 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3537 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3538 return -ENOMEM; 3539 } 3540 3541 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3542 0, 0); 3543 amdgpu_ring_commit(kiq_ring); 3544 3545 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3546 3547 r = amdgpu_ring_test_ring(kiq_ring); 3548 if (r) { 3549 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3550 ring->name); 3551 goto pipe_reset; 3552 } 3553 3554 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3555 if (r) 3556 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3557 3558 pipe_reset: 3559 if(r) { 3560 r = gfx_v9_4_3_reset_hw_pipe(ring); 3561 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3562 r ? "failed" : "successfully"); 3563 if (r) 3564 return r; 3565 } 3566 3567 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3568 if (r) { 3569 dev_err(adev->dev, "fail to init kcq\n"); 3570 return r; 3571 } 3572 spin_lock_irqsave(&kiq->ring_lock, flags); 3573 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3574 if (r) { 3575 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3576 return -ENOMEM; 3577 } 3578 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3579 amdgpu_ring_commit(kiq_ring); 3580 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3581 3582 r = amdgpu_ring_test_ring(kiq_ring); 3583 if (r) { 3584 dev_err(adev->dev, "fail to remap queue\n"); 3585 return r; 3586 } 3587 return amdgpu_ring_test_ring(ring); 3588 } 3589 3590 enum amdgpu_gfx_cp_ras_mem_id { 3591 AMDGPU_GFX_CP_MEM1 = 1, 3592 AMDGPU_GFX_CP_MEM2, 3593 AMDGPU_GFX_CP_MEM3, 3594 AMDGPU_GFX_CP_MEM4, 3595 AMDGPU_GFX_CP_MEM5, 3596 }; 3597 3598 enum amdgpu_gfx_gcea_ras_mem_id { 3599 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3600 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3601 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3602 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3603 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3604 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3605 AMDGPU_GFX_GCEA_MAM_DMEM0, 3606 AMDGPU_GFX_GCEA_MAM_DMEM1, 3607 AMDGPU_GFX_GCEA_MAM_DMEM2, 3608 AMDGPU_GFX_GCEA_MAM_DMEM3, 3609 AMDGPU_GFX_GCEA_MAM_AMEM0, 3610 AMDGPU_GFX_GCEA_MAM_AMEM1, 3611 AMDGPU_GFX_GCEA_MAM_AMEM2, 3612 AMDGPU_GFX_GCEA_MAM_AMEM3, 3613 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3614 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3615 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3616 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3617 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3618 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3619 }; 3620 3621 enum amdgpu_gfx_gc_cane_ras_mem_id { 3622 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3623 }; 3624 3625 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3626 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3627 }; 3628 3629 enum amdgpu_gfx_gds_ras_mem_id { 3630 AMDGPU_GFX_GDS_MEM0 = 0, 3631 }; 3632 3633 enum amdgpu_gfx_lds_ras_mem_id { 3634 AMDGPU_GFX_LDS_BANK0 = 0, 3635 AMDGPU_GFX_LDS_BANK1, 3636 AMDGPU_GFX_LDS_BANK2, 3637 AMDGPU_GFX_LDS_BANK3, 3638 AMDGPU_GFX_LDS_BANK4, 3639 AMDGPU_GFX_LDS_BANK5, 3640 AMDGPU_GFX_LDS_BANK6, 3641 AMDGPU_GFX_LDS_BANK7, 3642 AMDGPU_GFX_LDS_BANK8, 3643 AMDGPU_GFX_LDS_BANK9, 3644 AMDGPU_GFX_LDS_BANK10, 3645 AMDGPU_GFX_LDS_BANK11, 3646 AMDGPU_GFX_LDS_BANK12, 3647 AMDGPU_GFX_LDS_BANK13, 3648 AMDGPU_GFX_LDS_BANK14, 3649 AMDGPU_GFX_LDS_BANK15, 3650 AMDGPU_GFX_LDS_BANK16, 3651 AMDGPU_GFX_LDS_BANK17, 3652 AMDGPU_GFX_LDS_BANK18, 3653 AMDGPU_GFX_LDS_BANK19, 3654 AMDGPU_GFX_LDS_BANK20, 3655 AMDGPU_GFX_LDS_BANK21, 3656 AMDGPU_GFX_LDS_BANK22, 3657 AMDGPU_GFX_LDS_BANK23, 3658 AMDGPU_GFX_LDS_BANK24, 3659 AMDGPU_GFX_LDS_BANK25, 3660 AMDGPU_GFX_LDS_BANK26, 3661 AMDGPU_GFX_LDS_BANK27, 3662 AMDGPU_GFX_LDS_BANK28, 3663 AMDGPU_GFX_LDS_BANK29, 3664 AMDGPU_GFX_LDS_BANK30, 3665 AMDGPU_GFX_LDS_BANK31, 3666 AMDGPU_GFX_LDS_SP_BUFFER_A, 3667 AMDGPU_GFX_LDS_SP_BUFFER_B, 3668 }; 3669 3670 enum amdgpu_gfx_rlc_ras_mem_id { 3671 AMDGPU_GFX_RLC_GPMF32 = 1, 3672 AMDGPU_GFX_RLC_RLCVF32, 3673 AMDGPU_GFX_RLC_SCRATCH, 3674 AMDGPU_GFX_RLC_SRM_ARAM, 3675 AMDGPU_GFX_RLC_SRM_DRAM, 3676 AMDGPU_GFX_RLC_TCTAG, 3677 AMDGPU_GFX_RLC_SPM_SE, 3678 AMDGPU_GFX_RLC_SPM_GRBMT, 3679 }; 3680 3681 enum amdgpu_gfx_sp_ras_mem_id { 3682 AMDGPU_GFX_SP_SIMDID0 = 0, 3683 }; 3684 3685 enum amdgpu_gfx_spi_ras_mem_id { 3686 AMDGPU_GFX_SPI_MEM0 = 0, 3687 AMDGPU_GFX_SPI_MEM1, 3688 AMDGPU_GFX_SPI_MEM2, 3689 AMDGPU_GFX_SPI_MEM3, 3690 }; 3691 3692 enum amdgpu_gfx_sqc_ras_mem_id { 3693 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3694 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3695 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3696 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3697 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3698 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3699 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3700 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3701 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3702 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3703 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3704 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3705 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3706 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3707 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3708 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3709 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3710 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3711 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3712 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3713 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3714 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3715 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3716 }; 3717 3718 enum amdgpu_gfx_sq_ras_mem_id { 3719 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3720 AMDGPU_GFX_SQ_SGPR_MEM1, 3721 AMDGPU_GFX_SQ_SGPR_MEM2, 3722 AMDGPU_GFX_SQ_SGPR_MEM3, 3723 }; 3724 3725 enum amdgpu_gfx_ta_ras_mem_id { 3726 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3727 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3728 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3729 AMDGPU_GFX_TA_FSX_LFIFO, 3730 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3731 }; 3732 3733 enum amdgpu_gfx_tcc_ras_mem_id { 3734 AMDGPU_GFX_TCC_MEM1 = 1, 3735 }; 3736 3737 enum amdgpu_gfx_tca_ras_mem_id { 3738 AMDGPU_GFX_TCA_MEM1 = 1, 3739 }; 3740 3741 enum amdgpu_gfx_tci_ras_mem_id { 3742 AMDGPU_GFX_TCIW_MEM = 1, 3743 }; 3744 3745 enum amdgpu_gfx_tcp_ras_mem_id { 3746 AMDGPU_GFX_TCP_LFIFO0 = 1, 3747 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3748 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3749 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3750 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3751 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3752 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3753 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3754 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3755 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3756 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3757 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3758 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3759 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3760 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3761 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3762 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3763 AMDGPU_GFX_TCP_VM_FIFO, 3764 AMDGPU_GFX_TCP_DB_TAGRAM0, 3765 AMDGPU_GFX_TCP_DB_TAGRAM1, 3766 AMDGPU_GFX_TCP_DB_TAGRAM2, 3767 AMDGPU_GFX_TCP_DB_TAGRAM3, 3768 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3769 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3770 AMDGPU_GFX_TCP_CMD_FIFO, 3771 }; 3772 3773 enum amdgpu_gfx_td_ras_mem_id { 3774 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3775 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3776 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3777 }; 3778 3779 enum amdgpu_gfx_tcx_ras_mem_id { 3780 AMDGPU_GFX_TCX_FIFOD0 = 0, 3781 AMDGPU_GFX_TCX_FIFOD1, 3782 AMDGPU_GFX_TCX_FIFOD2, 3783 AMDGPU_GFX_TCX_FIFOD3, 3784 AMDGPU_GFX_TCX_FIFOD4, 3785 AMDGPU_GFX_TCX_FIFOD5, 3786 AMDGPU_GFX_TCX_FIFOD6, 3787 AMDGPU_GFX_TCX_FIFOD7, 3788 AMDGPU_GFX_TCX_FIFOB0, 3789 AMDGPU_GFX_TCX_FIFOB1, 3790 AMDGPU_GFX_TCX_FIFOB2, 3791 AMDGPU_GFX_TCX_FIFOB3, 3792 AMDGPU_GFX_TCX_FIFOB4, 3793 AMDGPU_GFX_TCX_FIFOB5, 3794 AMDGPU_GFX_TCX_FIFOB6, 3795 AMDGPU_GFX_TCX_FIFOB7, 3796 AMDGPU_GFX_TCX_FIFOA0, 3797 AMDGPU_GFX_TCX_FIFOA1, 3798 AMDGPU_GFX_TCX_FIFOA2, 3799 AMDGPU_GFX_TCX_FIFOA3, 3800 AMDGPU_GFX_TCX_FIFOA4, 3801 AMDGPU_GFX_TCX_FIFOA5, 3802 AMDGPU_GFX_TCX_FIFOA6, 3803 AMDGPU_GFX_TCX_FIFOA7, 3804 AMDGPU_GFX_TCX_CFIFO0, 3805 AMDGPU_GFX_TCX_CFIFO1, 3806 AMDGPU_GFX_TCX_CFIFO2, 3807 AMDGPU_GFX_TCX_CFIFO3, 3808 AMDGPU_GFX_TCX_CFIFO4, 3809 AMDGPU_GFX_TCX_CFIFO5, 3810 AMDGPU_GFX_TCX_CFIFO6, 3811 AMDGPU_GFX_TCX_CFIFO7, 3812 AMDGPU_GFX_TCX_FIFO_ACKB0, 3813 AMDGPU_GFX_TCX_FIFO_ACKB1, 3814 AMDGPU_GFX_TCX_FIFO_ACKB2, 3815 AMDGPU_GFX_TCX_FIFO_ACKB3, 3816 AMDGPU_GFX_TCX_FIFO_ACKB4, 3817 AMDGPU_GFX_TCX_FIFO_ACKB5, 3818 AMDGPU_GFX_TCX_FIFO_ACKB6, 3819 AMDGPU_GFX_TCX_FIFO_ACKB7, 3820 AMDGPU_GFX_TCX_FIFO_ACKD0, 3821 AMDGPU_GFX_TCX_FIFO_ACKD1, 3822 AMDGPU_GFX_TCX_FIFO_ACKD2, 3823 AMDGPU_GFX_TCX_FIFO_ACKD3, 3824 AMDGPU_GFX_TCX_FIFO_ACKD4, 3825 AMDGPU_GFX_TCX_FIFO_ACKD5, 3826 AMDGPU_GFX_TCX_FIFO_ACKD6, 3827 AMDGPU_GFX_TCX_FIFO_ACKD7, 3828 AMDGPU_GFX_TCX_DST_FIFOA0, 3829 AMDGPU_GFX_TCX_DST_FIFOA1, 3830 AMDGPU_GFX_TCX_DST_FIFOA2, 3831 AMDGPU_GFX_TCX_DST_FIFOA3, 3832 AMDGPU_GFX_TCX_DST_FIFOA4, 3833 AMDGPU_GFX_TCX_DST_FIFOA5, 3834 AMDGPU_GFX_TCX_DST_FIFOA6, 3835 AMDGPU_GFX_TCX_DST_FIFOA7, 3836 AMDGPU_GFX_TCX_DST_FIFOB0, 3837 AMDGPU_GFX_TCX_DST_FIFOB1, 3838 AMDGPU_GFX_TCX_DST_FIFOB2, 3839 AMDGPU_GFX_TCX_DST_FIFOB3, 3840 AMDGPU_GFX_TCX_DST_FIFOB4, 3841 AMDGPU_GFX_TCX_DST_FIFOB5, 3842 AMDGPU_GFX_TCX_DST_FIFOB6, 3843 AMDGPU_GFX_TCX_DST_FIFOB7, 3844 AMDGPU_GFX_TCX_DST_FIFOD0, 3845 AMDGPU_GFX_TCX_DST_FIFOD1, 3846 AMDGPU_GFX_TCX_DST_FIFOD2, 3847 AMDGPU_GFX_TCX_DST_FIFOD3, 3848 AMDGPU_GFX_TCX_DST_FIFOD4, 3849 AMDGPU_GFX_TCX_DST_FIFOD5, 3850 AMDGPU_GFX_TCX_DST_FIFOD6, 3851 AMDGPU_GFX_TCX_DST_FIFOD7, 3852 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3853 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3854 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3855 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3856 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3857 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3858 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3859 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3860 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3861 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3862 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3863 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3864 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3865 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3866 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3867 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3868 }; 3869 3870 enum amdgpu_gfx_atc_l2_ras_mem_id { 3871 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3872 }; 3873 3874 enum amdgpu_gfx_utcl2_ras_mem_id { 3875 AMDGPU_GFX_UTCL2_MEM0 = 0, 3876 }; 3877 3878 enum amdgpu_gfx_vml2_ras_mem_id { 3879 AMDGPU_GFX_VML2_MEM0 = 0, 3880 }; 3881 3882 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3883 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3884 }; 3885 3886 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3887 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3888 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3889 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3890 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3891 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3892 }; 3893 3894 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3895 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3896 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3897 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3898 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3899 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3900 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3901 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3902 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3903 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3904 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3905 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3906 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3907 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3908 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3909 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3910 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3911 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3912 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3913 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3914 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3915 }; 3916 3917 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3918 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3919 }; 3920 3921 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3922 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3923 }; 3924 3925 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3926 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3927 }; 3928 3929 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3930 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3931 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3932 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3933 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3934 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3935 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3936 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3937 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3938 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3939 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3940 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3941 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3942 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3943 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3944 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3945 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3946 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3947 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3948 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3949 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3950 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3951 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3952 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3953 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3954 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3955 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3956 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3957 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3958 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3959 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3960 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3961 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3962 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3963 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3964 }; 3965 3966 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3967 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3968 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3969 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3970 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3971 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3972 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3973 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3974 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3975 }; 3976 3977 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3978 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3979 }; 3980 3981 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3982 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3983 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3984 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3985 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3986 }; 3987 3988 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3989 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3990 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3991 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3992 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3993 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3994 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3995 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3996 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3997 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3998 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3999 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4000 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4001 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4002 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4003 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4004 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4005 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4006 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4007 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4008 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4009 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4010 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4011 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4012 }; 4013 4014 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4015 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4016 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4017 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4018 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4019 }; 4020 4021 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4022 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4023 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4024 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4025 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4026 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4027 }; 4028 4029 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4030 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4031 }; 4032 4033 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4034 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4035 }; 4036 4037 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4038 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4039 }; 4040 4041 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4042 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4043 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4044 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4045 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4046 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4047 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4048 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4049 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4050 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4051 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4052 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4053 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4054 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4055 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4056 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4057 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4058 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4059 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4060 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4061 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4062 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4063 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4064 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4065 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4066 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4067 }; 4068 4069 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4070 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4071 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4072 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4073 }; 4074 4075 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4076 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4077 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4078 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4079 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4080 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4081 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4082 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4083 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4084 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4085 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4086 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4087 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4088 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4089 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4090 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4091 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4092 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4093 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4094 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4095 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4096 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4097 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4098 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4099 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4100 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4101 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4102 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4103 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4104 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4105 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4106 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4107 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4108 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4109 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4110 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4111 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4112 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4113 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4114 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4115 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4116 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4117 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4118 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4119 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4120 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4121 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4122 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4123 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4124 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4125 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4126 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4127 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4128 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4129 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4130 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4131 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4132 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4133 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4134 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4135 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4136 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4137 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4138 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4139 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4140 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4141 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4142 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4143 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4144 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4145 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4146 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4147 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4148 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4149 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4150 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4151 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4152 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4153 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4154 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4155 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4156 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4157 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4158 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4159 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4160 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4161 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4162 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4163 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4164 }; 4165 4166 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4167 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4168 }; 4169 4170 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4171 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4172 }; 4173 4174 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4175 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4176 }; 4177 4178 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4179 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4180 }; 4181 4182 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4183 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4184 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4185 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4186 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4187 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4188 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4189 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4190 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4191 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4192 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4193 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4194 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4195 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4196 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4197 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4198 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4199 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4200 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4201 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4202 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4203 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4204 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4205 }; 4206 4207 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4208 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4209 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4210 AMDGPU_GFX_RLC_MEM, 1}, 4211 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4212 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4213 AMDGPU_GFX_CP_MEM, 1}, 4214 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4215 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4216 AMDGPU_GFX_CP_MEM, 1}, 4217 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4218 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4219 AMDGPU_GFX_CP_MEM, 1}, 4220 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4221 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4222 AMDGPU_GFX_GDS_MEM, 1}, 4223 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4224 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4225 AMDGPU_GFX_GC_CANE_MEM, 1}, 4226 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4227 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4228 AMDGPU_GFX_SPI_MEM, 1}, 4229 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4230 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4231 AMDGPU_GFX_SP_MEM, 4}, 4232 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4233 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4234 AMDGPU_GFX_SP_MEM, 4}, 4235 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4236 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4237 AMDGPU_GFX_SQ_MEM, 4}, 4238 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4239 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4240 AMDGPU_GFX_SQC_MEM, 4}, 4241 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4242 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4243 AMDGPU_GFX_TCX_MEM, 1}, 4244 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4245 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4246 AMDGPU_GFX_TCC_MEM, 1}, 4247 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4248 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4249 AMDGPU_GFX_TA_MEM, 4}, 4250 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4251 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4252 AMDGPU_GFX_TCI_MEM, 1}, 4253 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4254 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4255 AMDGPU_GFX_TCP_MEM, 4}, 4256 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4257 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4258 AMDGPU_GFX_TD_MEM, 4}, 4259 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4260 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4261 AMDGPU_GFX_GCEA_MEM, 1}, 4262 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4263 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4264 AMDGPU_GFX_LDS_MEM, 4}, 4265 }; 4266 4267 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4268 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4269 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4270 AMDGPU_GFX_RLC_MEM, 1}, 4271 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4272 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4273 AMDGPU_GFX_CP_MEM, 1}, 4274 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4275 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4276 AMDGPU_GFX_CP_MEM, 1}, 4277 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4278 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4279 AMDGPU_GFX_CP_MEM, 1}, 4280 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4281 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4282 AMDGPU_GFX_GDS_MEM, 1}, 4283 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4284 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4285 AMDGPU_GFX_GC_CANE_MEM, 1}, 4286 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4287 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4288 AMDGPU_GFX_SPI_MEM, 1}, 4289 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4290 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4291 AMDGPU_GFX_SP_MEM, 4}, 4292 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4293 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4294 AMDGPU_GFX_SP_MEM, 4}, 4295 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4296 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4297 AMDGPU_GFX_SQ_MEM, 4}, 4298 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4299 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4300 AMDGPU_GFX_SQC_MEM, 4}, 4301 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4302 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4303 AMDGPU_GFX_TCX_MEM, 1}, 4304 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4305 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4306 AMDGPU_GFX_TCC_MEM, 1}, 4307 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4308 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4309 AMDGPU_GFX_TA_MEM, 4}, 4310 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4311 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4312 AMDGPU_GFX_TCI_MEM, 1}, 4313 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4314 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4315 AMDGPU_GFX_TCP_MEM, 4}, 4316 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4317 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4318 AMDGPU_GFX_TD_MEM, 4}, 4319 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4320 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4321 AMDGPU_GFX_TCA_MEM, 1}, 4322 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4323 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4324 AMDGPU_GFX_GCEA_MEM, 1}, 4325 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4326 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4327 AMDGPU_GFX_LDS_MEM, 4}, 4328 }; 4329 4330 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4331 void *ras_error_status, int xcc_id) 4332 { 4333 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4334 unsigned long ce_count = 0, ue_count = 0; 4335 uint32_t i, j, k; 4336 4337 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4338 struct amdgpu_smuio_mcm_config_info mcm_info = { 4339 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4340 .die_id = xcc_id & 0x01 ? 1 : 0, 4341 }; 4342 4343 mutex_lock(&adev->grbm_idx_mutex); 4344 4345 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4346 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4347 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4348 /* no need to select if instance number is 1 */ 4349 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4350 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4351 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4352 4353 amdgpu_ras_inst_query_ras_error_count(adev, 4354 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4355 1, 4356 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4357 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4358 GET_INST(GC, xcc_id), 4359 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4360 &ce_count); 4361 4362 amdgpu_ras_inst_query_ras_error_count(adev, 4363 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4364 1, 4365 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4366 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4367 GET_INST(GC, xcc_id), 4368 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4369 &ue_count); 4370 } 4371 } 4372 } 4373 4374 /* handle extra register entries of UE */ 4375 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4376 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4377 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4378 /* no need to select if instance number is 1 */ 4379 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4380 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4381 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4382 4383 amdgpu_ras_inst_query_ras_error_count(adev, 4384 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4385 1, 4386 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4387 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4388 GET_INST(GC, xcc_id), 4389 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4390 &ue_count); 4391 } 4392 } 4393 } 4394 4395 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4396 xcc_id); 4397 mutex_unlock(&adev->grbm_idx_mutex); 4398 4399 /* the caller should make sure initialize value of 4400 * err_data->ue_count and err_data->ce_count 4401 */ 4402 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4403 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4404 } 4405 4406 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4407 void *ras_error_status, int xcc_id) 4408 { 4409 uint32_t i, j, k; 4410 4411 mutex_lock(&adev->grbm_idx_mutex); 4412 4413 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4414 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4415 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4416 /* no need to select if instance number is 1 */ 4417 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4418 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4419 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4420 4421 amdgpu_ras_inst_reset_ras_error_count(adev, 4422 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4423 1, 4424 GET_INST(GC, xcc_id)); 4425 4426 amdgpu_ras_inst_reset_ras_error_count(adev, 4427 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4428 1, 4429 GET_INST(GC, xcc_id)); 4430 } 4431 } 4432 } 4433 4434 /* handle extra register entries of UE */ 4435 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4436 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4437 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4438 /* no need to select if instance number is 1 */ 4439 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4440 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4441 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4442 4443 amdgpu_ras_inst_reset_ras_error_count(adev, 4444 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4445 1, 4446 GET_INST(GC, xcc_id)); 4447 } 4448 } 4449 } 4450 4451 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4452 xcc_id); 4453 mutex_unlock(&adev->grbm_idx_mutex); 4454 } 4455 4456 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4457 void *ras_error_status, int xcc_id) 4458 { 4459 uint32_t i; 4460 uint32_t data; 4461 4462 if (amdgpu_sriov_vf(adev)) 4463 return; 4464 4465 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4466 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4467 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4468 4469 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4470 (amdgpu_watchdog_timer.period < 1 || 4471 amdgpu_watchdog_timer.period > 0x23)) { 4472 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4473 amdgpu_watchdog_timer.period = 0x23; 4474 } 4475 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4476 amdgpu_watchdog_timer.period); 4477 4478 mutex_lock(&adev->grbm_idx_mutex); 4479 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4480 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4481 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4482 } 4483 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4484 xcc_id); 4485 mutex_unlock(&adev->grbm_idx_mutex); 4486 } 4487 4488 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4489 void *ras_error_status) 4490 { 4491 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4492 gfx_v9_4_3_inst_query_ras_err_count); 4493 } 4494 4495 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4496 { 4497 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4498 } 4499 4500 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4501 { 4502 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4503 } 4504 4505 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4506 { 4507 /* Header itself is a NOP packet */ 4508 if (num_nop == 1) { 4509 amdgpu_ring_write(ring, ring->funcs->nop); 4510 return; 4511 } 4512 4513 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4514 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4515 4516 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4517 amdgpu_ring_insert_nop(ring, num_nop - 1); 4518 } 4519 4520 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4521 { 4522 struct amdgpu_device *adev = ip_block->adev; 4523 uint32_t i, j, k; 4524 uint32_t xcc_id, xcc_offset, inst_offset; 4525 uint32_t num_xcc, reg, num_inst; 4526 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4527 4528 if (!adev->gfx.ip_dump_core) 4529 return; 4530 4531 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4532 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4533 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4534 xcc_offset = xcc_id * reg_count; 4535 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4536 for (i = 0; i < reg_count; i++) 4537 drm_printf(p, "%-50s \t 0x%08x\n", 4538 gc_reg_list_9_4_3[i].reg_name, 4539 adev->gfx.ip_dump_core[xcc_offset + i]); 4540 } 4541 4542 /* print compute queue registers for all instances */ 4543 if (!adev->gfx.ip_dump_compute_queues) 4544 return; 4545 4546 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4547 adev->gfx.mec.num_queue_per_pipe; 4548 4549 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4550 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4551 num_xcc, 4552 adev->gfx.mec.num_mec, 4553 adev->gfx.mec.num_pipe_per_mec, 4554 adev->gfx.mec.num_queue_per_pipe); 4555 4556 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4557 xcc_offset = xcc_id * reg_count * num_inst; 4558 inst_offset = 0; 4559 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4560 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4561 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4562 drm_printf(p, 4563 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4564 xcc_id, i, j, k); 4565 for (reg = 0; reg < reg_count; reg++) { 4566 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4567 regCP_MEC_ME1_HEADER_DUMP) 4568 drm_printf(p, 4569 "%-50s \t 0x%08x\n", 4570 "regCP_MEC_ME2_HEADER_DUMP", 4571 adev->gfx.ip_dump_compute_queues 4572 [xcc_offset + inst_offset + 4573 reg]); 4574 else 4575 drm_printf(p, 4576 "%-50s \t 0x%08x\n", 4577 gc_cp_reg_list_9_4_3[reg].reg_name, 4578 adev->gfx.ip_dump_compute_queues 4579 [xcc_offset + inst_offset + 4580 reg]); 4581 } 4582 inst_offset += reg_count; 4583 } 4584 } 4585 } 4586 } 4587 } 4588 4589 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4590 { 4591 struct amdgpu_device *adev = ip_block->adev; 4592 uint32_t i, j, k; 4593 uint32_t num_xcc, reg, num_inst; 4594 uint32_t xcc_id, xcc_offset, inst_offset; 4595 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4596 4597 if (!adev->gfx.ip_dump_core) 4598 return; 4599 4600 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4601 4602 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4603 xcc_offset = xcc_id * reg_count; 4604 for (i = 0; i < reg_count; i++) 4605 adev->gfx.ip_dump_core[xcc_offset + i] = 4606 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4607 GET_INST(GC, xcc_id))); 4608 } 4609 4610 /* dump compute queue registers for all instances */ 4611 if (!adev->gfx.ip_dump_compute_queues) 4612 return; 4613 4614 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4615 adev->gfx.mec.num_queue_per_pipe; 4616 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4617 mutex_lock(&adev->srbm_mutex); 4618 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4619 xcc_offset = xcc_id * reg_count * num_inst; 4620 inst_offset = 0; 4621 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4622 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4623 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4624 /* ME0 is for GFX so start from 1 for CP */ 4625 soc15_grbm_select(adev, 1 + i, j, k, 0, 4626 GET_INST(GC, xcc_id)); 4627 4628 for (reg = 0; reg < reg_count; reg++) { 4629 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4630 regCP_MEC_ME1_HEADER_DUMP) 4631 adev->gfx.ip_dump_compute_queues 4632 [xcc_offset + 4633 inst_offset + reg] = 4634 RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), 4635 regCP_MEC_ME2_HEADER_DUMP)); 4636 else 4637 adev->gfx.ip_dump_compute_queues 4638 [xcc_offset + 4639 inst_offset + reg] = 4640 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4641 gc_cp_reg_list_9_4_3[reg], 4642 GET_INST(GC, xcc_id))); 4643 } 4644 inst_offset += reg_count; 4645 } 4646 } 4647 } 4648 } 4649 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4650 mutex_unlock(&adev->srbm_mutex); 4651 } 4652 4653 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4654 { 4655 /* Emit the cleaner shader */ 4656 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4657 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4658 } 4659 4660 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4661 .name = "gfx_v9_4_3", 4662 .early_init = gfx_v9_4_3_early_init, 4663 .late_init = gfx_v9_4_3_late_init, 4664 .sw_init = gfx_v9_4_3_sw_init, 4665 .sw_fini = gfx_v9_4_3_sw_fini, 4666 .hw_init = gfx_v9_4_3_hw_init, 4667 .hw_fini = gfx_v9_4_3_hw_fini, 4668 .suspend = gfx_v9_4_3_suspend, 4669 .resume = gfx_v9_4_3_resume, 4670 .is_idle = gfx_v9_4_3_is_idle, 4671 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4672 .soft_reset = gfx_v9_4_3_soft_reset, 4673 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4674 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4675 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4676 .dump_ip_state = gfx_v9_4_3_ip_dump, 4677 .print_ip_state = gfx_v9_4_3_ip_print, 4678 }; 4679 4680 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4681 .type = AMDGPU_RING_TYPE_COMPUTE, 4682 .align_mask = 0xff, 4683 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4684 .support_64bit_ptrs = true, 4685 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4686 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4687 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4688 .emit_frame_size = 4689 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4690 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4691 5 + /* hdp invalidate */ 4692 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4693 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4694 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4695 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4696 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4697 7 + /* gfx_v9_4_3_emit_mem_sync */ 4698 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4699 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4700 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4701 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4702 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4703 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4704 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4705 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4706 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4707 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4708 .test_ring = gfx_v9_4_3_ring_test_ring, 4709 .test_ib = gfx_v9_4_3_ring_test_ib, 4710 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4711 .pad_ib = amdgpu_ring_generic_pad_ib, 4712 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4713 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4714 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4715 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4716 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4717 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4718 .reset = gfx_v9_4_3_reset_kcq, 4719 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4720 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4721 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4722 }; 4723 4724 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4725 .type = AMDGPU_RING_TYPE_KIQ, 4726 .align_mask = 0xff, 4727 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4728 .support_64bit_ptrs = true, 4729 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4730 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4731 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4732 .emit_frame_size = 4733 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4734 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4735 5 + /* hdp invalidate */ 4736 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4737 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4738 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4739 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4740 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4741 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4742 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4743 .test_ring = gfx_v9_4_3_ring_test_ring, 4744 .insert_nop = amdgpu_ring_insert_nop, 4745 .pad_ib = amdgpu_ring_generic_pad_ib, 4746 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4747 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4748 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4749 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4750 }; 4751 4752 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4753 { 4754 int i, j, num_xcc; 4755 4756 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4757 for (i = 0; i < num_xcc; i++) { 4758 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4759 4760 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4761 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4762 = &gfx_v9_4_3_ring_funcs_compute; 4763 } 4764 } 4765 4766 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4767 .set = gfx_v9_4_3_set_eop_interrupt_state, 4768 .process = gfx_v9_4_3_eop_irq, 4769 }; 4770 4771 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4772 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4773 .process = gfx_v9_4_3_priv_reg_irq, 4774 }; 4775 4776 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4777 .set = gfx_v9_4_3_set_bad_op_fault_state, 4778 .process = gfx_v9_4_3_bad_op_irq, 4779 }; 4780 4781 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4782 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4783 .process = gfx_v9_4_3_priv_inst_irq, 4784 }; 4785 4786 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4787 { 4788 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4789 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4790 4791 adev->gfx.priv_reg_irq.num_types = 1; 4792 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4793 4794 adev->gfx.bad_op_irq.num_types = 1; 4795 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4796 4797 adev->gfx.priv_inst_irq.num_types = 1; 4798 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4799 } 4800 4801 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4802 { 4803 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4804 } 4805 4806 4807 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4808 { 4809 /* 9.4.3 variants removed all the GDS internal memory, 4810 * only support GWS opcode in kernel, like barrier 4811 * semaphore.etc */ 4812 4813 /* init asic gds info */ 4814 adev->gds.gds_size = 0; 4815 adev->gds.gds_compute_max_wave_id = 0; 4816 adev->gds.gws_size = 64; 4817 adev->gds.oa_size = 16; 4818 } 4819 4820 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4821 u32 bitmap, int xcc_id) 4822 { 4823 u32 data; 4824 4825 if (!bitmap) 4826 return; 4827 4828 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4829 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4830 4831 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4832 } 4833 4834 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4835 { 4836 u32 data, mask; 4837 4838 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4839 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4840 4841 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4842 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4843 4844 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4845 4846 return (~data) & mask; 4847 } 4848 4849 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4850 struct amdgpu_cu_info *cu_info) 4851 { 4852 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4853 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4854 unsigned disable_masks[4 * 4]; 4855 bool is_symmetric_cus; 4856 4857 if (!adev || !cu_info) 4858 return -EINVAL; 4859 4860 /* 4861 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4862 */ 4863 if (adev->gfx.config.max_shader_engines * 4864 adev->gfx.config.max_sh_per_se > 16) 4865 return -EINVAL; 4866 4867 amdgpu_gfx_parse_disable_cu(disable_masks, 4868 adev->gfx.config.max_shader_engines, 4869 adev->gfx.config.max_sh_per_se); 4870 4871 mutex_lock(&adev->grbm_idx_mutex); 4872 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4873 is_symmetric_cus = true; 4874 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4875 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4876 mask = 1; 4877 ao_bitmap = 0; 4878 counter = 0; 4879 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4880 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4881 adev, 4882 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4883 xcc_id); 4884 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4885 4886 cu_info->bitmap[xcc_id][i][j] = bitmap; 4887 4888 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4889 if (bitmap & mask) { 4890 if (counter < adev->gfx.config.max_cu_per_sh) 4891 ao_bitmap |= mask; 4892 counter++; 4893 } 4894 mask <<= 1; 4895 } 4896 active_cu_number += counter; 4897 if (i < 2 && j < 2) 4898 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4899 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4900 } 4901 if (i && is_symmetric_cus && prev_counter != counter) 4902 is_symmetric_cus = false; 4903 prev_counter = counter; 4904 } 4905 if (is_symmetric_cus) { 4906 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4907 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4908 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4909 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4910 } 4911 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4912 xcc_id); 4913 } 4914 mutex_unlock(&adev->grbm_idx_mutex); 4915 4916 cu_info->number = active_cu_number; 4917 cu_info->ao_cu_mask = ao_cu_mask; 4918 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4919 4920 return 0; 4921 } 4922 4923 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4924 .type = AMD_IP_BLOCK_TYPE_GFX, 4925 .major = 9, 4926 .minor = 4, 4927 .rev = 3, 4928 .funcs = &gfx_v9_4_3_ip_funcs, 4929 }; 4930 4931 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4932 { 4933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4934 uint32_t tmp_mask; 4935 int i, r; 4936 4937 /* TODO : Initialize golden regs */ 4938 /* gfx_v9_4_3_init_golden_registers(adev); */ 4939 4940 tmp_mask = inst_mask; 4941 for_each_inst(i, tmp_mask) 4942 gfx_v9_4_3_xcc_constants_init(adev, i); 4943 4944 if (!amdgpu_sriov_vf(adev)) { 4945 tmp_mask = inst_mask; 4946 for_each_inst(i, tmp_mask) { 4947 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4948 if (r) 4949 return r; 4950 } 4951 } 4952 4953 tmp_mask = inst_mask; 4954 for_each_inst(i, tmp_mask) { 4955 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4956 if (r) 4957 return r; 4958 } 4959 4960 return 0; 4961 } 4962 4963 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4964 { 4965 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4966 int i; 4967 4968 for_each_inst(i, inst_mask) 4969 gfx_v9_4_3_xcc_fini(adev, i); 4970 4971 return 0; 4972 } 4973 4974 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4975 .suspend = &gfx_v9_4_3_xcp_suspend, 4976 .resume = &gfx_v9_4_3_xcp_resume 4977 }; 4978 4979 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4980 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4981 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4982 }; 4983 4984 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 4985 { 4986 int r; 4987 4988 r = amdgpu_ras_block_late_init(adev, ras_block); 4989 if (r) 4990 return r; 4991 4992 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 4993 &gfx_v9_4_3_aca_info, 4994 NULL); 4995 if (r) 4996 goto late_fini; 4997 4998 return 0; 4999 5000 late_fini: 5001 amdgpu_ras_block_late_fini(adev, ras_block); 5002 5003 return r; 5004 } 5005 5006 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5007 .ras_block = { 5008 .hw_ops = &gfx_v9_4_3_ras_ops, 5009 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5010 }, 5011 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5012 }; 5013