1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 48 49 #define GFX9_MEC_HPD_SIZE 4096 50 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 51 52 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 53 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 54 55 #define mmSMNAID_XCD0_MCA_SMU 0x36430400 /* SMN AID XCD0 */ 56 #define mmSMNAID_XCD1_MCA_SMU 0x38430400 /* SMN AID XCD1 */ 57 #define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */ 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* cp header registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP), 111 /* SE status registers */ 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 113 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 115 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 116 }; 117 118 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 119 /* compute queue registers */ 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 157 }; 158 159 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 160 161 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 162 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 163 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 164 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 165 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 166 struct amdgpu_cu_info *cu_info); 167 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 168 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 169 170 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 171 uint64_t queue_mask) 172 { 173 struct amdgpu_device *adev = kiq_ring->adev; 174 u64 shader_mc_addr; 175 176 /* Cleaner shader MC address */ 177 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 178 179 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 180 amdgpu_ring_write(kiq_ring, 181 PACKET3_SET_RESOURCES_VMID_MASK(0) | 182 /* vmid_mask:0* queue_type:0 (KIQ) */ 183 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 184 amdgpu_ring_write(kiq_ring, 185 lower_32_bits(queue_mask)); /* queue mask lo */ 186 amdgpu_ring_write(kiq_ring, 187 upper_32_bits(queue_mask)); /* queue mask hi */ 188 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 189 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 190 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 191 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 192 } 193 194 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 195 struct amdgpu_ring *ring) 196 { 197 struct amdgpu_device *adev = kiq_ring->adev; 198 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 199 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 200 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 201 202 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 203 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 204 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 205 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 206 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 207 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 208 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 209 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 210 /*queue_type: normal compute queue */ 211 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 212 /* alloc format: all_on_one_pipe */ 213 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 214 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 215 /* num_queues: must be 1 */ 216 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 217 amdgpu_ring_write(kiq_ring, 218 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 219 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 220 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 221 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 222 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 223 } 224 225 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 226 struct amdgpu_ring *ring, 227 enum amdgpu_unmap_queues_action action, 228 u64 gpu_addr, u64 seq) 229 { 230 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 231 232 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 233 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 234 PACKET3_UNMAP_QUEUES_ACTION(action) | 235 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 236 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 237 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 238 amdgpu_ring_write(kiq_ring, 239 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 240 241 if (action == PREEMPT_QUEUES_NO_UNMAP) { 242 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 243 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 244 amdgpu_ring_write(kiq_ring, seq); 245 } else { 246 amdgpu_ring_write(kiq_ring, 0); 247 amdgpu_ring_write(kiq_ring, 0); 248 amdgpu_ring_write(kiq_ring, 0); 249 } 250 } 251 252 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 253 struct amdgpu_ring *ring, 254 u64 addr, 255 u64 seq) 256 { 257 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 258 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 260 amdgpu_ring_write(kiq_ring, 261 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 262 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 263 PACKET3_QUERY_STATUS_COMMAND(2)); 264 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 267 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 268 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 269 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 270 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 271 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 272 } 273 274 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 275 uint16_t pasid, uint32_t flush_type, 276 bool all_hub) 277 { 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 279 amdgpu_ring_write(kiq_ring, 280 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 281 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 282 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 283 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 284 } 285 286 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 287 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 288 uint32_t xcc_id, uint32_t vmid) 289 { 290 struct amdgpu_device *adev = kiq_ring->adev; 291 unsigned i; 292 293 /* enter save mode */ 294 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 295 mutex_lock(&adev->srbm_mutex); 296 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 297 298 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 301 /* wait till dequeue take effects */ 302 for (i = 0; i < adev->usec_timeout; i++) { 303 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 304 break; 305 udelay(1); 306 } 307 if (i >= adev->usec_timeout) 308 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 309 } else { 310 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 311 } 312 313 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 314 mutex_unlock(&adev->srbm_mutex); 315 /* exit safe mode */ 316 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 317 } 318 319 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 320 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 321 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 322 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 323 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 324 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 325 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 326 .set_resources_size = 8, 327 .map_queues_size = 7, 328 .unmap_queues_size = 6, 329 .query_status_size = 7, 330 .invalidate_tlbs_size = 2, 331 }; 332 333 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 334 { 335 int i, num_xcc; 336 337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 338 for (i = 0; i < num_xcc; i++) 339 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 340 } 341 342 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 343 { 344 int i, num_xcc, dev_inst; 345 346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 347 for (i = 0; i < num_xcc; i++) { 348 dev_inst = GET_INST(GC, i); 349 350 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 351 GOLDEN_GB_ADDR_CONFIG); 352 /* Golden settings applied by driver for ASIC with rev_id 0 */ 353 if (adev->rev_id == 0) { 354 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 355 REDUCE_FIFO_DEPTH_BY_2, 2); 356 } else { 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 358 SPARE, 0x1); 359 } 360 } 361 } 362 363 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 364 { 365 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 366 367 /* If it is an XCC reg, normalize the reg to keep 368 lower 16 bits in local xcc */ 369 370 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 371 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 372 return normalized_reg; 373 else 374 return reg; 375 } 376 377 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 378 bool wc, uint32_t reg, uint32_t val) 379 { 380 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 381 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 382 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 383 WRITE_DATA_DST_SEL(0) | 384 (wc ? WR_CONFIRM : 0)); 385 amdgpu_ring_write(ring, reg); 386 amdgpu_ring_write(ring, 0); 387 amdgpu_ring_write(ring, val); 388 } 389 390 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 391 int mem_space, int opt, uint32_t addr0, 392 uint32_t addr1, uint32_t ref, uint32_t mask, 393 uint32_t inv) 394 { 395 /* Only do the normalization on regspace */ 396 if (mem_space == 0) { 397 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 398 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 399 } 400 401 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 402 amdgpu_ring_write(ring, 403 /* memory (1) or register (0) */ 404 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 405 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 406 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 407 WAIT_REG_MEM_ENGINE(eng_sel))); 408 409 if (mem_space) 410 BUG_ON(addr0 & 0x3); /* Dword align */ 411 amdgpu_ring_write(ring, addr0); 412 amdgpu_ring_write(ring, addr1); 413 amdgpu_ring_write(ring, ref); 414 amdgpu_ring_write(ring, mask); 415 amdgpu_ring_write(ring, inv); /* poll interval */ 416 } 417 418 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 419 { 420 uint32_t scratch_reg0_offset, xcc_offset; 421 struct amdgpu_device *adev = ring->adev; 422 uint32_t tmp = 0; 423 unsigned i; 424 int r; 425 426 /* Use register offset which is local to XCC in the packet */ 427 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 428 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 429 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 430 tmp = RREG32(scratch_reg0_offset); 431 432 r = amdgpu_ring_alloc(ring, 3); 433 if (r) 434 return r; 435 436 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 437 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 438 amdgpu_ring_write(ring, 0xDEADBEEF); 439 amdgpu_ring_commit(ring); 440 441 for (i = 0; i < adev->usec_timeout; i++) { 442 tmp = RREG32(scratch_reg0_offset); 443 if (tmp == 0xDEADBEEF) 444 break; 445 udelay(1); 446 } 447 448 if (i >= adev->usec_timeout) 449 r = -ETIMEDOUT; 450 return r; 451 } 452 453 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 454 { 455 struct amdgpu_device *adev = ring->adev; 456 struct amdgpu_ib ib; 457 struct dma_fence *f = NULL; 458 459 unsigned index; 460 uint64_t gpu_addr; 461 uint32_t tmp; 462 long r; 463 464 r = amdgpu_device_wb_get(adev, &index); 465 if (r) 466 return r; 467 468 gpu_addr = adev->wb.gpu_addr + (index * 4); 469 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 470 memset(&ib, 0, sizeof(ib)); 471 472 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 473 if (r) 474 goto err1; 475 476 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 477 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 478 ib.ptr[2] = lower_32_bits(gpu_addr); 479 ib.ptr[3] = upper_32_bits(gpu_addr); 480 ib.ptr[4] = 0xDEADBEEF; 481 ib.length_dw = 5; 482 483 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 484 if (r) 485 goto err2; 486 487 r = dma_fence_wait_timeout(f, false, timeout); 488 if (r == 0) { 489 r = -ETIMEDOUT; 490 goto err2; 491 } else if (r < 0) { 492 goto err2; 493 } 494 495 tmp = adev->wb.wb[index]; 496 if (tmp == 0xDEADBEEF) 497 r = 0; 498 else 499 r = -EINVAL; 500 501 err2: 502 amdgpu_ib_free(adev, &ib, NULL); 503 dma_fence_put(f); 504 err1: 505 amdgpu_device_wb_free(adev, index); 506 return r; 507 } 508 509 510 /* This value might differs per partition */ 511 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 512 { 513 uint64_t clock; 514 515 mutex_lock(&adev->gfx.gpu_clock_mutex); 516 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 517 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 518 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 519 mutex_unlock(&adev->gfx.gpu_clock_mutex); 520 521 return clock; 522 } 523 524 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 525 { 526 amdgpu_ucode_release(&adev->gfx.pfp_fw); 527 amdgpu_ucode_release(&adev->gfx.me_fw); 528 amdgpu_ucode_release(&adev->gfx.ce_fw); 529 amdgpu_ucode_release(&adev->gfx.rlc_fw); 530 amdgpu_ucode_release(&adev->gfx.mec_fw); 531 amdgpu_ucode_release(&adev->gfx.mec2_fw); 532 533 kfree(adev->gfx.rlc.register_list_format); 534 } 535 536 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 537 const char *chip_name) 538 { 539 int err; 540 const struct rlc_firmware_header_v2_0 *rlc_hdr; 541 uint16_t version_major; 542 uint16_t version_minor; 543 544 545 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 546 "amdgpu/%s_rlc.bin", chip_name); 547 if (err) 548 goto out; 549 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 550 551 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 552 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 553 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 554 out: 555 if (err) 556 amdgpu_ucode_release(&adev->gfx.rlc_fw); 557 558 return err; 559 } 560 561 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 562 { 563 return true; 564 } 565 566 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 567 { 568 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 569 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 570 } 571 572 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 573 const char *chip_name) 574 { 575 int err; 576 577 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 578 "amdgpu/%s_mec.bin", chip_name); 579 if (err) 580 goto out; 581 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 582 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 583 584 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 585 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 586 587 gfx_v9_4_3_check_if_need_gfxoff(adev); 588 589 out: 590 if (err) 591 amdgpu_ucode_release(&adev->gfx.mec_fw); 592 return err; 593 } 594 595 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 596 { 597 char ucode_prefix[15]; 598 int r; 599 600 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 601 602 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 603 if (r) 604 return r; 605 606 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 607 if (r) 608 return r; 609 610 return r; 611 } 612 613 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 614 { 615 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 616 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 617 } 618 619 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 620 { 621 int r, i, num_xcc; 622 u32 *hpd; 623 const __le32 *fw_data; 624 unsigned fw_size; 625 u32 *fw; 626 size_t mec_hpd_size; 627 628 const struct gfx_firmware_header_v1_0 *mec_hdr; 629 630 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 631 for (i = 0; i < num_xcc; i++) 632 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 633 AMDGPU_MAX_COMPUTE_QUEUES); 634 635 /* take ownership of the relevant compute queues */ 636 amdgpu_gfx_compute_queue_acquire(adev); 637 mec_hpd_size = 638 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 639 if (mec_hpd_size) { 640 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 641 AMDGPU_GEM_DOMAIN_VRAM | 642 AMDGPU_GEM_DOMAIN_GTT, 643 &adev->gfx.mec.hpd_eop_obj, 644 &adev->gfx.mec.hpd_eop_gpu_addr, 645 (void **)&hpd); 646 if (r) { 647 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 648 gfx_v9_4_3_mec_fini(adev); 649 return r; 650 } 651 652 if (amdgpu_emu_mode == 1) { 653 for (i = 0; i < mec_hpd_size / 4; i++) { 654 memset((void *)(hpd + i), 0, 4); 655 if (i % 50 == 0) 656 msleep(1); 657 } 658 } else { 659 memset(hpd, 0, mec_hpd_size); 660 } 661 662 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 663 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 664 } 665 666 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 667 668 fw_data = (const __le32 *) 669 (adev->gfx.mec_fw->data + 670 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 671 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 672 673 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 674 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 675 &adev->gfx.mec.mec_fw_obj, 676 &adev->gfx.mec.mec_fw_gpu_addr, 677 (void **)&fw); 678 if (r) { 679 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 680 gfx_v9_4_3_mec_fini(adev); 681 return r; 682 } 683 684 memcpy(fw, fw_data, fw_size); 685 686 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 687 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 688 689 return 0; 690 } 691 692 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 693 u32 sh_num, u32 instance, int xcc_id) 694 { 695 u32 data; 696 697 if (instance == 0xffffffff) 698 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 699 INSTANCE_BROADCAST_WRITES, 1); 700 else 701 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 702 INSTANCE_INDEX, instance); 703 704 if (se_num == 0xffffffff) 705 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 706 SE_BROADCAST_WRITES, 1); 707 else 708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 709 710 if (sh_num == 0xffffffff) 711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 712 SH_BROADCAST_WRITES, 1); 713 else 714 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 715 716 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 717 } 718 719 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 720 { 721 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 722 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 723 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 724 (address << SQ_IND_INDEX__INDEX__SHIFT) | 725 (SQ_IND_INDEX__FORCE_READ_MASK)); 726 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 727 } 728 729 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 730 uint32_t wave, uint32_t thread, 731 uint32_t regno, uint32_t num, uint32_t *out) 732 { 733 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 734 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 735 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 736 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 737 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 738 (SQ_IND_INDEX__FORCE_READ_MASK) | 739 (SQ_IND_INDEX__AUTO_INCR_MASK)); 740 while (num--) 741 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 742 } 743 744 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 745 uint32_t xcc_id, uint32_t simd, uint32_t wave, 746 uint32_t *dst, int *no_fields) 747 { 748 /* type 1 wave data */ 749 dst[(*no_fields)++] = 1; 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 761 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 762 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 763 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 764 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 765 } 766 767 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 768 uint32_t wave, uint32_t start, 769 uint32_t size, uint32_t *dst) 770 { 771 wave_read_regs(adev, xcc_id, simd, wave, 0, 772 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 773 } 774 775 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 776 uint32_t wave, uint32_t thread, 777 uint32_t start, uint32_t size, 778 uint32_t *dst) 779 { 780 wave_read_regs(adev, xcc_id, simd, wave, thread, 781 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 782 } 783 784 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 785 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 786 { 787 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 788 } 789 790 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 791 { 792 u32 xcp_ctl; 793 794 /* Value is expected to be the same on all, fetch from first instance */ 795 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 796 797 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 798 } 799 800 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 801 int num_xccs_per_xcp) 802 { 803 int ret, i, num_xcc; 804 u32 tmp = 0; 805 806 if (adev->psp.funcs) { 807 ret = psp_spatial_partition(&adev->psp, 808 NUM_XCC(adev->gfx.xcc_mask) / 809 num_xccs_per_xcp); 810 if (ret) 811 return ret; 812 } else { 813 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 814 815 for (i = 0; i < num_xcc; i++) { 816 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 817 num_xccs_per_xcp); 818 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 819 i % num_xccs_per_xcp); 820 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 821 tmp); 822 } 823 ret = 0; 824 } 825 826 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 827 828 return ret; 829 } 830 831 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 832 { 833 int xcc; 834 835 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 836 if (!xcc) { 837 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 838 return -EINVAL; 839 } 840 841 return xcc - 1; 842 } 843 844 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 845 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 846 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 847 .read_wave_data = &gfx_v9_4_3_read_wave_data, 848 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 849 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 850 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 851 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 852 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 853 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 854 }; 855 856 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 857 struct aca_bank *bank, enum aca_smu_type type, 858 void *data) 859 { 860 struct aca_bank_info info; 861 u64 misc0; 862 u32 instlo; 863 int ret; 864 865 ret = aca_bank_info_decode(bank, &info); 866 if (ret) 867 return ret; 868 869 /* NOTE: overwrite info.die_id with xcd id for gfx */ 870 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 871 instlo &= GENMASK(31, 1); 872 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 873 874 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 875 876 switch (type) { 877 case ACA_SMU_TYPE_UE: 878 ret = aca_error_cache_log_bank_error(handle, &info, 879 ACA_ERROR_TYPE_UE, 1ULL); 880 break; 881 case ACA_SMU_TYPE_CE: 882 ret = aca_error_cache_log_bank_error(handle, &info, 883 ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0)); 884 break; 885 default: 886 return -EINVAL; 887 } 888 889 return ret; 890 } 891 892 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 893 enum aca_smu_type type, void *data) 894 { 895 u32 instlo; 896 897 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 898 instlo &= GENMASK(31, 1); 899 switch (instlo) { 900 case mmSMNAID_XCD0_MCA_SMU: 901 case mmSMNAID_XCD1_MCA_SMU: 902 case mmSMNXCD_XCD0_MCA_SMU: 903 return true; 904 default: 905 break; 906 } 907 908 return false; 909 } 910 911 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 912 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 913 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 914 }; 915 916 static const struct aca_info gfx_v9_4_3_aca_info = { 917 .hwip = ACA_HWIP_TYPE_SMU, 918 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 919 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 920 }; 921 922 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 923 { 924 u32 gb_addr_config; 925 926 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 927 adev->gfx.ras = &gfx_v9_4_3_ras; 928 929 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 930 case IP_VERSION(9, 4, 3): 931 case IP_VERSION(9, 4, 4): 932 adev->gfx.config.max_hw_contexts = 8; 933 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 934 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 935 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 936 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 937 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 938 break; 939 default: 940 BUG(); 941 break; 942 } 943 944 adev->gfx.config.gb_addr_config = gb_addr_config; 945 946 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 947 REG_GET_FIELD( 948 adev->gfx.config.gb_addr_config, 949 GB_ADDR_CONFIG, 950 NUM_PIPES); 951 952 adev->gfx.config.max_tile_pipes = 953 adev->gfx.config.gb_addr_config_fields.num_pipes; 954 955 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 956 REG_GET_FIELD( 957 adev->gfx.config.gb_addr_config, 958 GB_ADDR_CONFIG, 959 NUM_BANKS); 960 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 961 REG_GET_FIELD( 962 adev->gfx.config.gb_addr_config, 963 GB_ADDR_CONFIG, 964 MAX_COMPRESSED_FRAGS); 965 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 966 REG_GET_FIELD( 967 adev->gfx.config.gb_addr_config, 968 GB_ADDR_CONFIG, 969 NUM_RB_PER_SE); 970 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 971 REG_GET_FIELD( 972 adev->gfx.config.gb_addr_config, 973 GB_ADDR_CONFIG, 974 NUM_SHADER_ENGINES); 975 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 976 REG_GET_FIELD( 977 adev->gfx.config.gb_addr_config, 978 GB_ADDR_CONFIG, 979 PIPE_INTERLEAVE_SIZE)); 980 981 return 0; 982 } 983 984 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 985 int xcc_id, int mec, int pipe, int queue) 986 { 987 unsigned irq_type; 988 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 989 unsigned int hw_prio; 990 uint32_t xcc_doorbell_start; 991 992 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 993 ring_id]; 994 995 /* mec0 is me1 */ 996 ring->xcc_id = xcc_id; 997 ring->me = mec + 1; 998 ring->pipe = pipe; 999 ring->queue = queue; 1000 1001 ring->ring_obj = NULL; 1002 ring->use_doorbell = true; 1003 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 1004 xcc_id * adev->doorbell_index.xcc_doorbell_range; 1005 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 1006 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 1007 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 1008 GFX9_MEC_HPD_SIZE; 1009 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1010 sprintf(ring->name, "comp_%d.%d.%d.%d", 1011 ring->xcc_id, ring->me, ring->pipe, ring->queue); 1012 1013 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1014 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1015 + ring->pipe; 1016 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1017 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1018 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1019 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1020 hw_prio, NULL); 1021 } 1022 1023 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1024 { 1025 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1026 uint32_t *ptr, num_xcc, inst; 1027 1028 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1029 1030 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1031 if (!ptr) { 1032 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1033 adev->gfx.ip_dump_core = NULL; 1034 } else { 1035 adev->gfx.ip_dump_core = ptr; 1036 } 1037 1038 /* Allocate memory for compute queue registers for all the instances */ 1039 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1040 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1041 adev->gfx.mec.num_queue_per_pipe; 1042 1043 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1044 if (!ptr) { 1045 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1046 adev->gfx.ip_dump_compute_queues = NULL; 1047 } else { 1048 adev->gfx.ip_dump_compute_queues = ptr; 1049 } 1050 } 1051 1052 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1053 { 1054 int i, j, k, r, ring_id, xcc_id, num_xcc; 1055 struct amdgpu_device *adev = ip_block->adev; 1056 1057 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1058 case IP_VERSION(9, 4, 3): 1059 case IP_VERSION(9, 4, 4): 1060 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1061 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1062 if (adev->gfx.mec_fw_version >= 153) { 1063 adev->gfx.enable_cleaner_shader = true; 1064 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1065 if (r) { 1066 adev->gfx.enable_cleaner_shader = false; 1067 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1068 } 1069 } 1070 break; 1071 default: 1072 adev->gfx.enable_cleaner_shader = false; 1073 break; 1074 } 1075 1076 adev->gfx.mec.num_mec = 2; 1077 adev->gfx.mec.num_pipe_per_mec = 4; 1078 adev->gfx.mec.num_queue_per_pipe = 8; 1079 1080 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1081 1082 /* EOP Event */ 1083 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1084 if (r) 1085 return r; 1086 1087 /* Bad opcode Event */ 1088 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1089 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1090 &adev->gfx.bad_op_irq); 1091 if (r) 1092 return r; 1093 1094 /* Privileged reg */ 1095 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1096 &adev->gfx.priv_reg_irq); 1097 if (r) 1098 return r; 1099 1100 /* Privileged inst */ 1101 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1102 &adev->gfx.priv_inst_irq); 1103 if (r) 1104 return r; 1105 1106 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1107 1108 r = adev->gfx.rlc.funcs->init(adev); 1109 if (r) { 1110 DRM_ERROR("Failed to init rlc BOs!\n"); 1111 return r; 1112 } 1113 1114 r = gfx_v9_4_3_mec_init(adev); 1115 if (r) { 1116 DRM_ERROR("Failed to init MEC BOs!\n"); 1117 return r; 1118 } 1119 1120 /* set up the compute queues - allocate horizontally across pipes */ 1121 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1122 ring_id = 0; 1123 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1124 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1125 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1126 k++) { 1127 if (!amdgpu_gfx_is_mec_queue_enabled( 1128 adev, xcc_id, i, k, j)) 1129 continue; 1130 1131 r = gfx_v9_4_3_compute_ring_init(adev, 1132 ring_id, 1133 xcc_id, 1134 i, k, j); 1135 if (r) 1136 return r; 1137 1138 ring_id++; 1139 } 1140 } 1141 } 1142 1143 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1144 if (r) { 1145 DRM_ERROR("Failed to init KIQ BOs!\n"); 1146 return r; 1147 } 1148 1149 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1150 if (r) 1151 return r; 1152 1153 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1154 r = amdgpu_gfx_mqd_sw_init(adev, 1155 sizeof(struct v9_mqd_allocation), xcc_id); 1156 if (r) 1157 return r; 1158 } 1159 1160 r = gfx_v9_4_3_gpu_early_init(adev); 1161 if (r) 1162 return r; 1163 1164 r = amdgpu_gfx_ras_sw_init(adev); 1165 if (r) 1166 return r; 1167 1168 r = amdgpu_gfx_sysfs_init(adev); 1169 if (r) 1170 return r; 1171 1172 gfx_v9_4_3_alloc_ip_dump(adev); 1173 1174 r = amdgpu_gfx_sysfs_isolation_shader_init(adev); 1175 if (r) 1176 return r; 1177 1178 return 0; 1179 } 1180 1181 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1182 { 1183 int i, num_xcc; 1184 struct amdgpu_device *adev = ip_block->adev; 1185 1186 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1187 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1188 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1189 1190 for (i = 0; i < num_xcc; i++) { 1191 amdgpu_gfx_mqd_sw_fini(adev, i); 1192 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1193 amdgpu_gfx_kiq_fini(adev, i); 1194 } 1195 1196 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1197 1198 gfx_v9_4_3_mec_fini(adev); 1199 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1200 gfx_v9_4_3_free_microcode(adev); 1201 amdgpu_gfx_sysfs_fini(adev); 1202 amdgpu_gfx_sysfs_isolation_shader_fini(adev); 1203 1204 kfree(adev->gfx.ip_dump_core); 1205 kfree(adev->gfx.ip_dump_compute_queues); 1206 1207 return 0; 1208 } 1209 1210 #define DEFAULT_SH_MEM_BASES (0x6000) 1211 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1212 int xcc_id) 1213 { 1214 int i; 1215 uint32_t sh_mem_config; 1216 uint32_t sh_mem_bases; 1217 uint32_t data; 1218 1219 /* 1220 * Configure apertures: 1221 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1222 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1223 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1224 */ 1225 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1226 1227 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1228 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1229 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1230 1231 mutex_lock(&adev->srbm_mutex); 1232 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1233 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1234 /* CP and shaders */ 1235 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1236 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1237 1238 /* Enable trap for each kfd vmid. */ 1239 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1240 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1241 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1242 } 1243 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1244 mutex_unlock(&adev->srbm_mutex); 1245 1246 /* 1247 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1248 * access. These should be enabled by FW for target VMIDs. 1249 */ 1250 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1251 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1252 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1253 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1254 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1255 } 1256 } 1257 1258 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1259 { 1260 int vmid; 1261 1262 /* 1263 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1264 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1265 * the driver can enable them for graphics. VMID0 should maintain 1266 * access so that HWS firmware can save/restore entries. 1267 */ 1268 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1269 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1270 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1271 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1272 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1273 } 1274 } 1275 1276 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1277 int xcc_id) 1278 { 1279 u32 tmp; 1280 int i; 1281 1282 /* XXX SH_MEM regs */ 1283 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1284 mutex_lock(&adev->srbm_mutex); 1285 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1286 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1287 /* CP and shaders */ 1288 if (i == 0) { 1289 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1290 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1291 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1292 !!adev->gmc.noretry); 1293 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1294 regSH_MEM_CONFIG, tmp); 1295 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1296 regSH_MEM_BASES, 0); 1297 } else { 1298 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1299 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1300 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1301 !!adev->gmc.noretry); 1302 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1303 regSH_MEM_CONFIG, tmp); 1304 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1305 (adev->gmc.private_aperture_start >> 1306 48)); 1307 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1308 (adev->gmc.shared_aperture_start >> 1309 48)); 1310 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1311 regSH_MEM_BASES, tmp); 1312 } 1313 } 1314 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1315 1316 mutex_unlock(&adev->srbm_mutex); 1317 1318 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1319 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1320 } 1321 1322 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1323 { 1324 int i, num_xcc; 1325 1326 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1327 1328 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1329 adev->gfx.config.db_debug2 = 1330 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1331 1332 for (i = 0; i < num_xcc; i++) 1333 gfx_v9_4_3_xcc_constants_init(adev, i); 1334 } 1335 1336 static void 1337 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1338 int xcc_id) 1339 { 1340 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1341 } 1342 1343 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1344 { 1345 /* 1346 * Rlc save restore list is workable since v2_1. 1347 * And it's needed by gfxoff feature. 1348 */ 1349 if (adev->gfx.rlc.is_rlc_v2_1) 1350 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1351 } 1352 1353 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1354 { 1355 uint32_t data; 1356 1357 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1358 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1359 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1360 } 1361 1362 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1363 { 1364 uint32_t rlc_setting; 1365 1366 /* if RLC is not enabled, do nothing */ 1367 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1368 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1369 return false; 1370 1371 return true; 1372 } 1373 1374 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1375 { 1376 uint32_t data; 1377 unsigned i; 1378 1379 data = RLC_SAFE_MODE__CMD_MASK; 1380 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1381 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1382 1383 /* wait for RLC_SAFE_MODE */ 1384 for (i = 0; i < adev->usec_timeout; i++) { 1385 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1386 break; 1387 udelay(1); 1388 } 1389 } 1390 1391 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1392 int xcc_id) 1393 { 1394 uint32_t data; 1395 1396 data = RLC_SAFE_MODE__CMD_MASK; 1397 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1398 } 1399 1400 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1401 { 1402 int xcc_id, num_xcc; 1403 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1404 1405 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1406 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1407 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1408 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1409 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1410 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1411 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1412 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1413 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1414 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1415 } 1416 adev->gfx.rlc.rlcg_reg_access_supported = true; 1417 } 1418 1419 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1420 { 1421 /* init spm vmid with 0xf */ 1422 if (adev->gfx.rlc.funcs->update_spm_vmid) 1423 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1424 1425 return 0; 1426 } 1427 1428 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1429 int xcc_id) 1430 { 1431 u32 i, j, k; 1432 u32 mask; 1433 1434 mutex_lock(&adev->grbm_idx_mutex); 1435 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1436 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1437 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1438 xcc_id); 1439 for (k = 0; k < adev->usec_timeout; k++) { 1440 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1441 break; 1442 udelay(1); 1443 } 1444 if (k == adev->usec_timeout) { 1445 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1446 0xffffffff, 1447 0xffffffff, xcc_id); 1448 mutex_unlock(&adev->grbm_idx_mutex); 1449 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1450 i, j); 1451 return; 1452 } 1453 } 1454 } 1455 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1456 xcc_id); 1457 mutex_unlock(&adev->grbm_idx_mutex); 1458 1459 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1460 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1461 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1462 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1463 for (k = 0; k < adev->usec_timeout; k++) { 1464 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1465 break; 1466 udelay(1); 1467 } 1468 } 1469 1470 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1471 bool enable, int xcc_id) 1472 { 1473 u32 tmp; 1474 1475 /* These interrupts should be enabled to drive DS clock */ 1476 1477 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1478 1479 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1480 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1481 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1482 1483 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1484 } 1485 1486 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1487 { 1488 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1489 RLC_ENABLE_F32, 0); 1490 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1491 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1492 } 1493 1494 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1495 { 1496 int i, num_xcc; 1497 1498 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1499 for (i = 0; i < num_xcc; i++) 1500 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1501 } 1502 1503 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1504 { 1505 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1506 SOFT_RESET_RLC, 1); 1507 udelay(50); 1508 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1509 SOFT_RESET_RLC, 0); 1510 udelay(50); 1511 } 1512 1513 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1514 { 1515 int i, num_xcc; 1516 1517 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1518 for (i = 0; i < num_xcc; i++) 1519 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1520 } 1521 1522 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1523 { 1524 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1525 RLC_ENABLE_F32, 1); 1526 udelay(50); 1527 1528 /* carrizo do enable cp interrupt after cp inited */ 1529 if (!(adev->flags & AMD_IS_APU)) { 1530 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1531 udelay(50); 1532 } 1533 } 1534 1535 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1536 { 1537 #ifdef AMDGPU_RLC_DEBUG_RETRY 1538 u32 rlc_ucode_ver; 1539 #endif 1540 int i, num_xcc; 1541 1542 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1543 for (i = 0; i < num_xcc; i++) { 1544 gfx_v9_4_3_xcc_rlc_start(adev, i); 1545 #ifdef AMDGPU_RLC_DEBUG_RETRY 1546 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1547 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1548 if (rlc_ucode_ver == 0x108) { 1549 dev_info(adev->dev, 1550 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1551 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1552 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1553 * default is 0x9C4 to create a 100us interval */ 1554 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1555 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1556 * to disable the page fault retry interrupts, default is 1557 * 0x100 (256) */ 1558 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1559 } 1560 #endif 1561 } 1562 } 1563 1564 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1565 int xcc_id) 1566 { 1567 const struct rlc_firmware_header_v2_0 *hdr; 1568 const __le32 *fw_data; 1569 unsigned i, fw_size; 1570 1571 if (!adev->gfx.rlc_fw) 1572 return -EINVAL; 1573 1574 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1575 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1576 1577 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1578 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1579 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1580 1581 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1582 RLCG_UCODE_LOADING_START_ADDRESS); 1583 for (i = 0; i < fw_size; i++) { 1584 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1585 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1586 msleep(1); 1587 } 1588 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1589 } 1590 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1591 1592 return 0; 1593 } 1594 1595 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1596 { 1597 int r; 1598 1599 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1600 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1601 /* legacy rlc firmware loading */ 1602 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1603 if (r) 1604 return r; 1605 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1606 } 1607 1608 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1609 /* disable CG */ 1610 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1611 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1612 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1613 1614 return 0; 1615 } 1616 1617 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1618 { 1619 int r, i, num_xcc; 1620 1621 if (amdgpu_sriov_vf(adev)) 1622 return 0; 1623 1624 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1625 for (i = 0; i < num_xcc; i++) { 1626 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1627 if (r) 1628 return r; 1629 } 1630 1631 return 0; 1632 } 1633 1634 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1635 unsigned vmid) 1636 { 1637 u32 reg, pre_data, data; 1638 1639 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1640 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1641 pre_data = RREG32_NO_KIQ(reg); 1642 else 1643 pre_data = RREG32(reg); 1644 1645 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1646 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1647 1648 if (pre_data != data) { 1649 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1650 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1651 } else 1652 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1653 } 1654 } 1655 1656 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1657 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1658 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1659 }; 1660 1661 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1662 uint32_t offset, 1663 struct soc15_reg_rlcg *entries, int arr_size) 1664 { 1665 int i, inst; 1666 uint32_t reg; 1667 1668 if (!entries) 1669 return false; 1670 1671 for (i = 0; i < arr_size; i++) { 1672 const struct soc15_reg_rlcg *entry; 1673 1674 entry = &entries[i]; 1675 inst = adev->ip_map.logical_to_dev_inst ? 1676 adev->ip_map.logical_to_dev_inst( 1677 adev, entry->hwip, entry->instance) : 1678 entry->instance; 1679 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1680 entry->reg; 1681 if (offset == reg) 1682 return true; 1683 } 1684 1685 return false; 1686 } 1687 1688 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1689 { 1690 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1691 (void *)rlcg_access_gc_9_4_3, 1692 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1693 } 1694 1695 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1696 bool enable, int xcc_id) 1697 { 1698 if (enable) { 1699 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1700 } else { 1701 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1702 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1703 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1704 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1705 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1706 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1707 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1708 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1709 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1710 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1711 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1712 } 1713 udelay(50); 1714 } 1715 1716 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1717 int xcc_id) 1718 { 1719 const struct gfx_firmware_header_v1_0 *mec_hdr; 1720 const __le32 *fw_data; 1721 unsigned i; 1722 u32 tmp; 1723 u32 mec_ucode_addr_offset; 1724 u32 mec_ucode_data_offset; 1725 1726 if (!adev->gfx.mec_fw) 1727 return -EINVAL; 1728 1729 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1730 1731 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1732 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1733 1734 fw_data = (const __le32 *) 1735 (adev->gfx.mec_fw->data + 1736 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1737 tmp = 0; 1738 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1739 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1740 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1741 1742 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1743 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1744 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1745 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1746 1747 mec_ucode_addr_offset = 1748 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1749 mec_ucode_data_offset = 1750 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1751 1752 /* MEC1 */ 1753 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1754 for (i = 0; i < mec_hdr->jt_size; i++) 1755 WREG32(mec_ucode_data_offset, 1756 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1757 1758 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1759 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1760 1761 return 0; 1762 } 1763 1764 /* KIQ functions */ 1765 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1766 { 1767 uint32_t tmp; 1768 struct amdgpu_device *adev = ring->adev; 1769 1770 /* tell RLC which is KIQ queue */ 1771 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1772 tmp &= 0xffffff00; 1773 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1774 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1775 tmp |= 0x80; 1776 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1777 } 1778 1779 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1780 { 1781 struct amdgpu_device *adev = ring->adev; 1782 1783 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1784 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1785 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1786 mqd->cp_hqd_queue_priority = 1787 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1788 } 1789 } 1790 } 1791 1792 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1793 { 1794 struct amdgpu_device *adev = ring->adev; 1795 struct v9_mqd *mqd = ring->mqd_ptr; 1796 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1797 uint32_t tmp; 1798 1799 mqd->header = 0xC0310800; 1800 mqd->compute_pipelinestat_enable = 0x00000001; 1801 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1802 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1803 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1804 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1805 mqd->compute_misc_reserved = 0x00000003; 1806 1807 mqd->dynamic_cu_mask_addr_lo = 1808 lower_32_bits(ring->mqd_gpu_addr 1809 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1810 mqd->dynamic_cu_mask_addr_hi = 1811 upper_32_bits(ring->mqd_gpu_addr 1812 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1813 1814 eop_base_addr = ring->eop_gpu_addr >> 8; 1815 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1816 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1817 1818 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1819 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1820 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1821 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1822 1823 mqd->cp_hqd_eop_control = tmp; 1824 1825 /* enable doorbell? */ 1826 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1827 1828 if (ring->use_doorbell) { 1829 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1830 DOORBELL_OFFSET, ring->doorbell_index); 1831 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1832 DOORBELL_EN, 1); 1833 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1834 DOORBELL_SOURCE, 0); 1835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1836 DOORBELL_HIT, 0); 1837 if (amdgpu_sriov_vf(adev)) 1838 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1839 DOORBELL_MODE, 1); 1840 } else { 1841 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1842 DOORBELL_EN, 0); 1843 } 1844 1845 mqd->cp_hqd_pq_doorbell_control = tmp; 1846 1847 /* disable the queue if it's active */ 1848 ring->wptr = 0; 1849 mqd->cp_hqd_dequeue_request = 0; 1850 mqd->cp_hqd_pq_rptr = 0; 1851 mqd->cp_hqd_pq_wptr_lo = 0; 1852 mqd->cp_hqd_pq_wptr_hi = 0; 1853 1854 /* set the pointer to the MQD */ 1855 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1856 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1857 1858 /* set MQD vmid to 0 */ 1859 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1860 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1861 mqd->cp_mqd_control = tmp; 1862 1863 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1864 hqd_gpu_addr = ring->gpu_addr >> 8; 1865 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1866 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1867 1868 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1869 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1870 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1871 (order_base_2(ring->ring_size / 4) - 1)); 1872 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1873 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1874 #ifdef __BIG_ENDIAN 1875 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1876 #endif 1877 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1878 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1879 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1880 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1881 mqd->cp_hqd_pq_control = tmp; 1882 1883 /* set the wb address whether it's enabled or not */ 1884 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1885 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1886 mqd->cp_hqd_pq_rptr_report_addr_hi = 1887 upper_32_bits(wb_gpu_addr) & 0xffff; 1888 1889 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1890 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1891 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1892 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1893 1894 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1895 ring->wptr = 0; 1896 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1897 1898 /* set the vmid for the queue */ 1899 mqd->cp_hqd_vmid = 0; 1900 1901 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1902 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1903 mqd->cp_hqd_persistent_state = tmp; 1904 1905 /* set MIN_IB_AVAIL_SIZE */ 1906 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1907 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1908 mqd->cp_hqd_ib_control = tmp; 1909 1910 /* set static priority for a queue/ring */ 1911 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1912 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1913 1914 /* map_queues packet doesn't need activate the queue, 1915 * so only kiq need set this field. 1916 */ 1917 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1918 mqd->cp_hqd_active = 1; 1919 1920 return 0; 1921 } 1922 1923 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1924 int xcc_id) 1925 { 1926 struct amdgpu_device *adev = ring->adev; 1927 struct v9_mqd *mqd = ring->mqd_ptr; 1928 int j; 1929 1930 /* disable wptr polling */ 1931 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1932 1933 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1934 mqd->cp_hqd_eop_base_addr_lo); 1935 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1936 mqd->cp_hqd_eop_base_addr_hi); 1937 1938 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1939 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1940 mqd->cp_hqd_eop_control); 1941 1942 /* enable doorbell? */ 1943 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1944 mqd->cp_hqd_pq_doorbell_control); 1945 1946 /* disable the queue if it's active */ 1947 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1948 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1949 for (j = 0; j < adev->usec_timeout; j++) { 1950 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1951 break; 1952 udelay(1); 1953 } 1954 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1955 mqd->cp_hqd_dequeue_request); 1956 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1957 mqd->cp_hqd_pq_rptr); 1958 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1959 mqd->cp_hqd_pq_wptr_lo); 1960 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1961 mqd->cp_hqd_pq_wptr_hi); 1962 } 1963 1964 /* set the pointer to the MQD */ 1965 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1966 mqd->cp_mqd_base_addr_lo); 1967 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1968 mqd->cp_mqd_base_addr_hi); 1969 1970 /* set MQD vmid to 0 */ 1971 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1972 mqd->cp_mqd_control); 1973 1974 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1975 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1976 mqd->cp_hqd_pq_base_lo); 1977 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1978 mqd->cp_hqd_pq_base_hi); 1979 1980 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1981 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1982 mqd->cp_hqd_pq_control); 1983 1984 /* set the wb address whether it's enabled or not */ 1985 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1986 mqd->cp_hqd_pq_rptr_report_addr_lo); 1987 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1988 mqd->cp_hqd_pq_rptr_report_addr_hi); 1989 1990 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1991 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1992 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1993 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1994 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1995 1996 /* enable the doorbell if requested */ 1997 if (ring->use_doorbell) { 1998 WREG32_SOC15( 1999 GC, GET_INST(GC, xcc_id), 2000 regCP_MEC_DOORBELL_RANGE_LOWER, 2001 ((adev->doorbell_index.kiq + 2002 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2003 2) << 2); 2004 WREG32_SOC15( 2005 GC, GET_INST(GC, xcc_id), 2006 regCP_MEC_DOORBELL_RANGE_UPPER, 2007 ((adev->doorbell_index.userqueue_end + 2008 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2009 2) << 2); 2010 } 2011 2012 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2013 mqd->cp_hqd_pq_doorbell_control); 2014 2015 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2016 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2017 mqd->cp_hqd_pq_wptr_lo); 2018 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2019 mqd->cp_hqd_pq_wptr_hi); 2020 2021 /* set the vmid for the queue */ 2022 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2023 2024 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2025 mqd->cp_hqd_persistent_state); 2026 2027 /* activate the queue */ 2028 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2029 mqd->cp_hqd_active); 2030 2031 if (ring->use_doorbell) 2032 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2033 2034 return 0; 2035 } 2036 2037 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2038 int xcc_id) 2039 { 2040 struct amdgpu_device *adev = ring->adev; 2041 int j; 2042 2043 /* disable the queue if it's active */ 2044 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2045 2046 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2047 2048 for (j = 0; j < adev->usec_timeout; j++) { 2049 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2050 break; 2051 udelay(1); 2052 } 2053 2054 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2055 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2056 2057 /* Manual disable if dequeue request times out */ 2058 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2059 } 2060 2061 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2062 0); 2063 } 2064 2065 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2066 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2067 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2068 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2069 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2070 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2071 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2072 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2073 2074 return 0; 2075 } 2076 2077 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2078 { 2079 struct amdgpu_device *adev = ring->adev; 2080 struct v9_mqd *mqd = ring->mqd_ptr; 2081 struct v9_mqd *tmp_mqd; 2082 2083 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2084 2085 /* GPU could be in bad state during probe, driver trigger the reset 2086 * after load the SMU, in this case , the mqd is not be initialized. 2087 * driver need to re-init the mqd. 2088 * check mqd->cp_hqd_pq_control since this value should not be 0 2089 */ 2090 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2091 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2092 /* for GPU_RESET case , reset MQD to a clean status */ 2093 if (adev->gfx.kiq[xcc_id].mqd_backup) 2094 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2095 2096 /* reset ring buffer */ 2097 ring->wptr = 0; 2098 amdgpu_ring_clear_ring(ring); 2099 mutex_lock(&adev->srbm_mutex); 2100 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2101 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2102 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2103 mutex_unlock(&adev->srbm_mutex); 2104 } else { 2105 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2106 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2107 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2108 mutex_lock(&adev->srbm_mutex); 2109 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2110 amdgpu_ring_clear_ring(ring); 2111 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2112 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2113 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2114 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2115 mutex_unlock(&adev->srbm_mutex); 2116 2117 if (adev->gfx.kiq[xcc_id].mqd_backup) 2118 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2119 } 2120 2121 return 0; 2122 } 2123 2124 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) 2125 { 2126 struct amdgpu_device *adev = ring->adev; 2127 struct v9_mqd *mqd = ring->mqd_ptr; 2128 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2129 struct v9_mqd *tmp_mqd; 2130 2131 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2132 * is not be initialized before 2133 */ 2134 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2135 2136 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2137 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2138 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2139 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2140 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2141 mutex_lock(&adev->srbm_mutex); 2142 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2143 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2144 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2145 mutex_unlock(&adev->srbm_mutex); 2146 2147 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2148 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2149 } else { 2150 /* restore MQD to a clean status */ 2151 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2152 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2153 /* reset ring buffer */ 2154 ring->wptr = 0; 2155 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2156 amdgpu_ring_clear_ring(ring); 2157 } 2158 2159 return 0; 2160 } 2161 2162 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2163 { 2164 struct amdgpu_ring *ring; 2165 int j; 2166 2167 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2168 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2169 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2170 mutex_lock(&adev->srbm_mutex); 2171 soc15_grbm_select(adev, ring->me, 2172 ring->pipe, 2173 ring->queue, 0, GET_INST(GC, xcc_id)); 2174 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2175 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2176 mutex_unlock(&adev->srbm_mutex); 2177 } 2178 } 2179 2180 return 0; 2181 } 2182 2183 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2184 { 2185 struct amdgpu_ring *ring; 2186 int r; 2187 2188 ring = &adev->gfx.kiq[xcc_id].ring; 2189 2190 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2191 if (unlikely(r != 0)) 2192 return r; 2193 2194 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2195 if (unlikely(r != 0)) { 2196 amdgpu_bo_unreserve(ring->mqd_obj); 2197 return r; 2198 } 2199 2200 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 2201 amdgpu_bo_kunmap(ring->mqd_obj); 2202 ring->mqd_ptr = NULL; 2203 amdgpu_bo_unreserve(ring->mqd_obj); 2204 return 0; 2205 } 2206 2207 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2208 { 2209 struct amdgpu_ring *ring = NULL; 2210 int r = 0, i; 2211 2212 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2213 2214 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2215 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2216 2217 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2218 if (unlikely(r != 0)) 2219 goto done; 2220 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2221 if (!r) { 2222 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2223 amdgpu_bo_kunmap(ring->mqd_obj); 2224 ring->mqd_ptr = NULL; 2225 } 2226 amdgpu_bo_unreserve(ring->mqd_obj); 2227 if (r) 2228 goto done; 2229 } 2230 2231 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2232 done: 2233 return r; 2234 } 2235 2236 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2237 { 2238 struct amdgpu_ring *ring; 2239 int r, j; 2240 2241 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2242 2243 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2244 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2245 2246 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2247 if (r) 2248 return r; 2249 } else { 2250 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2251 } 2252 2253 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2254 if (r) 2255 return r; 2256 2257 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2258 if (r) 2259 return r; 2260 2261 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2262 ring = &adev->gfx.compute_ring 2263 [j + xcc_id * adev->gfx.num_compute_rings]; 2264 r = amdgpu_ring_test_helper(ring); 2265 if (r) 2266 return r; 2267 } 2268 2269 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2270 2271 return 0; 2272 } 2273 2274 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2275 { 2276 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2277 2278 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2279 if (amdgpu_sriov_vf(adev)) { 2280 enum amdgpu_gfx_partition mode; 2281 2282 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2283 AMDGPU_XCP_FL_NONE); 2284 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2285 return -EINVAL; 2286 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2287 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2288 num_xcp = num_xcc / num_xcc_per_xcp; 2289 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2290 2291 } else { 2292 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2293 AMDGPU_XCP_FL_NONE) == 2294 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2295 r = amdgpu_xcp_switch_partition_mode( 2296 adev->xcp_mgr, amdgpu_user_partt_mode); 2297 } 2298 if (r) 2299 return r; 2300 2301 for (i = 0; i < num_xcc; i++) { 2302 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2303 if (r) 2304 return r; 2305 } 2306 2307 return 0; 2308 } 2309 2310 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2311 { 2312 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2313 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2314 2315 if (amdgpu_sriov_vf(adev)) { 2316 /* must disable polling for SRIOV when hw finished, otherwise 2317 * CPC engine may still keep fetching WB address which is already 2318 * invalid after sw finished and trigger DMAR reading error in 2319 * hypervisor side. 2320 */ 2321 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2322 return; 2323 } 2324 2325 /* Use deinitialize sequence from CAIL when unbinding device 2326 * from driver, otherwise KIQ is hanging when binding back 2327 */ 2328 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2329 mutex_lock(&adev->srbm_mutex); 2330 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2331 adev->gfx.kiq[xcc_id].ring.pipe, 2332 adev->gfx.kiq[xcc_id].ring.queue, 0, 2333 GET_INST(GC, xcc_id)); 2334 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2335 xcc_id); 2336 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2337 mutex_unlock(&adev->srbm_mutex); 2338 } 2339 2340 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2341 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2342 } 2343 2344 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2345 { 2346 int r; 2347 struct amdgpu_device *adev = ip_block->adev; 2348 2349 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2350 adev->gfx.cleaner_shader_ptr); 2351 2352 if (!amdgpu_sriov_vf(adev)) 2353 gfx_v9_4_3_init_golden_registers(adev); 2354 2355 gfx_v9_4_3_constants_init(adev); 2356 2357 r = adev->gfx.rlc.funcs->resume(adev); 2358 if (r) 2359 return r; 2360 2361 r = gfx_v9_4_3_cp_resume(adev); 2362 if (r) 2363 return r; 2364 2365 return r; 2366 } 2367 2368 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2369 { 2370 struct amdgpu_device *adev = ip_block->adev; 2371 int i, num_xcc; 2372 2373 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2374 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2375 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2376 2377 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2378 for (i = 0; i < num_xcc; i++) { 2379 gfx_v9_4_3_xcc_fini(adev, i); 2380 } 2381 2382 return 0; 2383 } 2384 2385 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2386 { 2387 return gfx_v9_4_3_hw_fini(ip_block); 2388 } 2389 2390 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2391 { 2392 return gfx_v9_4_3_hw_init(ip_block); 2393 } 2394 2395 static bool gfx_v9_4_3_is_idle(void *handle) 2396 { 2397 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2398 int i, num_xcc; 2399 2400 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2401 for (i = 0; i < num_xcc; i++) { 2402 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2403 GRBM_STATUS, GUI_ACTIVE)) 2404 return false; 2405 } 2406 return true; 2407 } 2408 2409 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2410 { 2411 unsigned i; 2412 struct amdgpu_device *adev = ip_block->adev; 2413 2414 for (i = 0; i < adev->usec_timeout; i++) { 2415 if (gfx_v9_4_3_is_idle(adev)) 2416 return 0; 2417 udelay(1); 2418 } 2419 return -ETIMEDOUT; 2420 } 2421 2422 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2423 { 2424 u32 grbm_soft_reset = 0; 2425 u32 tmp; 2426 struct amdgpu_device *adev = ip_block->adev; 2427 2428 /* GRBM_STATUS */ 2429 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2430 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2431 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2432 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2433 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2434 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2435 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2436 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2437 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2438 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2439 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2440 } 2441 2442 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2443 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2444 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2445 } 2446 2447 /* GRBM_STATUS2 */ 2448 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2449 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2450 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2451 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2452 2453 2454 if (grbm_soft_reset) { 2455 /* stop the rlc */ 2456 adev->gfx.rlc.funcs->stop(adev); 2457 2458 /* Disable MEC parsing/prefetching */ 2459 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2460 2461 if (grbm_soft_reset) { 2462 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2463 tmp |= grbm_soft_reset; 2464 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2465 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2466 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2467 2468 udelay(50); 2469 2470 tmp &= ~grbm_soft_reset; 2471 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2472 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2473 } 2474 2475 /* Wait a little for things to settle down */ 2476 udelay(50); 2477 } 2478 return 0; 2479 } 2480 2481 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2482 uint32_t vmid, 2483 uint32_t gds_base, uint32_t gds_size, 2484 uint32_t gws_base, uint32_t gws_size, 2485 uint32_t oa_base, uint32_t oa_size) 2486 { 2487 struct amdgpu_device *adev = ring->adev; 2488 2489 /* GDS Base */ 2490 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2491 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2492 gds_base); 2493 2494 /* GDS Size */ 2495 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2496 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2497 gds_size); 2498 2499 /* GWS */ 2500 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2501 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2502 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2503 2504 /* OA */ 2505 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2506 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2507 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2508 } 2509 2510 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2511 { 2512 struct amdgpu_device *adev = ip_block->adev; 2513 2514 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2515 AMDGPU_MAX_COMPUTE_RINGS); 2516 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2517 gfx_v9_4_3_set_ring_funcs(adev); 2518 gfx_v9_4_3_set_irq_funcs(adev); 2519 gfx_v9_4_3_set_gds_init(adev); 2520 gfx_v9_4_3_set_rlc_funcs(adev); 2521 2522 /* init rlcg reg access ctrl */ 2523 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2524 2525 return gfx_v9_4_3_init_microcode(adev); 2526 } 2527 2528 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2529 { 2530 struct amdgpu_device *adev = ip_block->adev; 2531 int r; 2532 2533 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2534 if (r) 2535 return r; 2536 2537 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2538 if (r) 2539 return r; 2540 2541 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2542 if (r) 2543 return r; 2544 2545 if (adev->gfx.ras && 2546 adev->gfx.ras->enable_watchdog_timer) 2547 adev->gfx.ras->enable_watchdog_timer(adev); 2548 2549 return 0; 2550 } 2551 2552 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2553 bool enable, int xcc_id) 2554 { 2555 uint32_t def, data; 2556 2557 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2558 return; 2559 2560 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2561 regRLC_CGTT_MGCG_OVERRIDE); 2562 2563 if (enable) 2564 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2565 else 2566 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2567 2568 if (def != data) 2569 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2570 regRLC_CGTT_MGCG_OVERRIDE, data); 2571 2572 } 2573 2574 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2575 bool enable, int xcc_id) 2576 { 2577 uint32_t def, data; 2578 2579 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2580 return; 2581 2582 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2583 regRLC_CGTT_MGCG_OVERRIDE); 2584 2585 if (enable) 2586 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2587 else 2588 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2589 2590 if (def != data) 2591 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2592 regRLC_CGTT_MGCG_OVERRIDE, data); 2593 } 2594 2595 static void 2596 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2597 bool enable, int xcc_id) 2598 { 2599 uint32_t data, def; 2600 2601 /* It is disabled by HW by default */ 2602 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2603 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2604 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2605 2606 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2607 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2608 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2609 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2610 2611 if (def != data) 2612 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2613 2614 /* MGLS is a global flag to control all MGLS in GFX */ 2615 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2616 /* 2 - RLC memory Light sleep */ 2617 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2618 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2619 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2620 if (def != data) 2621 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2622 } 2623 /* 3 - CP memory Light sleep */ 2624 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2625 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2626 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2627 if (def != data) 2628 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2629 } 2630 } 2631 } else { 2632 /* 1 - MGCG_OVERRIDE */ 2633 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2634 2635 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2636 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2637 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2638 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2639 2640 if (def != data) 2641 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2642 2643 /* 2 - disable MGLS in RLC */ 2644 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2645 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2646 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2647 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2648 } 2649 2650 /* 3 - disable MGLS in CP */ 2651 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2652 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2653 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2654 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2655 } 2656 } 2657 2658 } 2659 2660 static void 2661 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2662 bool enable, int xcc_id) 2663 { 2664 uint32_t def, data; 2665 2666 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2667 2668 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2669 /* unset CGCG override */ 2670 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2671 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2672 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2673 else 2674 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2675 /* update CGCG and CGLS override bits */ 2676 if (def != data) 2677 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2678 2679 /* CGCG Hysteresis: 400us */ 2680 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2681 2682 data = (0x2710 2683 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2684 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2685 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2686 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2687 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2688 if (def != data) 2689 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2690 2691 /* set IDLE_POLL_COUNT(0x33450100)*/ 2692 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2693 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2694 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2695 if (def != data) 2696 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2697 } else { 2698 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2699 /* reset CGCG/CGLS bits */ 2700 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2701 /* disable cgcg and cgls in FSM */ 2702 if (def != data) 2703 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2704 } 2705 2706 } 2707 2708 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2709 bool enable, int xcc_id) 2710 { 2711 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2712 2713 if (enable) { 2714 /* FGCG */ 2715 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2716 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2717 2718 /* CGCG/CGLS should be enabled after MGCG/MGLS 2719 * === MGCG + MGLS === 2720 */ 2721 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2722 xcc_id); 2723 /* === CGCG + CGLS === */ 2724 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2725 xcc_id); 2726 } else { 2727 /* CGCG/CGLS should be disabled before MGCG/MGLS 2728 * === CGCG + CGLS === 2729 */ 2730 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2731 xcc_id); 2732 /* === MGCG + MGLS === */ 2733 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2734 xcc_id); 2735 2736 /* FGCG */ 2737 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2738 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2739 } 2740 2741 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2742 2743 return 0; 2744 } 2745 2746 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2747 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2748 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2749 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2750 .init = gfx_v9_4_3_rlc_init, 2751 .resume = gfx_v9_4_3_rlc_resume, 2752 .stop = gfx_v9_4_3_rlc_stop, 2753 .reset = gfx_v9_4_3_rlc_reset, 2754 .start = gfx_v9_4_3_rlc_start, 2755 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2756 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2757 }; 2758 2759 static int gfx_v9_4_3_set_powergating_state(void *handle, 2760 enum amd_powergating_state state) 2761 { 2762 return 0; 2763 } 2764 2765 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2766 enum amd_clockgating_state state) 2767 { 2768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2769 int i, num_xcc; 2770 2771 if (amdgpu_sriov_vf(adev)) 2772 return 0; 2773 2774 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2775 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2776 case IP_VERSION(9, 4, 3): 2777 case IP_VERSION(9, 4, 4): 2778 for (i = 0; i < num_xcc; i++) 2779 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2780 adev, state == AMD_CG_STATE_GATE, i); 2781 break; 2782 default: 2783 break; 2784 } 2785 return 0; 2786 } 2787 2788 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2789 { 2790 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2791 int data; 2792 2793 if (amdgpu_sriov_vf(adev)) 2794 *flags = 0; 2795 2796 /* AMD_CG_SUPPORT_GFX_MGCG */ 2797 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2798 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2799 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2800 2801 /* AMD_CG_SUPPORT_GFX_CGCG */ 2802 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2803 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2804 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2805 2806 /* AMD_CG_SUPPORT_GFX_CGLS */ 2807 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2808 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2809 2810 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2811 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2812 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2813 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2814 2815 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2816 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2817 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2818 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2819 } 2820 2821 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2822 { 2823 struct amdgpu_device *adev = ring->adev; 2824 u32 ref_and_mask, reg_mem_engine; 2825 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2826 2827 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2828 switch (ring->me) { 2829 case 1: 2830 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2831 break; 2832 case 2: 2833 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2834 break; 2835 default: 2836 return; 2837 } 2838 reg_mem_engine = 0; 2839 } else { 2840 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2841 reg_mem_engine = 1; /* pfp */ 2842 } 2843 2844 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2845 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2846 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2847 ref_and_mask, ref_and_mask, 0x20); 2848 } 2849 2850 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2851 struct amdgpu_job *job, 2852 struct amdgpu_ib *ib, 2853 uint32_t flags) 2854 { 2855 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2856 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2857 2858 /* Currently, there is a high possibility to get wave ID mismatch 2859 * between ME and GDS, leading to a hw deadlock, because ME generates 2860 * different wave IDs than the GDS expects. This situation happens 2861 * randomly when at least 5 compute pipes use GDS ordered append. 2862 * The wave IDs generated by ME are also wrong after suspend/resume. 2863 * Those are probably bugs somewhere else in the kernel driver. 2864 * 2865 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2866 * GDS to 0 for this ring (me/pipe). 2867 */ 2868 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2869 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2870 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2871 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2872 } 2873 2874 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2875 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2876 amdgpu_ring_write(ring, 2877 #ifdef __BIG_ENDIAN 2878 (2 << 0) | 2879 #endif 2880 lower_32_bits(ib->gpu_addr)); 2881 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2882 amdgpu_ring_write(ring, control); 2883 } 2884 2885 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2886 u64 seq, unsigned flags) 2887 { 2888 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2889 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2890 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2891 2892 /* RELEASE_MEM - flush caches, send int */ 2893 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2894 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2895 EOP_TC_NC_ACTION_EN) : 2896 (EOP_TCL1_ACTION_EN | 2897 EOP_TC_ACTION_EN | 2898 EOP_TC_WB_ACTION_EN | 2899 EOP_TC_MD_ACTION_EN)) | 2900 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2901 EVENT_INDEX(5))); 2902 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2903 2904 /* 2905 * the address should be Qword aligned if 64bit write, Dword 2906 * aligned if only send 32bit data low (discard data high) 2907 */ 2908 if (write64bit) 2909 BUG_ON(addr & 0x7); 2910 else 2911 BUG_ON(addr & 0x3); 2912 amdgpu_ring_write(ring, lower_32_bits(addr)); 2913 amdgpu_ring_write(ring, upper_32_bits(addr)); 2914 amdgpu_ring_write(ring, lower_32_bits(seq)); 2915 amdgpu_ring_write(ring, upper_32_bits(seq)); 2916 amdgpu_ring_write(ring, 0); 2917 } 2918 2919 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2920 { 2921 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2922 uint32_t seq = ring->fence_drv.sync_seq; 2923 uint64_t addr = ring->fence_drv.gpu_addr; 2924 2925 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2926 lower_32_bits(addr), upper_32_bits(addr), 2927 seq, 0xffffffff, 4); 2928 } 2929 2930 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2931 unsigned vmid, uint64_t pd_addr) 2932 { 2933 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2934 } 2935 2936 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2937 { 2938 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2939 } 2940 2941 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2942 { 2943 u64 wptr; 2944 2945 /* XXX check if swapping is necessary on BE */ 2946 if (ring->use_doorbell) 2947 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2948 else 2949 BUG(); 2950 return wptr; 2951 } 2952 2953 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2954 { 2955 struct amdgpu_device *adev = ring->adev; 2956 2957 /* XXX check if swapping is necessary on BE */ 2958 if (ring->use_doorbell) { 2959 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2960 WDOORBELL64(ring->doorbell_index, ring->wptr); 2961 } else { 2962 BUG(); /* only DOORBELL method supported on gfx9 now */ 2963 } 2964 } 2965 2966 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2967 u64 seq, unsigned int flags) 2968 { 2969 struct amdgpu_device *adev = ring->adev; 2970 2971 /* we only allocate 32bit for each seq wb address */ 2972 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2973 2974 /* write fence seq to the "addr" */ 2975 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2976 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2977 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2978 amdgpu_ring_write(ring, lower_32_bits(addr)); 2979 amdgpu_ring_write(ring, upper_32_bits(addr)); 2980 amdgpu_ring_write(ring, lower_32_bits(seq)); 2981 2982 if (flags & AMDGPU_FENCE_FLAG_INT) { 2983 /* set register to trigger INT */ 2984 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2985 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2986 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2987 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2988 amdgpu_ring_write(ring, 0); 2989 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2990 } 2991 } 2992 2993 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2994 uint32_t reg_val_offs) 2995 { 2996 struct amdgpu_device *adev = ring->adev; 2997 2998 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2999 3000 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3001 amdgpu_ring_write(ring, 0 | /* src: register*/ 3002 (5 << 8) | /* dst: memory */ 3003 (1 << 20)); /* write confirm */ 3004 amdgpu_ring_write(ring, reg); 3005 amdgpu_ring_write(ring, 0); 3006 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3007 reg_val_offs * 4)); 3008 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3009 reg_val_offs * 4)); 3010 } 3011 3012 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3013 uint32_t val) 3014 { 3015 uint32_t cmd = 0; 3016 3017 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3018 3019 switch (ring->funcs->type) { 3020 case AMDGPU_RING_TYPE_GFX: 3021 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3022 break; 3023 case AMDGPU_RING_TYPE_KIQ: 3024 cmd = (1 << 16); /* no inc addr */ 3025 break; 3026 default: 3027 cmd = WR_CONFIRM; 3028 break; 3029 } 3030 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3031 amdgpu_ring_write(ring, cmd); 3032 amdgpu_ring_write(ring, reg); 3033 amdgpu_ring_write(ring, 0); 3034 amdgpu_ring_write(ring, val); 3035 } 3036 3037 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3038 uint32_t val, uint32_t mask) 3039 { 3040 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3041 } 3042 3043 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3044 uint32_t reg0, uint32_t reg1, 3045 uint32_t ref, uint32_t mask) 3046 { 3047 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3048 ref, mask); 3049 } 3050 3051 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3052 unsigned vmid) 3053 { 3054 struct amdgpu_device *adev = ring->adev; 3055 uint32_t value = 0; 3056 3057 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3058 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3059 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3060 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3061 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3062 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3063 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3064 } 3065 3066 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3067 struct amdgpu_device *adev, int me, int pipe, 3068 enum amdgpu_interrupt_state state, int xcc_id) 3069 { 3070 u32 mec_int_cntl, mec_int_cntl_reg; 3071 3072 /* 3073 * amdgpu controls only the first MEC. That's why this function only 3074 * handles the setting of interrupts for this specific MEC. All other 3075 * pipes' interrupts are set by amdkfd. 3076 */ 3077 3078 if (me == 1) { 3079 switch (pipe) { 3080 case 0: 3081 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3082 break; 3083 case 1: 3084 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3085 break; 3086 case 2: 3087 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3088 break; 3089 case 3: 3090 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3091 break; 3092 default: 3093 DRM_DEBUG("invalid pipe %d\n", pipe); 3094 return; 3095 } 3096 } else { 3097 DRM_DEBUG("invalid me %d\n", me); 3098 return; 3099 } 3100 3101 switch (state) { 3102 case AMDGPU_IRQ_STATE_DISABLE: 3103 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3104 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3105 TIME_STAMP_INT_ENABLE, 0); 3106 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3107 break; 3108 case AMDGPU_IRQ_STATE_ENABLE: 3109 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3110 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3111 TIME_STAMP_INT_ENABLE, 1); 3112 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3113 break; 3114 default: 3115 break; 3116 } 3117 } 3118 3119 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3120 int xcc_id, int me, int pipe) 3121 { 3122 /* 3123 * amdgpu controls only the first MEC. That's why this function only 3124 * handles the setting of interrupts for this specific MEC. All other 3125 * pipes' interrupts are set by amdkfd. 3126 */ 3127 if (me != 1) 3128 return 0; 3129 3130 switch (pipe) { 3131 case 0: 3132 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3133 case 1: 3134 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3135 case 2: 3136 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3137 case 3: 3138 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3139 default: 3140 return 0; 3141 } 3142 } 3143 3144 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3145 struct amdgpu_irq_src *source, 3146 unsigned type, 3147 enum amdgpu_interrupt_state state) 3148 { 3149 u32 mec_int_cntl_reg, mec_int_cntl; 3150 int i, j, k, num_xcc; 3151 3152 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3153 switch (state) { 3154 case AMDGPU_IRQ_STATE_DISABLE: 3155 case AMDGPU_IRQ_STATE_ENABLE: 3156 for (i = 0; i < num_xcc; i++) { 3157 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3158 PRIV_REG_INT_ENABLE, 3159 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3160 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3161 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3162 /* MECs start at 1 */ 3163 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3164 3165 if (mec_int_cntl_reg) { 3166 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3167 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3168 PRIV_REG_INT_ENABLE, 3169 state == AMDGPU_IRQ_STATE_ENABLE ? 3170 1 : 0); 3171 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3172 } 3173 } 3174 } 3175 } 3176 break; 3177 default: 3178 break; 3179 } 3180 3181 return 0; 3182 } 3183 3184 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3185 struct amdgpu_irq_src *source, 3186 unsigned type, 3187 enum amdgpu_interrupt_state state) 3188 { 3189 u32 mec_int_cntl_reg, mec_int_cntl; 3190 int i, j, k, num_xcc; 3191 3192 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3193 switch (state) { 3194 case AMDGPU_IRQ_STATE_DISABLE: 3195 case AMDGPU_IRQ_STATE_ENABLE: 3196 for (i = 0; i < num_xcc; i++) { 3197 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3198 OPCODE_ERROR_INT_ENABLE, 3199 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3200 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3201 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3202 /* MECs start at 1 */ 3203 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3204 3205 if (mec_int_cntl_reg) { 3206 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3207 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3208 OPCODE_ERROR_INT_ENABLE, 3209 state == AMDGPU_IRQ_STATE_ENABLE ? 3210 1 : 0); 3211 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3212 } 3213 } 3214 } 3215 } 3216 break; 3217 default: 3218 break; 3219 } 3220 3221 return 0; 3222 } 3223 3224 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3225 struct amdgpu_irq_src *source, 3226 unsigned type, 3227 enum amdgpu_interrupt_state state) 3228 { 3229 int i, num_xcc; 3230 3231 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3232 switch (state) { 3233 case AMDGPU_IRQ_STATE_DISABLE: 3234 case AMDGPU_IRQ_STATE_ENABLE: 3235 for (i = 0; i < num_xcc; i++) 3236 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3237 PRIV_INSTR_INT_ENABLE, 3238 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3239 break; 3240 default: 3241 break; 3242 } 3243 3244 return 0; 3245 } 3246 3247 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3248 struct amdgpu_irq_src *src, 3249 unsigned type, 3250 enum amdgpu_interrupt_state state) 3251 { 3252 int i, num_xcc; 3253 3254 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3255 for (i = 0; i < num_xcc; i++) { 3256 switch (type) { 3257 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3258 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3259 adev, 1, 0, state, i); 3260 break; 3261 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3262 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3263 adev, 1, 1, state, i); 3264 break; 3265 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3266 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3267 adev, 1, 2, state, i); 3268 break; 3269 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3270 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3271 adev, 1, 3, state, i); 3272 break; 3273 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3274 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3275 adev, 2, 0, state, i); 3276 break; 3277 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3278 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3279 adev, 2, 1, state, i); 3280 break; 3281 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3282 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3283 adev, 2, 2, state, i); 3284 break; 3285 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3286 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3287 adev, 2, 3, state, i); 3288 break; 3289 default: 3290 break; 3291 } 3292 } 3293 3294 return 0; 3295 } 3296 3297 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3298 struct amdgpu_irq_src *source, 3299 struct amdgpu_iv_entry *entry) 3300 { 3301 int i, xcc_id; 3302 u8 me_id, pipe_id, queue_id; 3303 struct amdgpu_ring *ring; 3304 3305 DRM_DEBUG("IH: CP EOP\n"); 3306 me_id = (entry->ring_id & 0x0c) >> 2; 3307 pipe_id = (entry->ring_id & 0x03) >> 0; 3308 queue_id = (entry->ring_id & 0x70) >> 4; 3309 3310 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3311 3312 if (xcc_id == -EINVAL) 3313 return -EINVAL; 3314 3315 switch (me_id) { 3316 case 0: 3317 case 1: 3318 case 2: 3319 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3320 ring = &adev->gfx.compute_ring 3321 [i + 3322 xcc_id * adev->gfx.num_compute_rings]; 3323 /* Per-queue interrupt is supported for MEC starting from VI. 3324 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3325 */ 3326 3327 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3328 amdgpu_fence_process(ring); 3329 } 3330 break; 3331 } 3332 return 0; 3333 } 3334 3335 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3336 struct amdgpu_iv_entry *entry) 3337 { 3338 u8 me_id, pipe_id, queue_id; 3339 struct amdgpu_ring *ring; 3340 int i, xcc_id; 3341 3342 me_id = (entry->ring_id & 0x0c) >> 2; 3343 pipe_id = (entry->ring_id & 0x03) >> 0; 3344 queue_id = (entry->ring_id & 0x70) >> 4; 3345 3346 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3347 3348 if (xcc_id == -EINVAL) 3349 return; 3350 3351 switch (me_id) { 3352 case 0: 3353 case 1: 3354 case 2: 3355 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3356 ring = &adev->gfx.compute_ring 3357 [i + 3358 xcc_id * adev->gfx.num_compute_rings]; 3359 if (ring->me == me_id && ring->pipe == pipe_id && 3360 ring->queue == queue_id) 3361 drm_sched_fault(&ring->sched); 3362 } 3363 break; 3364 } 3365 } 3366 3367 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3368 struct amdgpu_irq_src *source, 3369 struct amdgpu_iv_entry *entry) 3370 { 3371 DRM_ERROR("Illegal register access in command stream\n"); 3372 gfx_v9_4_3_fault(adev, entry); 3373 return 0; 3374 } 3375 3376 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3377 struct amdgpu_irq_src *source, 3378 struct amdgpu_iv_entry *entry) 3379 { 3380 DRM_ERROR("Illegal opcode in command stream\n"); 3381 gfx_v9_4_3_fault(adev, entry); 3382 return 0; 3383 } 3384 3385 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3386 struct amdgpu_irq_src *source, 3387 struct amdgpu_iv_entry *entry) 3388 { 3389 DRM_ERROR("Illegal instruction in command stream\n"); 3390 gfx_v9_4_3_fault(adev, entry); 3391 return 0; 3392 } 3393 3394 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3395 { 3396 const unsigned int cp_coher_cntl = 3397 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3398 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3399 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3400 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3401 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3402 3403 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3404 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3405 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3406 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3407 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3408 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3409 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3410 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3411 } 3412 3413 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3414 uint32_t pipe, bool enable) 3415 { 3416 struct amdgpu_device *adev = ring->adev; 3417 uint32_t val; 3418 uint32_t wcl_cs_reg; 3419 3420 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3421 val = enable ? 0x1 : 0x7f; 3422 3423 switch (pipe) { 3424 case 0: 3425 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3426 break; 3427 case 1: 3428 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3429 break; 3430 case 2: 3431 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3432 break; 3433 case 3: 3434 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3435 break; 3436 default: 3437 DRM_DEBUG("invalid pipe %d\n", pipe); 3438 return; 3439 } 3440 3441 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3442 3443 } 3444 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3445 { 3446 struct amdgpu_device *adev = ring->adev; 3447 uint32_t val; 3448 int i; 3449 3450 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3451 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3452 * around 25% of gpu resources. 3453 */ 3454 val = enable ? 0x1f : 0x07ffffff; 3455 amdgpu_ring_emit_wreg(ring, 3456 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3457 val); 3458 3459 /* Restrict waves for normal/low priority compute queues as well 3460 * to get best QoS for high priority compute jobs. 3461 * 3462 * amdgpu controls only 1st ME(0-3 CS pipes). 3463 */ 3464 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3465 if (i != ring->pipe) 3466 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3467 3468 } 3469 } 3470 3471 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3472 uint32_t pipe, uint32_t queue, 3473 uint32_t xcc_id) 3474 { 3475 int i, r; 3476 /* make sure dequeue is complete*/ 3477 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3478 mutex_lock(&adev->srbm_mutex); 3479 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3480 for (i = 0; i < adev->usec_timeout; i++) { 3481 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3482 break; 3483 udelay(1); 3484 } 3485 if (i >= adev->usec_timeout) 3486 r = -ETIMEDOUT; 3487 else 3488 r = 0; 3489 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3490 mutex_unlock(&adev->srbm_mutex); 3491 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3492 3493 return r; 3494 3495 } 3496 3497 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3498 { 3499 /*TODO: Need check gfx9.4.4 mec fw whether supports pipe reset as well.*/ 3500 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 3501 adev->gfx.mec_fw_version >= 0x0000009b) 3502 return true; 3503 else 3504 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3505 3506 return false; 3507 } 3508 3509 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3510 { 3511 struct amdgpu_device *adev = ring->adev; 3512 uint32_t reset_pipe, clean_pipe; 3513 int r; 3514 3515 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3516 return -EINVAL; 3517 3518 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3519 mutex_lock(&adev->srbm_mutex); 3520 3521 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3522 clean_pipe = reset_pipe; 3523 3524 if (ring->me == 1) { 3525 switch (ring->pipe) { 3526 case 0: 3527 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3528 MEC_ME1_PIPE0_RESET, 1); 3529 break; 3530 case 1: 3531 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3532 MEC_ME1_PIPE1_RESET, 1); 3533 break; 3534 case 2: 3535 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3536 MEC_ME1_PIPE2_RESET, 1); 3537 break; 3538 case 3: 3539 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3540 MEC_ME1_PIPE3_RESET, 1); 3541 break; 3542 default: 3543 break; 3544 } 3545 } else { 3546 if (ring->pipe) 3547 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3548 MEC_ME2_PIPE1_RESET, 1); 3549 else 3550 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3551 MEC_ME2_PIPE0_RESET, 1); 3552 } 3553 3554 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3555 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3556 mutex_unlock(&adev->srbm_mutex); 3557 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3558 3559 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3560 return r; 3561 } 3562 3563 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3564 unsigned int vmid) 3565 { 3566 struct amdgpu_device *adev = ring->adev; 3567 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3568 struct amdgpu_ring *kiq_ring = &kiq->ring; 3569 unsigned long flags; 3570 int r; 3571 3572 if (amdgpu_sriov_vf(adev)) 3573 return -EINVAL; 3574 3575 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3576 return -EINVAL; 3577 3578 spin_lock_irqsave(&kiq->ring_lock, flags); 3579 3580 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3581 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3582 return -ENOMEM; 3583 } 3584 3585 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3586 0, 0); 3587 amdgpu_ring_commit(kiq_ring); 3588 3589 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3590 3591 r = amdgpu_ring_test_ring(kiq_ring); 3592 if (r) { 3593 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3594 ring->name); 3595 goto pipe_reset; 3596 } 3597 3598 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3599 if (r) 3600 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3601 3602 pipe_reset: 3603 if(r) { 3604 r = gfx_v9_4_3_reset_hw_pipe(ring); 3605 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3606 r ? "failed" : "successfully"); 3607 if (r) 3608 return r; 3609 } 3610 3611 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3612 if (unlikely(r != 0)){ 3613 dev_err(adev->dev, "fail to resv mqd_obj\n"); 3614 return r; 3615 } 3616 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3617 if (!r) { 3618 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3619 amdgpu_bo_kunmap(ring->mqd_obj); 3620 ring->mqd_ptr = NULL; 3621 } 3622 amdgpu_bo_unreserve(ring->mqd_obj); 3623 if (r) { 3624 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 3625 return r; 3626 } 3627 spin_lock_irqsave(&kiq->ring_lock, flags); 3628 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3629 if (r) { 3630 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3631 return -ENOMEM; 3632 } 3633 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3634 amdgpu_ring_commit(kiq_ring); 3635 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3636 3637 r = amdgpu_ring_test_ring(kiq_ring); 3638 if (r) { 3639 dev_err(adev->dev, "fail to remap queue\n"); 3640 return r; 3641 } 3642 return amdgpu_ring_test_ring(ring); 3643 } 3644 3645 enum amdgpu_gfx_cp_ras_mem_id { 3646 AMDGPU_GFX_CP_MEM1 = 1, 3647 AMDGPU_GFX_CP_MEM2, 3648 AMDGPU_GFX_CP_MEM3, 3649 AMDGPU_GFX_CP_MEM4, 3650 AMDGPU_GFX_CP_MEM5, 3651 }; 3652 3653 enum amdgpu_gfx_gcea_ras_mem_id { 3654 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3655 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3656 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3657 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3658 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3659 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3660 AMDGPU_GFX_GCEA_MAM_DMEM0, 3661 AMDGPU_GFX_GCEA_MAM_DMEM1, 3662 AMDGPU_GFX_GCEA_MAM_DMEM2, 3663 AMDGPU_GFX_GCEA_MAM_DMEM3, 3664 AMDGPU_GFX_GCEA_MAM_AMEM0, 3665 AMDGPU_GFX_GCEA_MAM_AMEM1, 3666 AMDGPU_GFX_GCEA_MAM_AMEM2, 3667 AMDGPU_GFX_GCEA_MAM_AMEM3, 3668 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3669 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3670 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3671 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3672 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3673 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3674 }; 3675 3676 enum amdgpu_gfx_gc_cane_ras_mem_id { 3677 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3678 }; 3679 3680 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3681 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3682 }; 3683 3684 enum amdgpu_gfx_gds_ras_mem_id { 3685 AMDGPU_GFX_GDS_MEM0 = 0, 3686 }; 3687 3688 enum amdgpu_gfx_lds_ras_mem_id { 3689 AMDGPU_GFX_LDS_BANK0 = 0, 3690 AMDGPU_GFX_LDS_BANK1, 3691 AMDGPU_GFX_LDS_BANK2, 3692 AMDGPU_GFX_LDS_BANK3, 3693 AMDGPU_GFX_LDS_BANK4, 3694 AMDGPU_GFX_LDS_BANK5, 3695 AMDGPU_GFX_LDS_BANK6, 3696 AMDGPU_GFX_LDS_BANK7, 3697 AMDGPU_GFX_LDS_BANK8, 3698 AMDGPU_GFX_LDS_BANK9, 3699 AMDGPU_GFX_LDS_BANK10, 3700 AMDGPU_GFX_LDS_BANK11, 3701 AMDGPU_GFX_LDS_BANK12, 3702 AMDGPU_GFX_LDS_BANK13, 3703 AMDGPU_GFX_LDS_BANK14, 3704 AMDGPU_GFX_LDS_BANK15, 3705 AMDGPU_GFX_LDS_BANK16, 3706 AMDGPU_GFX_LDS_BANK17, 3707 AMDGPU_GFX_LDS_BANK18, 3708 AMDGPU_GFX_LDS_BANK19, 3709 AMDGPU_GFX_LDS_BANK20, 3710 AMDGPU_GFX_LDS_BANK21, 3711 AMDGPU_GFX_LDS_BANK22, 3712 AMDGPU_GFX_LDS_BANK23, 3713 AMDGPU_GFX_LDS_BANK24, 3714 AMDGPU_GFX_LDS_BANK25, 3715 AMDGPU_GFX_LDS_BANK26, 3716 AMDGPU_GFX_LDS_BANK27, 3717 AMDGPU_GFX_LDS_BANK28, 3718 AMDGPU_GFX_LDS_BANK29, 3719 AMDGPU_GFX_LDS_BANK30, 3720 AMDGPU_GFX_LDS_BANK31, 3721 AMDGPU_GFX_LDS_SP_BUFFER_A, 3722 AMDGPU_GFX_LDS_SP_BUFFER_B, 3723 }; 3724 3725 enum amdgpu_gfx_rlc_ras_mem_id { 3726 AMDGPU_GFX_RLC_GPMF32 = 1, 3727 AMDGPU_GFX_RLC_RLCVF32, 3728 AMDGPU_GFX_RLC_SCRATCH, 3729 AMDGPU_GFX_RLC_SRM_ARAM, 3730 AMDGPU_GFX_RLC_SRM_DRAM, 3731 AMDGPU_GFX_RLC_TCTAG, 3732 AMDGPU_GFX_RLC_SPM_SE, 3733 AMDGPU_GFX_RLC_SPM_GRBMT, 3734 }; 3735 3736 enum amdgpu_gfx_sp_ras_mem_id { 3737 AMDGPU_GFX_SP_SIMDID0 = 0, 3738 }; 3739 3740 enum amdgpu_gfx_spi_ras_mem_id { 3741 AMDGPU_GFX_SPI_MEM0 = 0, 3742 AMDGPU_GFX_SPI_MEM1, 3743 AMDGPU_GFX_SPI_MEM2, 3744 AMDGPU_GFX_SPI_MEM3, 3745 }; 3746 3747 enum amdgpu_gfx_sqc_ras_mem_id { 3748 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3749 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3750 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3751 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3752 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3753 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3754 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3755 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3756 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3757 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3758 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3759 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3760 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3761 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3762 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3763 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3764 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3765 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3766 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3767 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3768 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3769 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3770 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3771 }; 3772 3773 enum amdgpu_gfx_sq_ras_mem_id { 3774 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3775 AMDGPU_GFX_SQ_SGPR_MEM1, 3776 AMDGPU_GFX_SQ_SGPR_MEM2, 3777 AMDGPU_GFX_SQ_SGPR_MEM3, 3778 }; 3779 3780 enum amdgpu_gfx_ta_ras_mem_id { 3781 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3782 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3783 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3784 AMDGPU_GFX_TA_FSX_LFIFO, 3785 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3786 }; 3787 3788 enum amdgpu_gfx_tcc_ras_mem_id { 3789 AMDGPU_GFX_TCC_MEM1 = 1, 3790 }; 3791 3792 enum amdgpu_gfx_tca_ras_mem_id { 3793 AMDGPU_GFX_TCA_MEM1 = 1, 3794 }; 3795 3796 enum amdgpu_gfx_tci_ras_mem_id { 3797 AMDGPU_GFX_TCIW_MEM = 1, 3798 }; 3799 3800 enum amdgpu_gfx_tcp_ras_mem_id { 3801 AMDGPU_GFX_TCP_LFIFO0 = 1, 3802 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3803 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3804 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3805 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3806 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3807 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3808 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3809 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3810 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3811 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3812 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3813 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3814 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3815 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3816 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3817 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3818 AMDGPU_GFX_TCP_VM_FIFO, 3819 AMDGPU_GFX_TCP_DB_TAGRAM0, 3820 AMDGPU_GFX_TCP_DB_TAGRAM1, 3821 AMDGPU_GFX_TCP_DB_TAGRAM2, 3822 AMDGPU_GFX_TCP_DB_TAGRAM3, 3823 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3824 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3825 AMDGPU_GFX_TCP_CMD_FIFO, 3826 }; 3827 3828 enum amdgpu_gfx_td_ras_mem_id { 3829 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3830 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3831 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3832 }; 3833 3834 enum amdgpu_gfx_tcx_ras_mem_id { 3835 AMDGPU_GFX_TCX_FIFOD0 = 0, 3836 AMDGPU_GFX_TCX_FIFOD1, 3837 AMDGPU_GFX_TCX_FIFOD2, 3838 AMDGPU_GFX_TCX_FIFOD3, 3839 AMDGPU_GFX_TCX_FIFOD4, 3840 AMDGPU_GFX_TCX_FIFOD5, 3841 AMDGPU_GFX_TCX_FIFOD6, 3842 AMDGPU_GFX_TCX_FIFOD7, 3843 AMDGPU_GFX_TCX_FIFOB0, 3844 AMDGPU_GFX_TCX_FIFOB1, 3845 AMDGPU_GFX_TCX_FIFOB2, 3846 AMDGPU_GFX_TCX_FIFOB3, 3847 AMDGPU_GFX_TCX_FIFOB4, 3848 AMDGPU_GFX_TCX_FIFOB5, 3849 AMDGPU_GFX_TCX_FIFOB6, 3850 AMDGPU_GFX_TCX_FIFOB7, 3851 AMDGPU_GFX_TCX_FIFOA0, 3852 AMDGPU_GFX_TCX_FIFOA1, 3853 AMDGPU_GFX_TCX_FIFOA2, 3854 AMDGPU_GFX_TCX_FIFOA3, 3855 AMDGPU_GFX_TCX_FIFOA4, 3856 AMDGPU_GFX_TCX_FIFOA5, 3857 AMDGPU_GFX_TCX_FIFOA6, 3858 AMDGPU_GFX_TCX_FIFOA7, 3859 AMDGPU_GFX_TCX_CFIFO0, 3860 AMDGPU_GFX_TCX_CFIFO1, 3861 AMDGPU_GFX_TCX_CFIFO2, 3862 AMDGPU_GFX_TCX_CFIFO3, 3863 AMDGPU_GFX_TCX_CFIFO4, 3864 AMDGPU_GFX_TCX_CFIFO5, 3865 AMDGPU_GFX_TCX_CFIFO6, 3866 AMDGPU_GFX_TCX_CFIFO7, 3867 AMDGPU_GFX_TCX_FIFO_ACKB0, 3868 AMDGPU_GFX_TCX_FIFO_ACKB1, 3869 AMDGPU_GFX_TCX_FIFO_ACKB2, 3870 AMDGPU_GFX_TCX_FIFO_ACKB3, 3871 AMDGPU_GFX_TCX_FIFO_ACKB4, 3872 AMDGPU_GFX_TCX_FIFO_ACKB5, 3873 AMDGPU_GFX_TCX_FIFO_ACKB6, 3874 AMDGPU_GFX_TCX_FIFO_ACKB7, 3875 AMDGPU_GFX_TCX_FIFO_ACKD0, 3876 AMDGPU_GFX_TCX_FIFO_ACKD1, 3877 AMDGPU_GFX_TCX_FIFO_ACKD2, 3878 AMDGPU_GFX_TCX_FIFO_ACKD3, 3879 AMDGPU_GFX_TCX_FIFO_ACKD4, 3880 AMDGPU_GFX_TCX_FIFO_ACKD5, 3881 AMDGPU_GFX_TCX_FIFO_ACKD6, 3882 AMDGPU_GFX_TCX_FIFO_ACKD7, 3883 AMDGPU_GFX_TCX_DST_FIFOA0, 3884 AMDGPU_GFX_TCX_DST_FIFOA1, 3885 AMDGPU_GFX_TCX_DST_FIFOA2, 3886 AMDGPU_GFX_TCX_DST_FIFOA3, 3887 AMDGPU_GFX_TCX_DST_FIFOA4, 3888 AMDGPU_GFX_TCX_DST_FIFOA5, 3889 AMDGPU_GFX_TCX_DST_FIFOA6, 3890 AMDGPU_GFX_TCX_DST_FIFOA7, 3891 AMDGPU_GFX_TCX_DST_FIFOB0, 3892 AMDGPU_GFX_TCX_DST_FIFOB1, 3893 AMDGPU_GFX_TCX_DST_FIFOB2, 3894 AMDGPU_GFX_TCX_DST_FIFOB3, 3895 AMDGPU_GFX_TCX_DST_FIFOB4, 3896 AMDGPU_GFX_TCX_DST_FIFOB5, 3897 AMDGPU_GFX_TCX_DST_FIFOB6, 3898 AMDGPU_GFX_TCX_DST_FIFOB7, 3899 AMDGPU_GFX_TCX_DST_FIFOD0, 3900 AMDGPU_GFX_TCX_DST_FIFOD1, 3901 AMDGPU_GFX_TCX_DST_FIFOD2, 3902 AMDGPU_GFX_TCX_DST_FIFOD3, 3903 AMDGPU_GFX_TCX_DST_FIFOD4, 3904 AMDGPU_GFX_TCX_DST_FIFOD5, 3905 AMDGPU_GFX_TCX_DST_FIFOD6, 3906 AMDGPU_GFX_TCX_DST_FIFOD7, 3907 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3908 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3909 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3910 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3911 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3912 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3913 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3914 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3915 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3916 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3917 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3918 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3919 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3920 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3921 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3922 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3923 }; 3924 3925 enum amdgpu_gfx_atc_l2_ras_mem_id { 3926 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3927 }; 3928 3929 enum amdgpu_gfx_utcl2_ras_mem_id { 3930 AMDGPU_GFX_UTCL2_MEM0 = 0, 3931 }; 3932 3933 enum amdgpu_gfx_vml2_ras_mem_id { 3934 AMDGPU_GFX_VML2_MEM0 = 0, 3935 }; 3936 3937 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3938 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3939 }; 3940 3941 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3942 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3943 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3944 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3945 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3946 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3947 }; 3948 3949 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3950 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3951 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3952 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3953 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3954 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3955 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3956 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3957 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3958 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3959 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3960 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3961 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3962 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3963 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3964 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3965 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3966 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3967 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3968 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3969 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3970 }; 3971 3972 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3973 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3974 }; 3975 3976 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3977 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3978 }; 3979 3980 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3981 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3982 }; 3983 3984 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3985 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3986 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3987 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3988 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3989 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3990 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3991 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3992 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3993 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3994 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3995 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3996 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3997 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3998 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3999 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 4000 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 4001 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 4002 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 4003 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 4004 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 4005 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 4006 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 4007 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 4008 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 4009 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 4010 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 4011 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 4012 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 4013 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 4014 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 4015 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 4016 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 4017 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 4018 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4019 }; 4020 4021 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4022 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4023 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4024 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4025 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4026 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4027 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4028 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4029 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4030 }; 4031 4032 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4033 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4034 }; 4035 4036 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4037 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4038 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4039 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4040 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4041 }; 4042 4043 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4044 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4045 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4046 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4047 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4048 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4049 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4050 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4051 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4052 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4053 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4054 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4055 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4056 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4057 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4058 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4059 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4060 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4061 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4062 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4063 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4064 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4065 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4066 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4067 }; 4068 4069 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4070 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4071 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4072 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4073 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4074 }; 4075 4076 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4077 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4078 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4079 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4080 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4081 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4082 }; 4083 4084 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4085 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4086 }; 4087 4088 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4089 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4090 }; 4091 4092 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4093 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4094 }; 4095 4096 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4097 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4098 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4099 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4100 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4101 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4102 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4103 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4104 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4105 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4106 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4107 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4108 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4109 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4110 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4111 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4112 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4113 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4114 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4115 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4116 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4117 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4118 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4119 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4120 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4121 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4122 }; 4123 4124 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4125 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4126 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4127 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4128 }; 4129 4130 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4131 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4132 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4133 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4134 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4135 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4136 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4137 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4138 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4139 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4140 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4141 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4142 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4143 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4144 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4145 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4146 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4147 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4148 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4149 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4150 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4151 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4152 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4153 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4154 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4155 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4156 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4157 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4158 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4159 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4160 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4161 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4162 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4163 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4164 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4165 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4166 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4167 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4168 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4169 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4170 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4171 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4172 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4173 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4174 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4175 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4176 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4177 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4178 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4179 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4180 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4181 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4182 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4183 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4184 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4185 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4186 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4187 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4188 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4189 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4190 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4191 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4192 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4193 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4194 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4195 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4196 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4197 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4198 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4199 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4200 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4201 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4202 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4203 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4204 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4205 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4206 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4207 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4208 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4209 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4210 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4211 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4212 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4213 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4214 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4215 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4216 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4217 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4218 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4219 }; 4220 4221 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4222 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4223 }; 4224 4225 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4226 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4227 }; 4228 4229 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4230 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4231 }; 4232 4233 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4234 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4235 }; 4236 4237 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4238 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4239 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4240 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4241 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4242 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4243 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4244 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4245 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4246 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4247 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4248 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4249 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4250 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4251 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4252 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4253 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4254 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4255 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4256 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4257 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4258 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4259 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4260 }; 4261 4262 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4263 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4264 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4265 AMDGPU_GFX_RLC_MEM, 1}, 4266 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4267 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4268 AMDGPU_GFX_CP_MEM, 1}, 4269 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4270 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4271 AMDGPU_GFX_CP_MEM, 1}, 4272 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4273 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4274 AMDGPU_GFX_CP_MEM, 1}, 4275 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4276 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4277 AMDGPU_GFX_GDS_MEM, 1}, 4278 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4279 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4280 AMDGPU_GFX_GC_CANE_MEM, 1}, 4281 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4282 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4283 AMDGPU_GFX_SPI_MEM, 1}, 4284 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4285 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4286 AMDGPU_GFX_SP_MEM, 4}, 4287 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4288 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4289 AMDGPU_GFX_SP_MEM, 4}, 4290 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4291 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4292 AMDGPU_GFX_SQ_MEM, 4}, 4293 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4294 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4295 AMDGPU_GFX_SQC_MEM, 4}, 4296 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4297 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4298 AMDGPU_GFX_TCX_MEM, 1}, 4299 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4300 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4301 AMDGPU_GFX_TCC_MEM, 1}, 4302 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4303 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4304 AMDGPU_GFX_TA_MEM, 4}, 4305 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4306 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4307 AMDGPU_GFX_TCI_MEM, 1}, 4308 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4309 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4310 AMDGPU_GFX_TCP_MEM, 4}, 4311 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4312 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4313 AMDGPU_GFX_TD_MEM, 4}, 4314 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4315 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4316 AMDGPU_GFX_GCEA_MEM, 1}, 4317 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4318 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4319 AMDGPU_GFX_LDS_MEM, 4}, 4320 }; 4321 4322 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4323 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4324 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4325 AMDGPU_GFX_RLC_MEM, 1}, 4326 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4327 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4328 AMDGPU_GFX_CP_MEM, 1}, 4329 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4330 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4331 AMDGPU_GFX_CP_MEM, 1}, 4332 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4333 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4334 AMDGPU_GFX_CP_MEM, 1}, 4335 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4336 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4337 AMDGPU_GFX_GDS_MEM, 1}, 4338 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4339 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4340 AMDGPU_GFX_GC_CANE_MEM, 1}, 4341 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4342 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4343 AMDGPU_GFX_SPI_MEM, 1}, 4344 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4345 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4346 AMDGPU_GFX_SP_MEM, 4}, 4347 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4348 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4349 AMDGPU_GFX_SP_MEM, 4}, 4350 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4351 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4352 AMDGPU_GFX_SQ_MEM, 4}, 4353 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4354 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4355 AMDGPU_GFX_SQC_MEM, 4}, 4356 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4357 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4358 AMDGPU_GFX_TCX_MEM, 1}, 4359 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4360 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4361 AMDGPU_GFX_TCC_MEM, 1}, 4362 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4363 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4364 AMDGPU_GFX_TA_MEM, 4}, 4365 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4366 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4367 AMDGPU_GFX_TCI_MEM, 1}, 4368 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4369 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4370 AMDGPU_GFX_TCP_MEM, 4}, 4371 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4372 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4373 AMDGPU_GFX_TD_MEM, 4}, 4374 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4375 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4376 AMDGPU_GFX_TCA_MEM, 1}, 4377 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4378 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4379 AMDGPU_GFX_GCEA_MEM, 1}, 4380 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4381 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4382 AMDGPU_GFX_LDS_MEM, 4}, 4383 }; 4384 4385 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4386 void *ras_error_status, int xcc_id) 4387 { 4388 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4389 unsigned long ce_count = 0, ue_count = 0; 4390 uint32_t i, j, k; 4391 4392 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4393 struct amdgpu_smuio_mcm_config_info mcm_info = { 4394 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4395 .die_id = xcc_id & 0x01 ? 1 : 0, 4396 }; 4397 4398 mutex_lock(&adev->grbm_idx_mutex); 4399 4400 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4401 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4402 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4403 /* no need to select if instance number is 1 */ 4404 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4405 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4406 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4407 4408 amdgpu_ras_inst_query_ras_error_count(adev, 4409 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4410 1, 4411 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4412 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4413 GET_INST(GC, xcc_id), 4414 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4415 &ce_count); 4416 4417 amdgpu_ras_inst_query_ras_error_count(adev, 4418 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4419 1, 4420 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4421 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4422 GET_INST(GC, xcc_id), 4423 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4424 &ue_count); 4425 } 4426 } 4427 } 4428 4429 /* handle extra register entries of UE */ 4430 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4431 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4432 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4433 /* no need to select if instance number is 1 */ 4434 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4435 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4436 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4437 4438 amdgpu_ras_inst_query_ras_error_count(adev, 4439 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4440 1, 4441 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4442 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4443 GET_INST(GC, xcc_id), 4444 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4445 &ue_count); 4446 } 4447 } 4448 } 4449 4450 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4451 xcc_id); 4452 mutex_unlock(&adev->grbm_idx_mutex); 4453 4454 /* the caller should make sure initialize value of 4455 * err_data->ue_count and err_data->ce_count 4456 */ 4457 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4458 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4459 } 4460 4461 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4462 void *ras_error_status, int xcc_id) 4463 { 4464 uint32_t i, j, k; 4465 4466 mutex_lock(&adev->grbm_idx_mutex); 4467 4468 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4469 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4470 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4471 /* no need to select if instance number is 1 */ 4472 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4473 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4474 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4475 4476 amdgpu_ras_inst_reset_ras_error_count(adev, 4477 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4478 1, 4479 GET_INST(GC, xcc_id)); 4480 4481 amdgpu_ras_inst_reset_ras_error_count(adev, 4482 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4483 1, 4484 GET_INST(GC, xcc_id)); 4485 } 4486 } 4487 } 4488 4489 /* handle extra register entries of UE */ 4490 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4491 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4492 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4493 /* no need to select if instance number is 1 */ 4494 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4495 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4496 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4497 4498 amdgpu_ras_inst_reset_ras_error_count(adev, 4499 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4500 1, 4501 GET_INST(GC, xcc_id)); 4502 } 4503 } 4504 } 4505 4506 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4507 xcc_id); 4508 mutex_unlock(&adev->grbm_idx_mutex); 4509 } 4510 4511 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4512 void *ras_error_status, int xcc_id) 4513 { 4514 uint32_t i; 4515 uint32_t data; 4516 4517 if (amdgpu_sriov_vf(adev)) 4518 return; 4519 4520 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4521 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4522 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4523 4524 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4525 (amdgpu_watchdog_timer.period < 1 || 4526 amdgpu_watchdog_timer.period > 0x23)) { 4527 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4528 amdgpu_watchdog_timer.period = 0x23; 4529 } 4530 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4531 amdgpu_watchdog_timer.period); 4532 4533 mutex_lock(&adev->grbm_idx_mutex); 4534 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4535 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4536 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4537 } 4538 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4539 xcc_id); 4540 mutex_unlock(&adev->grbm_idx_mutex); 4541 } 4542 4543 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4544 void *ras_error_status) 4545 { 4546 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4547 gfx_v9_4_3_inst_query_ras_err_count); 4548 } 4549 4550 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4551 { 4552 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4553 } 4554 4555 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4556 { 4557 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4558 } 4559 4560 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4561 { 4562 /* Header itself is a NOP packet */ 4563 if (num_nop == 1) { 4564 amdgpu_ring_write(ring, ring->funcs->nop); 4565 return; 4566 } 4567 4568 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4569 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4570 4571 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4572 amdgpu_ring_insert_nop(ring, num_nop - 1); 4573 } 4574 4575 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4576 { 4577 struct amdgpu_device *adev = ip_block->adev; 4578 uint32_t i, j, k; 4579 uint32_t xcc_id, xcc_offset, inst_offset; 4580 uint32_t num_xcc, reg, num_inst; 4581 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4582 4583 if (!adev->gfx.ip_dump_core) 4584 return; 4585 4586 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4587 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4588 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4589 xcc_offset = xcc_id * reg_count; 4590 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4591 for (i = 0; i < reg_count; i++) 4592 drm_printf(p, "%-50s \t 0x%08x\n", 4593 gc_reg_list_9_4_3[i].reg_name, 4594 adev->gfx.ip_dump_core[xcc_offset + i]); 4595 } 4596 4597 /* print compute queue registers for all instances */ 4598 if (!adev->gfx.ip_dump_compute_queues) 4599 return; 4600 4601 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4602 adev->gfx.mec.num_queue_per_pipe; 4603 4604 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4605 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4606 num_xcc, 4607 adev->gfx.mec.num_mec, 4608 adev->gfx.mec.num_pipe_per_mec, 4609 adev->gfx.mec.num_queue_per_pipe); 4610 4611 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4612 xcc_offset = xcc_id * reg_count * num_inst; 4613 inst_offset = 0; 4614 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4615 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4616 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4617 drm_printf(p, 4618 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4619 xcc_id, i, j, k); 4620 for (reg = 0; reg < reg_count; reg++) { 4621 drm_printf(p, 4622 "%-50s \t 0x%08x\n", 4623 gc_cp_reg_list_9_4_3[reg].reg_name, 4624 adev->gfx.ip_dump_compute_queues 4625 [xcc_offset + inst_offset + 4626 reg]); 4627 } 4628 inst_offset += reg_count; 4629 } 4630 } 4631 } 4632 } 4633 } 4634 4635 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4636 { 4637 struct amdgpu_device *adev = ip_block->adev; 4638 uint32_t i, j, k; 4639 uint32_t num_xcc, reg, num_inst; 4640 uint32_t xcc_id, xcc_offset, inst_offset; 4641 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4642 4643 if (!adev->gfx.ip_dump_core) 4644 return; 4645 4646 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4647 4648 amdgpu_gfx_off_ctrl(adev, false); 4649 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4650 xcc_offset = xcc_id * reg_count; 4651 for (i = 0; i < reg_count; i++) 4652 adev->gfx.ip_dump_core[xcc_offset + i] = 4653 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4654 GET_INST(GC, xcc_id))); 4655 } 4656 amdgpu_gfx_off_ctrl(adev, true); 4657 4658 /* dump compute queue registers for all instances */ 4659 if (!adev->gfx.ip_dump_compute_queues) 4660 return; 4661 4662 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4663 adev->gfx.mec.num_queue_per_pipe; 4664 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4665 amdgpu_gfx_off_ctrl(adev, false); 4666 mutex_lock(&adev->srbm_mutex); 4667 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4668 xcc_offset = xcc_id * reg_count * num_inst; 4669 inst_offset = 0; 4670 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4671 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4672 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4673 /* ME0 is for GFX so start from 1 for CP */ 4674 soc15_grbm_select(adev, 1 + i, j, k, 0, 4675 GET_INST(GC, xcc_id)); 4676 4677 for (reg = 0; reg < reg_count; reg++) { 4678 adev->gfx.ip_dump_compute_queues 4679 [xcc_offset + 4680 inst_offset + reg] = 4681 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4682 gc_cp_reg_list_9_4_3[reg], 4683 GET_INST(GC, xcc_id))); 4684 } 4685 inst_offset += reg_count; 4686 } 4687 } 4688 } 4689 } 4690 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4691 mutex_unlock(&adev->srbm_mutex); 4692 amdgpu_gfx_off_ctrl(adev, true); 4693 } 4694 4695 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4696 { 4697 /* Emit the cleaner shader */ 4698 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4699 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4700 } 4701 4702 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4703 .name = "gfx_v9_4_3", 4704 .early_init = gfx_v9_4_3_early_init, 4705 .late_init = gfx_v9_4_3_late_init, 4706 .sw_init = gfx_v9_4_3_sw_init, 4707 .sw_fini = gfx_v9_4_3_sw_fini, 4708 .hw_init = gfx_v9_4_3_hw_init, 4709 .hw_fini = gfx_v9_4_3_hw_fini, 4710 .suspend = gfx_v9_4_3_suspend, 4711 .resume = gfx_v9_4_3_resume, 4712 .is_idle = gfx_v9_4_3_is_idle, 4713 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4714 .soft_reset = gfx_v9_4_3_soft_reset, 4715 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4716 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4717 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4718 .dump_ip_state = gfx_v9_4_3_ip_dump, 4719 .print_ip_state = gfx_v9_4_3_ip_print, 4720 }; 4721 4722 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4723 .type = AMDGPU_RING_TYPE_COMPUTE, 4724 .align_mask = 0xff, 4725 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4726 .support_64bit_ptrs = true, 4727 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4728 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4729 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4730 .emit_frame_size = 4731 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4732 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4733 5 + /* hdp invalidate */ 4734 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4735 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4736 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4737 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4738 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4739 7 + /* gfx_v9_4_3_emit_mem_sync */ 4740 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4741 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4742 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4743 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4744 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4745 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4746 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4747 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4748 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4749 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4750 .test_ring = gfx_v9_4_3_ring_test_ring, 4751 .test_ib = gfx_v9_4_3_ring_test_ib, 4752 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4753 .pad_ib = amdgpu_ring_generic_pad_ib, 4754 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4755 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4756 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4757 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4758 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4759 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4760 .reset = gfx_v9_4_3_reset_kcq, 4761 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4762 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4763 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4764 }; 4765 4766 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4767 .type = AMDGPU_RING_TYPE_KIQ, 4768 .align_mask = 0xff, 4769 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4770 .support_64bit_ptrs = true, 4771 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4772 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4773 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4774 .emit_frame_size = 4775 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4776 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4777 5 + /* hdp invalidate */ 4778 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4779 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4780 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4781 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4782 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4783 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4784 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4785 .test_ring = gfx_v9_4_3_ring_test_ring, 4786 .insert_nop = amdgpu_ring_insert_nop, 4787 .pad_ib = amdgpu_ring_generic_pad_ib, 4788 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4789 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4790 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4791 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4792 }; 4793 4794 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4795 { 4796 int i, j, num_xcc; 4797 4798 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4799 for (i = 0; i < num_xcc; i++) { 4800 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4801 4802 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4803 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4804 = &gfx_v9_4_3_ring_funcs_compute; 4805 } 4806 } 4807 4808 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4809 .set = gfx_v9_4_3_set_eop_interrupt_state, 4810 .process = gfx_v9_4_3_eop_irq, 4811 }; 4812 4813 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4814 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4815 .process = gfx_v9_4_3_priv_reg_irq, 4816 }; 4817 4818 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4819 .set = gfx_v9_4_3_set_bad_op_fault_state, 4820 .process = gfx_v9_4_3_bad_op_irq, 4821 }; 4822 4823 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4824 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4825 .process = gfx_v9_4_3_priv_inst_irq, 4826 }; 4827 4828 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4829 { 4830 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4831 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4832 4833 adev->gfx.priv_reg_irq.num_types = 1; 4834 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4835 4836 adev->gfx.bad_op_irq.num_types = 1; 4837 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4838 4839 adev->gfx.priv_inst_irq.num_types = 1; 4840 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4841 } 4842 4843 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4844 { 4845 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4846 } 4847 4848 4849 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4850 { 4851 /* init asci gds info */ 4852 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4853 case IP_VERSION(9, 4, 3): 4854 case IP_VERSION(9, 4, 4): 4855 /* 9.4.3 removed all the GDS internal memory, 4856 * only support GWS opcode in kernel, like barrier 4857 * semaphore.etc */ 4858 adev->gds.gds_size = 0; 4859 break; 4860 default: 4861 adev->gds.gds_size = 0x10000; 4862 break; 4863 } 4864 4865 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4866 case IP_VERSION(9, 4, 3): 4867 case IP_VERSION(9, 4, 4): 4868 /* deprecated for 9.4.3, no usage at all */ 4869 adev->gds.gds_compute_max_wave_id = 0; 4870 break; 4871 default: 4872 /* this really depends on the chip */ 4873 adev->gds.gds_compute_max_wave_id = 0x7ff; 4874 break; 4875 } 4876 4877 adev->gds.gws_size = 64; 4878 adev->gds.oa_size = 16; 4879 } 4880 4881 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4882 u32 bitmap, int xcc_id) 4883 { 4884 u32 data; 4885 4886 if (!bitmap) 4887 return; 4888 4889 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4890 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4891 4892 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4893 } 4894 4895 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4896 { 4897 u32 data, mask; 4898 4899 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4900 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4901 4902 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4903 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4904 4905 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4906 4907 return (~data) & mask; 4908 } 4909 4910 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4911 struct amdgpu_cu_info *cu_info) 4912 { 4913 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4914 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4915 unsigned disable_masks[4 * 4]; 4916 bool is_symmetric_cus; 4917 4918 if (!adev || !cu_info) 4919 return -EINVAL; 4920 4921 /* 4922 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4923 */ 4924 if (adev->gfx.config.max_shader_engines * 4925 adev->gfx.config.max_sh_per_se > 16) 4926 return -EINVAL; 4927 4928 amdgpu_gfx_parse_disable_cu(disable_masks, 4929 adev->gfx.config.max_shader_engines, 4930 adev->gfx.config.max_sh_per_se); 4931 4932 mutex_lock(&adev->grbm_idx_mutex); 4933 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4934 is_symmetric_cus = true; 4935 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4936 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4937 mask = 1; 4938 ao_bitmap = 0; 4939 counter = 0; 4940 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4941 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4942 adev, 4943 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4944 xcc_id); 4945 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4946 4947 cu_info->bitmap[xcc_id][i][j] = bitmap; 4948 4949 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4950 if (bitmap & mask) { 4951 if (counter < adev->gfx.config.max_cu_per_sh) 4952 ao_bitmap |= mask; 4953 counter++; 4954 } 4955 mask <<= 1; 4956 } 4957 active_cu_number += counter; 4958 if (i < 2 && j < 2) 4959 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4960 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4961 } 4962 if (i && is_symmetric_cus && prev_counter != counter) 4963 is_symmetric_cus = false; 4964 prev_counter = counter; 4965 } 4966 if (is_symmetric_cus) { 4967 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4968 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4969 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4970 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4971 } 4972 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4973 xcc_id); 4974 } 4975 mutex_unlock(&adev->grbm_idx_mutex); 4976 4977 cu_info->number = active_cu_number; 4978 cu_info->ao_cu_mask = ao_cu_mask; 4979 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4980 4981 return 0; 4982 } 4983 4984 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4985 .type = AMD_IP_BLOCK_TYPE_GFX, 4986 .major = 9, 4987 .minor = 4, 4988 .rev = 3, 4989 .funcs = &gfx_v9_4_3_ip_funcs, 4990 }; 4991 4992 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4993 { 4994 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4995 uint32_t tmp_mask; 4996 int i, r; 4997 4998 /* TODO : Initialize golden regs */ 4999 /* gfx_v9_4_3_init_golden_registers(adev); */ 5000 5001 tmp_mask = inst_mask; 5002 for_each_inst(i, tmp_mask) 5003 gfx_v9_4_3_xcc_constants_init(adev, i); 5004 5005 if (!amdgpu_sriov_vf(adev)) { 5006 tmp_mask = inst_mask; 5007 for_each_inst(i, tmp_mask) { 5008 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 5009 if (r) 5010 return r; 5011 } 5012 } 5013 5014 tmp_mask = inst_mask; 5015 for_each_inst(i, tmp_mask) { 5016 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 5017 if (r) 5018 return r; 5019 } 5020 5021 return 0; 5022 } 5023 5024 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 5025 { 5026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5027 int i; 5028 5029 for_each_inst(i, inst_mask) 5030 gfx_v9_4_3_xcc_fini(adev, i); 5031 5032 return 0; 5033 } 5034 5035 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5036 .suspend = &gfx_v9_4_3_xcp_suspend, 5037 .resume = &gfx_v9_4_3_xcp_resume 5038 }; 5039 5040 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5041 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5042 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5043 }; 5044 5045 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5046 { 5047 int r; 5048 5049 r = amdgpu_ras_block_late_init(adev, ras_block); 5050 if (r) 5051 return r; 5052 5053 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5054 &gfx_v9_4_3_aca_info, 5055 NULL); 5056 if (r) 5057 goto late_fini; 5058 5059 return 0; 5060 5061 late_fini: 5062 amdgpu_ras_block_late_fini(adev, ras_block); 5063 5064 return r; 5065 } 5066 5067 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5068 .ras_block = { 5069 .hw_ops = &gfx_v9_4_3_ras_ops, 5070 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5071 }, 5072 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5073 }; 5074