1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* cp header registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP), 111 /* SE status registers */ 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 113 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 115 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 116 }; 117 118 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 119 /* compute queue registers */ 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 157 }; 158 159 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 160 161 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 162 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 163 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 164 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 165 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 166 struct amdgpu_cu_info *cu_info); 167 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 168 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 169 170 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 171 uint64_t queue_mask) 172 { 173 struct amdgpu_device *adev = kiq_ring->adev; 174 u64 shader_mc_addr; 175 176 /* Cleaner shader MC address */ 177 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 178 179 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 180 amdgpu_ring_write(kiq_ring, 181 PACKET3_SET_RESOURCES_VMID_MASK(0) | 182 /* vmid_mask:0* queue_type:0 (KIQ) */ 183 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 184 amdgpu_ring_write(kiq_ring, 185 lower_32_bits(queue_mask)); /* queue mask lo */ 186 amdgpu_ring_write(kiq_ring, 187 upper_32_bits(queue_mask)); /* queue mask hi */ 188 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 189 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 190 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 191 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 192 } 193 194 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 195 struct amdgpu_ring *ring) 196 { 197 struct amdgpu_device *adev = kiq_ring->adev; 198 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 199 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 200 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 201 202 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 203 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 204 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 205 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 206 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 207 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 208 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 209 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 210 /*queue_type: normal compute queue */ 211 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 212 /* alloc format: all_on_one_pipe */ 213 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 214 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 215 /* num_queues: must be 1 */ 216 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 217 amdgpu_ring_write(kiq_ring, 218 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 219 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 220 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 221 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 222 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 223 } 224 225 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 226 struct amdgpu_ring *ring, 227 enum amdgpu_unmap_queues_action action, 228 u64 gpu_addr, u64 seq) 229 { 230 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 231 232 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 233 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 234 PACKET3_UNMAP_QUEUES_ACTION(action) | 235 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 236 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 237 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 238 amdgpu_ring_write(kiq_ring, 239 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 240 241 if (action == PREEMPT_QUEUES_NO_UNMAP) { 242 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 243 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 244 amdgpu_ring_write(kiq_ring, seq); 245 } else { 246 amdgpu_ring_write(kiq_ring, 0); 247 amdgpu_ring_write(kiq_ring, 0); 248 amdgpu_ring_write(kiq_ring, 0); 249 } 250 } 251 252 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 253 struct amdgpu_ring *ring, 254 u64 addr, 255 u64 seq) 256 { 257 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 258 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 260 amdgpu_ring_write(kiq_ring, 261 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 262 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 263 PACKET3_QUERY_STATUS_COMMAND(2)); 264 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 267 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 268 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 269 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 270 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 271 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 272 } 273 274 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 275 uint16_t pasid, uint32_t flush_type, 276 bool all_hub) 277 { 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 279 amdgpu_ring_write(kiq_ring, 280 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 281 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 282 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 283 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 284 } 285 286 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 287 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 288 uint32_t xcc_id, uint32_t vmid) 289 { 290 struct amdgpu_device *adev = kiq_ring->adev; 291 unsigned i; 292 293 /* enter save mode */ 294 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 295 mutex_lock(&adev->srbm_mutex); 296 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 297 298 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 301 /* wait till dequeue take effects */ 302 for (i = 0; i < adev->usec_timeout; i++) { 303 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 304 break; 305 udelay(1); 306 } 307 if (i >= adev->usec_timeout) 308 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 309 } else { 310 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 311 } 312 313 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 314 mutex_unlock(&adev->srbm_mutex); 315 /* exit safe mode */ 316 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 317 } 318 319 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 320 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 321 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 322 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 323 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 324 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 325 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 326 .set_resources_size = 8, 327 .map_queues_size = 7, 328 .unmap_queues_size = 6, 329 .query_status_size = 7, 330 .invalidate_tlbs_size = 2, 331 }; 332 333 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 334 { 335 int i, num_xcc; 336 337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 338 for (i = 0; i < num_xcc; i++) 339 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 340 } 341 342 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 343 { 344 int i, num_xcc, dev_inst; 345 346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 347 for (i = 0; i < num_xcc; i++) { 348 dev_inst = GET_INST(GC, i); 349 350 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 351 GOLDEN_GB_ADDR_CONFIG); 352 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 353 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 354 } else { 355 /* Golden settings applied by driver for ASIC with rev_id 0 */ 356 if (adev->rev_id == 0) { 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 358 REDUCE_FIFO_DEPTH_BY_2, 2); 359 } else { 360 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 361 SPARE, 0x1); 362 } 363 } 364 } 365 } 366 367 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 368 { 369 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 370 371 /* If it is an XCC reg, normalize the reg to keep 372 lower 16 bits in local xcc */ 373 374 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 375 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 376 return normalized_reg; 377 else 378 return reg; 379 } 380 381 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 382 bool wc, uint32_t reg, uint32_t val) 383 { 384 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 385 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 386 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 387 WRITE_DATA_DST_SEL(0) | 388 (wc ? WR_CONFIRM : 0)); 389 amdgpu_ring_write(ring, reg); 390 amdgpu_ring_write(ring, 0); 391 amdgpu_ring_write(ring, val); 392 } 393 394 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 395 int mem_space, int opt, uint32_t addr0, 396 uint32_t addr1, uint32_t ref, uint32_t mask, 397 uint32_t inv) 398 { 399 /* Only do the normalization on regspace */ 400 if (mem_space == 0) { 401 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 402 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 403 } 404 405 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 406 amdgpu_ring_write(ring, 407 /* memory (1) or register (0) */ 408 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 409 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 410 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 411 WAIT_REG_MEM_ENGINE(eng_sel))); 412 413 if (mem_space) 414 BUG_ON(addr0 & 0x3); /* Dword align */ 415 amdgpu_ring_write(ring, addr0); 416 amdgpu_ring_write(ring, addr1); 417 amdgpu_ring_write(ring, ref); 418 amdgpu_ring_write(ring, mask); 419 amdgpu_ring_write(ring, inv); /* poll interval */ 420 } 421 422 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 423 { 424 uint32_t scratch_reg0_offset, xcc_offset; 425 struct amdgpu_device *adev = ring->adev; 426 uint32_t tmp = 0; 427 unsigned i; 428 int r; 429 430 /* Use register offset which is local to XCC in the packet */ 431 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 432 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 433 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 434 tmp = RREG32(scratch_reg0_offset); 435 436 r = amdgpu_ring_alloc(ring, 3); 437 if (r) 438 return r; 439 440 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 441 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 442 amdgpu_ring_write(ring, 0xDEADBEEF); 443 amdgpu_ring_commit(ring); 444 445 for (i = 0; i < adev->usec_timeout; i++) { 446 tmp = RREG32(scratch_reg0_offset); 447 if (tmp == 0xDEADBEEF) 448 break; 449 udelay(1); 450 } 451 452 if (i >= adev->usec_timeout) 453 r = -ETIMEDOUT; 454 return r; 455 } 456 457 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 458 { 459 struct amdgpu_device *adev = ring->adev; 460 struct amdgpu_ib ib; 461 struct dma_fence *f = NULL; 462 463 unsigned index; 464 uint64_t gpu_addr; 465 uint32_t tmp; 466 long r; 467 468 r = amdgpu_device_wb_get(adev, &index); 469 if (r) 470 return r; 471 472 gpu_addr = adev->wb.gpu_addr + (index * 4); 473 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 474 memset(&ib, 0, sizeof(ib)); 475 476 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 477 if (r) 478 goto err1; 479 480 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 481 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 482 ib.ptr[2] = lower_32_bits(gpu_addr); 483 ib.ptr[3] = upper_32_bits(gpu_addr); 484 ib.ptr[4] = 0xDEADBEEF; 485 ib.length_dw = 5; 486 487 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 488 if (r) 489 goto err2; 490 491 r = dma_fence_wait_timeout(f, false, timeout); 492 if (r == 0) { 493 r = -ETIMEDOUT; 494 goto err2; 495 } else if (r < 0) { 496 goto err2; 497 } 498 499 tmp = adev->wb.wb[index]; 500 if (tmp == 0xDEADBEEF) 501 r = 0; 502 else 503 r = -EINVAL; 504 505 err2: 506 amdgpu_ib_free(&ib, NULL); 507 dma_fence_put(f); 508 err1: 509 amdgpu_device_wb_free(adev, index); 510 return r; 511 } 512 513 514 /* This value might differs per partition */ 515 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 516 { 517 uint64_t clock; 518 519 mutex_lock(&adev->gfx.gpu_clock_mutex); 520 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 521 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 522 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 523 mutex_unlock(&adev->gfx.gpu_clock_mutex); 524 525 return clock; 526 } 527 528 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 529 { 530 amdgpu_ucode_release(&adev->gfx.pfp_fw); 531 amdgpu_ucode_release(&adev->gfx.me_fw); 532 amdgpu_ucode_release(&adev->gfx.ce_fw); 533 amdgpu_ucode_release(&adev->gfx.rlc_fw); 534 amdgpu_ucode_release(&adev->gfx.mec_fw); 535 amdgpu_ucode_release(&adev->gfx.mec2_fw); 536 537 kfree(adev->gfx.rlc.register_list_format); 538 } 539 540 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 541 const char *chip_name) 542 { 543 int err; 544 const struct rlc_firmware_header_v2_0 *rlc_hdr; 545 uint16_t version_major; 546 uint16_t version_minor; 547 548 549 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 550 AMDGPU_UCODE_REQUIRED, 551 "amdgpu/%s_rlc.bin", chip_name); 552 if (err) 553 goto out; 554 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 555 556 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 557 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 558 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 559 out: 560 if (err) 561 amdgpu_ucode_release(&adev->gfx.rlc_fw); 562 563 return err; 564 } 565 566 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 567 { 568 return true; 569 } 570 571 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 572 { 573 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 574 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 575 } 576 577 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 578 const char *chip_name) 579 { 580 int err; 581 582 if (amdgpu_sriov_vf(adev)) 583 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 584 AMDGPU_UCODE_REQUIRED, 585 "amdgpu/%s_sjt_mec.bin", chip_name); 586 else 587 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 588 AMDGPU_UCODE_REQUIRED, 589 "amdgpu/%s_mec.bin", chip_name); 590 if (err) 591 goto out; 592 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 593 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 594 595 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 596 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 597 598 gfx_v9_4_3_check_if_need_gfxoff(adev); 599 600 out: 601 if (err) 602 amdgpu_ucode_release(&adev->gfx.mec_fw); 603 return err; 604 } 605 606 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 607 { 608 char ucode_prefix[15]; 609 int r; 610 611 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 612 613 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 614 if (r) 615 return r; 616 617 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 618 if (r) 619 return r; 620 621 return r; 622 } 623 624 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 625 { 626 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 627 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 628 } 629 630 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 631 { 632 int r, i, num_xcc; 633 u32 *hpd; 634 const __le32 *fw_data; 635 unsigned fw_size; 636 u32 *fw; 637 size_t mec_hpd_size; 638 639 const struct gfx_firmware_header_v1_0 *mec_hdr; 640 641 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 642 for (i = 0; i < num_xcc; i++) 643 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 644 AMDGPU_MAX_COMPUTE_QUEUES); 645 646 /* take ownership of the relevant compute queues */ 647 amdgpu_gfx_compute_queue_acquire(adev); 648 mec_hpd_size = 649 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 650 if (mec_hpd_size) { 651 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 652 AMDGPU_GEM_DOMAIN_VRAM | 653 AMDGPU_GEM_DOMAIN_GTT, 654 &adev->gfx.mec.hpd_eop_obj, 655 &adev->gfx.mec.hpd_eop_gpu_addr, 656 (void **)&hpd); 657 if (r) { 658 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 659 gfx_v9_4_3_mec_fini(adev); 660 return r; 661 } 662 663 if (amdgpu_emu_mode == 1) { 664 for (i = 0; i < mec_hpd_size / 4; i++) { 665 memset((void *)(hpd + i), 0, 4); 666 if (i % 50 == 0) 667 msleep(1); 668 } 669 } else { 670 memset(hpd, 0, mec_hpd_size); 671 } 672 673 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 674 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 675 } 676 677 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 678 679 fw_data = (const __le32 *) 680 (adev->gfx.mec_fw->data + 681 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 682 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 683 684 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 685 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 686 &adev->gfx.mec.mec_fw_obj, 687 &adev->gfx.mec.mec_fw_gpu_addr, 688 (void **)&fw); 689 if (r) { 690 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 691 gfx_v9_4_3_mec_fini(adev); 692 return r; 693 } 694 695 memcpy(fw, fw_data, fw_size); 696 697 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 698 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 699 700 return 0; 701 } 702 703 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 704 u32 sh_num, u32 instance, int xcc_id) 705 { 706 u32 data; 707 708 if (instance == 0xffffffff) 709 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 710 INSTANCE_BROADCAST_WRITES, 1); 711 else 712 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 713 INSTANCE_INDEX, instance); 714 715 if (se_num == 0xffffffff) 716 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 717 SE_BROADCAST_WRITES, 1); 718 else 719 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 720 721 if (sh_num == 0xffffffff) 722 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 723 SH_BROADCAST_WRITES, 1); 724 else 725 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 726 727 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 728 } 729 730 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 731 { 732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 733 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 734 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 735 (address << SQ_IND_INDEX__INDEX__SHIFT) | 736 (SQ_IND_INDEX__FORCE_READ_MASK)); 737 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 738 } 739 740 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 741 uint32_t wave, uint32_t thread, 742 uint32_t regno, uint32_t num, uint32_t *out) 743 { 744 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 745 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 746 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 747 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 748 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 749 (SQ_IND_INDEX__FORCE_READ_MASK) | 750 (SQ_IND_INDEX__AUTO_INCR_MASK)); 751 while (num--) 752 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 753 } 754 755 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 756 uint32_t xcc_id, uint32_t simd, uint32_t wave, 757 uint32_t *dst, int *no_fields) 758 { 759 /* type 1 wave data */ 760 dst[(*no_fields)++] = 1; 761 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 762 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 763 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 764 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 765 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 766 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 767 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 768 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 769 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 770 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 771 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 772 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 773 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 774 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 775 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 776 } 777 778 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 779 uint32_t wave, uint32_t start, 780 uint32_t size, uint32_t *dst) 781 { 782 wave_read_regs(adev, xcc_id, simd, wave, 0, 783 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 784 } 785 786 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 787 uint32_t wave, uint32_t thread, 788 uint32_t start, uint32_t size, 789 uint32_t *dst) 790 { 791 wave_read_regs(adev, xcc_id, simd, wave, thread, 792 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 793 } 794 795 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 796 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 797 { 798 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 799 } 800 801 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 802 { 803 u32 xcp_ctl; 804 805 /* Value is expected to be the same on all, fetch from first instance */ 806 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 807 808 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 809 } 810 811 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 812 int num_xccs_per_xcp) 813 { 814 int ret, i, num_xcc; 815 u32 tmp = 0; 816 817 if (adev->psp.funcs) { 818 ret = psp_spatial_partition(&adev->psp, 819 NUM_XCC(adev->gfx.xcc_mask) / 820 num_xccs_per_xcp); 821 if (ret) 822 return ret; 823 } else { 824 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 825 826 for (i = 0; i < num_xcc; i++) { 827 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 828 num_xccs_per_xcp); 829 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 830 i % num_xccs_per_xcp); 831 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 832 tmp); 833 } 834 ret = 0; 835 } 836 837 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 838 839 return ret; 840 } 841 842 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 843 { 844 int xcc; 845 846 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 847 if (!xcc) { 848 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 849 return -EINVAL; 850 } 851 852 return xcc - 1; 853 } 854 855 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 856 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 857 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 858 .read_wave_data = &gfx_v9_4_3_read_wave_data, 859 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 860 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 861 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 862 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 863 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 864 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 865 }; 866 867 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 868 struct aca_bank *bank, enum aca_smu_type type, 869 void *data) 870 { 871 struct aca_bank_info info; 872 u64 misc0; 873 u32 instlo; 874 int ret; 875 876 ret = aca_bank_info_decode(bank, &info); 877 if (ret) 878 return ret; 879 880 /* NOTE: overwrite info.die_id with xcd id for gfx */ 881 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 882 instlo &= GENMASK(31, 1); 883 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 884 885 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 886 887 switch (type) { 888 case ACA_SMU_TYPE_UE: 889 ret = aca_error_cache_log_bank_error(handle, &info, 890 ACA_ERROR_TYPE_UE, 1ULL); 891 break; 892 case ACA_SMU_TYPE_CE: 893 ret = aca_error_cache_log_bank_error(handle, &info, 894 ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0)); 895 break; 896 default: 897 return -EINVAL; 898 } 899 900 return ret; 901 } 902 903 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 904 enum aca_smu_type type, void *data) 905 { 906 u32 instlo; 907 908 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 909 instlo &= GENMASK(31, 1); 910 switch (instlo) { 911 case mmSMNAID_XCD0_MCA_SMU: 912 case mmSMNAID_XCD1_MCA_SMU: 913 case mmSMNXCD_XCD0_MCA_SMU: 914 return true; 915 default: 916 break; 917 } 918 919 return false; 920 } 921 922 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 923 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 924 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 925 }; 926 927 static const struct aca_info gfx_v9_4_3_aca_info = { 928 .hwip = ACA_HWIP_TYPE_SMU, 929 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 930 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 931 }; 932 933 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 934 { 935 u32 gb_addr_config; 936 937 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 938 adev->gfx.ras = &gfx_v9_4_3_ras; 939 940 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 941 case IP_VERSION(9, 4, 3): 942 case IP_VERSION(9, 4, 4): 943 case IP_VERSION(9, 5, 0): 944 adev->gfx.config.max_hw_contexts = 8; 945 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 946 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 947 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 948 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 949 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 950 break; 951 default: 952 BUG(); 953 break; 954 } 955 956 adev->gfx.config.gb_addr_config = gb_addr_config; 957 958 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 959 REG_GET_FIELD( 960 adev->gfx.config.gb_addr_config, 961 GB_ADDR_CONFIG, 962 NUM_PIPES); 963 964 adev->gfx.config.max_tile_pipes = 965 adev->gfx.config.gb_addr_config_fields.num_pipes; 966 967 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 968 REG_GET_FIELD( 969 adev->gfx.config.gb_addr_config, 970 GB_ADDR_CONFIG, 971 NUM_BANKS); 972 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 973 REG_GET_FIELD( 974 adev->gfx.config.gb_addr_config, 975 GB_ADDR_CONFIG, 976 MAX_COMPRESSED_FRAGS); 977 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 978 REG_GET_FIELD( 979 adev->gfx.config.gb_addr_config, 980 GB_ADDR_CONFIG, 981 NUM_RB_PER_SE); 982 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 983 REG_GET_FIELD( 984 adev->gfx.config.gb_addr_config, 985 GB_ADDR_CONFIG, 986 NUM_SHADER_ENGINES); 987 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 988 REG_GET_FIELD( 989 adev->gfx.config.gb_addr_config, 990 GB_ADDR_CONFIG, 991 PIPE_INTERLEAVE_SIZE)); 992 993 return 0; 994 } 995 996 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 997 int xcc_id, int mec, int pipe, int queue) 998 { 999 unsigned irq_type; 1000 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1001 unsigned int hw_prio; 1002 uint32_t xcc_doorbell_start; 1003 1004 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 1005 ring_id]; 1006 1007 /* mec0 is me1 */ 1008 ring->xcc_id = xcc_id; 1009 ring->me = mec + 1; 1010 ring->pipe = pipe; 1011 ring->queue = queue; 1012 1013 ring->ring_obj = NULL; 1014 ring->use_doorbell = true; 1015 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 1016 xcc_id * adev->doorbell_index.xcc_doorbell_range; 1017 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 1018 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 1019 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 1020 GFX9_MEC_HPD_SIZE; 1021 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1022 sprintf(ring->name, "comp_%d.%d.%d.%d", 1023 ring->xcc_id, ring->me, ring->pipe, ring->queue); 1024 1025 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1026 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1027 + ring->pipe; 1028 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1029 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1030 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1031 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1032 hw_prio, NULL); 1033 } 1034 1035 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1036 { 1037 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1038 uint32_t *ptr, num_xcc, inst; 1039 1040 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1041 1042 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1043 if (!ptr) { 1044 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1045 adev->gfx.ip_dump_core = NULL; 1046 } else { 1047 adev->gfx.ip_dump_core = ptr; 1048 } 1049 1050 /* Allocate memory for compute queue registers for all the instances */ 1051 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1052 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1053 adev->gfx.mec.num_queue_per_pipe; 1054 1055 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1056 if (!ptr) { 1057 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1058 adev->gfx.ip_dump_compute_queues = NULL; 1059 } else { 1060 adev->gfx.ip_dump_compute_queues = ptr; 1061 } 1062 } 1063 1064 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1065 { 1066 int i, j, k, r, ring_id, xcc_id, num_xcc; 1067 struct amdgpu_device *adev = ip_block->adev; 1068 1069 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1070 case IP_VERSION(9, 4, 3): 1071 case IP_VERSION(9, 4, 4): 1072 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1073 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1074 if (adev->gfx.mec_fw_version >= 153) { 1075 adev->gfx.enable_cleaner_shader = true; 1076 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1077 if (r) { 1078 adev->gfx.enable_cleaner_shader = false; 1079 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1080 } 1081 } 1082 break; 1083 default: 1084 adev->gfx.enable_cleaner_shader = false; 1085 break; 1086 } 1087 1088 adev->gfx.mec.num_mec = 2; 1089 adev->gfx.mec.num_pipe_per_mec = 4; 1090 adev->gfx.mec.num_queue_per_pipe = 8; 1091 1092 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1093 1094 /* EOP Event */ 1095 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1096 if (r) 1097 return r; 1098 1099 /* Bad opcode Event */ 1100 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1101 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1102 &adev->gfx.bad_op_irq); 1103 if (r) 1104 return r; 1105 1106 /* Privileged reg */ 1107 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1108 &adev->gfx.priv_reg_irq); 1109 if (r) 1110 return r; 1111 1112 /* Privileged inst */ 1113 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1114 &adev->gfx.priv_inst_irq); 1115 if (r) 1116 return r; 1117 1118 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1119 1120 r = adev->gfx.rlc.funcs->init(adev); 1121 if (r) { 1122 DRM_ERROR("Failed to init rlc BOs!\n"); 1123 return r; 1124 } 1125 1126 r = gfx_v9_4_3_mec_init(adev); 1127 if (r) { 1128 DRM_ERROR("Failed to init MEC BOs!\n"); 1129 return r; 1130 } 1131 1132 /* set up the compute queues - allocate horizontally across pipes */ 1133 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1134 ring_id = 0; 1135 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1136 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1137 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1138 k++) { 1139 if (!amdgpu_gfx_is_mec_queue_enabled( 1140 adev, xcc_id, i, k, j)) 1141 continue; 1142 1143 r = gfx_v9_4_3_compute_ring_init(adev, 1144 ring_id, 1145 xcc_id, 1146 i, k, j); 1147 if (r) 1148 return r; 1149 1150 ring_id++; 1151 } 1152 } 1153 } 1154 1155 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1156 if (r) { 1157 DRM_ERROR("Failed to init KIQ BOs!\n"); 1158 return r; 1159 } 1160 1161 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1162 if (r) 1163 return r; 1164 1165 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1166 r = amdgpu_gfx_mqd_sw_init(adev, 1167 sizeof(struct v9_mqd_allocation), xcc_id); 1168 if (r) 1169 return r; 1170 } 1171 1172 adev->gfx.compute_supported_reset = 1173 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1174 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1175 case IP_VERSION(9, 4, 3): 1176 case IP_VERSION(9, 4, 4): 1177 if (adev->gfx.mec_fw_version >= 155) { 1178 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1179 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1180 } 1181 break; 1182 default: 1183 break; 1184 } 1185 r = gfx_v9_4_3_gpu_early_init(adev); 1186 if (r) 1187 return r; 1188 1189 r = amdgpu_gfx_ras_sw_init(adev); 1190 if (r) 1191 return r; 1192 1193 r = amdgpu_gfx_sysfs_init(adev); 1194 if (r) 1195 return r; 1196 1197 gfx_v9_4_3_alloc_ip_dump(adev); 1198 1199 return 0; 1200 } 1201 1202 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1203 { 1204 int i, num_xcc; 1205 struct amdgpu_device *adev = ip_block->adev; 1206 1207 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1208 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1209 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1210 1211 for (i = 0; i < num_xcc; i++) { 1212 amdgpu_gfx_mqd_sw_fini(adev, i); 1213 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1214 amdgpu_gfx_kiq_fini(adev, i); 1215 } 1216 1217 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1218 1219 gfx_v9_4_3_mec_fini(adev); 1220 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1221 gfx_v9_4_3_free_microcode(adev); 1222 amdgpu_gfx_sysfs_fini(adev); 1223 1224 kfree(adev->gfx.ip_dump_core); 1225 kfree(adev->gfx.ip_dump_compute_queues); 1226 1227 return 0; 1228 } 1229 1230 #define DEFAULT_SH_MEM_BASES (0x6000) 1231 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1232 int xcc_id) 1233 { 1234 int i; 1235 uint32_t sh_mem_config; 1236 uint32_t sh_mem_bases; 1237 uint32_t data; 1238 1239 /* 1240 * Configure apertures: 1241 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1242 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1243 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1244 */ 1245 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1246 1247 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1248 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1249 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1250 1251 mutex_lock(&adev->srbm_mutex); 1252 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1253 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1254 /* CP and shaders */ 1255 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1256 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1257 1258 /* Enable trap for each kfd vmid. */ 1259 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1260 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1261 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1262 } 1263 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1264 mutex_unlock(&adev->srbm_mutex); 1265 1266 /* 1267 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1268 * access. These should be enabled by FW for target VMIDs. 1269 */ 1270 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1271 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1272 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1273 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1274 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1275 } 1276 } 1277 1278 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1279 { 1280 int vmid; 1281 1282 /* 1283 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1284 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1285 * the driver can enable them for graphics. VMID0 should maintain 1286 * access so that HWS firmware can save/restore entries. 1287 */ 1288 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1289 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1290 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1291 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1292 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1293 } 1294 } 1295 1296 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1297 int xcc_id) 1298 { 1299 u32 tmp; 1300 int i; 1301 1302 /* XXX SH_MEM regs */ 1303 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1304 mutex_lock(&adev->srbm_mutex); 1305 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1306 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1307 /* CP and shaders */ 1308 if (i == 0) { 1309 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1310 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1311 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1312 !!adev->gmc.noretry); 1313 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1314 regSH_MEM_CONFIG, tmp); 1315 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1316 regSH_MEM_BASES, 0); 1317 } else { 1318 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1319 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1320 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1321 !!adev->gmc.noretry); 1322 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1323 regSH_MEM_CONFIG, tmp); 1324 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1325 (adev->gmc.private_aperture_start >> 1326 48)); 1327 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1328 (adev->gmc.shared_aperture_start >> 1329 48)); 1330 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1331 regSH_MEM_BASES, tmp); 1332 } 1333 } 1334 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1335 1336 mutex_unlock(&adev->srbm_mutex); 1337 1338 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1339 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1340 } 1341 1342 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1343 { 1344 int i, num_xcc; 1345 1346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1347 1348 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1349 adev->gfx.config.db_debug2 = 1350 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1351 1352 for (i = 0; i < num_xcc; i++) 1353 gfx_v9_4_3_xcc_constants_init(adev, i); 1354 } 1355 1356 static void 1357 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1358 int xcc_id) 1359 { 1360 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1361 } 1362 1363 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1364 { 1365 /* 1366 * Rlc save restore list is workable since v2_1. 1367 * And it's needed by gfxoff feature. 1368 */ 1369 if (adev->gfx.rlc.is_rlc_v2_1) 1370 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1371 } 1372 1373 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1374 { 1375 uint32_t data; 1376 1377 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1378 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1379 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1380 } 1381 1382 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1383 { 1384 uint32_t rlc_setting; 1385 1386 /* if RLC is not enabled, do nothing */ 1387 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1388 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1389 return false; 1390 1391 return true; 1392 } 1393 1394 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1395 { 1396 uint32_t data; 1397 unsigned i; 1398 1399 data = RLC_SAFE_MODE__CMD_MASK; 1400 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1401 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1402 1403 /* wait for RLC_SAFE_MODE */ 1404 for (i = 0; i < adev->usec_timeout; i++) { 1405 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1406 break; 1407 udelay(1); 1408 } 1409 } 1410 1411 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1412 int xcc_id) 1413 { 1414 uint32_t data; 1415 1416 data = RLC_SAFE_MODE__CMD_MASK; 1417 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1418 } 1419 1420 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1421 { 1422 int xcc_id, num_xcc; 1423 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1424 1425 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1426 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1427 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1428 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1429 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1430 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1431 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1432 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1433 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1434 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1435 } 1436 adev->gfx.rlc.rlcg_reg_access_supported = true; 1437 } 1438 1439 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1440 { 1441 /* init spm vmid with 0xf */ 1442 if (adev->gfx.rlc.funcs->update_spm_vmid) 1443 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1444 1445 return 0; 1446 } 1447 1448 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1449 int xcc_id) 1450 { 1451 u32 i, j, k; 1452 u32 mask; 1453 1454 mutex_lock(&adev->grbm_idx_mutex); 1455 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1456 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1457 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1458 xcc_id); 1459 for (k = 0; k < adev->usec_timeout; k++) { 1460 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1461 break; 1462 udelay(1); 1463 } 1464 if (k == adev->usec_timeout) { 1465 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1466 0xffffffff, 1467 0xffffffff, xcc_id); 1468 mutex_unlock(&adev->grbm_idx_mutex); 1469 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1470 i, j); 1471 return; 1472 } 1473 } 1474 } 1475 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1476 xcc_id); 1477 mutex_unlock(&adev->grbm_idx_mutex); 1478 1479 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1480 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1481 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1482 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1483 for (k = 0; k < adev->usec_timeout; k++) { 1484 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1485 break; 1486 udelay(1); 1487 } 1488 } 1489 1490 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1491 bool enable, int xcc_id) 1492 { 1493 u32 tmp; 1494 1495 /* These interrupts should be enabled to drive DS clock */ 1496 1497 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1498 1499 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1500 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1501 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1502 1503 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1504 } 1505 1506 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1507 { 1508 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1509 RLC_ENABLE_F32, 0); 1510 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1511 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1512 } 1513 1514 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1515 { 1516 int i, num_xcc; 1517 1518 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1519 for (i = 0; i < num_xcc; i++) 1520 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1521 } 1522 1523 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1524 { 1525 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1526 SOFT_RESET_RLC, 1); 1527 udelay(50); 1528 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1529 SOFT_RESET_RLC, 0); 1530 udelay(50); 1531 } 1532 1533 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1534 { 1535 int i, num_xcc; 1536 1537 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1538 for (i = 0; i < num_xcc; i++) 1539 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1540 } 1541 1542 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1543 { 1544 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1545 RLC_ENABLE_F32, 1); 1546 udelay(50); 1547 1548 /* carrizo do enable cp interrupt after cp inited */ 1549 if (!(adev->flags & AMD_IS_APU)) { 1550 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1551 udelay(50); 1552 } 1553 } 1554 1555 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1556 { 1557 #ifdef AMDGPU_RLC_DEBUG_RETRY 1558 u32 rlc_ucode_ver; 1559 #endif 1560 int i, num_xcc; 1561 1562 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1563 for (i = 0; i < num_xcc; i++) { 1564 gfx_v9_4_3_xcc_rlc_start(adev, i); 1565 #ifdef AMDGPU_RLC_DEBUG_RETRY 1566 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1567 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1568 if (rlc_ucode_ver == 0x108) { 1569 dev_info(adev->dev, 1570 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1571 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1572 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1573 * default is 0x9C4 to create a 100us interval */ 1574 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1575 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1576 * to disable the page fault retry interrupts, default is 1577 * 0x100 (256) */ 1578 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1579 } 1580 #endif 1581 } 1582 } 1583 1584 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1585 int xcc_id) 1586 { 1587 const struct rlc_firmware_header_v2_0 *hdr; 1588 const __le32 *fw_data; 1589 unsigned i, fw_size; 1590 1591 if (!adev->gfx.rlc_fw) 1592 return -EINVAL; 1593 1594 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1595 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1596 1597 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1598 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1599 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1600 1601 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1602 RLCG_UCODE_LOADING_START_ADDRESS); 1603 for (i = 0; i < fw_size; i++) { 1604 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1605 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1606 msleep(1); 1607 } 1608 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1609 } 1610 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1611 1612 return 0; 1613 } 1614 1615 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1616 { 1617 int r; 1618 1619 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1620 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1621 /* legacy rlc firmware loading */ 1622 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1623 if (r) 1624 return r; 1625 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1626 } 1627 1628 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1629 /* disable CG */ 1630 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1631 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1632 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1633 1634 return 0; 1635 } 1636 1637 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1638 { 1639 int r, i, num_xcc; 1640 1641 if (amdgpu_sriov_vf(adev)) 1642 return 0; 1643 1644 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1645 for (i = 0; i < num_xcc; i++) { 1646 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1647 if (r) 1648 return r; 1649 } 1650 1651 return 0; 1652 } 1653 1654 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1655 unsigned vmid) 1656 { 1657 u32 reg, pre_data, data; 1658 1659 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1660 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1661 pre_data = RREG32_NO_KIQ(reg); 1662 else 1663 pre_data = RREG32(reg); 1664 1665 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1666 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1667 1668 if (pre_data != data) { 1669 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1670 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1671 } else 1672 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1673 } 1674 } 1675 1676 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1677 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1678 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1679 }; 1680 1681 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1682 uint32_t offset, 1683 struct soc15_reg_rlcg *entries, int arr_size) 1684 { 1685 int i, inst; 1686 uint32_t reg; 1687 1688 if (!entries) 1689 return false; 1690 1691 for (i = 0; i < arr_size; i++) { 1692 const struct soc15_reg_rlcg *entry; 1693 1694 entry = &entries[i]; 1695 inst = adev->ip_map.logical_to_dev_inst ? 1696 adev->ip_map.logical_to_dev_inst( 1697 adev, entry->hwip, entry->instance) : 1698 entry->instance; 1699 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1700 entry->reg; 1701 if (offset == reg) 1702 return true; 1703 } 1704 1705 return false; 1706 } 1707 1708 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1709 { 1710 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1711 (void *)rlcg_access_gc_9_4_3, 1712 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1713 } 1714 1715 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1716 bool enable, int xcc_id) 1717 { 1718 if (enable) { 1719 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1720 } else { 1721 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1722 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1723 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1724 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1725 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1726 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1727 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1728 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1729 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1730 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1731 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1732 } 1733 udelay(50); 1734 } 1735 1736 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1737 int xcc_id) 1738 { 1739 const struct gfx_firmware_header_v1_0 *mec_hdr; 1740 const __le32 *fw_data; 1741 unsigned i; 1742 u32 tmp; 1743 u32 mec_ucode_addr_offset; 1744 u32 mec_ucode_data_offset; 1745 1746 if (!adev->gfx.mec_fw) 1747 return -EINVAL; 1748 1749 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1750 1751 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1752 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1753 1754 fw_data = (const __le32 *) 1755 (adev->gfx.mec_fw->data + 1756 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1757 tmp = 0; 1758 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1759 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1760 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1761 1762 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1763 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1764 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1765 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1766 1767 mec_ucode_addr_offset = 1768 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1769 mec_ucode_data_offset = 1770 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1771 1772 /* MEC1 */ 1773 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1774 for (i = 0; i < mec_hdr->jt_size; i++) 1775 WREG32(mec_ucode_data_offset, 1776 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1777 1778 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1779 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1780 1781 return 0; 1782 } 1783 1784 /* KIQ functions */ 1785 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1786 { 1787 uint32_t tmp; 1788 struct amdgpu_device *adev = ring->adev; 1789 1790 /* tell RLC which is KIQ queue */ 1791 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1792 tmp &= 0xffffff00; 1793 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1794 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1795 } 1796 1797 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1798 { 1799 struct amdgpu_device *adev = ring->adev; 1800 1801 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1802 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1803 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1804 mqd->cp_hqd_queue_priority = 1805 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1806 } 1807 } 1808 } 1809 1810 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1811 { 1812 struct amdgpu_device *adev = ring->adev; 1813 struct v9_mqd *mqd = ring->mqd_ptr; 1814 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1815 uint32_t tmp; 1816 1817 mqd->header = 0xC0310800; 1818 mqd->compute_pipelinestat_enable = 0x00000001; 1819 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1820 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1821 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1822 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1823 mqd->compute_misc_reserved = 0x00000003; 1824 1825 mqd->dynamic_cu_mask_addr_lo = 1826 lower_32_bits(ring->mqd_gpu_addr 1827 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1828 mqd->dynamic_cu_mask_addr_hi = 1829 upper_32_bits(ring->mqd_gpu_addr 1830 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1831 1832 eop_base_addr = ring->eop_gpu_addr >> 8; 1833 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1834 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1835 1836 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1837 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1838 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1839 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1840 1841 mqd->cp_hqd_eop_control = tmp; 1842 1843 /* enable doorbell? */ 1844 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1845 1846 if (ring->use_doorbell) { 1847 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1848 DOORBELL_OFFSET, ring->doorbell_index); 1849 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1850 DOORBELL_EN, 1); 1851 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1852 DOORBELL_SOURCE, 0); 1853 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1854 DOORBELL_HIT, 0); 1855 if (amdgpu_sriov_vf(adev)) 1856 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1857 DOORBELL_MODE, 1); 1858 } else { 1859 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1860 DOORBELL_EN, 0); 1861 } 1862 1863 mqd->cp_hqd_pq_doorbell_control = tmp; 1864 1865 /* disable the queue if it's active */ 1866 ring->wptr = 0; 1867 mqd->cp_hqd_dequeue_request = 0; 1868 mqd->cp_hqd_pq_rptr = 0; 1869 mqd->cp_hqd_pq_wptr_lo = 0; 1870 mqd->cp_hqd_pq_wptr_hi = 0; 1871 1872 /* set the pointer to the MQD */ 1873 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1874 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1875 1876 /* set MQD vmid to 0 */ 1877 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1878 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1879 mqd->cp_mqd_control = tmp; 1880 1881 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1882 hqd_gpu_addr = ring->gpu_addr >> 8; 1883 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1884 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1885 1886 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1887 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1888 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1889 (order_base_2(ring->ring_size / 4) - 1)); 1890 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1891 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1892 #ifdef __BIG_ENDIAN 1893 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1894 #endif 1895 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1896 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1897 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1898 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1899 mqd->cp_hqd_pq_control = tmp; 1900 1901 /* set the wb address whether it's enabled or not */ 1902 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1903 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1904 mqd->cp_hqd_pq_rptr_report_addr_hi = 1905 upper_32_bits(wb_gpu_addr) & 0xffff; 1906 1907 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1908 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1909 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1910 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1911 1912 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1913 ring->wptr = 0; 1914 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1915 1916 /* set the vmid for the queue */ 1917 mqd->cp_hqd_vmid = 0; 1918 1919 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1920 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1921 mqd->cp_hqd_persistent_state = tmp; 1922 1923 /* set MIN_IB_AVAIL_SIZE */ 1924 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1925 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1926 mqd->cp_hqd_ib_control = tmp; 1927 1928 /* set static priority for a queue/ring */ 1929 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1930 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1931 1932 /* map_queues packet doesn't need activate the queue, 1933 * so only kiq need set this field. 1934 */ 1935 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1936 mqd->cp_hqd_active = 1; 1937 1938 return 0; 1939 } 1940 1941 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1942 int xcc_id) 1943 { 1944 struct amdgpu_device *adev = ring->adev; 1945 struct v9_mqd *mqd = ring->mqd_ptr; 1946 int j; 1947 1948 /* disable wptr polling */ 1949 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1950 1951 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1952 mqd->cp_hqd_eop_base_addr_lo); 1953 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1954 mqd->cp_hqd_eop_base_addr_hi); 1955 1956 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1957 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1958 mqd->cp_hqd_eop_control); 1959 1960 /* enable doorbell? */ 1961 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1962 mqd->cp_hqd_pq_doorbell_control); 1963 1964 /* disable the queue if it's active */ 1965 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1966 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1967 for (j = 0; j < adev->usec_timeout; j++) { 1968 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1969 break; 1970 udelay(1); 1971 } 1972 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1973 mqd->cp_hqd_dequeue_request); 1974 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1975 mqd->cp_hqd_pq_rptr); 1976 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1977 mqd->cp_hqd_pq_wptr_lo); 1978 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1979 mqd->cp_hqd_pq_wptr_hi); 1980 } 1981 1982 /* set the pointer to the MQD */ 1983 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1984 mqd->cp_mqd_base_addr_lo); 1985 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1986 mqd->cp_mqd_base_addr_hi); 1987 1988 /* set MQD vmid to 0 */ 1989 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1990 mqd->cp_mqd_control); 1991 1992 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1993 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1994 mqd->cp_hqd_pq_base_lo); 1995 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1996 mqd->cp_hqd_pq_base_hi); 1997 1998 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1999 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 2000 mqd->cp_hqd_pq_control); 2001 2002 /* set the wb address whether it's enabled or not */ 2003 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2004 mqd->cp_hqd_pq_rptr_report_addr_lo); 2005 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2006 mqd->cp_hqd_pq_rptr_report_addr_hi); 2007 2008 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2009 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2010 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2011 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2012 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2013 2014 /* enable the doorbell if requested */ 2015 if (ring->use_doorbell) { 2016 WREG32_SOC15( 2017 GC, GET_INST(GC, xcc_id), 2018 regCP_MEC_DOORBELL_RANGE_LOWER, 2019 ((adev->doorbell_index.kiq + 2020 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2021 2) << 2); 2022 WREG32_SOC15( 2023 GC, GET_INST(GC, xcc_id), 2024 regCP_MEC_DOORBELL_RANGE_UPPER, 2025 ((adev->doorbell_index.userqueue_end + 2026 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2027 2) << 2); 2028 } 2029 2030 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2031 mqd->cp_hqd_pq_doorbell_control); 2032 2033 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2034 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2035 mqd->cp_hqd_pq_wptr_lo); 2036 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2037 mqd->cp_hqd_pq_wptr_hi); 2038 2039 /* set the vmid for the queue */ 2040 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2041 2042 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2043 mqd->cp_hqd_persistent_state); 2044 2045 /* activate the queue */ 2046 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2047 mqd->cp_hqd_active); 2048 2049 if (ring->use_doorbell) 2050 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2051 2052 return 0; 2053 } 2054 2055 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2056 int xcc_id) 2057 { 2058 struct amdgpu_device *adev = ring->adev; 2059 int j; 2060 2061 /* disable the queue if it's active */ 2062 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2063 2064 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2065 2066 for (j = 0; j < adev->usec_timeout; j++) { 2067 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2068 break; 2069 udelay(1); 2070 } 2071 2072 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2073 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2074 2075 /* Manual disable if dequeue request times out */ 2076 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2077 } 2078 2079 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2080 0); 2081 } 2082 2083 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2084 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2085 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2086 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2087 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2088 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2089 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2090 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2091 2092 return 0; 2093 } 2094 2095 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2096 { 2097 struct amdgpu_device *adev = ring->adev; 2098 struct v9_mqd *mqd = ring->mqd_ptr; 2099 struct v9_mqd *tmp_mqd; 2100 2101 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2102 2103 /* GPU could be in bad state during probe, driver trigger the reset 2104 * after load the SMU, in this case , the mqd is not be initialized. 2105 * driver need to re-init the mqd. 2106 * check mqd->cp_hqd_pq_control since this value should not be 0 2107 */ 2108 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2109 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2110 /* for GPU_RESET case , reset MQD to a clean status */ 2111 if (adev->gfx.kiq[xcc_id].mqd_backup) 2112 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2113 2114 /* reset ring buffer */ 2115 ring->wptr = 0; 2116 amdgpu_ring_clear_ring(ring); 2117 mutex_lock(&adev->srbm_mutex); 2118 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2119 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2120 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2121 mutex_unlock(&adev->srbm_mutex); 2122 } else { 2123 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2124 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2125 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2126 mutex_lock(&adev->srbm_mutex); 2127 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2128 amdgpu_ring_clear_ring(ring); 2129 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2130 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2131 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2132 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2133 mutex_unlock(&adev->srbm_mutex); 2134 2135 if (adev->gfx.kiq[xcc_id].mqd_backup) 2136 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2137 } 2138 2139 return 0; 2140 } 2141 2142 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) 2143 { 2144 struct amdgpu_device *adev = ring->adev; 2145 struct v9_mqd *mqd = ring->mqd_ptr; 2146 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2147 struct v9_mqd *tmp_mqd; 2148 2149 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2150 * is not be initialized before 2151 */ 2152 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2153 2154 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2155 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2156 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2157 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2158 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2159 mutex_lock(&adev->srbm_mutex); 2160 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2161 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2162 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2163 mutex_unlock(&adev->srbm_mutex); 2164 2165 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2166 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2167 } else { 2168 /* restore MQD to a clean status */ 2169 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2170 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2171 /* reset ring buffer */ 2172 ring->wptr = 0; 2173 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2174 amdgpu_ring_clear_ring(ring); 2175 } 2176 2177 return 0; 2178 } 2179 2180 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2181 { 2182 struct amdgpu_ring *ring; 2183 int j; 2184 2185 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2186 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2187 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2188 mutex_lock(&adev->srbm_mutex); 2189 soc15_grbm_select(adev, ring->me, 2190 ring->pipe, 2191 ring->queue, 0, GET_INST(GC, xcc_id)); 2192 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2193 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2194 mutex_unlock(&adev->srbm_mutex); 2195 } 2196 } 2197 2198 return 0; 2199 } 2200 2201 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2202 { 2203 struct amdgpu_ring *ring; 2204 int r; 2205 2206 ring = &adev->gfx.kiq[xcc_id].ring; 2207 2208 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2209 if (unlikely(r != 0)) 2210 return r; 2211 2212 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2213 if (unlikely(r != 0)) { 2214 amdgpu_bo_unreserve(ring->mqd_obj); 2215 return r; 2216 } 2217 2218 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 2219 amdgpu_bo_kunmap(ring->mqd_obj); 2220 ring->mqd_ptr = NULL; 2221 amdgpu_bo_unreserve(ring->mqd_obj); 2222 return 0; 2223 } 2224 2225 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2226 { 2227 struct amdgpu_ring *ring = NULL; 2228 int r = 0, i; 2229 2230 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2231 2232 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2233 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2234 2235 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2236 if (unlikely(r != 0)) 2237 goto done; 2238 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2239 if (!r) { 2240 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2241 amdgpu_bo_kunmap(ring->mqd_obj); 2242 ring->mqd_ptr = NULL; 2243 } 2244 amdgpu_bo_unreserve(ring->mqd_obj); 2245 if (r) 2246 goto done; 2247 } 2248 2249 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2250 done: 2251 return r; 2252 } 2253 2254 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2255 { 2256 struct amdgpu_ring *ring; 2257 int r, j; 2258 2259 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2260 2261 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2262 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2263 2264 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2265 if (r) 2266 return r; 2267 } else { 2268 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2269 } 2270 2271 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2272 if (r) 2273 return r; 2274 2275 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2276 if (r) 2277 return r; 2278 2279 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2280 ring = &adev->gfx.compute_ring 2281 [j + xcc_id * adev->gfx.num_compute_rings]; 2282 r = amdgpu_ring_test_helper(ring); 2283 if (r) 2284 return r; 2285 } 2286 2287 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2288 2289 return 0; 2290 } 2291 2292 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2293 { 2294 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2295 2296 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2297 if (amdgpu_sriov_vf(adev)) { 2298 enum amdgpu_gfx_partition mode; 2299 2300 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2301 AMDGPU_XCP_FL_NONE); 2302 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2303 return -EINVAL; 2304 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2305 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2306 num_xcp = num_xcc / num_xcc_per_xcp; 2307 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2308 2309 } else { 2310 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2311 AMDGPU_XCP_FL_NONE) == 2312 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2313 r = amdgpu_xcp_switch_partition_mode( 2314 adev->xcp_mgr, amdgpu_user_partt_mode); 2315 } 2316 if (r) 2317 return r; 2318 2319 for (i = 0; i < num_xcc; i++) { 2320 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2321 if (r) 2322 return r; 2323 } 2324 2325 return 0; 2326 } 2327 2328 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2329 { 2330 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2331 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2332 2333 if (amdgpu_sriov_vf(adev)) { 2334 /* must disable polling for SRIOV when hw finished, otherwise 2335 * CPC engine may still keep fetching WB address which is already 2336 * invalid after sw finished and trigger DMAR reading error in 2337 * hypervisor side. 2338 */ 2339 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2340 return; 2341 } 2342 2343 /* Use deinitialize sequence from CAIL when unbinding device 2344 * from driver, otherwise KIQ is hanging when binding back 2345 */ 2346 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2347 mutex_lock(&adev->srbm_mutex); 2348 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2349 adev->gfx.kiq[xcc_id].ring.pipe, 2350 adev->gfx.kiq[xcc_id].ring.queue, 0, 2351 GET_INST(GC, xcc_id)); 2352 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2353 xcc_id); 2354 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2355 mutex_unlock(&adev->srbm_mutex); 2356 } 2357 2358 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2359 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2360 } 2361 2362 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2363 { 2364 int r; 2365 struct amdgpu_device *adev = ip_block->adev; 2366 2367 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2368 adev->gfx.cleaner_shader_ptr); 2369 2370 if (!amdgpu_sriov_vf(adev)) 2371 gfx_v9_4_3_init_golden_registers(adev); 2372 2373 gfx_v9_4_3_constants_init(adev); 2374 2375 r = adev->gfx.rlc.funcs->resume(adev); 2376 if (r) 2377 return r; 2378 2379 r = gfx_v9_4_3_cp_resume(adev); 2380 if (r) 2381 return r; 2382 2383 return r; 2384 } 2385 2386 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2387 { 2388 struct amdgpu_device *adev = ip_block->adev; 2389 int i, num_xcc; 2390 2391 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2392 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2393 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2394 2395 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2396 for (i = 0; i < num_xcc; i++) { 2397 gfx_v9_4_3_xcc_fini(adev, i); 2398 } 2399 2400 return 0; 2401 } 2402 2403 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2404 { 2405 return gfx_v9_4_3_hw_fini(ip_block); 2406 } 2407 2408 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2409 { 2410 return gfx_v9_4_3_hw_init(ip_block); 2411 } 2412 2413 static bool gfx_v9_4_3_is_idle(void *handle) 2414 { 2415 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2416 int i, num_xcc; 2417 2418 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2419 for (i = 0; i < num_xcc; i++) { 2420 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2421 GRBM_STATUS, GUI_ACTIVE)) 2422 return false; 2423 } 2424 return true; 2425 } 2426 2427 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2428 { 2429 unsigned i; 2430 struct amdgpu_device *adev = ip_block->adev; 2431 2432 for (i = 0; i < adev->usec_timeout; i++) { 2433 if (gfx_v9_4_3_is_idle(adev)) 2434 return 0; 2435 udelay(1); 2436 } 2437 return -ETIMEDOUT; 2438 } 2439 2440 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2441 { 2442 u32 grbm_soft_reset = 0; 2443 u32 tmp; 2444 struct amdgpu_device *adev = ip_block->adev; 2445 2446 /* GRBM_STATUS */ 2447 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2448 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2449 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2450 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2451 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2452 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2453 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2454 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2455 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2456 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2457 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2458 } 2459 2460 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2461 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2462 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2463 } 2464 2465 /* GRBM_STATUS2 */ 2466 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2467 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2468 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2469 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2470 2471 2472 if (grbm_soft_reset) { 2473 /* stop the rlc */ 2474 adev->gfx.rlc.funcs->stop(adev); 2475 2476 /* Disable MEC parsing/prefetching */ 2477 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2478 2479 if (grbm_soft_reset) { 2480 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2481 tmp |= grbm_soft_reset; 2482 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2483 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2484 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2485 2486 udelay(50); 2487 2488 tmp &= ~grbm_soft_reset; 2489 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2490 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2491 } 2492 2493 /* Wait a little for things to settle down */ 2494 udelay(50); 2495 } 2496 return 0; 2497 } 2498 2499 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2500 uint32_t vmid, 2501 uint32_t gds_base, uint32_t gds_size, 2502 uint32_t gws_base, uint32_t gws_size, 2503 uint32_t oa_base, uint32_t oa_size) 2504 { 2505 struct amdgpu_device *adev = ring->adev; 2506 2507 /* GDS Base */ 2508 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2509 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2510 gds_base); 2511 2512 /* GDS Size */ 2513 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2514 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2515 gds_size); 2516 2517 /* GWS */ 2518 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2519 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2520 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2521 2522 /* OA */ 2523 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2524 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2525 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2526 } 2527 2528 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2529 { 2530 struct amdgpu_device *adev = ip_block->adev; 2531 2532 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2533 AMDGPU_MAX_COMPUTE_RINGS); 2534 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2535 gfx_v9_4_3_set_ring_funcs(adev); 2536 gfx_v9_4_3_set_irq_funcs(adev); 2537 gfx_v9_4_3_set_gds_init(adev); 2538 gfx_v9_4_3_set_rlc_funcs(adev); 2539 2540 /* init rlcg reg access ctrl */ 2541 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2542 2543 return gfx_v9_4_3_init_microcode(adev); 2544 } 2545 2546 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2547 { 2548 struct amdgpu_device *adev = ip_block->adev; 2549 int r; 2550 2551 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2552 if (r) 2553 return r; 2554 2555 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2556 if (r) 2557 return r; 2558 2559 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2560 if (r) 2561 return r; 2562 2563 if (adev->gfx.ras && 2564 adev->gfx.ras->enable_watchdog_timer) 2565 adev->gfx.ras->enable_watchdog_timer(adev); 2566 2567 return 0; 2568 } 2569 2570 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2571 bool enable, int xcc_id) 2572 { 2573 uint32_t def, data; 2574 2575 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2576 return; 2577 2578 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2579 regRLC_CGTT_MGCG_OVERRIDE); 2580 2581 if (enable) 2582 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2583 else 2584 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2585 2586 if (def != data) 2587 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2588 regRLC_CGTT_MGCG_OVERRIDE, data); 2589 2590 } 2591 2592 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2593 bool enable, int xcc_id) 2594 { 2595 uint32_t def, data; 2596 2597 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2598 return; 2599 2600 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2601 regRLC_CGTT_MGCG_OVERRIDE); 2602 2603 if (enable) 2604 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2605 else 2606 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2607 2608 if (def != data) 2609 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2610 regRLC_CGTT_MGCG_OVERRIDE, data); 2611 } 2612 2613 static void 2614 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2615 bool enable, int xcc_id) 2616 { 2617 uint32_t data, def; 2618 2619 /* It is disabled by HW by default */ 2620 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2621 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2622 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2623 2624 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2625 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2626 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2627 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2628 2629 if (def != data) 2630 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2631 2632 /* MGLS is a global flag to control all MGLS in GFX */ 2633 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2634 /* 2 - RLC memory Light sleep */ 2635 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2636 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2637 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2638 if (def != data) 2639 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2640 } 2641 /* 3 - CP memory Light sleep */ 2642 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2643 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2644 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2645 if (def != data) 2646 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2647 } 2648 } 2649 } else { 2650 /* 1 - MGCG_OVERRIDE */ 2651 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2652 2653 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2654 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2655 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2656 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2657 2658 if (def != data) 2659 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2660 2661 /* 2 - disable MGLS in RLC */ 2662 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2663 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2664 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2665 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2666 } 2667 2668 /* 3 - disable MGLS in CP */ 2669 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2670 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2671 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2672 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2673 } 2674 } 2675 2676 } 2677 2678 static void 2679 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2680 bool enable, int xcc_id) 2681 { 2682 uint32_t def, data; 2683 2684 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2685 2686 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2687 /* unset CGCG override */ 2688 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2689 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2690 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2691 else 2692 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2693 /* update CGCG and CGLS override bits */ 2694 if (def != data) 2695 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2696 2697 /* CGCG Hysteresis: 400us */ 2698 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2699 2700 data = (0x2710 2701 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2702 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2703 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2704 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2705 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2706 if (def != data) 2707 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2708 2709 /* set IDLE_POLL_COUNT(0x33450100)*/ 2710 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2711 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2712 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2713 if (def != data) 2714 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2715 } else { 2716 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2717 /* reset CGCG/CGLS bits */ 2718 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2719 /* disable cgcg and cgls in FSM */ 2720 if (def != data) 2721 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2722 } 2723 2724 } 2725 2726 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2727 bool enable, int xcc_id) 2728 { 2729 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2730 2731 if (enable) { 2732 /* FGCG */ 2733 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2734 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2735 2736 /* CGCG/CGLS should be enabled after MGCG/MGLS 2737 * === MGCG + MGLS === 2738 */ 2739 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2740 xcc_id); 2741 /* === CGCG + CGLS === */ 2742 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2743 xcc_id); 2744 } else { 2745 /* CGCG/CGLS should be disabled before MGCG/MGLS 2746 * === CGCG + CGLS === 2747 */ 2748 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2749 xcc_id); 2750 /* === MGCG + MGLS === */ 2751 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2752 xcc_id); 2753 2754 /* FGCG */ 2755 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2756 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2757 } 2758 2759 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2760 2761 return 0; 2762 } 2763 2764 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2765 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2766 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2767 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2768 .init = gfx_v9_4_3_rlc_init, 2769 .resume = gfx_v9_4_3_rlc_resume, 2770 .stop = gfx_v9_4_3_rlc_stop, 2771 .reset = gfx_v9_4_3_rlc_reset, 2772 .start = gfx_v9_4_3_rlc_start, 2773 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2774 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2775 }; 2776 2777 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2778 enum amd_powergating_state state) 2779 { 2780 return 0; 2781 } 2782 2783 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2784 enum amd_clockgating_state state) 2785 { 2786 struct amdgpu_device *adev = ip_block->adev; 2787 int i, num_xcc; 2788 2789 if (amdgpu_sriov_vf(adev)) 2790 return 0; 2791 2792 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2793 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2794 case IP_VERSION(9, 4, 3): 2795 case IP_VERSION(9, 4, 4): 2796 for (i = 0; i < num_xcc; i++) 2797 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2798 adev, state == AMD_CG_STATE_GATE, i); 2799 break; 2800 default: 2801 break; 2802 } 2803 return 0; 2804 } 2805 2806 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2807 { 2808 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2809 int data; 2810 2811 if (amdgpu_sriov_vf(adev)) 2812 *flags = 0; 2813 2814 /* AMD_CG_SUPPORT_GFX_MGCG */ 2815 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2816 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2817 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2818 2819 /* AMD_CG_SUPPORT_GFX_CGCG */ 2820 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2821 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2822 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2823 2824 /* AMD_CG_SUPPORT_GFX_CGLS */ 2825 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2826 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2827 2828 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2829 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2830 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2831 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2832 2833 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2834 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2835 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2836 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2837 } 2838 2839 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2840 { 2841 struct amdgpu_device *adev = ring->adev; 2842 u32 ref_and_mask, reg_mem_engine; 2843 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2844 2845 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2846 switch (ring->me) { 2847 case 1: 2848 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2849 break; 2850 case 2: 2851 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2852 break; 2853 default: 2854 return; 2855 } 2856 reg_mem_engine = 0; 2857 } else { 2858 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2859 reg_mem_engine = 1; /* pfp */ 2860 } 2861 2862 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2863 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2864 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2865 ref_and_mask, ref_and_mask, 0x20); 2866 } 2867 2868 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2869 struct amdgpu_job *job, 2870 struct amdgpu_ib *ib, 2871 uint32_t flags) 2872 { 2873 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2874 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2875 2876 /* Currently, there is a high possibility to get wave ID mismatch 2877 * between ME and GDS, leading to a hw deadlock, because ME generates 2878 * different wave IDs than the GDS expects. This situation happens 2879 * randomly when at least 5 compute pipes use GDS ordered append. 2880 * The wave IDs generated by ME are also wrong after suspend/resume. 2881 * Those are probably bugs somewhere else in the kernel driver. 2882 * 2883 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2884 * GDS to 0 for this ring (me/pipe). 2885 */ 2886 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2887 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2888 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2889 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2890 } 2891 2892 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2893 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2894 amdgpu_ring_write(ring, 2895 #ifdef __BIG_ENDIAN 2896 (2 << 0) | 2897 #endif 2898 lower_32_bits(ib->gpu_addr)); 2899 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2900 amdgpu_ring_write(ring, control); 2901 } 2902 2903 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2904 u64 seq, unsigned flags) 2905 { 2906 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2907 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2908 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2909 2910 /* RELEASE_MEM - flush caches, send int */ 2911 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2912 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2913 EOP_TC_NC_ACTION_EN) : 2914 (EOP_TCL1_ACTION_EN | 2915 EOP_TC_ACTION_EN | 2916 EOP_TC_WB_ACTION_EN | 2917 EOP_TC_MD_ACTION_EN)) | 2918 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2919 EVENT_INDEX(5))); 2920 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2921 2922 /* 2923 * the address should be Qword aligned if 64bit write, Dword 2924 * aligned if only send 32bit data low (discard data high) 2925 */ 2926 if (write64bit) 2927 BUG_ON(addr & 0x7); 2928 else 2929 BUG_ON(addr & 0x3); 2930 amdgpu_ring_write(ring, lower_32_bits(addr)); 2931 amdgpu_ring_write(ring, upper_32_bits(addr)); 2932 amdgpu_ring_write(ring, lower_32_bits(seq)); 2933 amdgpu_ring_write(ring, upper_32_bits(seq)); 2934 amdgpu_ring_write(ring, 0); 2935 } 2936 2937 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2938 { 2939 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2940 uint32_t seq = ring->fence_drv.sync_seq; 2941 uint64_t addr = ring->fence_drv.gpu_addr; 2942 2943 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2944 lower_32_bits(addr), upper_32_bits(addr), 2945 seq, 0xffffffff, 4); 2946 } 2947 2948 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2949 unsigned vmid, uint64_t pd_addr) 2950 { 2951 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2952 } 2953 2954 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2955 { 2956 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2957 } 2958 2959 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2960 { 2961 u64 wptr; 2962 2963 /* XXX check if swapping is necessary on BE */ 2964 if (ring->use_doorbell) 2965 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2966 else 2967 BUG(); 2968 return wptr; 2969 } 2970 2971 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2972 { 2973 struct amdgpu_device *adev = ring->adev; 2974 2975 /* XXX check if swapping is necessary on BE */ 2976 if (ring->use_doorbell) { 2977 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2978 WDOORBELL64(ring->doorbell_index, ring->wptr); 2979 } else { 2980 BUG(); /* only DOORBELL method supported on gfx9 now */ 2981 } 2982 } 2983 2984 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2985 u64 seq, unsigned int flags) 2986 { 2987 struct amdgpu_device *adev = ring->adev; 2988 2989 /* we only allocate 32bit for each seq wb address */ 2990 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2991 2992 /* write fence seq to the "addr" */ 2993 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2994 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2995 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2996 amdgpu_ring_write(ring, lower_32_bits(addr)); 2997 amdgpu_ring_write(ring, upper_32_bits(addr)); 2998 amdgpu_ring_write(ring, lower_32_bits(seq)); 2999 3000 if (flags & AMDGPU_FENCE_FLAG_INT) { 3001 /* set register to trigger INT */ 3002 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3003 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3004 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 3005 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 3006 amdgpu_ring_write(ring, 0); 3007 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3008 } 3009 } 3010 3011 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3012 uint32_t reg_val_offs) 3013 { 3014 struct amdgpu_device *adev = ring->adev; 3015 3016 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3017 3018 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3019 amdgpu_ring_write(ring, 0 | /* src: register*/ 3020 (5 << 8) | /* dst: memory */ 3021 (1 << 20)); /* write confirm */ 3022 amdgpu_ring_write(ring, reg); 3023 amdgpu_ring_write(ring, 0); 3024 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3025 reg_val_offs * 4)); 3026 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3027 reg_val_offs * 4)); 3028 } 3029 3030 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3031 uint32_t val) 3032 { 3033 uint32_t cmd = 0; 3034 3035 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3036 3037 switch (ring->funcs->type) { 3038 case AMDGPU_RING_TYPE_GFX: 3039 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3040 break; 3041 case AMDGPU_RING_TYPE_KIQ: 3042 cmd = (1 << 16); /* no inc addr */ 3043 break; 3044 default: 3045 cmd = WR_CONFIRM; 3046 break; 3047 } 3048 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3049 amdgpu_ring_write(ring, cmd); 3050 amdgpu_ring_write(ring, reg); 3051 amdgpu_ring_write(ring, 0); 3052 amdgpu_ring_write(ring, val); 3053 } 3054 3055 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3056 uint32_t val, uint32_t mask) 3057 { 3058 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3059 } 3060 3061 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3062 uint32_t reg0, uint32_t reg1, 3063 uint32_t ref, uint32_t mask) 3064 { 3065 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3066 ref, mask); 3067 } 3068 3069 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3070 unsigned vmid) 3071 { 3072 struct amdgpu_device *adev = ring->adev; 3073 uint32_t value = 0; 3074 3075 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3076 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3077 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3078 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3079 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3080 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3081 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3082 } 3083 3084 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3085 struct amdgpu_device *adev, int me, int pipe, 3086 enum amdgpu_interrupt_state state, int xcc_id) 3087 { 3088 u32 mec_int_cntl, mec_int_cntl_reg; 3089 3090 /* 3091 * amdgpu controls only the first MEC. That's why this function only 3092 * handles the setting of interrupts for this specific MEC. All other 3093 * pipes' interrupts are set by amdkfd. 3094 */ 3095 3096 if (me == 1) { 3097 switch (pipe) { 3098 case 0: 3099 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3100 break; 3101 case 1: 3102 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3103 break; 3104 case 2: 3105 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3106 break; 3107 case 3: 3108 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3109 break; 3110 default: 3111 DRM_DEBUG("invalid pipe %d\n", pipe); 3112 return; 3113 } 3114 } else { 3115 DRM_DEBUG("invalid me %d\n", me); 3116 return; 3117 } 3118 3119 switch (state) { 3120 case AMDGPU_IRQ_STATE_DISABLE: 3121 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3122 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3123 TIME_STAMP_INT_ENABLE, 0); 3124 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3125 break; 3126 case AMDGPU_IRQ_STATE_ENABLE: 3127 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3128 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3129 TIME_STAMP_INT_ENABLE, 1); 3130 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3131 break; 3132 default: 3133 break; 3134 } 3135 } 3136 3137 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3138 int xcc_id, int me, int pipe) 3139 { 3140 /* 3141 * amdgpu controls only the first MEC. That's why this function only 3142 * handles the setting of interrupts for this specific MEC. All other 3143 * pipes' interrupts are set by amdkfd. 3144 */ 3145 if (me != 1) 3146 return 0; 3147 3148 switch (pipe) { 3149 case 0: 3150 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3151 case 1: 3152 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3153 case 2: 3154 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3155 case 3: 3156 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3157 default: 3158 return 0; 3159 } 3160 } 3161 3162 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3163 struct amdgpu_irq_src *source, 3164 unsigned type, 3165 enum amdgpu_interrupt_state state) 3166 { 3167 u32 mec_int_cntl_reg, mec_int_cntl; 3168 int i, j, k, num_xcc; 3169 3170 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3171 switch (state) { 3172 case AMDGPU_IRQ_STATE_DISABLE: 3173 case AMDGPU_IRQ_STATE_ENABLE: 3174 for (i = 0; i < num_xcc; i++) { 3175 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3176 PRIV_REG_INT_ENABLE, 3177 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3178 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3179 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3180 /* MECs start at 1 */ 3181 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3182 3183 if (mec_int_cntl_reg) { 3184 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3185 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3186 PRIV_REG_INT_ENABLE, 3187 state == AMDGPU_IRQ_STATE_ENABLE ? 3188 1 : 0); 3189 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3190 } 3191 } 3192 } 3193 } 3194 break; 3195 default: 3196 break; 3197 } 3198 3199 return 0; 3200 } 3201 3202 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3203 struct amdgpu_irq_src *source, 3204 unsigned type, 3205 enum amdgpu_interrupt_state state) 3206 { 3207 u32 mec_int_cntl_reg, mec_int_cntl; 3208 int i, j, k, num_xcc; 3209 3210 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3211 switch (state) { 3212 case AMDGPU_IRQ_STATE_DISABLE: 3213 case AMDGPU_IRQ_STATE_ENABLE: 3214 for (i = 0; i < num_xcc; i++) { 3215 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3216 OPCODE_ERROR_INT_ENABLE, 3217 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3218 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3219 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3220 /* MECs start at 1 */ 3221 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3222 3223 if (mec_int_cntl_reg) { 3224 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3225 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3226 OPCODE_ERROR_INT_ENABLE, 3227 state == AMDGPU_IRQ_STATE_ENABLE ? 3228 1 : 0); 3229 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3230 } 3231 } 3232 } 3233 } 3234 break; 3235 default: 3236 break; 3237 } 3238 3239 return 0; 3240 } 3241 3242 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3243 struct amdgpu_irq_src *source, 3244 unsigned type, 3245 enum amdgpu_interrupt_state state) 3246 { 3247 int i, num_xcc; 3248 3249 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3250 switch (state) { 3251 case AMDGPU_IRQ_STATE_DISABLE: 3252 case AMDGPU_IRQ_STATE_ENABLE: 3253 for (i = 0; i < num_xcc; i++) 3254 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3255 PRIV_INSTR_INT_ENABLE, 3256 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3257 break; 3258 default: 3259 break; 3260 } 3261 3262 return 0; 3263 } 3264 3265 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3266 struct amdgpu_irq_src *src, 3267 unsigned type, 3268 enum amdgpu_interrupt_state state) 3269 { 3270 int i, num_xcc; 3271 3272 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3273 for (i = 0; i < num_xcc; i++) { 3274 switch (type) { 3275 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3276 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3277 adev, 1, 0, state, i); 3278 break; 3279 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3280 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3281 adev, 1, 1, state, i); 3282 break; 3283 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3284 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3285 adev, 1, 2, state, i); 3286 break; 3287 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3288 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3289 adev, 1, 3, state, i); 3290 break; 3291 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3292 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3293 adev, 2, 0, state, i); 3294 break; 3295 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3296 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3297 adev, 2, 1, state, i); 3298 break; 3299 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3300 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3301 adev, 2, 2, state, i); 3302 break; 3303 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3304 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3305 adev, 2, 3, state, i); 3306 break; 3307 default: 3308 break; 3309 } 3310 } 3311 3312 return 0; 3313 } 3314 3315 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3316 struct amdgpu_irq_src *source, 3317 struct amdgpu_iv_entry *entry) 3318 { 3319 int i, xcc_id; 3320 u8 me_id, pipe_id, queue_id; 3321 struct amdgpu_ring *ring; 3322 3323 DRM_DEBUG("IH: CP EOP\n"); 3324 me_id = (entry->ring_id & 0x0c) >> 2; 3325 pipe_id = (entry->ring_id & 0x03) >> 0; 3326 queue_id = (entry->ring_id & 0x70) >> 4; 3327 3328 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3329 3330 if (xcc_id == -EINVAL) 3331 return -EINVAL; 3332 3333 switch (me_id) { 3334 case 0: 3335 case 1: 3336 case 2: 3337 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3338 ring = &adev->gfx.compute_ring 3339 [i + 3340 xcc_id * adev->gfx.num_compute_rings]; 3341 /* Per-queue interrupt is supported for MEC starting from VI. 3342 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3343 */ 3344 3345 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3346 amdgpu_fence_process(ring); 3347 } 3348 break; 3349 } 3350 return 0; 3351 } 3352 3353 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3354 struct amdgpu_iv_entry *entry) 3355 { 3356 u8 me_id, pipe_id, queue_id; 3357 struct amdgpu_ring *ring; 3358 int i, xcc_id; 3359 3360 me_id = (entry->ring_id & 0x0c) >> 2; 3361 pipe_id = (entry->ring_id & 0x03) >> 0; 3362 queue_id = (entry->ring_id & 0x70) >> 4; 3363 3364 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3365 3366 if (xcc_id == -EINVAL) 3367 return; 3368 3369 switch (me_id) { 3370 case 0: 3371 case 1: 3372 case 2: 3373 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3374 ring = &adev->gfx.compute_ring 3375 [i + 3376 xcc_id * adev->gfx.num_compute_rings]; 3377 if (ring->me == me_id && ring->pipe == pipe_id && 3378 ring->queue == queue_id) 3379 drm_sched_fault(&ring->sched); 3380 } 3381 break; 3382 } 3383 } 3384 3385 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3386 struct amdgpu_irq_src *source, 3387 struct amdgpu_iv_entry *entry) 3388 { 3389 DRM_ERROR("Illegal register access in command stream\n"); 3390 gfx_v9_4_3_fault(adev, entry); 3391 return 0; 3392 } 3393 3394 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3395 struct amdgpu_irq_src *source, 3396 struct amdgpu_iv_entry *entry) 3397 { 3398 DRM_ERROR("Illegal opcode in command stream\n"); 3399 gfx_v9_4_3_fault(adev, entry); 3400 return 0; 3401 } 3402 3403 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3404 struct amdgpu_irq_src *source, 3405 struct amdgpu_iv_entry *entry) 3406 { 3407 DRM_ERROR("Illegal instruction in command stream\n"); 3408 gfx_v9_4_3_fault(adev, entry); 3409 return 0; 3410 } 3411 3412 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3413 { 3414 const unsigned int cp_coher_cntl = 3415 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3416 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3417 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3418 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3419 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3420 3421 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3422 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3423 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3424 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3425 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3426 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3427 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3428 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3429 } 3430 3431 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3432 uint32_t pipe, bool enable) 3433 { 3434 struct amdgpu_device *adev = ring->adev; 3435 uint32_t val; 3436 uint32_t wcl_cs_reg; 3437 3438 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3439 val = enable ? 0x1 : 0x7f; 3440 3441 switch (pipe) { 3442 case 0: 3443 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3444 break; 3445 case 1: 3446 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3447 break; 3448 case 2: 3449 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3450 break; 3451 case 3: 3452 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3453 break; 3454 default: 3455 DRM_DEBUG("invalid pipe %d\n", pipe); 3456 return; 3457 } 3458 3459 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3460 3461 } 3462 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3463 { 3464 struct amdgpu_device *adev = ring->adev; 3465 uint32_t val; 3466 int i; 3467 3468 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3469 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3470 * around 25% of gpu resources. 3471 */ 3472 val = enable ? 0x1f : 0x07ffffff; 3473 amdgpu_ring_emit_wreg(ring, 3474 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3475 val); 3476 3477 /* Restrict waves for normal/low priority compute queues as well 3478 * to get best QoS for high priority compute jobs. 3479 * 3480 * amdgpu controls only 1st ME(0-3 CS pipes). 3481 */ 3482 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3483 if (i != ring->pipe) 3484 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3485 3486 } 3487 } 3488 3489 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3490 uint32_t pipe, uint32_t queue, 3491 uint32_t xcc_id) 3492 { 3493 int i, r; 3494 /* make sure dequeue is complete*/ 3495 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3496 mutex_lock(&adev->srbm_mutex); 3497 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3498 for (i = 0; i < adev->usec_timeout; i++) { 3499 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3500 break; 3501 udelay(1); 3502 } 3503 if (i >= adev->usec_timeout) 3504 r = -ETIMEDOUT; 3505 else 3506 r = 0; 3507 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3508 mutex_unlock(&adev->srbm_mutex); 3509 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3510 3511 return r; 3512 3513 } 3514 3515 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3516 { 3517 /*TODO: Need check gfx9.4.4 mec fw whether supports pipe reset as well.*/ 3518 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 3519 adev->gfx.mec_fw_version >= 0x0000009b) 3520 return true; 3521 else 3522 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3523 3524 return false; 3525 } 3526 3527 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3528 { 3529 struct amdgpu_device *adev = ring->adev; 3530 uint32_t reset_pipe, clean_pipe; 3531 int r; 3532 3533 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3534 return -EINVAL; 3535 3536 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3537 mutex_lock(&adev->srbm_mutex); 3538 3539 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3540 clean_pipe = reset_pipe; 3541 3542 if (ring->me == 1) { 3543 switch (ring->pipe) { 3544 case 0: 3545 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3546 MEC_ME1_PIPE0_RESET, 1); 3547 break; 3548 case 1: 3549 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3550 MEC_ME1_PIPE1_RESET, 1); 3551 break; 3552 case 2: 3553 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3554 MEC_ME1_PIPE2_RESET, 1); 3555 break; 3556 case 3: 3557 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3558 MEC_ME1_PIPE3_RESET, 1); 3559 break; 3560 default: 3561 break; 3562 } 3563 } else { 3564 if (ring->pipe) 3565 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3566 MEC_ME2_PIPE1_RESET, 1); 3567 else 3568 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3569 MEC_ME2_PIPE0_RESET, 1); 3570 } 3571 3572 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3573 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3574 mutex_unlock(&adev->srbm_mutex); 3575 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3576 3577 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3578 return r; 3579 } 3580 3581 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3582 unsigned int vmid) 3583 { 3584 struct amdgpu_device *adev = ring->adev; 3585 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3586 struct amdgpu_ring *kiq_ring = &kiq->ring; 3587 unsigned long flags; 3588 int r; 3589 3590 if (amdgpu_sriov_vf(adev)) 3591 return -EINVAL; 3592 3593 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3594 return -EINVAL; 3595 3596 spin_lock_irqsave(&kiq->ring_lock, flags); 3597 3598 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3599 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3600 return -ENOMEM; 3601 } 3602 3603 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3604 0, 0); 3605 amdgpu_ring_commit(kiq_ring); 3606 3607 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3608 3609 r = amdgpu_ring_test_ring(kiq_ring); 3610 if (r) { 3611 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3612 ring->name); 3613 goto pipe_reset; 3614 } 3615 3616 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3617 if (r) 3618 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3619 3620 pipe_reset: 3621 if(r) { 3622 r = gfx_v9_4_3_reset_hw_pipe(ring); 3623 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3624 r ? "failed" : "successfully"); 3625 if (r) 3626 return r; 3627 } 3628 3629 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3630 if (unlikely(r != 0)){ 3631 dev_err(adev->dev, "fail to resv mqd_obj\n"); 3632 return r; 3633 } 3634 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3635 if (!r) { 3636 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3637 amdgpu_bo_kunmap(ring->mqd_obj); 3638 ring->mqd_ptr = NULL; 3639 } 3640 amdgpu_bo_unreserve(ring->mqd_obj); 3641 if (r) { 3642 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 3643 return r; 3644 } 3645 spin_lock_irqsave(&kiq->ring_lock, flags); 3646 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3647 if (r) { 3648 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3649 return -ENOMEM; 3650 } 3651 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3652 amdgpu_ring_commit(kiq_ring); 3653 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3654 3655 r = amdgpu_ring_test_ring(kiq_ring); 3656 if (r) { 3657 dev_err(adev->dev, "fail to remap queue\n"); 3658 return r; 3659 } 3660 return amdgpu_ring_test_ring(ring); 3661 } 3662 3663 enum amdgpu_gfx_cp_ras_mem_id { 3664 AMDGPU_GFX_CP_MEM1 = 1, 3665 AMDGPU_GFX_CP_MEM2, 3666 AMDGPU_GFX_CP_MEM3, 3667 AMDGPU_GFX_CP_MEM4, 3668 AMDGPU_GFX_CP_MEM5, 3669 }; 3670 3671 enum amdgpu_gfx_gcea_ras_mem_id { 3672 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3673 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3674 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3675 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3676 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3677 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3678 AMDGPU_GFX_GCEA_MAM_DMEM0, 3679 AMDGPU_GFX_GCEA_MAM_DMEM1, 3680 AMDGPU_GFX_GCEA_MAM_DMEM2, 3681 AMDGPU_GFX_GCEA_MAM_DMEM3, 3682 AMDGPU_GFX_GCEA_MAM_AMEM0, 3683 AMDGPU_GFX_GCEA_MAM_AMEM1, 3684 AMDGPU_GFX_GCEA_MAM_AMEM2, 3685 AMDGPU_GFX_GCEA_MAM_AMEM3, 3686 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3687 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3688 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3689 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3690 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3691 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3692 }; 3693 3694 enum amdgpu_gfx_gc_cane_ras_mem_id { 3695 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3696 }; 3697 3698 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3699 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3700 }; 3701 3702 enum amdgpu_gfx_gds_ras_mem_id { 3703 AMDGPU_GFX_GDS_MEM0 = 0, 3704 }; 3705 3706 enum amdgpu_gfx_lds_ras_mem_id { 3707 AMDGPU_GFX_LDS_BANK0 = 0, 3708 AMDGPU_GFX_LDS_BANK1, 3709 AMDGPU_GFX_LDS_BANK2, 3710 AMDGPU_GFX_LDS_BANK3, 3711 AMDGPU_GFX_LDS_BANK4, 3712 AMDGPU_GFX_LDS_BANK5, 3713 AMDGPU_GFX_LDS_BANK6, 3714 AMDGPU_GFX_LDS_BANK7, 3715 AMDGPU_GFX_LDS_BANK8, 3716 AMDGPU_GFX_LDS_BANK9, 3717 AMDGPU_GFX_LDS_BANK10, 3718 AMDGPU_GFX_LDS_BANK11, 3719 AMDGPU_GFX_LDS_BANK12, 3720 AMDGPU_GFX_LDS_BANK13, 3721 AMDGPU_GFX_LDS_BANK14, 3722 AMDGPU_GFX_LDS_BANK15, 3723 AMDGPU_GFX_LDS_BANK16, 3724 AMDGPU_GFX_LDS_BANK17, 3725 AMDGPU_GFX_LDS_BANK18, 3726 AMDGPU_GFX_LDS_BANK19, 3727 AMDGPU_GFX_LDS_BANK20, 3728 AMDGPU_GFX_LDS_BANK21, 3729 AMDGPU_GFX_LDS_BANK22, 3730 AMDGPU_GFX_LDS_BANK23, 3731 AMDGPU_GFX_LDS_BANK24, 3732 AMDGPU_GFX_LDS_BANK25, 3733 AMDGPU_GFX_LDS_BANK26, 3734 AMDGPU_GFX_LDS_BANK27, 3735 AMDGPU_GFX_LDS_BANK28, 3736 AMDGPU_GFX_LDS_BANK29, 3737 AMDGPU_GFX_LDS_BANK30, 3738 AMDGPU_GFX_LDS_BANK31, 3739 AMDGPU_GFX_LDS_SP_BUFFER_A, 3740 AMDGPU_GFX_LDS_SP_BUFFER_B, 3741 }; 3742 3743 enum amdgpu_gfx_rlc_ras_mem_id { 3744 AMDGPU_GFX_RLC_GPMF32 = 1, 3745 AMDGPU_GFX_RLC_RLCVF32, 3746 AMDGPU_GFX_RLC_SCRATCH, 3747 AMDGPU_GFX_RLC_SRM_ARAM, 3748 AMDGPU_GFX_RLC_SRM_DRAM, 3749 AMDGPU_GFX_RLC_TCTAG, 3750 AMDGPU_GFX_RLC_SPM_SE, 3751 AMDGPU_GFX_RLC_SPM_GRBMT, 3752 }; 3753 3754 enum amdgpu_gfx_sp_ras_mem_id { 3755 AMDGPU_GFX_SP_SIMDID0 = 0, 3756 }; 3757 3758 enum amdgpu_gfx_spi_ras_mem_id { 3759 AMDGPU_GFX_SPI_MEM0 = 0, 3760 AMDGPU_GFX_SPI_MEM1, 3761 AMDGPU_GFX_SPI_MEM2, 3762 AMDGPU_GFX_SPI_MEM3, 3763 }; 3764 3765 enum amdgpu_gfx_sqc_ras_mem_id { 3766 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3767 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3768 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3769 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3770 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3771 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3772 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3773 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3774 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3775 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3776 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3777 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3778 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3779 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3780 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3781 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3782 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3783 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3784 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3785 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3786 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3787 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3788 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3789 }; 3790 3791 enum amdgpu_gfx_sq_ras_mem_id { 3792 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3793 AMDGPU_GFX_SQ_SGPR_MEM1, 3794 AMDGPU_GFX_SQ_SGPR_MEM2, 3795 AMDGPU_GFX_SQ_SGPR_MEM3, 3796 }; 3797 3798 enum amdgpu_gfx_ta_ras_mem_id { 3799 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3800 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3801 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3802 AMDGPU_GFX_TA_FSX_LFIFO, 3803 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3804 }; 3805 3806 enum amdgpu_gfx_tcc_ras_mem_id { 3807 AMDGPU_GFX_TCC_MEM1 = 1, 3808 }; 3809 3810 enum amdgpu_gfx_tca_ras_mem_id { 3811 AMDGPU_GFX_TCA_MEM1 = 1, 3812 }; 3813 3814 enum amdgpu_gfx_tci_ras_mem_id { 3815 AMDGPU_GFX_TCIW_MEM = 1, 3816 }; 3817 3818 enum amdgpu_gfx_tcp_ras_mem_id { 3819 AMDGPU_GFX_TCP_LFIFO0 = 1, 3820 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3821 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3822 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3823 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3824 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3825 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3826 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3827 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3828 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3829 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3830 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3831 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3832 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3833 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3834 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3835 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3836 AMDGPU_GFX_TCP_VM_FIFO, 3837 AMDGPU_GFX_TCP_DB_TAGRAM0, 3838 AMDGPU_GFX_TCP_DB_TAGRAM1, 3839 AMDGPU_GFX_TCP_DB_TAGRAM2, 3840 AMDGPU_GFX_TCP_DB_TAGRAM3, 3841 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3842 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3843 AMDGPU_GFX_TCP_CMD_FIFO, 3844 }; 3845 3846 enum amdgpu_gfx_td_ras_mem_id { 3847 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3848 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3849 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3850 }; 3851 3852 enum amdgpu_gfx_tcx_ras_mem_id { 3853 AMDGPU_GFX_TCX_FIFOD0 = 0, 3854 AMDGPU_GFX_TCX_FIFOD1, 3855 AMDGPU_GFX_TCX_FIFOD2, 3856 AMDGPU_GFX_TCX_FIFOD3, 3857 AMDGPU_GFX_TCX_FIFOD4, 3858 AMDGPU_GFX_TCX_FIFOD5, 3859 AMDGPU_GFX_TCX_FIFOD6, 3860 AMDGPU_GFX_TCX_FIFOD7, 3861 AMDGPU_GFX_TCX_FIFOB0, 3862 AMDGPU_GFX_TCX_FIFOB1, 3863 AMDGPU_GFX_TCX_FIFOB2, 3864 AMDGPU_GFX_TCX_FIFOB3, 3865 AMDGPU_GFX_TCX_FIFOB4, 3866 AMDGPU_GFX_TCX_FIFOB5, 3867 AMDGPU_GFX_TCX_FIFOB6, 3868 AMDGPU_GFX_TCX_FIFOB7, 3869 AMDGPU_GFX_TCX_FIFOA0, 3870 AMDGPU_GFX_TCX_FIFOA1, 3871 AMDGPU_GFX_TCX_FIFOA2, 3872 AMDGPU_GFX_TCX_FIFOA3, 3873 AMDGPU_GFX_TCX_FIFOA4, 3874 AMDGPU_GFX_TCX_FIFOA5, 3875 AMDGPU_GFX_TCX_FIFOA6, 3876 AMDGPU_GFX_TCX_FIFOA7, 3877 AMDGPU_GFX_TCX_CFIFO0, 3878 AMDGPU_GFX_TCX_CFIFO1, 3879 AMDGPU_GFX_TCX_CFIFO2, 3880 AMDGPU_GFX_TCX_CFIFO3, 3881 AMDGPU_GFX_TCX_CFIFO4, 3882 AMDGPU_GFX_TCX_CFIFO5, 3883 AMDGPU_GFX_TCX_CFIFO6, 3884 AMDGPU_GFX_TCX_CFIFO7, 3885 AMDGPU_GFX_TCX_FIFO_ACKB0, 3886 AMDGPU_GFX_TCX_FIFO_ACKB1, 3887 AMDGPU_GFX_TCX_FIFO_ACKB2, 3888 AMDGPU_GFX_TCX_FIFO_ACKB3, 3889 AMDGPU_GFX_TCX_FIFO_ACKB4, 3890 AMDGPU_GFX_TCX_FIFO_ACKB5, 3891 AMDGPU_GFX_TCX_FIFO_ACKB6, 3892 AMDGPU_GFX_TCX_FIFO_ACKB7, 3893 AMDGPU_GFX_TCX_FIFO_ACKD0, 3894 AMDGPU_GFX_TCX_FIFO_ACKD1, 3895 AMDGPU_GFX_TCX_FIFO_ACKD2, 3896 AMDGPU_GFX_TCX_FIFO_ACKD3, 3897 AMDGPU_GFX_TCX_FIFO_ACKD4, 3898 AMDGPU_GFX_TCX_FIFO_ACKD5, 3899 AMDGPU_GFX_TCX_FIFO_ACKD6, 3900 AMDGPU_GFX_TCX_FIFO_ACKD7, 3901 AMDGPU_GFX_TCX_DST_FIFOA0, 3902 AMDGPU_GFX_TCX_DST_FIFOA1, 3903 AMDGPU_GFX_TCX_DST_FIFOA2, 3904 AMDGPU_GFX_TCX_DST_FIFOA3, 3905 AMDGPU_GFX_TCX_DST_FIFOA4, 3906 AMDGPU_GFX_TCX_DST_FIFOA5, 3907 AMDGPU_GFX_TCX_DST_FIFOA6, 3908 AMDGPU_GFX_TCX_DST_FIFOA7, 3909 AMDGPU_GFX_TCX_DST_FIFOB0, 3910 AMDGPU_GFX_TCX_DST_FIFOB1, 3911 AMDGPU_GFX_TCX_DST_FIFOB2, 3912 AMDGPU_GFX_TCX_DST_FIFOB3, 3913 AMDGPU_GFX_TCX_DST_FIFOB4, 3914 AMDGPU_GFX_TCX_DST_FIFOB5, 3915 AMDGPU_GFX_TCX_DST_FIFOB6, 3916 AMDGPU_GFX_TCX_DST_FIFOB7, 3917 AMDGPU_GFX_TCX_DST_FIFOD0, 3918 AMDGPU_GFX_TCX_DST_FIFOD1, 3919 AMDGPU_GFX_TCX_DST_FIFOD2, 3920 AMDGPU_GFX_TCX_DST_FIFOD3, 3921 AMDGPU_GFX_TCX_DST_FIFOD4, 3922 AMDGPU_GFX_TCX_DST_FIFOD5, 3923 AMDGPU_GFX_TCX_DST_FIFOD6, 3924 AMDGPU_GFX_TCX_DST_FIFOD7, 3925 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3926 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3927 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3928 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3929 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3930 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3931 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3932 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3933 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3934 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3935 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3936 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3937 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3938 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3939 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3940 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3941 }; 3942 3943 enum amdgpu_gfx_atc_l2_ras_mem_id { 3944 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3945 }; 3946 3947 enum amdgpu_gfx_utcl2_ras_mem_id { 3948 AMDGPU_GFX_UTCL2_MEM0 = 0, 3949 }; 3950 3951 enum amdgpu_gfx_vml2_ras_mem_id { 3952 AMDGPU_GFX_VML2_MEM0 = 0, 3953 }; 3954 3955 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3956 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3957 }; 3958 3959 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3960 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3961 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3962 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3963 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3964 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3965 }; 3966 3967 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3968 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3969 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3970 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3971 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3972 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3973 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3974 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3975 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3976 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3977 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3978 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3979 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3980 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3981 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3982 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3983 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3984 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3985 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3986 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3987 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3988 }; 3989 3990 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3991 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3992 }; 3993 3994 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3995 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3996 }; 3997 3998 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3999 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 4000 }; 4001 4002 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 4003 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 4004 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 4005 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 4006 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 4007 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 4008 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 4009 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 4010 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 4011 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 4012 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 4013 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 4014 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 4015 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 4016 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 4017 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 4018 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 4019 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 4020 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 4021 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 4022 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 4023 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 4024 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 4025 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 4026 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 4027 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 4028 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 4029 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 4030 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 4031 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 4032 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 4033 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 4034 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 4035 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 4036 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4037 }; 4038 4039 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4040 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4041 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4042 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4043 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4044 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4045 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4046 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4047 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4048 }; 4049 4050 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4051 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4052 }; 4053 4054 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4055 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4056 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4057 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4058 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4059 }; 4060 4061 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4062 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4063 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4064 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4065 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4066 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4067 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4068 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4069 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4070 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4071 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4072 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4073 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4074 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4075 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4076 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4077 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4078 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4079 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4080 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4081 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4082 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4083 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4084 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4085 }; 4086 4087 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4088 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4089 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4090 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4091 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4092 }; 4093 4094 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4095 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4096 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4097 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4098 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4099 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4100 }; 4101 4102 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4103 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4104 }; 4105 4106 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4107 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4108 }; 4109 4110 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4111 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4112 }; 4113 4114 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4115 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4116 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4117 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4118 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4119 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4120 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4121 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4122 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4123 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4124 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4125 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4126 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4127 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4128 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4129 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4130 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4131 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4132 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4133 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4134 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4135 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4136 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4137 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4138 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4139 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4140 }; 4141 4142 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4143 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4144 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4145 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4146 }; 4147 4148 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4149 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4150 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4151 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4152 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4153 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4154 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4155 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4156 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4157 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4158 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4159 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4160 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4161 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4162 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4163 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4164 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4165 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4166 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4167 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4168 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4169 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4170 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4171 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4172 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4173 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4174 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4175 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4176 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4177 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4178 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4179 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4180 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4181 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4182 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4183 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4184 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4185 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4186 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4187 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4188 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4189 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4190 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4191 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4192 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4193 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4194 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4195 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4196 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4197 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4198 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4199 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4200 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4201 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4202 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4203 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4204 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4205 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4206 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4207 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4208 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4209 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4210 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4211 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4212 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4213 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4214 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4215 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4216 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4217 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4218 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4219 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4220 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4221 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4222 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4223 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4224 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4225 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4226 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4227 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4228 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4229 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4230 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4231 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4232 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4233 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4234 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4235 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4236 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4237 }; 4238 4239 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4240 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4241 }; 4242 4243 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4244 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4245 }; 4246 4247 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4248 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4249 }; 4250 4251 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4252 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4253 }; 4254 4255 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4256 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4257 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4258 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4259 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4260 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4261 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4262 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4263 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4264 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4265 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4266 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4267 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4268 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4269 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4270 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4271 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4272 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4273 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4274 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4275 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4276 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4277 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4278 }; 4279 4280 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4281 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4282 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4283 AMDGPU_GFX_RLC_MEM, 1}, 4284 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4285 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4286 AMDGPU_GFX_CP_MEM, 1}, 4287 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4288 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4289 AMDGPU_GFX_CP_MEM, 1}, 4290 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4291 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4292 AMDGPU_GFX_CP_MEM, 1}, 4293 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4294 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4295 AMDGPU_GFX_GDS_MEM, 1}, 4296 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4297 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4298 AMDGPU_GFX_GC_CANE_MEM, 1}, 4299 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4300 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4301 AMDGPU_GFX_SPI_MEM, 1}, 4302 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4303 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4304 AMDGPU_GFX_SP_MEM, 4}, 4305 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4306 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4307 AMDGPU_GFX_SP_MEM, 4}, 4308 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4309 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4310 AMDGPU_GFX_SQ_MEM, 4}, 4311 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4312 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4313 AMDGPU_GFX_SQC_MEM, 4}, 4314 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4315 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4316 AMDGPU_GFX_TCX_MEM, 1}, 4317 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4318 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4319 AMDGPU_GFX_TCC_MEM, 1}, 4320 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4321 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4322 AMDGPU_GFX_TA_MEM, 4}, 4323 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4324 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4325 AMDGPU_GFX_TCI_MEM, 1}, 4326 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4327 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4328 AMDGPU_GFX_TCP_MEM, 4}, 4329 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4330 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4331 AMDGPU_GFX_TD_MEM, 4}, 4332 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4333 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4334 AMDGPU_GFX_GCEA_MEM, 1}, 4335 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4336 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4337 AMDGPU_GFX_LDS_MEM, 4}, 4338 }; 4339 4340 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4341 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4342 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4343 AMDGPU_GFX_RLC_MEM, 1}, 4344 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4345 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4346 AMDGPU_GFX_CP_MEM, 1}, 4347 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4348 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4349 AMDGPU_GFX_CP_MEM, 1}, 4350 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4351 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4352 AMDGPU_GFX_CP_MEM, 1}, 4353 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4354 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4355 AMDGPU_GFX_GDS_MEM, 1}, 4356 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4357 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4358 AMDGPU_GFX_GC_CANE_MEM, 1}, 4359 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4360 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4361 AMDGPU_GFX_SPI_MEM, 1}, 4362 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4363 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4364 AMDGPU_GFX_SP_MEM, 4}, 4365 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4366 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4367 AMDGPU_GFX_SP_MEM, 4}, 4368 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4369 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4370 AMDGPU_GFX_SQ_MEM, 4}, 4371 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4372 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4373 AMDGPU_GFX_SQC_MEM, 4}, 4374 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4375 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4376 AMDGPU_GFX_TCX_MEM, 1}, 4377 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4378 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4379 AMDGPU_GFX_TCC_MEM, 1}, 4380 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4381 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4382 AMDGPU_GFX_TA_MEM, 4}, 4383 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4384 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4385 AMDGPU_GFX_TCI_MEM, 1}, 4386 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4387 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4388 AMDGPU_GFX_TCP_MEM, 4}, 4389 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4390 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4391 AMDGPU_GFX_TD_MEM, 4}, 4392 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4393 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4394 AMDGPU_GFX_TCA_MEM, 1}, 4395 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4396 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4397 AMDGPU_GFX_GCEA_MEM, 1}, 4398 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4399 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4400 AMDGPU_GFX_LDS_MEM, 4}, 4401 }; 4402 4403 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4404 void *ras_error_status, int xcc_id) 4405 { 4406 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4407 unsigned long ce_count = 0, ue_count = 0; 4408 uint32_t i, j, k; 4409 4410 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4411 struct amdgpu_smuio_mcm_config_info mcm_info = { 4412 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4413 .die_id = xcc_id & 0x01 ? 1 : 0, 4414 }; 4415 4416 mutex_lock(&adev->grbm_idx_mutex); 4417 4418 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4419 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4420 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4421 /* no need to select if instance number is 1 */ 4422 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4423 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4424 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4425 4426 amdgpu_ras_inst_query_ras_error_count(adev, 4427 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4428 1, 4429 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4430 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4431 GET_INST(GC, xcc_id), 4432 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4433 &ce_count); 4434 4435 amdgpu_ras_inst_query_ras_error_count(adev, 4436 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4437 1, 4438 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4439 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4440 GET_INST(GC, xcc_id), 4441 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4442 &ue_count); 4443 } 4444 } 4445 } 4446 4447 /* handle extra register entries of UE */ 4448 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4449 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4450 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4451 /* no need to select if instance number is 1 */ 4452 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4453 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4454 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4455 4456 amdgpu_ras_inst_query_ras_error_count(adev, 4457 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4458 1, 4459 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4460 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4461 GET_INST(GC, xcc_id), 4462 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4463 &ue_count); 4464 } 4465 } 4466 } 4467 4468 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4469 xcc_id); 4470 mutex_unlock(&adev->grbm_idx_mutex); 4471 4472 /* the caller should make sure initialize value of 4473 * err_data->ue_count and err_data->ce_count 4474 */ 4475 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4476 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4477 } 4478 4479 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4480 void *ras_error_status, int xcc_id) 4481 { 4482 uint32_t i, j, k; 4483 4484 mutex_lock(&adev->grbm_idx_mutex); 4485 4486 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4487 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4488 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4489 /* no need to select if instance number is 1 */ 4490 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4491 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4492 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4493 4494 amdgpu_ras_inst_reset_ras_error_count(adev, 4495 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4496 1, 4497 GET_INST(GC, xcc_id)); 4498 4499 amdgpu_ras_inst_reset_ras_error_count(adev, 4500 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4501 1, 4502 GET_INST(GC, xcc_id)); 4503 } 4504 } 4505 } 4506 4507 /* handle extra register entries of UE */ 4508 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4509 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4510 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4511 /* no need to select if instance number is 1 */ 4512 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4513 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4514 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4515 4516 amdgpu_ras_inst_reset_ras_error_count(adev, 4517 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4518 1, 4519 GET_INST(GC, xcc_id)); 4520 } 4521 } 4522 } 4523 4524 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4525 xcc_id); 4526 mutex_unlock(&adev->grbm_idx_mutex); 4527 } 4528 4529 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4530 void *ras_error_status, int xcc_id) 4531 { 4532 uint32_t i; 4533 uint32_t data; 4534 4535 if (amdgpu_sriov_vf(adev)) 4536 return; 4537 4538 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4539 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4540 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4541 4542 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4543 (amdgpu_watchdog_timer.period < 1 || 4544 amdgpu_watchdog_timer.period > 0x23)) { 4545 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4546 amdgpu_watchdog_timer.period = 0x23; 4547 } 4548 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4549 amdgpu_watchdog_timer.period); 4550 4551 mutex_lock(&adev->grbm_idx_mutex); 4552 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4553 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4554 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4555 } 4556 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4557 xcc_id); 4558 mutex_unlock(&adev->grbm_idx_mutex); 4559 } 4560 4561 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4562 void *ras_error_status) 4563 { 4564 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4565 gfx_v9_4_3_inst_query_ras_err_count); 4566 } 4567 4568 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4569 { 4570 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4571 } 4572 4573 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4574 { 4575 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4576 } 4577 4578 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4579 { 4580 /* Header itself is a NOP packet */ 4581 if (num_nop == 1) { 4582 amdgpu_ring_write(ring, ring->funcs->nop); 4583 return; 4584 } 4585 4586 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4587 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4588 4589 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4590 amdgpu_ring_insert_nop(ring, num_nop - 1); 4591 } 4592 4593 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4594 { 4595 struct amdgpu_device *adev = ip_block->adev; 4596 uint32_t i, j, k; 4597 uint32_t xcc_id, xcc_offset, inst_offset; 4598 uint32_t num_xcc, reg, num_inst; 4599 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4600 4601 if (!adev->gfx.ip_dump_core) 4602 return; 4603 4604 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4605 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4606 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4607 xcc_offset = xcc_id * reg_count; 4608 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4609 for (i = 0; i < reg_count; i++) 4610 drm_printf(p, "%-50s \t 0x%08x\n", 4611 gc_reg_list_9_4_3[i].reg_name, 4612 adev->gfx.ip_dump_core[xcc_offset + i]); 4613 } 4614 4615 /* print compute queue registers for all instances */ 4616 if (!adev->gfx.ip_dump_compute_queues) 4617 return; 4618 4619 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4620 adev->gfx.mec.num_queue_per_pipe; 4621 4622 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4623 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4624 num_xcc, 4625 adev->gfx.mec.num_mec, 4626 adev->gfx.mec.num_pipe_per_mec, 4627 adev->gfx.mec.num_queue_per_pipe); 4628 4629 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4630 xcc_offset = xcc_id * reg_count * num_inst; 4631 inst_offset = 0; 4632 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4633 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4634 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4635 drm_printf(p, 4636 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4637 xcc_id, i, j, k); 4638 for (reg = 0; reg < reg_count; reg++) { 4639 drm_printf(p, 4640 "%-50s \t 0x%08x\n", 4641 gc_cp_reg_list_9_4_3[reg].reg_name, 4642 adev->gfx.ip_dump_compute_queues 4643 [xcc_offset + inst_offset + 4644 reg]); 4645 } 4646 inst_offset += reg_count; 4647 } 4648 } 4649 } 4650 } 4651 } 4652 4653 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4654 { 4655 struct amdgpu_device *adev = ip_block->adev; 4656 uint32_t i, j, k; 4657 uint32_t num_xcc, reg, num_inst; 4658 uint32_t xcc_id, xcc_offset, inst_offset; 4659 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4660 4661 if (!adev->gfx.ip_dump_core) 4662 return; 4663 4664 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4665 4666 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4667 xcc_offset = xcc_id * reg_count; 4668 for (i = 0; i < reg_count; i++) 4669 adev->gfx.ip_dump_core[xcc_offset + i] = 4670 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4671 GET_INST(GC, xcc_id))); 4672 } 4673 4674 /* dump compute queue registers for all instances */ 4675 if (!adev->gfx.ip_dump_compute_queues) 4676 return; 4677 4678 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4679 adev->gfx.mec.num_queue_per_pipe; 4680 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4681 mutex_lock(&adev->srbm_mutex); 4682 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4683 xcc_offset = xcc_id * reg_count * num_inst; 4684 inst_offset = 0; 4685 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4686 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4687 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4688 /* ME0 is for GFX so start from 1 for CP */ 4689 soc15_grbm_select(adev, 1 + i, j, k, 0, 4690 GET_INST(GC, xcc_id)); 4691 4692 for (reg = 0; reg < reg_count; reg++) { 4693 adev->gfx.ip_dump_compute_queues 4694 [xcc_offset + 4695 inst_offset + reg] = 4696 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4697 gc_cp_reg_list_9_4_3[reg], 4698 GET_INST(GC, xcc_id))); 4699 } 4700 inst_offset += reg_count; 4701 } 4702 } 4703 } 4704 } 4705 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4706 mutex_unlock(&adev->srbm_mutex); 4707 } 4708 4709 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4710 { 4711 /* Emit the cleaner shader */ 4712 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4713 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4714 } 4715 4716 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4717 .name = "gfx_v9_4_3", 4718 .early_init = gfx_v9_4_3_early_init, 4719 .late_init = gfx_v9_4_3_late_init, 4720 .sw_init = gfx_v9_4_3_sw_init, 4721 .sw_fini = gfx_v9_4_3_sw_fini, 4722 .hw_init = gfx_v9_4_3_hw_init, 4723 .hw_fini = gfx_v9_4_3_hw_fini, 4724 .suspend = gfx_v9_4_3_suspend, 4725 .resume = gfx_v9_4_3_resume, 4726 .is_idle = gfx_v9_4_3_is_idle, 4727 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4728 .soft_reset = gfx_v9_4_3_soft_reset, 4729 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4730 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4731 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4732 .dump_ip_state = gfx_v9_4_3_ip_dump, 4733 .print_ip_state = gfx_v9_4_3_ip_print, 4734 }; 4735 4736 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4737 .type = AMDGPU_RING_TYPE_COMPUTE, 4738 .align_mask = 0xff, 4739 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4740 .support_64bit_ptrs = true, 4741 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4742 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4743 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4744 .emit_frame_size = 4745 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4746 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4747 5 + /* hdp invalidate */ 4748 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4749 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4750 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4751 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4752 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4753 7 + /* gfx_v9_4_3_emit_mem_sync */ 4754 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4755 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4756 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4757 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4758 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4759 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4760 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4761 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4762 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4763 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4764 .test_ring = gfx_v9_4_3_ring_test_ring, 4765 .test_ib = gfx_v9_4_3_ring_test_ib, 4766 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4767 .pad_ib = amdgpu_ring_generic_pad_ib, 4768 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4769 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4770 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4771 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4772 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4773 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4774 .reset = gfx_v9_4_3_reset_kcq, 4775 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4776 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4777 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4778 }; 4779 4780 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4781 .type = AMDGPU_RING_TYPE_KIQ, 4782 .align_mask = 0xff, 4783 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4784 .support_64bit_ptrs = true, 4785 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4786 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4787 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4788 .emit_frame_size = 4789 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4790 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4791 5 + /* hdp invalidate */ 4792 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4793 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4794 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4795 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4796 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4797 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4798 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4799 .test_ring = gfx_v9_4_3_ring_test_ring, 4800 .insert_nop = amdgpu_ring_insert_nop, 4801 .pad_ib = amdgpu_ring_generic_pad_ib, 4802 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4803 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4804 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4805 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4806 }; 4807 4808 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4809 { 4810 int i, j, num_xcc; 4811 4812 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4813 for (i = 0; i < num_xcc; i++) { 4814 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4815 4816 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4817 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4818 = &gfx_v9_4_3_ring_funcs_compute; 4819 } 4820 } 4821 4822 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4823 .set = gfx_v9_4_3_set_eop_interrupt_state, 4824 .process = gfx_v9_4_3_eop_irq, 4825 }; 4826 4827 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4828 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4829 .process = gfx_v9_4_3_priv_reg_irq, 4830 }; 4831 4832 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4833 .set = gfx_v9_4_3_set_bad_op_fault_state, 4834 .process = gfx_v9_4_3_bad_op_irq, 4835 }; 4836 4837 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4838 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4839 .process = gfx_v9_4_3_priv_inst_irq, 4840 }; 4841 4842 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4843 { 4844 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4845 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4846 4847 adev->gfx.priv_reg_irq.num_types = 1; 4848 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4849 4850 adev->gfx.bad_op_irq.num_types = 1; 4851 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4852 4853 adev->gfx.priv_inst_irq.num_types = 1; 4854 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4855 } 4856 4857 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4858 { 4859 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4860 } 4861 4862 4863 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4864 { 4865 /* init asci gds info */ 4866 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4867 case IP_VERSION(9, 4, 3): 4868 case IP_VERSION(9, 4, 4): 4869 case IP_VERSION(9, 5, 0): 4870 /* 9.4.3 removed all the GDS internal memory, 4871 * only support GWS opcode in kernel, like barrier 4872 * semaphore.etc */ 4873 adev->gds.gds_size = 0; 4874 break; 4875 default: 4876 adev->gds.gds_size = 0x10000; 4877 break; 4878 } 4879 4880 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4881 case IP_VERSION(9, 4, 3): 4882 case IP_VERSION(9, 4, 4): 4883 case IP_VERSION(9, 5, 0): 4884 /* deprecated for 9.4.3, no usage at all */ 4885 adev->gds.gds_compute_max_wave_id = 0; 4886 break; 4887 default: 4888 /* this really depends on the chip */ 4889 adev->gds.gds_compute_max_wave_id = 0x7ff; 4890 break; 4891 } 4892 4893 adev->gds.gws_size = 64; 4894 adev->gds.oa_size = 16; 4895 } 4896 4897 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4898 u32 bitmap, int xcc_id) 4899 { 4900 u32 data; 4901 4902 if (!bitmap) 4903 return; 4904 4905 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4906 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4907 4908 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4909 } 4910 4911 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4912 { 4913 u32 data, mask; 4914 4915 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4916 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4917 4918 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4919 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4920 4921 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4922 4923 return (~data) & mask; 4924 } 4925 4926 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4927 struct amdgpu_cu_info *cu_info) 4928 { 4929 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4930 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4931 unsigned disable_masks[4 * 4]; 4932 bool is_symmetric_cus; 4933 4934 if (!adev || !cu_info) 4935 return -EINVAL; 4936 4937 /* 4938 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4939 */ 4940 if (adev->gfx.config.max_shader_engines * 4941 adev->gfx.config.max_sh_per_se > 16) 4942 return -EINVAL; 4943 4944 amdgpu_gfx_parse_disable_cu(disable_masks, 4945 adev->gfx.config.max_shader_engines, 4946 adev->gfx.config.max_sh_per_se); 4947 4948 mutex_lock(&adev->grbm_idx_mutex); 4949 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4950 is_symmetric_cus = true; 4951 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4952 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4953 mask = 1; 4954 ao_bitmap = 0; 4955 counter = 0; 4956 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4957 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4958 adev, 4959 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4960 xcc_id); 4961 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4962 4963 cu_info->bitmap[xcc_id][i][j] = bitmap; 4964 4965 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4966 if (bitmap & mask) { 4967 if (counter < adev->gfx.config.max_cu_per_sh) 4968 ao_bitmap |= mask; 4969 counter++; 4970 } 4971 mask <<= 1; 4972 } 4973 active_cu_number += counter; 4974 if (i < 2 && j < 2) 4975 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4976 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4977 } 4978 if (i && is_symmetric_cus && prev_counter != counter) 4979 is_symmetric_cus = false; 4980 prev_counter = counter; 4981 } 4982 if (is_symmetric_cus) { 4983 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4984 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4985 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4986 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4987 } 4988 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4989 xcc_id); 4990 } 4991 mutex_unlock(&adev->grbm_idx_mutex); 4992 4993 cu_info->number = active_cu_number; 4994 cu_info->ao_cu_mask = ao_cu_mask; 4995 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4996 4997 return 0; 4998 } 4999 5000 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 5001 .type = AMD_IP_BLOCK_TYPE_GFX, 5002 .major = 9, 5003 .minor = 4, 5004 .rev = 3, 5005 .funcs = &gfx_v9_4_3_ip_funcs, 5006 }; 5007 5008 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 5009 { 5010 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5011 uint32_t tmp_mask; 5012 int i, r; 5013 5014 /* TODO : Initialize golden regs */ 5015 /* gfx_v9_4_3_init_golden_registers(adev); */ 5016 5017 tmp_mask = inst_mask; 5018 for_each_inst(i, tmp_mask) 5019 gfx_v9_4_3_xcc_constants_init(adev, i); 5020 5021 if (!amdgpu_sriov_vf(adev)) { 5022 tmp_mask = inst_mask; 5023 for_each_inst(i, tmp_mask) { 5024 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 5025 if (r) 5026 return r; 5027 } 5028 } 5029 5030 tmp_mask = inst_mask; 5031 for_each_inst(i, tmp_mask) { 5032 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 5033 if (r) 5034 return r; 5035 } 5036 5037 return 0; 5038 } 5039 5040 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 5041 { 5042 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5043 int i; 5044 5045 for_each_inst(i, inst_mask) 5046 gfx_v9_4_3_xcc_fini(adev, i); 5047 5048 return 0; 5049 } 5050 5051 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5052 .suspend = &gfx_v9_4_3_xcp_suspend, 5053 .resume = &gfx_v9_4_3_xcp_resume 5054 }; 5055 5056 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5057 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5058 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5059 }; 5060 5061 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5062 { 5063 int r; 5064 5065 r = amdgpu_ras_block_late_init(adev, ras_block); 5066 if (r) 5067 return r; 5068 5069 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5070 &gfx_v9_4_3_aca_info, 5071 NULL); 5072 if (r) 5073 goto late_fini; 5074 5075 return 0; 5076 5077 late_fini: 5078 amdgpu_ras_block_late_fini(adev, ras_block); 5079 5080 return r; 5081 } 5082 5083 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5084 .ras_block = { 5085 .hw_ops = &gfx_v9_4_3_ras_ops, 5086 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5087 }, 5088 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5089 }; 5090