1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* SE status registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 110 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 111 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 113 }; 114 115 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 116 /* compute queue registers */ 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 162 }; 163 164 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 165 166 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 167 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 168 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 169 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 170 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 171 struct amdgpu_cu_info *cu_info); 172 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 173 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 174 175 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 176 uint64_t queue_mask) 177 { 178 struct amdgpu_device *adev = kiq_ring->adev; 179 u64 shader_mc_addr; 180 181 /* Cleaner shader MC address */ 182 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 183 184 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 185 amdgpu_ring_write(kiq_ring, 186 PACKET3_SET_RESOURCES_VMID_MASK(0) | 187 /* vmid_mask:0* queue_type:0 (KIQ) */ 188 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 189 amdgpu_ring_write(kiq_ring, 190 lower_32_bits(queue_mask)); /* queue mask lo */ 191 amdgpu_ring_write(kiq_ring, 192 upper_32_bits(queue_mask)); /* queue mask hi */ 193 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 194 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 195 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 196 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 197 } 198 199 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 200 struct amdgpu_ring *ring) 201 { 202 struct amdgpu_device *adev = kiq_ring->adev; 203 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 204 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 205 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 206 207 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 208 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 209 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 210 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 211 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 212 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 213 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 214 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 215 /*queue_type: normal compute queue */ 216 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 217 /* alloc format: all_on_one_pipe */ 218 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 219 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 220 /* num_queues: must be 1 */ 221 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 222 amdgpu_ring_write(kiq_ring, 223 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 224 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 225 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 226 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 227 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 228 } 229 230 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 231 struct amdgpu_ring *ring, 232 enum amdgpu_unmap_queues_action action, 233 u64 gpu_addr, u64 seq) 234 { 235 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 236 237 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 238 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 239 PACKET3_UNMAP_QUEUES_ACTION(action) | 240 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 241 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 242 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 243 amdgpu_ring_write(kiq_ring, 244 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 245 246 if (action == PREEMPT_QUEUES_NO_UNMAP) { 247 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 248 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 249 amdgpu_ring_write(kiq_ring, seq); 250 } else { 251 amdgpu_ring_write(kiq_ring, 0); 252 amdgpu_ring_write(kiq_ring, 0); 253 amdgpu_ring_write(kiq_ring, 0); 254 } 255 } 256 257 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 258 struct amdgpu_ring *ring, 259 u64 addr, 260 u64 seq) 261 { 262 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 263 264 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 267 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 268 PACKET3_QUERY_STATUS_COMMAND(2)); 269 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 270 amdgpu_ring_write(kiq_ring, 271 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 272 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 273 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 274 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 275 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 276 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 277 } 278 279 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 280 uint16_t pasid, uint32_t flush_type, 281 bool all_hub) 282 { 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 284 amdgpu_ring_write(kiq_ring, 285 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 286 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 287 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 288 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 289 } 290 291 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 292 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 293 uint32_t xcc_id, uint32_t vmid) 294 { 295 struct amdgpu_device *adev = kiq_ring->adev; 296 unsigned i; 297 298 /* enter save mode */ 299 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 300 mutex_lock(&adev->srbm_mutex); 301 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 302 303 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 305 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 306 /* wait till dequeue take effects */ 307 for (i = 0; i < adev->usec_timeout; i++) { 308 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 309 break; 310 udelay(1); 311 } 312 if (i >= adev->usec_timeout) 313 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 314 } else { 315 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 316 } 317 318 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 319 mutex_unlock(&adev->srbm_mutex); 320 /* exit safe mode */ 321 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 322 } 323 324 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 325 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 326 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 327 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 328 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 329 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 330 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 331 .set_resources_size = 8, 332 .map_queues_size = 7, 333 .unmap_queues_size = 6, 334 .query_status_size = 7, 335 .invalidate_tlbs_size = 2, 336 }; 337 338 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 339 { 340 int i, num_xcc; 341 342 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 343 for (i = 0; i < num_xcc; i++) 344 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 345 } 346 347 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 348 { 349 int i, num_xcc, dev_inst; 350 351 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 352 for (i = 0; i < num_xcc; i++) { 353 dev_inst = GET_INST(GC, i); 354 355 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 356 GOLDEN_GB_ADDR_CONFIG); 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 358 } 359 } 360 361 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 362 { 363 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 364 365 /* If it is an XCC reg, normalize the reg to keep 366 lower 16 bits in local xcc */ 367 368 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 369 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 370 return normalized_reg; 371 else 372 return reg; 373 } 374 375 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 376 bool wc, uint32_t reg, uint32_t val) 377 { 378 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 379 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 380 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 381 WRITE_DATA_DST_SEL(0) | 382 (wc ? WR_CONFIRM : 0)); 383 amdgpu_ring_write(ring, reg); 384 amdgpu_ring_write(ring, 0); 385 amdgpu_ring_write(ring, val); 386 } 387 388 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 389 int mem_space, int opt, uint32_t addr0, 390 uint32_t addr1, uint32_t ref, uint32_t mask, 391 uint32_t inv) 392 { 393 /* Only do the normalization on regspace */ 394 if (mem_space == 0) { 395 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 396 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 397 } 398 399 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 400 amdgpu_ring_write(ring, 401 /* memory (1) or register (0) */ 402 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 403 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 404 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 405 WAIT_REG_MEM_ENGINE(eng_sel))); 406 407 if (mem_space) 408 BUG_ON(addr0 & 0x3); /* Dword align */ 409 amdgpu_ring_write(ring, addr0); 410 amdgpu_ring_write(ring, addr1); 411 amdgpu_ring_write(ring, ref); 412 amdgpu_ring_write(ring, mask); 413 amdgpu_ring_write(ring, inv); /* poll interval */ 414 } 415 416 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 417 { 418 uint32_t scratch_reg0_offset, xcc_offset; 419 struct amdgpu_device *adev = ring->adev; 420 uint32_t tmp = 0; 421 unsigned i; 422 int r; 423 424 /* Use register offset which is local to XCC in the packet */ 425 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 426 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 427 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 428 tmp = RREG32(scratch_reg0_offset); 429 430 r = amdgpu_ring_alloc(ring, 3); 431 if (r) 432 return r; 433 434 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 435 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 436 amdgpu_ring_write(ring, 0xDEADBEEF); 437 amdgpu_ring_commit(ring); 438 439 for (i = 0; i < adev->usec_timeout; i++) { 440 tmp = RREG32(scratch_reg0_offset); 441 if (tmp == 0xDEADBEEF) 442 break; 443 udelay(1); 444 } 445 446 if (i >= adev->usec_timeout) 447 r = -ETIMEDOUT; 448 return r; 449 } 450 451 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 struct amdgpu_ib ib; 455 struct dma_fence *f = NULL; 456 457 unsigned index; 458 uint64_t gpu_addr; 459 uint32_t tmp; 460 long r; 461 462 r = amdgpu_device_wb_get(adev, &index); 463 if (r) 464 return r; 465 466 gpu_addr = adev->wb.gpu_addr + (index * 4); 467 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 468 memset(&ib, 0, sizeof(ib)); 469 470 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 471 if (r) 472 goto err1; 473 474 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 475 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 476 ib.ptr[2] = lower_32_bits(gpu_addr); 477 ib.ptr[3] = upper_32_bits(gpu_addr); 478 ib.ptr[4] = 0xDEADBEEF; 479 ib.length_dw = 5; 480 481 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 482 if (r) 483 goto err2; 484 485 r = dma_fence_wait_timeout(f, false, timeout); 486 if (r == 0) { 487 r = -ETIMEDOUT; 488 goto err2; 489 } else if (r < 0) { 490 goto err2; 491 } 492 493 tmp = adev->wb.wb[index]; 494 if (tmp == 0xDEADBEEF) 495 r = 0; 496 else 497 r = -EINVAL; 498 499 err2: 500 amdgpu_ib_free(&ib, NULL); 501 dma_fence_put(f); 502 err1: 503 amdgpu_device_wb_free(adev, index); 504 return r; 505 } 506 507 508 /* This value might differs per partition */ 509 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 510 { 511 uint64_t clock; 512 513 mutex_lock(&adev->gfx.gpu_clock_mutex); 514 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 515 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 516 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 517 mutex_unlock(&adev->gfx.gpu_clock_mutex); 518 519 return clock; 520 } 521 522 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 523 { 524 amdgpu_ucode_release(&adev->gfx.pfp_fw); 525 amdgpu_ucode_release(&adev->gfx.me_fw); 526 amdgpu_ucode_release(&adev->gfx.ce_fw); 527 amdgpu_ucode_release(&adev->gfx.rlc_fw); 528 amdgpu_ucode_release(&adev->gfx.mec_fw); 529 amdgpu_ucode_release(&adev->gfx.mec2_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 535 const char *chip_name) 536 { 537 int err; 538 const struct rlc_firmware_header_v2_0 *rlc_hdr; 539 uint16_t version_major; 540 uint16_t version_minor; 541 542 543 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 544 AMDGPU_UCODE_REQUIRED, 545 "amdgpu/%s_rlc.bin", chip_name); 546 if (err) 547 goto out; 548 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 549 550 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 551 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 552 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 553 out: 554 if (err) 555 amdgpu_ucode_release(&adev->gfx.rlc_fw); 556 557 return err; 558 } 559 560 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 561 const char *chip_name) 562 { 563 int err; 564 565 if (amdgpu_sriov_vf(adev)) { 566 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 567 AMDGPU_UCODE_REQUIRED, 568 "amdgpu/%s_sjt_mec.bin", chip_name); 569 570 if (err) 571 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 572 AMDGPU_UCODE_REQUIRED, 573 "amdgpu/%s_mec.bin", chip_name); 574 } else 575 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 576 AMDGPU_UCODE_REQUIRED, 577 "amdgpu/%s_mec.bin", chip_name); 578 if (err) 579 goto out; 580 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 581 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 582 583 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 584 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 585 586 out: 587 if (err) 588 amdgpu_ucode_release(&adev->gfx.mec_fw); 589 return err; 590 } 591 592 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 593 { 594 char ucode_prefix[15]; 595 int r; 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 600 if (r) 601 return r; 602 603 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 604 if (r) 605 return r; 606 607 return r; 608 } 609 610 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 611 { 612 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 613 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 614 } 615 616 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 617 { 618 int r, i, num_xcc; 619 u32 *hpd; 620 const __le32 *fw_data; 621 unsigned fw_size; 622 u32 *fw; 623 size_t mec_hpd_size; 624 625 const struct gfx_firmware_header_v1_0 *mec_hdr; 626 627 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 628 for (i = 0; i < num_xcc; i++) 629 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 630 AMDGPU_MAX_COMPUTE_QUEUES); 631 632 /* take ownership of the relevant compute queues */ 633 amdgpu_gfx_compute_queue_acquire(adev); 634 mec_hpd_size = 635 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 636 if (mec_hpd_size) { 637 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 638 AMDGPU_GEM_DOMAIN_VRAM | 639 AMDGPU_GEM_DOMAIN_GTT, 640 &adev->gfx.mec.hpd_eop_obj, 641 &adev->gfx.mec.hpd_eop_gpu_addr, 642 (void **)&hpd); 643 if (r) { 644 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 645 gfx_v9_4_3_mec_fini(adev); 646 return r; 647 } 648 649 if (amdgpu_emu_mode == 1) { 650 for (i = 0; i < mec_hpd_size / 4; i++) { 651 memset((void *)(hpd + i), 0, 4); 652 if (i % 50 == 0) 653 msleep(1); 654 } 655 } else { 656 memset(hpd, 0, mec_hpd_size); 657 } 658 659 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 660 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 661 } 662 663 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 664 665 fw_data = (const __le32 *) 666 (adev->gfx.mec_fw->data + 667 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 668 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 669 670 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 671 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 672 &adev->gfx.mec.mec_fw_obj, 673 &adev->gfx.mec.mec_fw_gpu_addr, 674 (void **)&fw); 675 if (r) { 676 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 677 gfx_v9_4_3_mec_fini(adev); 678 return r; 679 } 680 681 memcpy(fw, fw_data, fw_size); 682 683 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 684 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 685 686 return 0; 687 } 688 689 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 690 u32 sh_num, u32 instance, int xcc_id) 691 { 692 u32 data; 693 694 if (instance == 0xffffffff) 695 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 696 INSTANCE_BROADCAST_WRITES, 1); 697 else 698 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 699 INSTANCE_INDEX, instance); 700 701 if (se_num == 0xffffffff) 702 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 703 SE_BROADCAST_WRITES, 1); 704 else 705 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 706 707 if (sh_num == 0xffffffff) 708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 709 SH_BROADCAST_WRITES, 1); 710 else 711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 712 713 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 714 } 715 716 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 717 { 718 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 719 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 720 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 721 (address << SQ_IND_INDEX__INDEX__SHIFT) | 722 (SQ_IND_INDEX__FORCE_READ_MASK)); 723 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 724 } 725 726 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 727 uint32_t wave, uint32_t thread, 728 uint32_t regno, uint32_t num, uint32_t *out) 729 { 730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 731 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 732 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 733 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 734 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 735 (SQ_IND_INDEX__FORCE_READ_MASK) | 736 (SQ_IND_INDEX__AUTO_INCR_MASK)); 737 while (num--) 738 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 739 } 740 741 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 742 uint32_t xcc_id, uint32_t simd, uint32_t wave, 743 uint32_t *dst, int *no_fields) 744 { 745 /* type 1 wave data */ 746 dst[(*no_fields)++] = 1; 747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 761 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 762 } 763 764 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 765 uint32_t wave, uint32_t start, 766 uint32_t size, uint32_t *dst) 767 { 768 wave_read_regs(adev, xcc_id, simd, wave, 0, 769 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 770 } 771 772 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 773 uint32_t wave, uint32_t thread, 774 uint32_t start, uint32_t size, 775 uint32_t *dst) 776 { 777 wave_read_regs(adev, xcc_id, simd, wave, thread, 778 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 779 } 780 781 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 782 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 783 { 784 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 785 } 786 787 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 788 { 789 u32 xcp_ctl; 790 791 /* Value is expected to be the same on all, fetch from first instance */ 792 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 793 794 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 795 } 796 797 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 798 int num_xccs_per_xcp) 799 { 800 int ret, i, num_xcc; 801 u32 tmp = 0; 802 803 if (adev->psp.funcs) { 804 ret = psp_spatial_partition(&adev->psp, 805 NUM_XCC(adev->gfx.xcc_mask) / 806 num_xccs_per_xcp); 807 if (ret) 808 return ret; 809 } else { 810 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 811 812 for (i = 0; i < num_xcc; i++) { 813 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 814 num_xccs_per_xcp); 815 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 816 i % num_xccs_per_xcp); 817 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 818 tmp); 819 } 820 ret = 0; 821 } 822 823 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 824 825 return ret; 826 } 827 828 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 829 { 830 int xcc; 831 832 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 833 if (!xcc) { 834 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 835 return -EINVAL; 836 } 837 838 return xcc - 1; 839 } 840 841 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 842 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 843 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 844 .read_wave_data = &gfx_v9_4_3_read_wave_data, 845 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 846 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 847 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 848 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 849 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 850 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 851 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 852 }; 853 854 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 855 struct aca_bank *bank, enum aca_smu_type type, 856 void *data) 857 { 858 struct aca_bank_info info; 859 u64 misc0; 860 u32 instlo; 861 int ret; 862 863 ret = aca_bank_info_decode(bank, &info); 864 if (ret) 865 return ret; 866 867 /* NOTE: overwrite info.die_id with xcd id for gfx */ 868 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 869 instlo &= GENMASK(31, 1); 870 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 871 872 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 873 874 switch (type) { 875 case ACA_SMU_TYPE_UE: 876 bank->aca_err_type = ACA_ERROR_TYPE_UE; 877 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL); 878 break; 879 case ACA_SMU_TYPE_CE: 880 bank->aca_err_type = ACA_ERROR_TYPE_CE; 881 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 882 ACA_REG__MISC0__ERRCNT(misc0)); 883 break; 884 default: 885 return -EINVAL; 886 } 887 888 return ret; 889 } 890 891 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 892 enum aca_smu_type type, void *data) 893 { 894 u32 instlo; 895 896 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 897 instlo &= GENMASK(31, 1); 898 switch (instlo) { 899 case mmSMNAID_XCD0_MCA_SMU: 900 case mmSMNAID_XCD1_MCA_SMU: 901 case mmSMNXCD_XCD0_MCA_SMU: 902 return true; 903 default: 904 break; 905 } 906 907 return false; 908 } 909 910 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 911 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 912 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 913 }; 914 915 static const struct aca_info gfx_v9_4_3_aca_info = { 916 .hwip = ACA_HWIP_TYPE_SMU, 917 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 918 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 919 }; 920 921 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 922 { 923 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 924 adev->gfx.ras = &gfx_v9_4_3_ras; 925 926 adev->gfx.config.max_hw_contexts = 8; 927 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 928 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 929 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 930 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 931 adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG; 932 933 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 934 REG_GET_FIELD( 935 adev->gfx.config.gb_addr_config, 936 GB_ADDR_CONFIG, 937 NUM_PIPES); 938 939 adev->gfx.config.max_tile_pipes = 940 adev->gfx.config.gb_addr_config_fields.num_pipes; 941 942 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 943 REG_GET_FIELD( 944 adev->gfx.config.gb_addr_config, 945 GB_ADDR_CONFIG, 946 NUM_BANKS); 947 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 948 REG_GET_FIELD( 949 adev->gfx.config.gb_addr_config, 950 GB_ADDR_CONFIG, 951 MAX_COMPRESSED_FRAGS); 952 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 953 REG_GET_FIELD( 954 adev->gfx.config.gb_addr_config, 955 GB_ADDR_CONFIG, 956 NUM_RB_PER_SE); 957 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 958 REG_GET_FIELD( 959 adev->gfx.config.gb_addr_config, 960 GB_ADDR_CONFIG, 961 NUM_SHADER_ENGINES); 962 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 963 REG_GET_FIELD( 964 adev->gfx.config.gb_addr_config, 965 GB_ADDR_CONFIG, 966 PIPE_INTERLEAVE_SIZE)); 967 968 return 0; 969 } 970 971 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 972 int xcc_id, int mec, int pipe, int queue) 973 { 974 unsigned irq_type; 975 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 976 unsigned int hw_prio; 977 uint32_t xcc_doorbell_start; 978 979 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 980 ring_id]; 981 982 /* mec0 is me1 */ 983 ring->xcc_id = xcc_id; 984 ring->me = mec + 1; 985 ring->pipe = pipe; 986 ring->queue = queue; 987 988 ring->ring_obj = NULL; 989 ring->use_doorbell = true; 990 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 991 xcc_id * adev->doorbell_index.xcc_doorbell_range; 992 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 993 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 994 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 995 GFX9_MEC_HPD_SIZE; 996 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 997 sprintf(ring->name, "comp_%d.%d.%d.%d", 998 ring->xcc_id, ring->me, ring->pipe, ring->queue); 999 1000 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1001 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1002 + ring->pipe; 1003 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1004 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1005 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1006 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1007 hw_prio, NULL); 1008 } 1009 1010 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1011 { 1012 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1013 uint32_t *ptr, num_xcc, inst; 1014 1015 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1016 1017 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1018 if (!ptr) { 1019 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1020 adev->gfx.ip_dump_core = NULL; 1021 } else { 1022 adev->gfx.ip_dump_core = ptr; 1023 } 1024 1025 /* Allocate memory for compute queue registers for all the instances */ 1026 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1027 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1028 adev->gfx.mec.num_queue_per_pipe; 1029 1030 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1031 if (!ptr) { 1032 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1033 adev->gfx.ip_dump_compute_queues = NULL; 1034 } else { 1035 adev->gfx.ip_dump_compute_queues = ptr; 1036 } 1037 } 1038 1039 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1040 { 1041 int i, j, k, r, ring_id, xcc_id, num_xcc; 1042 struct amdgpu_device *adev = ip_block->adev; 1043 1044 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1045 case IP_VERSION(9, 4, 3): 1046 case IP_VERSION(9, 4, 4): 1047 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1048 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1049 if (adev->gfx.mec_fw_version >= 153) { 1050 adev->gfx.enable_cleaner_shader = true; 1051 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1052 if (r) { 1053 adev->gfx.enable_cleaner_shader = false; 1054 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1055 } 1056 } 1057 break; 1058 default: 1059 adev->gfx.enable_cleaner_shader = false; 1060 break; 1061 } 1062 1063 adev->gfx.mec.num_mec = 2; 1064 adev->gfx.mec.num_pipe_per_mec = 4; 1065 adev->gfx.mec.num_queue_per_pipe = 8; 1066 1067 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1068 1069 /* EOP Event */ 1070 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1071 if (r) 1072 return r; 1073 1074 /* Bad opcode Event */ 1075 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1076 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1077 &adev->gfx.bad_op_irq); 1078 if (r) 1079 return r; 1080 1081 /* Privileged reg */ 1082 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1083 &adev->gfx.priv_reg_irq); 1084 if (r) 1085 return r; 1086 1087 /* Privileged inst */ 1088 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1089 &adev->gfx.priv_inst_irq); 1090 if (r) 1091 return r; 1092 1093 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1094 1095 r = adev->gfx.rlc.funcs->init(adev); 1096 if (r) { 1097 DRM_ERROR("Failed to init rlc BOs!\n"); 1098 return r; 1099 } 1100 1101 r = gfx_v9_4_3_mec_init(adev); 1102 if (r) { 1103 DRM_ERROR("Failed to init MEC BOs!\n"); 1104 return r; 1105 } 1106 1107 /* set up the compute queues - allocate horizontally across pipes */ 1108 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1109 ring_id = 0; 1110 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1111 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1112 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1113 k++) { 1114 if (!amdgpu_gfx_is_mec_queue_enabled( 1115 adev, xcc_id, i, k, j)) 1116 continue; 1117 1118 r = gfx_v9_4_3_compute_ring_init(adev, 1119 ring_id, 1120 xcc_id, 1121 i, k, j); 1122 if (r) 1123 return r; 1124 1125 ring_id++; 1126 } 1127 } 1128 } 1129 1130 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1131 if (r) { 1132 DRM_ERROR("Failed to init KIQ BOs!\n"); 1133 return r; 1134 } 1135 1136 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1137 if (r) 1138 return r; 1139 1140 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1141 r = amdgpu_gfx_mqd_sw_init(adev, 1142 sizeof(struct v9_mqd_allocation), xcc_id); 1143 if (r) 1144 return r; 1145 } 1146 1147 adev->gfx.compute_supported_reset = 1148 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1149 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1150 case IP_VERSION(9, 4, 3): 1151 case IP_VERSION(9, 4, 4): 1152 if ((adev->gfx.mec_fw_version >= 155) && 1153 !amdgpu_sriov_vf(adev) && 1154 !adev->debug_disable_gpu_ring_reset) { 1155 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1156 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1157 } 1158 break; 1159 case IP_VERSION(9, 5, 0): 1160 if ((adev->gfx.mec_fw_version >= 21) && 1161 !amdgpu_sriov_vf(adev) && 1162 !adev->debug_disable_gpu_ring_reset) { 1163 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1164 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1165 } 1166 break; 1167 default: 1168 break; 1169 } 1170 r = gfx_v9_4_3_gpu_early_init(adev); 1171 if (r) 1172 return r; 1173 1174 r = amdgpu_gfx_ras_sw_init(adev); 1175 if (r) 1176 return r; 1177 1178 r = amdgpu_gfx_sysfs_init(adev); 1179 if (r) 1180 return r; 1181 1182 gfx_v9_4_3_alloc_ip_dump(adev); 1183 1184 return 0; 1185 } 1186 1187 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1188 { 1189 int i, num_xcc; 1190 struct amdgpu_device *adev = ip_block->adev; 1191 1192 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1193 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1194 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1195 1196 for (i = 0; i < num_xcc; i++) { 1197 amdgpu_gfx_mqd_sw_fini(adev, i); 1198 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1199 amdgpu_gfx_kiq_fini(adev, i); 1200 } 1201 1202 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1203 1204 gfx_v9_4_3_mec_fini(adev); 1205 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1206 gfx_v9_4_3_free_microcode(adev); 1207 amdgpu_gfx_sysfs_fini(adev); 1208 1209 kfree(adev->gfx.ip_dump_core); 1210 kfree(adev->gfx.ip_dump_compute_queues); 1211 1212 return 0; 1213 } 1214 1215 #define DEFAULT_SH_MEM_BASES (0x6000) 1216 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1217 int xcc_id) 1218 { 1219 int i; 1220 uint32_t sh_mem_config; 1221 uint32_t sh_mem_bases; 1222 uint32_t data; 1223 1224 /* 1225 * Configure apertures: 1226 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1227 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1228 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1229 */ 1230 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1231 1232 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1233 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1234 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1235 1236 mutex_lock(&adev->srbm_mutex); 1237 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1238 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1239 /* CP and shaders */ 1240 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1241 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1242 1243 /* Enable trap for each kfd vmid. */ 1244 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1245 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1246 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1247 } 1248 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1249 mutex_unlock(&adev->srbm_mutex); 1250 1251 /* 1252 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1253 * access. These should be enabled by FW for target VMIDs. 1254 */ 1255 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1256 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1257 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1258 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1259 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1260 } 1261 } 1262 1263 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1264 { 1265 int vmid; 1266 1267 /* 1268 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1269 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1270 * the driver can enable them for graphics. VMID0 should maintain 1271 * access so that HWS firmware can save/restore entries. 1272 */ 1273 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1274 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1275 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1276 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1277 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1278 } 1279 } 1280 1281 /* For ASICs that needs xnack chain and MEC version supports, set SG_CONFIG1 1282 * DISABLE_XNACK_CHECK_IN_RETRY_DISABLE bit and inform KFD to set xnack_chain 1283 * bit in SET_RESOURCES 1284 */ 1285 static void gfx_v9_4_3_xcc_init_sq(struct amdgpu_device *adev, int xcc_id) 1286 { 1287 uint32_t data; 1288 1289 if (!(adev->gmc.xnack_flags & AMDGPU_GMC_XNACK_FLAG_CHAIN)) 1290 return; 1291 1292 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1); 1293 data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1); 1294 WREG32_SOC15(GC, xcc_id, regSQ_CONFIG1, data); 1295 } 1296 1297 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1298 int xcc_id) 1299 { 1300 u32 tmp; 1301 int i; 1302 1303 /* XXX SH_MEM regs */ 1304 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1305 mutex_lock(&adev->srbm_mutex); 1306 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1307 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1308 /* CP and shaders */ 1309 if (i == 0) { 1310 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1311 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1312 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1313 !!adev->gmc.noretry); 1314 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1315 regSH_MEM_CONFIG, tmp); 1316 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1317 regSH_MEM_BASES, 0); 1318 } else { 1319 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1320 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1321 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1322 !!adev->gmc.noretry); 1323 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1324 regSH_MEM_CONFIG, tmp); 1325 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1326 (adev->gmc.private_aperture_start >> 1327 48)); 1328 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1329 (adev->gmc.shared_aperture_start >> 1330 48)); 1331 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1332 regSH_MEM_BASES, tmp); 1333 } 1334 } 1335 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1336 1337 mutex_unlock(&adev->srbm_mutex); 1338 1339 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1340 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1341 gfx_v9_4_3_xcc_init_sq(adev, xcc_id); 1342 } 1343 1344 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1345 { 1346 int i, num_xcc; 1347 1348 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1349 1350 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1351 adev->gfx.config.db_debug2 = 1352 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1353 1354 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1355 /* ToDo: GC 9.4.4 */ 1356 case IP_VERSION(9, 4, 3): 1357 if (adev->gfx.mec_fw_version >= 184 && 1358 (amdgpu_sriov_reg_access_sq_config(adev) || 1359 !amdgpu_sriov_vf(adev))) 1360 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1361 break; 1362 case IP_VERSION(9, 5, 0): 1363 if (adev->gfx.mec_fw_version >= 23) 1364 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1365 break; 1366 default: 1367 break; 1368 } 1369 1370 for (i = 0; i < num_xcc; i++) 1371 gfx_v9_4_3_xcc_constants_init(adev, i); 1372 } 1373 1374 static void 1375 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1376 int xcc_id) 1377 { 1378 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1379 } 1380 1381 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1382 { 1383 /* 1384 * Rlc save restore list is workable since v2_1. 1385 */ 1386 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1387 } 1388 1389 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1390 { 1391 uint32_t data; 1392 1393 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1394 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1395 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1396 } 1397 1398 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1399 { 1400 uint32_t rlc_setting; 1401 1402 /* if RLC is not enabled, do nothing */ 1403 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1404 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1405 return false; 1406 1407 return true; 1408 } 1409 1410 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1411 { 1412 uint32_t data; 1413 unsigned i; 1414 1415 data = RLC_SAFE_MODE__CMD_MASK; 1416 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1417 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1418 1419 /* wait for RLC_SAFE_MODE */ 1420 for (i = 0; i < adev->usec_timeout; i++) { 1421 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1422 break; 1423 udelay(1); 1424 } 1425 } 1426 1427 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1428 int xcc_id) 1429 { 1430 uint32_t data; 1431 1432 data = RLC_SAFE_MODE__CMD_MASK; 1433 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1434 } 1435 1436 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1437 { 1438 int xcc_id, num_xcc; 1439 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1440 1441 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1442 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1443 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1444 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1445 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1446 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1447 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1448 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1449 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1450 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1451 } 1452 adev->gfx.rlc.rlcg_reg_access_supported = true; 1453 } 1454 1455 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1456 { 1457 /* init spm vmid with 0xf */ 1458 if (adev->gfx.rlc.funcs->update_spm_vmid) 1459 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 1460 1461 return 0; 1462 } 1463 1464 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1465 int xcc_id) 1466 { 1467 u32 i, j, k; 1468 u32 mask; 1469 1470 mutex_lock(&adev->grbm_idx_mutex); 1471 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1472 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1473 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1474 xcc_id); 1475 for (k = 0; k < adev->usec_timeout; k++) { 1476 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1477 break; 1478 udelay(1); 1479 } 1480 if (k == adev->usec_timeout) { 1481 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1482 0xffffffff, 1483 0xffffffff, xcc_id); 1484 mutex_unlock(&adev->grbm_idx_mutex); 1485 drm_info(adev_to_drm(adev), "Timeout wait for RLC serdes %u,%u\n", 1486 i, j); 1487 return; 1488 } 1489 } 1490 } 1491 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1492 xcc_id); 1493 mutex_unlock(&adev->grbm_idx_mutex); 1494 1495 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1496 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1497 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1498 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1499 for (k = 0; k < adev->usec_timeout; k++) { 1500 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1501 break; 1502 udelay(1); 1503 } 1504 } 1505 1506 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1507 bool enable, int xcc_id) 1508 { 1509 u32 tmp; 1510 1511 /* These interrupts should be enabled to drive DS clock */ 1512 1513 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1514 1515 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1516 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1517 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1518 1519 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1520 } 1521 1522 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1523 { 1524 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1525 RLC_ENABLE_F32, 0); 1526 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1527 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1528 } 1529 1530 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1531 { 1532 int i, num_xcc; 1533 1534 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1535 for (i = 0; i < num_xcc; i++) 1536 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1537 } 1538 1539 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1540 { 1541 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1542 SOFT_RESET_RLC, 1); 1543 udelay(50); 1544 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1545 SOFT_RESET_RLC, 0); 1546 udelay(50); 1547 } 1548 1549 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1550 { 1551 int i, num_xcc; 1552 1553 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1554 for (i = 0; i < num_xcc; i++) 1555 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1556 } 1557 1558 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1559 { 1560 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1561 RLC_ENABLE_F32, 1); 1562 udelay(50); 1563 1564 /* carrizo do enable cp interrupt after cp inited */ 1565 if (!(adev->flags & AMD_IS_APU)) { 1566 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1567 udelay(50); 1568 } 1569 } 1570 1571 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1572 { 1573 #ifdef AMDGPU_RLC_DEBUG_RETRY 1574 u32 rlc_ucode_ver; 1575 #endif 1576 int i, num_xcc; 1577 1578 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1579 for (i = 0; i < num_xcc; i++) { 1580 gfx_v9_4_3_xcc_rlc_start(adev, i); 1581 #ifdef AMDGPU_RLC_DEBUG_RETRY 1582 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1583 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1584 if (rlc_ucode_ver == 0x108) { 1585 dev_info(adev->dev, 1586 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i\n", 1587 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1588 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1589 * default is 0x9C4 to create a 100us interval */ 1590 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1591 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1592 * to disable the page fault retry interrupts, default is 1593 * 0x100 (256) */ 1594 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1595 } 1596 #endif 1597 } 1598 } 1599 1600 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1601 int xcc_id) 1602 { 1603 const struct rlc_firmware_header_v2_0 *hdr; 1604 const __le32 *fw_data; 1605 unsigned i, fw_size; 1606 1607 if (!adev->gfx.rlc_fw) 1608 return -EINVAL; 1609 1610 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1611 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1612 1613 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1614 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1615 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1616 1617 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1618 RLCG_UCODE_LOADING_START_ADDRESS); 1619 for (i = 0; i < fw_size; i++) { 1620 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1621 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1622 msleep(1); 1623 } 1624 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1625 } 1626 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1627 1628 return 0; 1629 } 1630 1631 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1632 { 1633 int r; 1634 1635 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1636 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1637 /* legacy rlc firmware loading */ 1638 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1639 if (r) 1640 return r; 1641 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1642 } 1643 1644 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1645 /* disable CG */ 1646 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1647 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1648 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1649 1650 return 0; 1651 } 1652 1653 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1654 { 1655 int r, i, num_xcc; 1656 1657 if (amdgpu_sriov_vf(adev)) 1658 return 0; 1659 1660 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1661 for (i = 0; i < num_xcc; i++) { 1662 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1663 if (r) 1664 return r; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1671 int inst, struct amdgpu_ring *ring, unsigned int vmid) 1672 { 1673 u32 reg, pre_data, data; 1674 1675 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL); 1676 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1677 pre_data = RREG32_NO_KIQ(reg); 1678 else 1679 pre_data = RREG32(reg); 1680 1681 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1682 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1683 1684 if (pre_data != data) { 1685 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1686 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1687 } else 1688 WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1689 } 1690 } 1691 1692 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1693 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1694 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1695 }; 1696 1697 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1698 uint32_t offset, 1699 struct soc15_reg_rlcg *entries, int arr_size) 1700 { 1701 int i, inst; 1702 uint32_t reg; 1703 1704 if (!entries) 1705 return false; 1706 1707 for (i = 0; i < arr_size; i++) { 1708 const struct soc15_reg_rlcg *entry; 1709 1710 entry = &entries[i]; 1711 inst = adev->ip_map.logical_to_dev_inst ? 1712 adev->ip_map.logical_to_dev_inst( 1713 adev, entry->hwip, entry->instance) : 1714 entry->instance; 1715 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1716 entry->reg; 1717 if (offset == reg) 1718 return true; 1719 } 1720 1721 return false; 1722 } 1723 1724 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1725 { 1726 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1727 (void *)rlcg_access_gc_9_4_3, 1728 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1729 } 1730 1731 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1732 bool enable, int xcc_id) 1733 { 1734 if (enable) { 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1736 } else { 1737 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1738 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1739 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1740 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1741 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1742 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1743 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1744 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1745 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1746 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1747 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1748 } 1749 udelay(50); 1750 } 1751 1752 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1753 int xcc_id) 1754 { 1755 const struct gfx_firmware_header_v1_0 *mec_hdr; 1756 const __le32 *fw_data; 1757 unsigned i; 1758 u32 tmp; 1759 u32 mec_ucode_addr_offset; 1760 u32 mec_ucode_data_offset; 1761 1762 if (!adev->gfx.mec_fw) 1763 return -EINVAL; 1764 1765 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1766 1767 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1768 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1769 1770 fw_data = (const __le32 *) 1771 (adev->gfx.mec_fw->data + 1772 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1773 tmp = 0; 1774 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1775 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1776 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1777 1778 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1779 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1780 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1781 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1782 1783 mec_ucode_addr_offset = 1784 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1785 mec_ucode_data_offset = 1786 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1787 1788 /* MEC1 */ 1789 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1790 for (i = 0; i < mec_hdr->jt_size; i++) 1791 WREG32(mec_ucode_data_offset, 1792 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1793 1794 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1795 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1796 1797 return 0; 1798 } 1799 1800 /* KIQ functions */ 1801 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1802 { 1803 uint32_t tmp; 1804 struct amdgpu_device *adev = ring->adev; 1805 1806 /* tell RLC which is KIQ queue */ 1807 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1808 tmp &= 0xffffff00; 1809 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1810 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1811 } 1812 1813 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1814 { 1815 struct amdgpu_device *adev = ring->adev; 1816 1817 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1818 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1819 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1820 mqd->cp_hqd_queue_priority = 1821 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1822 } 1823 } 1824 } 1825 1826 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1827 { 1828 struct amdgpu_device *adev = ring->adev; 1829 struct v9_mqd *mqd = ring->mqd_ptr; 1830 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1831 uint32_t tmp; 1832 1833 mqd->header = 0xC0310800; 1834 mqd->compute_pipelinestat_enable = 0x00000001; 1835 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1836 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1837 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1838 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1839 mqd->compute_misc_reserved = 0x00000003; 1840 1841 mqd->dynamic_cu_mask_addr_lo = 1842 lower_32_bits(ring->mqd_gpu_addr 1843 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1844 mqd->dynamic_cu_mask_addr_hi = 1845 upper_32_bits(ring->mqd_gpu_addr 1846 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1847 1848 eop_base_addr = ring->eop_gpu_addr >> 8; 1849 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1850 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1851 1852 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1853 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1854 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1855 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1856 1857 mqd->cp_hqd_eop_control = tmp; 1858 1859 /* enable doorbell? */ 1860 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1861 1862 if (ring->use_doorbell) { 1863 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1864 DOORBELL_OFFSET, ring->doorbell_index); 1865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1866 DOORBELL_EN, 1); 1867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1868 DOORBELL_SOURCE, 0); 1869 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1870 DOORBELL_HIT, 0); 1871 if (amdgpu_sriov_multi_vf_mode(adev)) 1872 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1873 DOORBELL_MODE, 1); 1874 } else { 1875 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1876 DOORBELL_EN, 0); 1877 } 1878 1879 mqd->cp_hqd_pq_doorbell_control = tmp; 1880 1881 /* disable the queue if it's active */ 1882 ring->wptr = 0; 1883 mqd->cp_hqd_dequeue_request = 0; 1884 mqd->cp_hqd_pq_rptr = 0; 1885 mqd->cp_hqd_pq_wptr_lo = 0; 1886 mqd->cp_hqd_pq_wptr_hi = 0; 1887 1888 /* set the pointer to the MQD */ 1889 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1890 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1891 1892 /* set MQD vmid to 0 */ 1893 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1894 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1895 mqd->cp_mqd_control = tmp; 1896 1897 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1898 hqd_gpu_addr = ring->gpu_addr >> 8; 1899 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1900 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1901 1902 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1903 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1904 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1905 (order_base_2(ring->ring_size / 4) - 1)); 1906 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1907 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1908 #ifdef __BIG_ENDIAN 1909 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1910 #endif 1911 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1912 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1913 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1914 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1915 mqd->cp_hqd_pq_control = tmp; 1916 1917 /* set the wb address whether it's enabled or not */ 1918 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1919 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1920 mqd->cp_hqd_pq_rptr_report_addr_hi = 1921 upper_32_bits(wb_gpu_addr) & 0xffff; 1922 1923 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1924 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1925 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1926 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1927 1928 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1929 ring->wptr = 0; 1930 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1931 1932 /* set the vmid for the queue */ 1933 mqd->cp_hqd_vmid = 0; 1934 1935 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1936 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1937 mqd->cp_hqd_persistent_state = tmp; 1938 1939 /* set MIN_IB_AVAIL_SIZE */ 1940 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1941 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1942 mqd->cp_hqd_ib_control = tmp; 1943 1944 /* set static priority for a queue/ring */ 1945 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1946 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1947 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); 1948 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 1949 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 1950 mqd->cp_hqd_quantum = tmp; 1951 1952 /* map_queues packet doesn't need activate the queue, 1953 * so only kiq need set this field. 1954 */ 1955 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1956 mqd->cp_hqd_active = 1; 1957 1958 return 0; 1959 } 1960 1961 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1962 int xcc_id) 1963 { 1964 struct amdgpu_device *adev = ring->adev; 1965 struct v9_mqd *mqd = ring->mqd_ptr; 1966 int j; 1967 1968 /* disable wptr polling */ 1969 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1970 1971 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1972 mqd->cp_hqd_eop_base_addr_lo); 1973 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1974 mqd->cp_hqd_eop_base_addr_hi); 1975 1976 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1977 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1978 mqd->cp_hqd_eop_control); 1979 1980 /* enable doorbell? */ 1981 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1982 mqd->cp_hqd_pq_doorbell_control); 1983 1984 /* disable the queue if it's active */ 1985 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1986 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1987 for (j = 0; j < adev->usec_timeout; j++) { 1988 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1989 break; 1990 udelay(1); 1991 } 1992 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1993 mqd->cp_hqd_dequeue_request); 1994 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1995 mqd->cp_hqd_pq_rptr); 1996 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1997 mqd->cp_hqd_pq_wptr_lo); 1998 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1999 mqd->cp_hqd_pq_wptr_hi); 2000 } 2001 2002 /* set the pointer to the MQD */ 2003 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 2004 mqd->cp_mqd_base_addr_lo); 2005 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 2006 mqd->cp_mqd_base_addr_hi); 2007 2008 /* set MQD vmid to 0 */ 2009 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 2010 mqd->cp_mqd_control); 2011 2012 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2013 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 2014 mqd->cp_hqd_pq_base_lo); 2015 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 2016 mqd->cp_hqd_pq_base_hi); 2017 2018 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2019 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 2020 mqd->cp_hqd_pq_control); 2021 2022 /* set the wb address whether it's enabled or not */ 2023 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2024 mqd->cp_hqd_pq_rptr_report_addr_lo); 2025 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2026 mqd->cp_hqd_pq_rptr_report_addr_hi); 2027 2028 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2029 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2030 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2031 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2032 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2033 2034 /* enable the doorbell if requested */ 2035 if (ring->use_doorbell) { 2036 WREG32_SOC15( 2037 GC, GET_INST(GC, xcc_id), 2038 regCP_MEC_DOORBELL_RANGE_LOWER, 2039 ((adev->doorbell_index.kiq + 2040 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2041 2) << 2); 2042 WREG32_SOC15( 2043 GC, GET_INST(GC, xcc_id), 2044 regCP_MEC_DOORBELL_RANGE_UPPER, 2045 ((adev->doorbell_index.userqueue_end + 2046 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2047 2) << 2); 2048 } 2049 2050 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2051 mqd->cp_hqd_pq_doorbell_control); 2052 2053 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2054 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2055 mqd->cp_hqd_pq_wptr_lo); 2056 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2057 mqd->cp_hqd_pq_wptr_hi); 2058 2059 /* set the vmid for the queue */ 2060 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2061 2062 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2063 mqd->cp_hqd_persistent_state); 2064 2065 /* activate the queue */ 2066 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2067 mqd->cp_hqd_active); 2068 2069 if (ring->use_doorbell) 2070 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2071 2072 return 0; 2073 } 2074 2075 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2076 int xcc_id) 2077 { 2078 struct amdgpu_device *adev = ring->adev; 2079 int j; 2080 2081 /* disable the queue if it's active */ 2082 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2083 2084 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2085 2086 for (j = 0; j < adev->usec_timeout; j++) { 2087 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2088 break; 2089 udelay(1); 2090 } 2091 2092 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2093 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2094 2095 /* Manual disable if dequeue request times out */ 2096 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2097 } 2098 2099 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2100 0); 2101 } 2102 2103 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2104 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2105 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2106 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2107 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2108 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2109 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2110 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2111 2112 return 0; 2113 } 2114 2115 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2116 { 2117 struct amdgpu_device *adev = ring->adev; 2118 struct v9_mqd *mqd = ring->mqd_ptr; 2119 struct v9_mqd *tmp_mqd; 2120 2121 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2122 2123 /* GPU could be in bad state during probe, driver trigger the reset 2124 * after load the SMU, in this case , the mqd is not be initialized. 2125 * driver need to re-init the mqd. 2126 * check mqd->cp_hqd_pq_control since this value should not be 0 2127 */ 2128 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2129 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2130 /* for GPU_RESET case , reset MQD to a clean status */ 2131 if (adev->gfx.kiq[xcc_id].mqd_backup) 2132 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2133 2134 /* reset ring buffer */ 2135 ring->wptr = 0; 2136 amdgpu_ring_clear_ring(ring); 2137 mutex_lock(&adev->srbm_mutex); 2138 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2139 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2140 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2141 mutex_unlock(&adev->srbm_mutex); 2142 } else { 2143 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2144 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2145 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2146 mutex_lock(&adev->srbm_mutex); 2147 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2148 amdgpu_ring_clear_ring(ring); 2149 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2150 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2151 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2152 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2153 mutex_unlock(&adev->srbm_mutex); 2154 2155 if (adev->gfx.kiq[xcc_id].mqd_backup) 2156 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2157 } 2158 2159 return 0; 2160 } 2161 2162 static void gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, 2163 bool restore) 2164 { 2165 struct amdgpu_device *adev = ring->adev; 2166 struct v9_mqd *mqd = ring->mqd_ptr; 2167 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2168 struct v9_mqd *tmp_mqd; 2169 2170 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2171 * is not be initialized before 2172 */ 2173 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2174 2175 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2176 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2177 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2178 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2179 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2180 mutex_lock(&adev->srbm_mutex); 2181 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2182 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2183 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2184 mutex_unlock(&adev->srbm_mutex); 2185 2186 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2187 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2188 } else { 2189 /* restore MQD to a clean status */ 2190 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2191 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2192 /* reset ring buffer */ 2193 ring->wptr = 0; 2194 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2195 amdgpu_ring_clear_ring(ring); 2196 } 2197 } 2198 2199 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2200 { 2201 struct amdgpu_ring *ring; 2202 int j; 2203 2204 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2205 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2206 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2207 mutex_lock(&adev->srbm_mutex); 2208 soc15_grbm_select(adev, ring->me, 2209 ring->pipe, 2210 ring->queue, 0, GET_INST(GC, xcc_id)); 2211 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2212 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2213 mutex_unlock(&adev->srbm_mutex); 2214 } 2215 } 2216 2217 return 0; 2218 } 2219 2220 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2221 { 2222 gfx_v9_4_3_xcc_kiq_init_queue(&adev->gfx.kiq[xcc_id].ring, xcc_id); 2223 return 0; 2224 } 2225 2226 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2227 { 2228 struct amdgpu_ring *ring; 2229 int i; 2230 2231 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2232 2233 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2234 ring = &adev->gfx.compute_ring[i + xcc_id * 2235 adev->gfx.num_compute_rings]; 2236 2237 gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2238 } 2239 2240 return amdgpu_gfx_enable_kcq(adev, xcc_id); 2241 } 2242 2243 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2244 { 2245 struct amdgpu_ring *ring; 2246 int r, j; 2247 2248 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2249 2250 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2251 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2252 2253 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2254 if (r) 2255 return r; 2256 } else { 2257 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2258 } 2259 2260 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2261 if (r) 2262 return r; 2263 2264 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2265 if (r) 2266 return r; 2267 2268 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2269 ring = &adev->gfx.compute_ring 2270 [j + xcc_id * adev->gfx.num_compute_rings]; 2271 r = amdgpu_ring_test_helper(ring); 2272 if (r) 2273 return r; 2274 } 2275 2276 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2277 2278 return 0; 2279 } 2280 2281 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2282 { 2283 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2284 2285 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2286 if (amdgpu_sriov_vf(adev)) { 2287 enum amdgpu_gfx_partition mode; 2288 2289 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2290 AMDGPU_XCP_FL_NONE); 2291 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2292 return -EINVAL; 2293 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2294 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2295 num_xcp = num_xcc / num_xcc_per_xcp; 2296 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2297 2298 } else { 2299 if (adev->in_suspend) 2300 amdgpu_xcp_restore_partition_mode(adev->xcp_mgr); 2301 else if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2302 AMDGPU_XCP_FL_NONE) == 2303 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2304 r = amdgpu_xcp_switch_partition_mode( 2305 adev->xcp_mgr, amdgpu_user_partt_mode); 2306 } 2307 if (r) 2308 return r; 2309 2310 for (i = 0; i < num_xcc; i++) { 2311 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2312 if (r) 2313 return r; 2314 } 2315 2316 return 0; 2317 } 2318 2319 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2320 { 2321 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2322 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2323 2324 if (amdgpu_sriov_vf(adev)) { 2325 /* must disable polling for SRIOV when hw finished, otherwise 2326 * CPC engine may still keep fetching WB address which is already 2327 * invalid after sw finished and trigger DMAR reading error in 2328 * hypervisor side. 2329 */ 2330 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2331 return; 2332 } 2333 2334 /* Use deinitialize sequence from CAIL when unbinding device 2335 * from driver, otherwise KIQ is hanging when binding back 2336 */ 2337 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2338 mutex_lock(&adev->srbm_mutex); 2339 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2340 adev->gfx.kiq[xcc_id].ring.pipe, 2341 adev->gfx.kiq[xcc_id].ring.queue, 0, 2342 GET_INST(GC, xcc_id)); 2343 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2344 xcc_id); 2345 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2346 mutex_unlock(&adev->srbm_mutex); 2347 } 2348 2349 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2350 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2351 } 2352 2353 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2354 { 2355 int r; 2356 struct amdgpu_device *adev = ip_block->adev; 2357 2358 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2359 adev->gfx.cleaner_shader_ptr); 2360 2361 if (!amdgpu_sriov_vf(adev)) 2362 gfx_v9_4_3_init_golden_registers(adev); 2363 2364 gfx_v9_4_3_constants_init(adev); 2365 2366 r = adev->gfx.rlc.funcs->resume(adev); 2367 if (r) 2368 return r; 2369 2370 r = gfx_v9_4_3_cp_resume(adev); 2371 if (r) 2372 return r; 2373 2374 return r; 2375 } 2376 2377 static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool enable) 2378 { 2379 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2380 uint32_t ptl_state = enable ? 1 : 0; 2381 uint32_t fmt1, fmt2; 2382 int r; 2383 2384 if (!adev->psp.funcs) 2385 return -EOPNOTSUPP; 2386 2387 if (!ptl->hw_supported) { 2388 fmt1 = GFX_FTYPE_VECTOR; 2389 fmt2 = GFX_FTYPE_F8; 2390 } else { 2391 fmt1 = ptl->fmt1; 2392 fmt2 = ptl->fmt2; 2393 } 2394 2395 /* initialize PTL with default formats: GFX_FTYPE_VECTOR & GFX_FTYPE_F8 */ 2396 r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, 2397 &fmt1, &fmt2); 2398 if (r) 2399 return r; 2400 2401 ptl->hw_supported = true; 2402 2403 atomic_set(&ptl->disable_ref, 0); 2404 if (!enable && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2405 dev_dbg(adev->dev, 2406 "PTL disabled (amdgpu.ptl=%d)\ 2407 To enable, set amdgpu.ptl=1 via module param or kernel cmdline\n", 2408 amdgpu_ptl); 2409 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 2410 } 2411 2412 return 0; 2413 } 2414 2415 static int gfx_v9_4_3_ptl_hw_init(struct amdgpu_device *adev) 2416 { 2417 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2418 bool enable; 2419 2420 switch (amdgpu_ptl) { 2421 case 1: 2422 enable = true; 2423 break; 2424 case 2: 2425 /* Permanently disabled - cannot be re-enabled */ 2426 enable = false; 2427 ptl->permanently_disabled = true; 2428 break; 2429 case -1: 2430 case 0: 2431 default: 2432 enable = false; 2433 break; 2434 } 2435 2436 gfx_v9_4_3_perf_monitor_ptl_init(adev, enable ? 1 : 0); 2437 2438 return 0; 2439 } 2440 2441 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2442 { 2443 struct amdgpu_device *adev = ip_block->adev; 2444 int i, num_xcc; 2445 2446 if (adev->psp.ptl.hw_supported && !amdgpu_in_reset(adev)) 2447 gfx_v9_4_3_perf_monitor_ptl_init(adev, false); 2448 2449 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2450 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2451 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2452 2453 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2454 for (i = 0; i < num_xcc; i++) { 2455 gfx_v9_4_3_xcc_fini(adev, i); 2456 } 2457 2458 return 0; 2459 } 2460 2461 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2462 { 2463 return gfx_v9_4_3_hw_fini(ip_block); 2464 } 2465 2466 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2467 { 2468 return gfx_v9_4_3_hw_init(ip_block); 2469 } 2470 2471 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2472 { 2473 struct amdgpu_device *adev = ip_block->adev; 2474 int i, num_xcc; 2475 u32 gc_ip_version; 2476 2477 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2478 gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 2479 2480 for (i = 0; i < num_xcc; i++) { 2481 if (gc_ip_version == IP_VERSION(9, 4, 4)) { 2482 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2483 GRBM_STATUS, SPI_BUSY)) 2484 return false; 2485 } else { 2486 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2487 GRBM_STATUS, GUI_ACTIVE)) 2488 return false; 2489 } 2490 } 2491 return true; 2492 } 2493 2494 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2495 { 2496 unsigned i; 2497 struct amdgpu_device *adev = ip_block->adev; 2498 2499 for (i = 0; i < adev->usec_timeout; i++) { 2500 if (gfx_v9_4_3_is_idle(ip_block)) 2501 return 0; 2502 udelay(1); 2503 } 2504 return -ETIMEDOUT; 2505 } 2506 2507 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2508 { 2509 u32 grbm_soft_reset = 0; 2510 u32 tmp; 2511 struct amdgpu_device *adev = ip_block->adev; 2512 2513 /* GRBM_STATUS */ 2514 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2515 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2516 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2517 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2518 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2519 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2520 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2521 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2522 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2523 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2524 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2525 } 2526 2527 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2528 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2529 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2530 } 2531 2532 /* GRBM_STATUS2 */ 2533 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2534 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2535 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2536 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2537 2538 2539 if (grbm_soft_reset) { 2540 /* stop the rlc */ 2541 adev->gfx.rlc.funcs->stop(adev); 2542 2543 /* Disable MEC parsing/prefetching */ 2544 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2545 2546 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2547 tmp |= grbm_soft_reset; 2548 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2549 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2550 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2551 2552 udelay(50); 2553 2554 tmp &= ~grbm_soft_reset; 2555 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2556 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2557 2558 /* Wait a little for things to settle down */ 2559 udelay(50); 2560 } 2561 return 0; 2562 } 2563 2564 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2565 uint32_t vmid, 2566 uint32_t gds_base, uint32_t gds_size, 2567 uint32_t gws_base, uint32_t gws_size, 2568 uint32_t oa_base, uint32_t oa_size) 2569 { 2570 struct amdgpu_device *adev = ring->adev; 2571 2572 /* GDS Base */ 2573 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2574 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2575 gds_base); 2576 2577 /* GDS Size */ 2578 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2579 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2580 gds_size); 2581 2582 /* GWS */ 2583 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2584 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2585 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2586 2587 /* OA */ 2588 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2589 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2590 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2591 } 2592 2593 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2594 { 2595 struct amdgpu_device *adev = ip_block->adev; 2596 2597 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2598 AMDGPU_MAX_COMPUTE_RINGS); 2599 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2600 gfx_v9_4_3_set_ring_funcs(adev); 2601 gfx_v9_4_3_set_irq_funcs(adev); 2602 gfx_v9_4_3_set_gds_init(adev); 2603 gfx_v9_4_3_set_rlc_funcs(adev); 2604 2605 /* init rlcg reg access ctrl */ 2606 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2607 2608 return gfx_v9_4_3_init_microcode(adev); 2609 } 2610 2611 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2612 { 2613 struct amdgpu_device *adev = ip_block->adev; 2614 int r; 2615 2616 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2617 if (r) 2618 return r; 2619 2620 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2621 if (r) 2622 return r; 2623 2624 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2625 if (r) 2626 return r; 2627 2628 if (adev->gfx.ras && 2629 adev->gfx.ras->enable_watchdog_timer) 2630 adev->gfx.ras->enable_watchdog_timer(adev); 2631 2632 gfx_v9_4_3_ptl_hw_init(adev); 2633 2634 return 0; 2635 } 2636 2637 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2638 bool enable, int xcc_id) 2639 { 2640 uint32_t def, data; 2641 2642 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2643 return; 2644 2645 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2646 regRLC_CGTT_MGCG_OVERRIDE); 2647 2648 if (enable) 2649 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2650 else 2651 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2652 2653 if (def != data) 2654 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2655 regRLC_CGTT_MGCG_OVERRIDE, data); 2656 2657 } 2658 2659 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2660 bool enable, int xcc_id) 2661 { 2662 uint32_t def, data; 2663 2664 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2665 return; 2666 2667 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2668 regRLC_CGTT_MGCG_OVERRIDE); 2669 2670 if (enable) 2671 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2672 else 2673 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2674 2675 if (def != data) 2676 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2677 regRLC_CGTT_MGCG_OVERRIDE, data); 2678 } 2679 2680 static void 2681 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2682 bool enable, int xcc_id) 2683 { 2684 uint32_t data, def; 2685 2686 /* It is disabled by HW by default */ 2687 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2688 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2689 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2690 2691 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2692 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2693 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2694 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2695 2696 if (def != data) 2697 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2698 2699 /* MGLS is a global flag to control all MGLS in GFX */ 2700 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2701 /* 2 - RLC memory Light sleep */ 2702 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2703 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2704 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2705 if (def != data) 2706 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2707 } 2708 /* 3 - CP memory Light sleep */ 2709 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2710 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2711 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2712 if (def != data) 2713 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2714 } 2715 } 2716 } else { 2717 /* 1 - MGCG_OVERRIDE */ 2718 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2719 2720 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2721 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2722 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2723 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2724 2725 if (def != data) 2726 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2727 2728 /* 2 - disable MGLS in RLC */ 2729 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2730 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2731 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2732 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2733 } 2734 2735 /* 3 - disable MGLS in CP */ 2736 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2737 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2738 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2739 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2740 } 2741 } 2742 2743 } 2744 2745 static void 2746 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2747 bool enable, int xcc_id) 2748 { 2749 uint32_t def, data; 2750 2751 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2752 2753 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2754 /* unset CGCG override */ 2755 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2756 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2757 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2758 else 2759 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2760 /* update CGCG and CGLS override bits */ 2761 if (def != data) 2762 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2763 2764 /* CGCG Hysteresis: 400us */ 2765 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2766 2767 data = (0x2710 2768 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2769 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2770 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2771 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2772 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2773 if (def != data) 2774 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2775 2776 /* set IDLE_POLL_COUNT(0x33450100)*/ 2777 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2778 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2779 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2780 if (def != data) 2781 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2782 } else { 2783 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2784 /* reset CGCG/CGLS bits */ 2785 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2786 /* disable cgcg and cgls in FSM */ 2787 if (def != data) 2788 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2789 } 2790 2791 } 2792 2793 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2794 bool enable, int xcc_id) 2795 { 2796 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2797 2798 if (enable) { 2799 /* FGCG */ 2800 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2801 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2802 2803 /* CGCG/CGLS should be enabled after MGCG/MGLS 2804 * === MGCG + MGLS === 2805 */ 2806 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2807 xcc_id); 2808 /* === CGCG + CGLS === */ 2809 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2810 xcc_id); 2811 } else { 2812 /* CGCG/CGLS should be disabled before MGCG/MGLS 2813 * === CGCG + CGLS === 2814 */ 2815 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2816 xcc_id); 2817 /* === MGCG + MGLS === */ 2818 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2819 xcc_id); 2820 2821 /* FGCG */ 2822 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2823 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2824 } 2825 2826 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2827 2828 return 0; 2829 } 2830 2831 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2832 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2833 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2834 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2835 .init = gfx_v9_4_3_rlc_init, 2836 .resume = gfx_v9_4_3_rlc_resume, 2837 .stop = gfx_v9_4_3_rlc_stop, 2838 .reset = gfx_v9_4_3_rlc_reset, 2839 .start = gfx_v9_4_3_rlc_start, 2840 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2841 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2842 }; 2843 2844 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2845 enum amd_powergating_state state) 2846 { 2847 return 0; 2848 } 2849 2850 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2851 enum amd_clockgating_state state) 2852 { 2853 struct amdgpu_device *adev = ip_block->adev; 2854 int i, num_xcc; 2855 2856 if (amdgpu_sriov_vf(adev)) 2857 return 0; 2858 2859 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2860 for (i = 0; i < num_xcc; i++) 2861 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2862 adev, state == AMD_CG_STATE_GATE, i); 2863 2864 return 0; 2865 } 2866 2867 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2868 { 2869 struct amdgpu_device *adev = ip_block->adev; 2870 int data; 2871 2872 if (amdgpu_sriov_vf(adev)) 2873 *flags = 0; 2874 2875 /* AMD_CG_SUPPORT_GFX_MGCG */ 2876 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2877 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2878 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2879 2880 /* AMD_CG_SUPPORT_GFX_CGCG */ 2881 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2882 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2883 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2884 2885 /* AMD_CG_SUPPORT_GFX_CGLS */ 2886 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2887 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2888 2889 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2890 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2891 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2892 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2893 2894 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2895 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2896 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2897 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2898 } 2899 2900 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2901 { 2902 struct amdgpu_device *adev = ring->adev; 2903 u32 ref_and_mask, reg_mem_engine; 2904 2905 if (!adev->gfx.funcs->get_hdp_flush_mask) { 2906 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 2907 return; 2908 } 2909 2910 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 2911 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2912 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2913 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2914 ref_and_mask, ref_and_mask, 0x20); 2915 } 2916 2917 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2918 struct amdgpu_job *job, 2919 struct amdgpu_ib *ib, 2920 uint32_t flags) 2921 { 2922 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2923 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2924 2925 /* Currently, there is a high possibility to get wave ID mismatch 2926 * between ME and GDS, leading to a hw deadlock, because ME generates 2927 * different wave IDs than the GDS expects. This situation happens 2928 * randomly when at least 5 compute pipes use GDS ordered append. 2929 * The wave IDs generated by ME are also wrong after suspend/resume. 2930 * Those are probably bugs somewhere else in the kernel driver. 2931 * 2932 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2933 * GDS to 0 for this ring (me/pipe). 2934 */ 2935 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2936 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2937 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2938 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2939 } 2940 2941 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2942 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2943 amdgpu_ring_write(ring, 2944 #ifdef __BIG_ENDIAN 2945 (2 << 0) | 2946 #endif 2947 lower_32_bits(ib->gpu_addr)); 2948 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2949 amdgpu_ring_write(ring, control); 2950 } 2951 2952 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2953 u64 seq, unsigned flags) 2954 { 2955 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2956 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2957 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2958 2959 /* RELEASE_MEM - flush caches, send int */ 2960 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2961 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2962 EOP_TC_NC_ACTION_EN) : 2963 (EOP_TCL1_ACTION_EN | 2964 EOP_TC_ACTION_EN | 2965 EOP_TC_WB_ACTION_EN | 2966 EOP_TC_MD_ACTION_EN)) | 2967 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2968 EVENT_INDEX(5))); 2969 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2970 2971 /* 2972 * the address should be Qword aligned if 64bit write, Dword 2973 * aligned if only send 32bit data low (discard data high) 2974 */ 2975 if (write64bit) 2976 BUG_ON(addr & 0x7); 2977 else 2978 BUG_ON(addr & 0x3); 2979 amdgpu_ring_write(ring, lower_32_bits(addr)); 2980 amdgpu_ring_write(ring, upper_32_bits(addr)); 2981 amdgpu_ring_write(ring, lower_32_bits(seq)); 2982 amdgpu_ring_write(ring, upper_32_bits(seq)); 2983 amdgpu_ring_write(ring, 0); 2984 } 2985 2986 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2987 { 2988 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2989 uint32_t seq = ring->fence_drv.sync_seq; 2990 uint64_t addr = ring->fence_drv.gpu_addr; 2991 2992 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2993 lower_32_bits(addr), upper_32_bits(addr), 2994 seq, 0xffffffff, 4); 2995 } 2996 2997 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2998 unsigned vmid, uint64_t pd_addr) 2999 { 3000 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3001 } 3002 3003 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 3004 { 3005 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 3006 } 3007 3008 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 3009 { 3010 u64 wptr; 3011 3012 /* XXX check if swapping is necessary on BE */ 3013 if (ring->use_doorbell) 3014 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 3015 else 3016 BUG(); 3017 return wptr; 3018 } 3019 3020 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 3021 { 3022 struct amdgpu_device *adev = ring->adev; 3023 3024 /* XXX check if swapping is necessary on BE */ 3025 if (ring->use_doorbell) { 3026 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3027 WDOORBELL64(ring->doorbell_index, ring->wptr); 3028 } else { 3029 BUG(); /* only DOORBELL method supported on gfx9 now */ 3030 } 3031 } 3032 3033 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3034 u64 seq, unsigned int flags) 3035 { 3036 struct amdgpu_device *adev = ring->adev; 3037 3038 /* we only allocate 32bit for each seq wb address */ 3039 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 3040 3041 /* write fence seq to the "addr" */ 3042 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3043 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3044 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 3045 amdgpu_ring_write(ring, lower_32_bits(addr)); 3046 amdgpu_ring_write(ring, upper_32_bits(addr)); 3047 amdgpu_ring_write(ring, lower_32_bits(seq)); 3048 3049 if (flags & AMDGPU_FENCE_FLAG_INT) { 3050 /* set register to trigger INT */ 3051 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3052 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3053 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 3054 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 3055 amdgpu_ring_write(ring, 0); 3056 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3057 } 3058 } 3059 3060 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3061 uint32_t reg_val_offs) 3062 { 3063 struct amdgpu_device *adev = ring->adev; 3064 3065 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3066 3067 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3068 amdgpu_ring_write(ring, 0 | /* src: register*/ 3069 (5 << 8) | /* dst: memory */ 3070 (1 << 20)); /* write confirm */ 3071 amdgpu_ring_write(ring, reg); 3072 amdgpu_ring_write(ring, 0); 3073 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3074 reg_val_offs * 4)); 3075 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3076 reg_val_offs * 4)); 3077 } 3078 3079 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3080 uint32_t val) 3081 { 3082 uint32_t cmd = 0; 3083 3084 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3085 3086 switch (ring->funcs->type) { 3087 case AMDGPU_RING_TYPE_GFX: 3088 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3089 break; 3090 case AMDGPU_RING_TYPE_KIQ: 3091 cmd = (1 << 16); /* no inc addr */ 3092 break; 3093 default: 3094 cmd = WR_CONFIRM; 3095 break; 3096 } 3097 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3098 amdgpu_ring_write(ring, cmd); 3099 amdgpu_ring_write(ring, reg); 3100 amdgpu_ring_write(ring, 0); 3101 amdgpu_ring_write(ring, val); 3102 } 3103 3104 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3105 uint32_t val, uint32_t mask) 3106 { 3107 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3108 } 3109 3110 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3111 uint32_t reg0, uint32_t reg1, 3112 uint32_t ref, uint32_t mask) 3113 { 3114 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3115 ref, mask); 3116 } 3117 3118 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3119 unsigned vmid) 3120 { 3121 struct amdgpu_device *adev = ring->adev; 3122 uint32_t value = 0; 3123 3124 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3125 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3126 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3127 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3128 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3129 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3130 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3131 } 3132 3133 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3134 struct amdgpu_device *adev, int me, int pipe, 3135 enum amdgpu_interrupt_state state, int xcc_id) 3136 { 3137 u32 mec_int_cntl, mec_int_cntl_reg; 3138 3139 /* 3140 * amdgpu controls only the first MEC. That's why this function only 3141 * handles the setting of interrupts for this specific MEC. All other 3142 * pipes' interrupts are set by amdkfd. 3143 */ 3144 3145 if (me == 1) { 3146 switch (pipe) { 3147 case 0: 3148 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3149 break; 3150 case 1: 3151 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3152 break; 3153 case 2: 3154 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3155 break; 3156 case 3: 3157 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3158 break; 3159 default: 3160 DRM_DEBUG("invalid pipe %d\n", pipe); 3161 return; 3162 } 3163 } else { 3164 DRM_DEBUG("invalid me %d\n", me); 3165 return; 3166 } 3167 3168 switch (state) { 3169 case AMDGPU_IRQ_STATE_DISABLE: 3170 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3171 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3172 TIME_STAMP_INT_ENABLE, 0); 3173 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3174 break; 3175 case AMDGPU_IRQ_STATE_ENABLE: 3176 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3177 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3178 TIME_STAMP_INT_ENABLE, 1); 3179 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3180 break; 3181 default: 3182 break; 3183 } 3184 } 3185 3186 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3187 int xcc_id, int me, int pipe) 3188 { 3189 /* 3190 * amdgpu controls only the first MEC. That's why this function only 3191 * handles the setting of interrupts for this specific MEC. All other 3192 * pipes' interrupts are set by amdkfd. 3193 */ 3194 if (me != 1) 3195 return 0; 3196 3197 switch (pipe) { 3198 case 0: 3199 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3200 case 1: 3201 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3202 case 2: 3203 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3204 case 3: 3205 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3206 default: 3207 return 0; 3208 } 3209 } 3210 3211 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3212 struct amdgpu_irq_src *source, 3213 unsigned type, 3214 enum amdgpu_interrupt_state state) 3215 { 3216 u32 mec_int_cntl_reg, mec_int_cntl; 3217 int i, j, k, num_xcc; 3218 3219 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3220 switch (state) { 3221 case AMDGPU_IRQ_STATE_DISABLE: 3222 case AMDGPU_IRQ_STATE_ENABLE: 3223 for (i = 0; i < num_xcc; i++) { 3224 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3225 PRIV_REG_INT_ENABLE, 3226 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3227 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3228 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3229 /* MECs start at 1 */ 3230 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3231 3232 if (mec_int_cntl_reg) { 3233 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3234 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3235 PRIV_REG_INT_ENABLE, 3236 state == AMDGPU_IRQ_STATE_ENABLE ? 3237 1 : 0); 3238 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3239 } 3240 } 3241 } 3242 } 3243 break; 3244 default: 3245 break; 3246 } 3247 3248 return 0; 3249 } 3250 3251 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3252 struct amdgpu_irq_src *source, 3253 unsigned type, 3254 enum amdgpu_interrupt_state state) 3255 { 3256 u32 mec_int_cntl_reg, mec_int_cntl; 3257 int i, j, k, num_xcc; 3258 3259 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3260 switch (state) { 3261 case AMDGPU_IRQ_STATE_DISABLE: 3262 case AMDGPU_IRQ_STATE_ENABLE: 3263 for (i = 0; i < num_xcc; i++) { 3264 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3265 OPCODE_ERROR_INT_ENABLE, 3266 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3267 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3268 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3269 /* MECs start at 1 */ 3270 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3271 3272 if (mec_int_cntl_reg) { 3273 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3274 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3275 OPCODE_ERROR_INT_ENABLE, 3276 state == AMDGPU_IRQ_STATE_ENABLE ? 3277 1 : 0); 3278 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3279 } 3280 } 3281 } 3282 } 3283 break; 3284 default: 3285 break; 3286 } 3287 3288 return 0; 3289 } 3290 3291 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3292 struct amdgpu_irq_src *source, 3293 unsigned type, 3294 enum amdgpu_interrupt_state state) 3295 { 3296 int i, num_xcc; 3297 3298 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3299 switch (state) { 3300 case AMDGPU_IRQ_STATE_DISABLE: 3301 case AMDGPU_IRQ_STATE_ENABLE: 3302 for (i = 0; i < num_xcc; i++) 3303 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3304 PRIV_INSTR_INT_ENABLE, 3305 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3306 break; 3307 default: 3308 break; 3309 } 3310 3311 return 0; 3312 } 3313 3314 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3315 struct amdgpu_irq_src *src, 3316 unsigned type, 3317 enum amdgpu_interrupt_state state) 3318 { 3319 int i, num_xcc; 3320 3321 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3322 for (i = 0; i < num_xcc; i++) { 3323 switch (type) { 3324 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3325 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3326 adev, 1, 0, state, i); 3327 break; 3328 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3329 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3330 adev, 1, 1, state, i); 3331 break; 3332 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3333 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3334 adev, 1, 2, state, i); 3335 break; 3336 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3337 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3338 adev, 1, 3, state, i); 3339 break; 3340 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3341 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3342 adev, 2, 0, state, i); 3343 break; 3344 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3345 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3346 adev, 2, 1, state, i); 3347 break; 3348 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3349 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3350 adev, 2, 2, state, i); 3351 break; 3352 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3353 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3354 adev, 2, 3, state, i); 3355 break; 3356 default: 3357 break; 3358 } 3359 } 3360 3361 return 0; 3362 } 3363 3364 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3365 struct amdgpu_irq_src *source, 3366 struct amdgpu_iv_entry *entry) 3367 { 3368 int i, xcc_id; 3369 u8 me_id, pipe_id, queue_id; 3370 struct amdgpu_ring *ring; 3371 3372 DRM_DEBUG("IH: CP EOP\n"); 3373 me_id = (entry->ring_id & 0x0c) >> 2; 3374 pipe_id = (entry->ring_id & 0x03) >> 0; 3375 queue_id = (entry->ring_id & 0x70) >> 4; 3376 3377 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3378 3379 if (xcc_id == -EINVAL) 3380 return -EINVAL; 3381 3382 switch (me_id) { 3383 case 0: 3384 case 1: 3385 case 2: 3386 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3387 ring = &adev->gfx.compute_ring 3388 [i + 3389 xcc_id * adev->gfx.num_compute_rings]; 3390 /* Per-queue interrupt is supported for MEC starting from VI. 3391 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3392 */ 3393 3394 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3395 amdgpu_fence_process(ring); 3396 } 3397 break; 3398 } 3399 return 0; 3400 } 3401 3402 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3403 struct amdgpu_iv_entry *entry) 3404 { 3405 u8 me_id, pipe_id, queue_id; 3406 struct amdgpu_ring *ring; 3407 int i, xcc_id; 3408 3409 me_id = (entry->ring_id & 0x0c) >> 2; 3410 pipe_id = (entry->ring_id & 0x03) >> 0; 3411 queue_id = (entry->ring_id & 0x70) >> 4; 3412 3413 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3414 3415 if (xcc_id == -EINVAL) 3416 return; 3417 3418 switch (me_id) { 3419 case 0: 3420 case 1: 3421 case 2: 3422 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3423 ring = &adev->gfx.compute_ring 3424 [i + 3425 xcc_id * adev->gfx.num_compute_rings]; 3426 if (ring->me == me_id && ring->pipe == pipe_id && 3427 ring->queue == queue_id) 3428 drm_sched_fault(&ring->sched); 3429 } 3430 break; 3431 } 3432 } 3433 3434 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3435 struct amdgpu_irq_src *source, 3436 struct amdgpu_iv_entry *entry) 3437 { 3438 DRM_ERROR("Illegal register access in command stream\n"); 3439 gfx_v9_4_3_fault(adev, entry); 3440 return 0; 3441 } 3442 3443 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3444 struct amdgpu_irq_src *source, 3445 struct amdgpu_iv_entry *entry) 3446 { 3447 DRM_ERROR("Illegal opcode in command stream\n"); 3448 gfx_v9_4_3_fault(adev, entry); 3449 return 0; 3450 } 3451 3452 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3453 struct amdgpu_irq_src *source, 3454 struct amdgpu_iv_entry *entry) 3455 { 3456 DRM_ERROR("Illegal instruction in command stream\n"); 3457 gfx_v9_4_3_fault(adev, entry); 3458 return 0; 3459 } 3460 3461 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3462 { 3463 const unsigned int cp_coher_cntl = 3464 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3465 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3466 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3467 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3468 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3469 3470 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3471 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3472 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3473 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3474 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3475 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3476 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3477 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3478 } 3479 3480 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3481 uint32_t pipe, bool enable) 3482 { 3483 struct amdgpu_device *adev = ring->adev; 3484 uint32_t val; 3485 uint32_t wcl_cs_reg; 3486 3487 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3488 val = enable ? 0x1 : 0x7f; 3489 3490 switch (pipe) { 3491 case 0: 3492 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3493 break; 3494 case 1: 3495 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3496 break; 3497 case 2: 3498 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3499 break; 3500 case 3: 3501 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3502 break; 3503 default: 3504 DRM_DEBUG("invalid pipe %d\n", pipe); 3505 return; 3506 } 3507 3508 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3509 3510 } 3511 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3512 { 3513 struct amdgpu_device *adev = ring->adev; 3514 uint32_t val; 3515 int i; 3516 3517 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3518 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3519 * around 25% of gpu resources. 3520 */ 3521 val = enable ? 0x1f : 0x07ffffff; 3522 amdgpu_ring_emit_wreg(ring, 3523 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3524 val); 3525 3526 /* Restrict waves for normal/low priority compute queues as well 3527 * to get best QoS for high priority compute jobs. 3528 * 3529 * amdgpu controls only 1st ME(0-3 CS pipes). 3530 */ 3531 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3532 if (i != ring->pipe) 3533 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3534 3535 } 3536 } 3537 3538 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3539 uint32_t pipe, uint32_t queue, 3540 uint32_t xcc_id) 3541 { 3542 int i, r; 3543 /* make sure dequeue is complete*/ 3544 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3545 mutex_lock(&adev->srbm_mutex); 3546 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3547 for (i = 0; i < adev->usec_timeout; i++) { 3548 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3549 break; 3550 udelay(1); 3551 } 3552 if (i >= adev->usec_timeout) 3553 r = -ETIMEDOUT; 3554 else 3555 r = 0; 3556 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3557 mutex_unlock(&adev->srbm_mutex); 3558 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3559 3560 return r; 3561 3562 } 3563 3564 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3565 { 3566 if (!!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3567 return true; 3568 else 3569 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3570 3571 return false; 3572 } 3573 3574 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3575 { 3576 struct amdgpu_device *adev = ring->adev; 3577 uint32_t reset_pipe, clean_pipe; 3578 int r; 3579 3580 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3581 return -EINVAL; 3582 3583 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3584 mutex_lock(&adev->srbm_mutex); 3585 3586 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3587 clean_pipe = reset_pipe; 3588 3589 if (ring->me == 1) { 3590 switch (ring->pipe) { 3591 case 0: 3592 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3593 MEC_ME1_PIPE0_RESET, 1); 3594 break; 3595 case 1: 3596 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3597 MEC_ME1_PIPE1_RESET, 1); 3598 break; 3599 case 2: 3600 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3601 MEC_ME1_PIPE2_RESET, 1); 3602 break; 3603 case 3: 3604 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3605 MEC_ME1_PIPE3_RESET, 1); 3606 break; 3607 default: 3608 break; 3609 } 3610 } else { 3611 if (ring->pipe) 3612 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3613 MEC_ME2_PIPE1_RESET, 1); 3614 else 3615 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3616 MEC_ME2_PIPE0_RESET, 1); 3617 } 3618 3619 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3620 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3621 mutex_unlock(&adev->srbm_mutex); 3622 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3623 3624 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3625 return r; 3626 } 3627 3628 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3629 unsigned int vmid, 3630 struct amdgpu_fence *timedout_fence) 3631 { 3632 struct amdgpu_device *adev = ring->adev; 3633 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3634 struct amdgpu_ring *kiq_ring = &kiq->ring; 3635 int reset_mode = AMDGPU_RESET_TYPE_PER_QUEUE; 3636 unsigned long flags; 3637 int r; 3638 3639 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3640 return -EINVAL; 3641 3642 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 3643 3644 spin_lock_irqsave(&kiq->ring_lock, flags); 3645 3646 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3647 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3648 return -ENOMEM; 3649 } 3650 3651 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3652 0, 0); 3653 amdgpu_ring_commit(kiq_ring); 3654 3655 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3656 3657 r = amdgpu_ring_test_ring(kiq_ring); 3658 if (r) { 3659 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3660 ring->name); 3661 goto pipe_reset; 3662 } 3663 3664 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3665 if (r) 3666 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3667 3668 pipe_reset: 3669 if (r) { 3670 if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3671 return -EOPNOTSUPP; 3672 r = gfx_v9_4_3_reset_hw_pipe(ring); 3673 reset_mode = AMDGPU_RESET_TYPE_PER_PIPE; 3674 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3675 r ? "failed" : "successfully"); 3676 if (r) 3677 return r; 3678 } 3679 3680 gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3681 3682 spin_lock_irqsave(&kiq->ring_lock, flags); 3683 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3684 if (r) { 3685 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3686 return -ENOMEM; 3687 } 3688 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3689 amdgpu_ring_commit(kiq_ring); 3690 r = amdgpu_ring_test_ring(kiq_ring); 3691 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3692 if (r) { 3693 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) 3694 goto pipe_reset; 3695 3696 dev_err(adev->dev, "fail to remap queue\n"); 3697 return r; 3698 } 3699 3700 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) { 3701 r = amdgpu_ring_test_ring(ring); 3702 if (r) 3703 goto pipe_reset; 3704 } 3705 3706 3707 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 3708 } 3709 3710 enum amdgpu_gfx_cp_ras_mem_id { 3711 AMDGPU_GFX_CP_MEM1 = 1, 3712 AMDGPU_GFX_CP_MEM2, 3713 AMDGPU_GFX_CP_MEM3, 3714 AMDGPU_GFX_CP_MEM4, 3715 AMDGPU_GFX_CP_MEM5, 3716 }; 3717 3718 enum amdgpu_gfx_gcea_ras_mem_id { 3719 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3720 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3721 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3722 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3723 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3724 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3725 AMDGPU_GFX_GCEA_MAM_DMEM0, 3726 AMDGPU_GFX_GCEA_MAM_DMEM1, 3727 AMDGPU_GFX_GCEA_MAM_DMEM2, 3728 AMDGPU_GFX_GCEA_MAM_DMEM3, 3729 AMDGPU_GFX_GCEA_MAM_AMEM0, 3730 AMDGPU_GFX_GCEA_MAM_AMEM1, 3731 AMDGPU_GFX_GCEA_MAM_AMEM2, 3732 AMDGPU_GFX_GCEA_MAM_AMEM3, 3733 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3734 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3735 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3736 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3737 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3738 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3739 }; 3740 3741 enum amdgpu_gfx_gc_cane_ras_mem_id { 3742 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3743 }; 3744 3745 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3746 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3747 }; 3748 3749 enum amdgpu_gfx_gds_ras_mem_id { 3750 AMDGPU_GFX_GDS_MEM0 = 0, 3751 }; 3752 3753 enum amdgpu_gfx_lds_ras_mem_id { 3754 AMDGPU_GFX_LDS_BANK0 = 0, 3755 AMDGPU_GFX_LDS_BANK1, 3756 AMDGPU_GFX_LDS_BANK2, 3757 AMDGPU_GFX_LDS_BANK3, 3758 AMDGPU_GFX_LDS_BANK4, 3759 AMDGPU_GFX_LDS_BANK5, 3760 AMDGPU_GFX_LDS_BANK6, 3761 AMDGPU_GFX_LDS_BANK7, 3762 AMDGPU_GFX_LDS_BANK8, 3763 AMDGPU_GFX_LDS_BANK9, 3764 AMDGPU_GFX_LDS_BANK10, 3765 AMDGPU_GFX_LDS_BANK11, 3766 AMDGPU_GFX_LDS_BANK12, 3767 AMDGPU_GFX_LDS_BANK13, 3768 AMDGPU_GFX_LDS_BANK14, 3769 AMDGPU_GFX_LDS_BANK15, 3770 AMDGPU_GFX_LDS_BANK16, 3771 AMDGPU_GFX_LDS_BANK17, 3772 AMDGPU_GFX_LDS_BANK18, 3773 AMDGPU_GFX_LDS_BANK19, 3774 AMDGPU_GFX_LDS_BANK20, 3775 AMDGPU_GFX_LDS_BANK21, 3776 AMDGPU_GFX_LDS_BANK22, 3777 AMDGPU_GFX_LDS_BANK23, 3778 AMDGPU_GFX_LDS_BANK24, 3779 AMDGPU_GFX_LDS_BANK25, 3780 AMDGPU_GFX_LDS_BANK26, 3781 AMDGPU_GFX_LDS_BANK27, 3782 AMDGPU_GFX_LDS_BANK28, 3783 AMDGPU_GFX_LDS_BANK29, 3784 AMDGPU_GFX_LDS_BANK30, 3785 AMDGPU_GFX_LDS_BANK31, 3786 AMDGPU_GFX_LDS_SP_BUFFER_A, 3787 AMDGPU_GFX_LDS_SP_BUFFER_B, 3788 }; 3789 3790 enum amdgpu_gfx_rlc_ras_mem_id { 3791 AMDGPU_GFX_RLC_GPMF32 = 1, 3792 AMDGPU_GFX_RLC_RLCVF32, 3793 AMDGPU_GFX_RLC_SCRATCH, 3794 AMDGPU_GFX_RLC_SRM_ARAM, 3795 AMDGPU_GFX_RLC_SRM_DRAM, 3796 AMDGPU_GFX_RLC_TCTAG, 3797 AMDGPU_GFX_RLC_SPM_SE, 3798 AMDGPU_GFX_RLC_SPM_GRBMT, 3799 }; 3800 3801 enum amdgpu_gfx_sp_ras_mem_id { 3802 AMDGPU_GFX_SP_SIMDID0 = 0, 3803 }; 3804 3805 enum amdgpu_gfx_spi_ras_mem_id { 3806 AMDGPU_GFX_SPI_MEM0 = 0, 3807 AMDGPU_GFX_SPI_MEM1, 3808 AMDGPU_GFX_SPI_MEM2, 3809 AMDGPU_GFX_SPI_MEM3, 3810 }; 3811 3812 enum amdgpu_gfx_sqc_ras_mem_id { 3813 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3814 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3815 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3816 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3817 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3818 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3819 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3820 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3821 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3822 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3823 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3824 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3825 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3826 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3827 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3828 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3829 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3830 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3831 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3832 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3833 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3834 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3835 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3836 }; 3837 3838 enum amdgpu_gfx_sq_ras_mem_id { 3839 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3840 AMDGPU_GFX_SQ_SGPR_MEM1, 3841 AMDGPU_GFX_SQ_SGPR_MEM2, 3842 AMDGPU_GFX_SQ_SGPR_MEM3, 3843 }; 3844 3845 enum amdgpu_gfx_ta_ras_mem_id { 3846 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3847 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3848 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3849 AMDGPU_GFX_TA_FSX_LFIFO, 3850 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3851 }; 3852 3853 enum amdgpu_gfx_tcc_ras_mem_id { 3854 AMDGPU_GFX_TCC_MEM1 = 1, 3855 }; 3856 3857 enum amdgpu_gfx_tca_ras_mem_id { 3858 AMDGPU_GFX_TCA_MEM1 = 1, 3859 }; 3860 3861 enum amdgpu_gfx_tci_ras_mem_id { 3862 AMDGPU_GFX_TCIW_MEM = 1, 3863 }; 3864 3865 enum amdgpu_gfx_tcp_ras_mem_id { 3866 AMDGPU_GFX_TCP_LFIFO0 = 1, 3867 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3868 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3869 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3870 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3871 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3872 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3873 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3874 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3875 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3876 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3877 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3878 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3879 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3880 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3881 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3882 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3883 AMDGPU_GFX_TCP_VM_FIFO, 3884 AMDGPU_GFX_TCP_DB_TAGRAM0, 3885 AMDGPU_GFX_TCP_DB_TAGRAM1, 3886 AMDGPU_GFX_TCP_DB_TAGRAM2, 3887 AMDGPU_GFX_TCP_DB_TAGRAM3, 3888 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3889 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3890 AMDGPU_GFX_TCP_CMD_FIFO, 3891 }; 3892 3893 enum amdgpu_gfx_td_ras_mem_id { 3894 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3895 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3896 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3897 }; 3898 3899 enum amdgpu_gfx_tcx_ras_mem_id { 3900 AMDGPU_GFX_TCX_FIFOD0 = 0, 3901 AMDGPU_GFX_TCX_FIFOD1, 3902 AMDGPU_GFX_TCX_FIFOD2, 3903 AMDGPU_GFX_TCX_FIFOD3, 3904 AMDGPU_GFX_TCX_FIFOD4, 3905 AMDGPU_GFX_TCX_FIFOD5, 3906 AMDGPU_GFX_TCX_FIFOD6, 3907 AMDGPU_GFX_TCX_FIFOD7, 3908 AMDGPU_GFX_TCX_FIFOB0, 3909 AMDGPU_GFX_TCX_FIFOB1, 3910 AMDGPU_GFX_TCX_FIFOB2, 3911 AMDGPU_GFX_TCX_FIFOB3, 3912 AMDGPU_GFX_TCX_FIFOB4, 3913 AMDGPU_GFX_TCX_FIFOB5, 3914 AMDGPU_GFX_TCX_FIFOB6, 3915 AMDGPU_GFX_TCX_FIFOB7, 3916 AMDGPU_GFX_TCX_FIFOA0, 3917 AMDGPU_GFX_TCX_FIFOA1, 3918 AMDGPU_GFX_TCX_FIFOA2, 3919 AMDGPU_GFX_TCX_FIFOA3, 3920 AMDGPU_GFX_TCX_FIFOA4, 3921 AMDGPU_GFX_TCX_FIFOA5, 3922 AMDGPU_GFX_TCX_FIFOA6, 3923 AMDGPU_GFX_TCX_FIFOA7, 3924 AMDGPU_GFX_TCX_CFIFO0, 3925 AMDGPU_GFX_TCX_CFIFO1, 3926 AMDGPU_GFX_TCX_CFIFO2, 3927 AMDGPU_GFX_TCX_CFIFO3, 3928 AMDGPU_GFX_TCX_CFIFO4, 3929 AMDGPU_GFX_TCX_CFIFO5, 3930 AMDGPU_GFX_TCX_CFIFO6, 3931 AMDGPU_GFX_TCX_CFIFO7, 3932 AMDGPU_GFX_TCX_FIFO_ACKB0, 3933 AMDGPU_GFX_TCX_FIFO_ACKB1, 3934 AMDGPU_GFX_TCX_FIFO_ACKB2, 3935 AMDGPU_GFX_TCX_FIFO_ACKB3, 3936 AMDGPU_GFX_TCX_FIFO_ACKB4, 3937 AMDGPU_GFX_TCX_FIFO_ACKB5, 3938 AMDGPU_GFX_TCX_FIFO_ACKB6, 3939 AMDGPU_GFX_TCX_FIFO_ACKB7, 3940 AMDGPU_GFX_TCX_FIFO_ACKD0, 3941 AMDGPU_GFX_TCX_FIFO_ACKD1, 3942 AMDGPU_GFX_TCX_FIFO_ACKD2, 3943 AMDGPU_GFX_TCX_FIFO_ACKD3, 3944 AMDGPU_GFX_TCX_FIFO_ACKD4, 3945 AMDGPU_GFX_TCX_FIFO_ACKD5, 3946 AMDGPU_GFX_TCX_FIFO_ACKD6, 3947 AMDGPU_GFX_TCX_FIFO_ACKD7, 3948 AMDGPU_GFX_TCX_DST_FIFOA0, 3949 AMDGPU_GFX_TCX_DST_FIFOA1, 3950 AMDGPU_GFX_TCX_DST_FIFOA2, 3951 AMDGPU_GFX_TCX_DST_FIFOA3, 3952 AMDGPU_GFX_TCX_DST_FIFOA4, 3953 AMDGPU_GFX_TCX_DST_FIFOA5, 3954 AMDGPU_GFX_TCX_DST_FIFOA6, 3955 AMDGPU_GFX_TCX_DST_FIFOA7, 3956 AMDGPU_GFX_TCX_DST_FIFOB0, 3957 AMDGPU_GFX_TCX_DST_FIFOB1, 3958 AMDGPU_GFX_TCX_DST_FIFOB2, 3959 AMDGPU_GFX_TCX_DST_FIFOB3, 3960 AMDGPU_GFX_TCX_DST_FIFOB4, 3961 AMDGPU_GFX_TCX_DST_FIFOB5, 3962 AMDGPU_GFX_TCX_DST_FIFOB6, 3963 AMDGPU_GFX_TCX_DST_FIFOB7, 3964 AMDGPU_GFX_TCX_DST_FIFOD0, 3965 AMDGPU_GFX_TCX_DST_FIFOD1, 3966 AMDGPU_GFX_TCX_DST_FIFOD2, 3967 AMDGPU_GFX_TCX_DST_FIFOD3, 3968 AMDGPU_GFX_TCX_DST_FIFOD4, 3969 AMDGPU_GFX_TCX_DST_FIFOD5, 3970 AMDGPU_GFX_TCX_DST_FIFOD6, 3971 AMDGPU_GFX_TCX_DST_FIFOD7, 3972 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3973 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3974 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3975 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3976 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3977 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3978 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3979 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3980 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3981 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3982 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3983 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3984 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3985 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3986 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3987 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3988 }; 3989 3990 enum amdgpu_gfx_atc_l2_ras_mem_id { 3991 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3992 }; 3993 3994 enum amdgpu_gfx_utcl2_ras_mem_id { 3995 AMDGPU_GFX_UTCL2_MEM0 = 0, 3996 }; 3997 3998 enum amdgpu_gfx_vml2_ras_mem_id { 3999 AMDGPU_GFX_VML2_MEM0 = 0, 4000 }; 4001 4002 enum amdgpu_gfx_vml2_walker_ras_mem_id { 4003 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 4004 }; 4005 4006 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 4007 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 4008 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 4009 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 4010 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 4011 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 4012 }; 4013 4014 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 4015 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 4016 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 4017 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 4018 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 4019 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 4020 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 4021 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 4022 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 4023 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 4024 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 4025 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 4026 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 4027 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 4028 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 4029 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 4030 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 4031 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 4032 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 4033 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 4034 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 4035 }; 4036 4037 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 4038 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 4039 }; 4040 4041 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 4042 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 4043 }; 4044 4045 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 4046 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 4047 }; 4048 4049 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 4050 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 4051 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 4052 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 4053 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 4054 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 4055 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 4056 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 4057 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 4058 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 4059 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 4060 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 4061 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 4062 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 4063 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 4064 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 4065 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 4066 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 4067 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 4068 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 4069 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 4070 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 4071 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 4072 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 4073 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 4074 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 4075 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 4076 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 4077 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 4078 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 4079 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 4080 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 4081 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 4082 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 4083 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4084 }; 4085 4086 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4087 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4088 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4089 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4090 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4091 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4092 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4093 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4094 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4095 }; 4096 4097 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4098 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4099 }; 4100 4101 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4102 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4103 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4104 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4105 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4106 }; 4107 4108 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4109 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4110 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4111 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4112 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4113 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4114 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4115 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4116 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4117 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4118 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4119 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4120 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4121 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4122 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4123 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4124 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4125 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4126 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4127 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4128 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4129 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4130 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4131 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4132 }; 4133 4134 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4135 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4136 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4137 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4138 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4139 }; 4140 4141 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4142 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4143 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4144 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4145 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4146 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4147 }; 4148 4149 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4150 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4151 }; 4152 4153 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4154 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4155 }; 4156 4157 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4158 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4159 }; 4160 4161 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4162 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4163 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4164 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4165 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4166 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4167 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4168 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4169 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4170 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4171 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4172 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4173 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4174 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4175 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4176 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4177 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4178 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4179 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4180 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4181 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4182 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4183 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4184 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4185 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4186 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4187 }; 4188 4189 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4190 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4191 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4192 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4193 }; 4194 4195 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4196 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4197 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4198 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4199 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4200 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4201 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4202 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4203 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4204 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4205 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4206 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4207 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4208 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4209 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4210 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4211 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4212 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4213 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4214 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4215 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4216 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4217 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4218 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4219 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4220 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4221 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4222 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4223 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4224 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4225 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4226 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4227 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4228 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4229 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4230 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4231 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4232 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4233 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4234 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4235 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4236 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4237 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4238 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4239 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4240 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4241 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4242 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4243 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4244 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4245 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4246 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4247 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4248 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4249 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4250 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4251 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4252 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4253 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4254 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4255 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4256 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4257 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4258 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4259 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4260 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4261 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4262 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4263 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4264 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4265 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4266 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4267 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4268 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4269 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4270 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4271 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4272 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4273 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4274 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4275 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4276 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4277 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4278 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4279 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4280 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4281 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4282 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4283 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4284 }; 4285 4286 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4287 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4288 }; 4289 4290 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4291 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4292 }; 4293 4294 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4295 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4296 }; 4297 4298 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4299 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4300 }; 4301 4302 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4303 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4304 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4305 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4306 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4307 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4308 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4309 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4310 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4311 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4312 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4313 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4314 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4315 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4316 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4317 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4318 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4319 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4320 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4321 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4322 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4323 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4324 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4325 }; 4326 4327 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4328 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4329 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4330 AMDGPU_GFX_RLC_MEM, 1}, 4331 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4332 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4333 AMDGPU_GFX_CP_MEM, 1}, 4334 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4335 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4336 AMDGPU_GFX_CP_MEM, 1}, 4337 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4338 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4339 AMDGPU_GFX_CP_MEM, 1}, 4340 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4341 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4342 AMDGPU_GFX_GDS_MEM, 1}, 4343 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4344 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4345 AMDGPU_GFX_GC_CANE_MEM, 1}, 4346 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4347 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4348 AMDGPU_GFX_SPI_MEM, 1}, 4349 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4350 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4351 AMDGPU_GFX_SP_MEM, 4}, 4352 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4353 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4354 AMDGPU_GFX_SP_MEM, 4}, 4355 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4356 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4357 AMDGPU_GFX_SQ_MEM, 4}, 4358 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4359 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4360 AMDGPU_GFX_SQC_MEM, 4}, 4361 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4362 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4363 AMDGPU_GFX_TCX_MEM, 1}, 4364 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4365 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4366 AMDGPU_GFX_TCC_MEM, 1}, 4367 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4368 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4369 AMDGPU_GFX_TA_MEM, 4}, 4370 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4371 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4372 AMDGPU_GFX_TCI_MEM, 1}, 4373 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4374 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4375 AMDGPU_GFX_TCP_MEM, 4}, 4376 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4377 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4378 AMDGPU_GFX_TD_MEM, 4}, 4379 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4380 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4381 AMDGPU_GFX_GCEA_MEM, 1}, 4382 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4383 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4384 AMDGPU_GFX_LDS_MEM, 4}, 4385 }; 4386 4387 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4388 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4389 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4390 AMDGPU_GFX_RLC_MEM, 1}, 4391 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4392 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4393 AMDGPU_GFX_CP_MEM, 1}, 4394 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4395 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4396 AMDGPU_GFX_CP_MEM, 1}, 4397 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4398 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4399 AMDGPU_GFX_CP_MEM, 1}, 4400 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4401 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4402 AMDGPU_GFX_GDS_MEM, 1}, 4403 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4404 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4405 AMDGPU_GFX_GC_CANE_MEM, 1}, 4406 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4407 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4408 AMDGPU_GFX_SPI_MEM, 1}, 4409 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4410 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4411 AMDGPU_GFX_SP_MEM, 4}, 4412 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4413 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4414 AMDGPU_GFX_SP_MEM, 4}, 4415 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4416 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4417 AMDGPU_GFX_SQ_MEM, 4}, 4418 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4419 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4420 AMDGPU_GFX_SQC_MEM, 4}, 4421 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4422 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4423 AMDGPU_GFX_TCX_MEM, 1}, 4424 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4425 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4426 AMDGPU_GFX_TCC_MEM, 1}, 4427 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4428 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4429 AMDGPU_GFX_TA_MEM, 4}, 4430 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4431 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4432 AMDGPU_GFX_TCI_MEM, 1}, 4433 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4434 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4435 AMDGPU_GFX_TCP_MEM, 4}, 4436 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4437 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4438 AMDGPU_GFX_TD_MEM, 4}, 4439 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4440 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4441 AMDGPU_GFX_TCA_MEM, 1}, 4442 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4443 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4444 AMDGPU_GFX_GCEA_MEM, 1}, 4445 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4446 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4447 AMDGPU_GFX_LDS_MEM, 4}, 4448 }; 4449 4450 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4451 void *ras_error_status, int xcc_id) 4452 { 4453 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4454 unsigned long ce_count = 0, ue_count = 0; 4455 uint32_t i, j, k; 4456 4457 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4458 struct amdgpu_smuio_mcm_config_info mcm_info = { 4459 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4460 .die_id = xcc_id & 0x01 ? 1 : 0, 4461 }; 4462 4463 mutex_lock(&adev->grbm_idx_mutex); 4464 4465 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4466 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4467 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4468 /* no need to select if instance number is 1 */ 4469 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4470 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4471 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4472 4473 amdgpu_ras_inst_query_ras_error_count(adev, 4474 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4475 1, 4476 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4477 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4478 GET_INST(GC, xcc_id), 4479 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4480 &ce_count); 4481 4482 amdgpu_ras_inst_query_ras_error_count(adev, 4483 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4484 1, 4485 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4486 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4487 GET_INST(GC, xcc_id), 4488 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4489 &ue_count); 4490 } 4491 } 4492 } 4493 4494 /* handle extra register entries of UE */ 4495 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4496 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4497 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4498 /* no need to select if instance number is 1 */ 4499 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4500 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4501 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4502 4503 amdgpu_ras_inst_query_ras_error_count(adev, 4504 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4505 1, 4506 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4507 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4508 GET_INST(GC, xcc_id), 4509 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4510 &ue_count); 4511 } 4512 } 4513 } 4514 4515 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4516 xcc_id); 4517 mutex_unlock(&adev->grbm_idx_mutex); 4518 4519 /* the caller should make sure initialize value of 4520 * err_data->ue_count and err_data->ce_count 4521 */ 4522 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4523 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4524 } 4525 4526 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4527 void *ras_error_status, int xcc_id) 4528 { 4529 uint32_t i, j, k; 4530 4531 mutex_lock(&adev->grbm_idx_mutex); 4532 4533 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4534 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4535 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4536 /* no need to select if instance number is 1 */ 4537 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4538 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4539 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4540 4541 amdgpu_ras_inst_reset_ras_error_count(adev, 4542 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4543 1, 4544 GET_INST(GC, xcc_id)); 4545 4546 amdgpu_ras_inst_reset_ras_error_count(adev, 4547 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4548 1, 4549 GET_INST(GC, xcc_id)); 4550 } 4551 } 4552 } 4553 4554 /* handle extra register entries of UE */ 4555 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4556 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4557 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4558 /* no need to select if instance number is 1 */ 4559 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4560 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4561 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4562 4563 amdgpu_ras_inst_reset_ras_error_count(adev, 4564 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4565 1, 4566 GET_INST(GC, xcc_id)); 4567 } 4568 } 4569 } 4570 4571 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4572 xcc_id); 4573 mutex_unlock(&adev->grbm_idx_mutex); 4574 } 4575 4576 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4577 void *ras_error_status, int xcc_id) 4578 { 4579 uint32_t i; 4580 uint32_t data; 4581 4582 if (amdgpu_sriov_vf(adev)) 4583 return; 4584 4585 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4586 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4587 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4588 4589 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4590 (amdgpu_watchdog_timer.period < 1 || 4591 amdgpu_watchdog_timer.period > 0x23)) { 4592 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4593 amdgpu_watchdog_timer.period = 0x23; 4594 } 4595 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4596 amdgpu_watchdog_timer.period); 4597 4598 mutex_lock(&adev->grbm_idx_mutex); 4599 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4600 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4601 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4602 } 4603 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4604 xcc_id); 4605 mutex_unlock(&adev->grbm_idx_mutex); 4606 } 4607 4608 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4609 void *ras_error_status) 4610 { 4611 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4612 gfx_v9_4_3_inst_query_ras_err_count); 4613 } 4614 4615 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4616 { 4617 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4618 } 4619 4620 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4621 { 4622 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4623 } 4624 4625 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4626 { 4627 /* Header itself is a NOP packet */ 4628 if (num_nop == 1) { 4629 amdgpu_ring_write(ring, ring->funcs->nop); 4630 return; 4631 } 4632 4633 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4634 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4635 4636 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4637 amdgpu_ring_insert_nop(ring, num_nop - 1); 4638 } 4639 4640 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4641 { 4642 struct amdgpu_device *adev = ip_block->adev; 4643 uint32_t i, j, k; 4644 uint32_t xcc_id, xcc_offset, inst_offset; 4645 uint32_t num_xcc, reg, num_inst; 4646 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4647 4648 if (!adev->gfx.ip_dump_core) 4649 return; 4650 4651 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4652 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4653 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4654 xcc_offset = xcc_id * reg_count; 4655 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4656 for (i = 0; i < reg_count; i++) 4657 drm_printf(p, "%-50s \t 0x%08x\n", 4658 gc_reg_list_9_4_3[i].reg_name, 4659 adev->gfx.ip_dump_core[xcc_offset + i]); 4660 } 4661 4662 /* print compute queue registers for all instances */ 4663 if (!adev->gfx.ip_dump_compute_queues) 4664 return; 4665 4666 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4667 adev->gfx.mec.num_queue_per_pipe; 4668 4669 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4670 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4671 num_xcc, 4672 adev->gfx.mec.num_mec, 4673 adev->gfx.mec.num_pipe_per_mec, 4674 adev->gfx.mec.num_queue_per_pipe); 4675 4676 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4677 xcc_offset = xcc_id * reg_count * num_inst; 4678 inst_offset = 0; 4679 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4680 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4681 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4682 drm_printf(p, 4683 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4684 xcc_id, i, j, k); 4685 for (reg = 0; reg < reg_count; reg++) { 4686 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4687 regCP_MEC_ME1_HEADER_DUMP) 4688 drm_printf(p, 4689 "%-50s \t 0x%08x\n", 4690 "regCP_MEC_ME2_HEADER_DUMP", 4691 adev->gfx.ip_dump_compute_queues 4692 [xcc_offset + inst_offset + 4693 reg]); 4694 else 4695 drm_printf(p, 4696 "%-50s \t 0x%08x\n", 4697 gc_cp_reg_list_9_4_3[reg].reg_name, 4698 adev->gfx.ip_dump_compute_queues 4699 [xcc_offset + inst_offset + 4700 reg]); 4701 } 4702 inst_offset += reg_count; 4703 } 4704 } 4705 } 4706 } 4707 } 4708 4709 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4710 { 4711 struct amdgpu_device *adev = ip_block->adev; 4712 uint32_t i, j, k; 4713 uint32_t num_xcc, reg, num_inst; 4714 uint32_t xcc_id, xcc_offset, inst_offset; 4715 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4716 4717 if (!adev->gfx.ip_dump_core) 4718 return; 4719 4720 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4721 4722 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4723 xcc_offset = xcc_id * reg_count; 4724 for (i = 0; i < reg_count; i++) 4725 adev->gfx.ip_dump_core[xcc_offset + i] = 4726 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4727 GET_INST(GC, xcc_id))); 4728 } 4729 4730 /* dump compute queue registers for all instances */ 4731 if (!adev->gfx.ip_dump_compute_queues) 4732 return; 4733 4734 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4735 adev->gfx.mec.num_queue_per_pipe; 4736 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4737 mutex_lock(&adev->srbm_mutex); 4738 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4739 xcc_offset = xcc_id * reg_count * num_inst; 4740 inst_offset = 0; 4741 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4742 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4743 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4744 /* ME0 is for GFX so start from 1 for CP */ 4745 soc15_grbm_select(adev, 1 + i, j, k, 0, 4746 GET_INST(GC, xcc_id)); 4747 4748 for (reg = 0; reg < reg_count; reg++) { 4749 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4750 regCP_MEC_ME1_HEADER_DUMP) 4751 adev->gfx.ip_dump_compute_queues 4752 [xcc_offset + 4753 inst_offset + reg] = 4754 RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), 4755 regCP_MEC_ME2_HEADER_DUMP)); 4756 else 4757 adev->gfx.ip_dump_compute_queues 4758 [xcc_offset + 4759 inst_offset + reg] = 4760 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4761 gc_cp_reg_list_9_4_3[reg], 4762 GET_INST(GC, xcc_id))); 4763 } 4764 inst_offset += reg_count; 4765 } 4766 } 4767 } 4768 } 4769 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4770 mutex_unlock(&adev->srbm_mutex); 4771 } 4772 4773 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4774 { 4775 /* Emit the cleaner shader */ 4776 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4777 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4778 } 4779 4780 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4781 .name = "gfx_v9_4_3", 4782 .early_init = gfx_v9_4_3_early_init, 4783 .late_init = gfx_v9_4_3_late_init, 4784 .sw_init = gfx_v9_4_3_sw_init, 4785 .sw_fini = gfx_v9_4_3_sw_fini, 4786 .hw_init = gfx_v9_4_3_hw_init, 4787 .hw_fini = gfx_v9_4_3_hw_fini, 4788 .suspend = gfx_v9_4_3_suspend, 4789 .resume = gfx_v9_4_3_resume, 4790 .is_idle = gfx_v9_4_3_is_idle, 4791 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4792 .soft_reset = gfx_v9_4_3_soft_reset, 4793 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4794 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4795 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4796 .dump_ip_state = gfx_v9_4_3_ip_dump, 4797 .print_ip_state = gfx_v9_4_3_ip_print, 4798 }; 4799 4800 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4801 .type = AMDGPU_RING_TYPE_COMPUTE, 4802 .align_mask = 0xff, 4803 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4804 .support_64bit_ptrs = true, 4805 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4806 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4807 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4808 .emit_frame_size = 4809 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4810 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4811 5 + /* hdp invalidate */ 4812 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4813 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4814 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4815 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4816 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4817 7 + /* gfx_v9_4_3_emit_mem_sync */ 4818 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4819 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4820 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4821 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4822 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4823 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4824 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4825 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4826 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4827 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4828 .test_ring = gfx_v9_4_3_ring_test_ring, 4829 .test_ib = gfx_v9_4_3_ring_test_ib, 4830 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4831 .pad_ib = amdgpu_ring_generic_pad_ib, 4832 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4833 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4834 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4835 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4836 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4837 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4838 .reset = gfx_v9_4_3_reset_kcq, 4839 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4840 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4841 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4842 }; 4843 4844 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4845 .type = AMDGPU_RING_TYPE_KIQ, 4846 .align_mask = 0xff, 4847 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4848 .support_64bit_ptrs = true, 4849 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4850 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4851 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4852 .emit_frame_size = 4853 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4854 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4855 5 + /* hdp invalidate */ 4856 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4857 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4858 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4859 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4860 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4861 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4862 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4863 .test_ring = gfx_v9_4_3_ring_test_ring, 4864 .insert_nop = amdgpu_ring_insert_nop, 4865 .pad_ib = amdgpu_ring_generic_pad_ib, 4866 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4867 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4868 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4869 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4870 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4871 }; 4872 4873 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4874 { 4875 int i, j, num_xcc; 4876 4877 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4878 for (i = 0; i < num_xcc; i++) { 4879 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4880 4881 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4882 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4883 = &gfx_v9_4_3_ring_funcs_compute; 4884 } 4885 } 4886 4887 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4888 .set = gfx_v9_4_3_set_eop_interrupt_state, 4889 .process = gfx_v9_4_3_eop_irq, 4890 }; 4891 4892 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4893 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4894 .process = gfx_v9_4_3_priv_reg_irq, 4895 }; 4896 4897 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4898 .set = gfx_v9_4_3_set_bad_op_fault_state, 4899 .process = gfx_v9_4_3_bad_op_irq, 4900 }; 4901 4902 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4903 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4904 .process = gfx_v9_4_3_priv_inst_irq, 4905 }; 4906 4907 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4908 { 4909 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4910 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4911 4912 adev->gfx.priv_reg_irq.num_types = 1; 4913 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4914 4915 adev->gfx.bad_op_irq.num_types = 1; 4916 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4917 4918 adev->gfx.priv_inst_irq.num_types = 1; 4919 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4920 } 4921 4922 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4923 { 4924 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4925 } 4926 4927 4928 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4929 { 4930 /* 9.4.3 variants removed all the GDS internal memory, 4931 * only support GWS opcode in kernel, like barrier 4932 * semaphore.etc */ 4933 4934 /* init asic gds info */ 4935 adev->gds.gds_size = 0; 4936 adev->gds.gds_compute_max_wave_id = 0; 4937 adev->gds.gws_size = 64; 4938 adev->gds.oa_size = 16; 4939 } 4940 4941 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4942 u32 bitmap, int xcc_id) 4943 { 4944 u32 data; 4945 4946 if (!bitmap) 4947 return; 4948 4949 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4950 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4951 4952 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4953 } 4954 4955 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4956 { 4957 u32 data, mask; 4958 4959 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4960 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4961 4962 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4963 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4964 4965 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4966 4967 return (~data) & mask; 4968 } 4969 4970 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4971 struct amdgpu_cu_info *cu_info) 4972 { 4973 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4974 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4975 unsigned disable_masks[4 * 4]; 4976 bool is_symmetric_cus; 4977 4978 if (!adev || !cu_info) 4979 return -EINVAL; 4980 4981 /* 4982 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4983 */ 4984 if (adev->gfx.config.max_shader_engines * 4985 adev->gfx.config.max_sh_per_se > 16) 4986 return -EINVAL; 4987 4988 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4989 adev->gfx.config.max_shader_engines, 4990 adev->gfx.config.max_sh_per_se); 4991 4992 mutex_lock(&adev->grbm_idx_mutex); 4993 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4994 is_symmetric_cus = true; 4995 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4996 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4997 mask = 1; 4998 ao_bitmap = 0; 4999 counter = 0; 5000 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 5001 gfx_v9_4_3_set_user_cu_inactive_bitmap( 5002 adev, 5003 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 5004 xcc_id); 5005 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 5006 5007 cu_info->bitmap[xcc_id][i][j] = bitmap; 5008 5009 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5010 if (bitmap & mask) { 5011 if (counter < adev->gfx.config.max_cu_per_sh) 5012 ao_bitmap |= mask; 5013 counter++; 5014 } 5015 mask <<= 1; 5016 } 5017 active_cu_number += counter; 5018 if (i < 2 && j < 2) 5019 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5020 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5021 } 5022 if (i && is_symmetric_cus && prev_counter != counter) 5023 is_symmetric_cus = false; 5024 prev_counter = counter; 5025 } 5026 if (is_symmetric_cus) { 5027 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 5028 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 5029 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 5030 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 5031 } 5032 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 5033 xcc_id); 5034 } 5035 mutex_unlock(&adev->grbm_idx_mutex); 5036 5037 cu_info->number = active_cu_number; 5038 cu_info->ao_cu_mask = ao_cu_mask; 5039 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5040 5041 return 0; 5042 } 5043 5044 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 5045 .type = AMD_IP_BLOCK_TYPE_GFX, 5046 .major = 9, 5047 .minor = 4, 5048 .rev = 3, 5049 .funcs = &gfx_v9_4_3_ip_funcs, 5050 }; 5051 5052 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 5053 { 5054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5055 uint32_t tmp_mask; 5056 int i, r; 5057 5058 /* TODO : Initialize golden regs */ 5059 /* gfx_v9_4_3_init_golden_registers(adev); */ 5060 5061 tmp_mask = inst_mask; 5062 for_each_inst(i, tmp_mask) 5063 gfx_v9_4_3_xcc_constants_init(adev, i); 5064 5065 if (!amdgpu_sriov_vf(adev)) { 5066 tmp_mask = inst_mask; 5067 for_each_inst(i, tmp_mask) { 5068 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 5069 if (r) 5070 return r; 5071 } 5072 } 5073 5074 tmp_mask = inst_mask; 5075 for_each_inst(i, tmp_mask) { 5076 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 5077 if (r) 5078 return r; 5079 } 5080 5081 return 0; 5082 } 5083 5084 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 5085 { 5086 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5087 int i; 5088 5089 for_each_inst(i, inst_mask) 5090 gfx_v9_4_3_xcc_fini(adev, i); 5091 5092 return 0; 5093 } 5094 5095 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5096 .suspend = &gfx_v9_4_3_xcp_suspend, 5097 .resume = &gfx_v9_4_3_xcp_resume 5098 }; 5099 5100 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5101 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5102 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5103 }; 5104 5105 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5106 { 5107 int r; 5108 5109 r = amdgpu_ras_block_late_init(adev, ras_block); 5110 if (r) 5111 return r; 5112 5113 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5114 &gfx_v9_4_3_aca_info, 5115 NULL); 5116 if (r) 5117 goto late_fini; 5118 5119 return 0; 5120 5121 late_fini: 5122 amdgpu_ras_block_late_fini(adev, ras_block); 5123 5124 return r; 5125 } 5126 5127 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5128 .ras_block = { 5129 .hw_ops = &gfx_v9_4_3_ras_ops, 5130 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5131 }, 5132 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5133 }; 5134