1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* SE status registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 110 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 111 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 113 }; 114 115 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 116 /* compute queue registers */ 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 162 }; 163 164 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 165 166 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 167 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 168 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 169 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 170 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 171 struct amdgpu_cu_info *cu_info); 172 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 173 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 174 175 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 176 uint64_t queue_mask) 177 { 178 struct amdgpu_device *adev = kiq_ring->adev; 179 u64 shader_mc_addr; 180 181 /* Cleaner shader MC address */ 182 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 183 184 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 185 amdgpu_ring_write(kiq_ring, 186 PACKET3_SET_RESOURCES_VMID_MASK(0) | 187 /* vmid_mask:0* queue_type:0 (KIQ) */ 188 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 189 amdgpu_ring_write(kiq_ring, 190 lower_32_bits(queue_mask)); /* queue mask lo */ 191 amdgpu_ring_write(kiq_ring, 192 upper_32_bits(queue_mask)); /* queue mask hi */ 193 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 194 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 195 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 196 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 197 } 198 199 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 200 struct amdgpu_ring *ring) 201 { 202 struct amdgpu_device *adev = kiq_ring->adev; 203 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 204 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 205 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 206 207 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 208 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 209 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 210 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 211 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 212 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 213 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 214 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 215 /*queue_type: normal compute queue */ 216 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 217 /* alloc format: all_on_one_pipe */ 218 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 219 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 220 /* num_queues: must be 1 */ 221 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 222 amdgpu_ring_write(kiq_ring, 223 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 224 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 225 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 226 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 227 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 228 } 229 230 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 231 struct amdgpu_ring *ring, 232 enum amdgpu_unmap_queues_action action, 233 u64 gpu_addr, u64 seq) 234 { 235 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 236 237 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 238 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 239 PACKET3_UNMAP_QUEUES_ACTION(action) | 240 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 241 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 242 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 243 amdgpu_ring_write(kiq_ring, 244 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 245 246 if (action == PREEMPT_QUEUES_NO_UNMAP) { 247 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 248 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 249 amdgpu_ring_write(kiq_ring, seq); 250 } else { 251 amdgpu_ring_write(kiq_ring, 0); 252 amdgpu_ring_write(kiq_ring, 0); 253 amdgpu_ring_write(kiq_ring, 0); 254 } 255 } 256 257 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 258 struct amdgpu_ring *ring, 259 u64 addr, 260 u64 seq) 261 { 262 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 263 264 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 267 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 268 PACKET3_QUERY_STATUS_COMMAND(2)); 269 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 270 amdgpu_ring_write(kiq_ring, 271 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 272 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 273 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 274 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 275 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 276 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 277 } 278 279 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 280 uint16_t pasid, uint32_t flush_type, 281 bool all_hub) 282 { 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 284 amdgpu_ring_write(kiq_ring, 285 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 286 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 287 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 288 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 289 } 290 291 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 292 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 293 uint32_t xcc_id, uint32_t vmid) 294 { 295 struct amdgpu_device *adev = kiq_ring->adev; 296 unsigned i; 297 298 /* enter save mode */ 299 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 300 mutex_lock(&adev->srbm_mutex); 301 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 302 303 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 305 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 306 /* wait till dequeue take effects */ 307 for (i = 0; i < adev->usec_timeout; i++) { 308 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 309 break; 310 udelay(1); 311 } 312 if (i >= adev->usec_timeout) 313 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 314 } else { 315 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 316 } 317 318 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 319 mutex_unlock(&adev->srbm_mutex); 320 /* exit safe mode */ 321 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 322 } 323 324 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 325 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 326 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 327 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 328 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 329 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 330 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 331 .set_resources_size = 8, 332 .map_queues_size = 7, 333 .unmap_queues_size = 6, 334 .query_status_size = 7, 335 .invalidate_tlbs_size = 2, 336 }; 337 338 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 339 { 340 int i, num_xcc; 341 342 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 343 for (i = 0; i < num_xcc; i++) 344 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 345 } 346 347 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 348 { 349 int i, num_xcc, dev_inst; 350 351 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 352 for (i = 0; i < num_xcc; i++) { 353 dev_inst = GET_INST(GC, i); 354 355 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 356 GOLDEN_GB_ADDR_CONFIG); 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 358 } 359 } 360 361 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 362 { 363 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 364 365 /* If it is an XCC reg, normalize the reg to keep 366 lower 16 bits in local xcc */ 367 368 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 369 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 370 return normalized_reg; 371 else 372 return reg; 373 } 374 375 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 376 bool wc, uint32_t reg, uint32_t val) 377 { 378 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 379 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 380 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 381 WRITE_DATA_DST_SEL(0) | 382 (wc ? WR_CONFIRM : 0)); 383 amdgpu_ring_write(ring, reg); 384 amdgpu_ring_write(ring, 0); 385 amdgpu_ring_write(ring, val); 386 } 387 388 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 389 int mem_space, int opt, uint32_t addr0, 390 uint32_t addr1, uint32_t ref, uint32_t mask, 391 uint32_t inv) 392 { 393 /* Only do the normalization on regspace */ 394 if (mem_space == 0) { 395 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 396 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 397 } 398 399 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 400 amdgpu_ring_write(ring, 401 /* memory (1) or register (0) */ 402 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 403 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 404 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 405 WAIT_REG_MEM_ENGINE(eng_sel))); 406 407 if (mem_space) 408 WARN_ON(addr0 & 0x3); /* Dword align */ 409 amdgpu_ring_write(ring, addr0); 410 amdgpu_ring_write(ring, addr1); 411 amdgpu_ring_write(ring, ref); 412 amdgpu_ring_write(ring, mask); 413 amdgpu_ring_write(ring, inv); /* poll interval */ 414 } 415 416 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 417 { 418 uint32_t scratch_reg0_offset, xcc_offset; 419 struct amdgpu_device *adev = ring->adev; 420 uint32_t tmp = 0; 421 unsigned i; 422 int r; 423 424 /* Use register offset which is local to XCC in the packet */ 425 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 426 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 427 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 428 tmp = RREG32(scratch_reg0_offset); 429 430 r = amdgpu_ring_alloc(ring, 3); 431 if (r) 432 return r; 433 434 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 435 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 436 amdgpu_ring_write(ring, 0xDEADBEEF); 437 amdgpu_ring_commit(ring); 438 439 for (i = 0; i < adev->usec_timeout; i++) { 440 tmp = RREG32(scratch_reg0_offset); 441 if (tmp == 0xDEADBEEF) 442 break; 443 udelay(1); 444 } 445 446 if (i >= adev->usec_timeout) 447 r = -ETIMEDOUT; 448 return r; 449 } 450 451 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 struct amdgpu_ib ib; 455 struct dma_fence *f = NULL; 456 457 unsigned index; 458 uint64_t gpu_addr; 459 uint32_t tmp; 460 long r; 461 462 r = amdgpu_device_wb_get(adev, &index); 463 if (r) 464 return r; 465 466 gpu_addr = adev->wb.gpu_addr + (index * 4); 467 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 468 memset(&ib, 0, sizeof(ib)); 469 470 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 471 if (r) 472 goto err1; 473 474 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 475 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 476 ib.ptr[2] = lower_32_bits(gpu_addr); 477 ib.ptr[3] = upper_32_bits(gpu_addr); 478 ib.ptr[4] = 0xDEADBEEF; 479 ib.length_dw = 5; 480 481 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 482 if (r) 483 goto err2; 484 485 r = dma_fence_wait_timeout(f, false, timeout); 486 if (r == 0) { 487 r = -ETIMEDOUT; 488 goto err2; 489 } else if (r < 0) { 490 goto err2; 491 } 492 493 tmp = adev->wb.wb[index]; 494 if (tmp == 0xDEADBEEF) 495 r = 0; 496 else 497 r = -EINVAL; 498 499 err2: 500 amdgpu_ib_free(&ib, NULL); 501 dma_fence_put(f); 502 err1: 503 amdgpu_device_wb_free(adev, index); 504 return r; 505 } 506 507 508 /* This value might differs per partition */ 509 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 510 { 511 uint64_t clock; 512 513 mutex_lock(&adev->gfx.gpu_clock_mutex); 514 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 515 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 516 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 517 mutex_unlock(&adev->gfx.gpu_clock_mutex); 518 519 return clock; 520 } 521 522 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 523 { 524 amdgpu_ucode_release(&adev->gfx.pfp_fw); 525 amdgpu_ucode_release(&adev->gfx.me_fw); 526 amdgpu_ucode_release(&adev->gfx.ce_fw); 527 amdgpu_ucode_release(&adev->gfx.rlc_fw); 528 amdgpu_ucode_release(&adev->gfx.mec_fw); 529 amdgpu_ucode_release(&adev->gfx.mec2_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 535 const char *chip_name) 536 { 537 int err; 538 const struct rlc_firmware_header_v2_0 *rlc_hdr; 539 uint16_t version_major; 540 uint16_t version_minor; 541 542 543 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 544 AMDGPU_UCODE_REQUIRED, 545 "amdgpu/%s_rlc.bin", chip_name); 546 if (err) 547 goto out; 548 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 549 550 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 551 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 552 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 553 out: 554 if (err) 555 amdgpu_ucode_release(&adev->gfx.rlc_fw); 556 557 return err; 558 } 559 560 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 561 const char *chip_name) 562 { 563 int err; 564 565 if (amdgpu_sriov_vf(adev)) { 566 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 567 AMDGPU_UCODE_REQUIRED, 568 "amdgpu/%s_sjt_mec.bin", chip_name); 569 570 if (err) 571 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 572 AMDGPU_UCODE_REQUIRED, 573 "amdgpu/%s_mec.bin", chip_name); 574 } else 575 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 576 AMDGPU_UCODE_REQUIRED, 577 "amdgpu/%s_mec.bin", chip_name); 578 if (err) 579 goto out; 580 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 581 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 582 583 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 584 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 585 586 out: 587 if (err) 588 amdgpu_ucode_release(&adev->gfx.mec_fw); 589 return err; 590 } 591 592 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 593 { 594 char ucode_prefix[15]; 595 int r; 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 600 if (r) 601 return r; 602 603 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 604 if (r) 605 return r; 606 607 return r; 608 } 609 610 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 611 { 612 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 613 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 614 } 615 616 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 617 { 618 int r, i, num_xcc; 619 u32 *hpd; 620 const __le32 *fw_data; 621 unsigned fw_size; 622 u32 *fw; 623 size_t mec_hpd_size; 624 625 const struct gfx_firmware_header_v1_0 *mec_hdr; 626 627 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 628 for (i = 0; i < num_xcc; i++) 629 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 630 AMDGPU_MAX_COMPUTE_QUEUES); 631 632 /* take ownership of the relevant compute queues */ 633 amdgpu_gfx_compute_queue_acquire(adev); 634 mec_hpd_size = 635 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 636 if (mec_hpd_size) { 637 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 638 AMDGPU_GEM_DOMAIN_VRAM | 639 AMDGPU_GEM_DOMAIN_GTT, 640 &adev->gfx.mec.hpd_eop_obj, 641 &adev->gfx.mec.hpd_eop_gpu_addr, 642 (void **)&hpd); 643 if (r) { 644 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 645 gfx_v9_4_3_mec_fini(adev); 646 return r; 647 } 648 649 if (amdgpu_emu_mode == 1) { 650 for (i = 0; i < mec_hpd_size / 4; i++) { 651 memset((void *)(hpd + i), 0, 4); 652 if (i % 50 == 0) 653 msleep(1); 654 } 655 } else { 656 memset(hpd, 0, mec_hpd_size); 657 } 658 659 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 660 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 661 } 662 663 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 664 665 fw_data = (const __le32 *) 666 (adev->gfx.mec_fw->data + 667 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 668 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 669 670 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 671 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 672 &adev->gfx.mec.mec_fw_obj, 673 &adev->gfx.mec.mec_fw_gpu_addr, 674 (void **)&fw); 675 if (r) { 676 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 677 gfx_v9_4_3_mec_fini(adev); 678 return r; 679 } 680 681 memcpy(fw, fw_data, fw_size); 682 683 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 684 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 685 686 return 0; 687 } 688 689 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 690 u32 sh_num, u32 instance, int xcc_id) 691 { 692 u32 data; 693 694 if (instance == 0xffffffff) 695 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 696 INSTANCE_BROADCAST_WRITES, 1); 697 else 698 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 699 INSTANCE_INDEX, instance); 700 701 if (se_num == 0xffffffff) 702 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 703 SE_BROADCAST_WRITES, 1); 704 else 705 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 706 707 if (sh_num == 0xffffffff) 708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 709 SH_BROADCAST_WRITES, 1); 710 else 711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 712 713 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 714 } 715 716 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 717 { 718 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 719 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 720 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 721 (address << SQ_IND_INDEX__INDEX__SHIFT) | 722 (SQ_IND_INDEX__FORCE_READ_MASK)); 723 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 724 } 725 726 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 727 uint32_t wave, uint32_t thread, 728 uint32_t regno, uint32_t num, uint32_t *out) 729 { 730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 731 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 732 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 733 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 734 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 735 (SQ_IND_INDEX__FORCE_READ_MASK) | 736 (SQ_IND_INDEX__AUTO_INCR_MASK)); 737 while (num--) 738 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 739 } 740 741 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 742 uint32_t xcc_id, uint32_t simd, uint32_t wave, 743 uint32_t *dst, int *no_fields) 744 { 745 /* type 1 wave data */ 746 dst[(*no_fields)++] = 1; 747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 761 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 762 } 763 764 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 765 uint32_t wave, uint32_t start, 766 uint32_t size, uint32_t *dst) 767 { 768 wave_read_regs(adev, xcc_id, simd, wave, 0, 769 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 770 } 771 772 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 773 uint32_t wave, uint32_t thread, 774 uint32_t start, uint32_t size, 775 uint32_t *dst) 776 { 777 wave_read_regs(adev, xcc_id, simd, wave, thread, 778 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 779 } 780 781 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 782 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 783 { 784 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 785 } 786 787 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 788 { 789 u32 xcp_ctl; 790 791 /* Value is expected to be the same on all, fetch from first instance */ 792 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 793 794 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 795 } 796 797 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 798 int num_xccs_per_xcp) 799 { 800 int ret, i, num_xcc; 801 u32 tmp = 0; 802 803 if (adev->psp.funcs) { 804 ret = psp_spatial_partition(&adev->psp, 805 NUM_XCC(adev->gfx.xcc_mask) / 806 num_xccs_per_xcp); 807 if (ret) 808 return ret; 809 } else { 810 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 811 812 for (i = 0; i < num_xcc; i++) { 813 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 814 num_xccs_per_xcp); 815 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 816 i % num_xccs_per_xcp); 817 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 818 tmp); 819 } 820 ret = 0; 821 } 822 823 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 824 825 return ret; 826 } 827 828 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 829 { 830 int xcc; 831 832 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 833 if (!xcc) { 834 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 835 return -EINVAL; 836 } 837 838 return xcc - 1; 839 } 840 841 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 842 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 843 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 844 .read_wave_data = &gfx_v9_4_3_read_wave_data, 845 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 846 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 847 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 848 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 849 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 850 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 851 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 852 }; 853 854 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 855 struct aca_bank *bank, enum aca_smu_type type, 856 void *data) 857 { 858 struct aca_bank_info info; 859 u64 misc0; 860 u32 instlo; 861 int ret; 862 863 ret = aca_bank_info_decode(bank, &info); 864 if (ret) 865 return ret; 866 867 /* NOTE: overwrite info.die_id with xcd id for gfx */ 868 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 869 instlo &= GENMASK(31, 1); 870 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 871 872 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 873 874 switch (type) { 875 case ACA_SMU_TYPE_UE: 876 bank->aca_err_type = ACA_ERROR_TYPE_UE; 877 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL); 878 break; 879 case ACA_SMU_TYPE_CE: 880 bank->aca_err_type = ACA_ERROR_TYPE_CE; 881 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 882 ACA_REG__MISC0__ERRCNT(misc0)); 883 break; 884 default: 885 return -EINVAL; 886 } 887 888 return ret; 889 } 890 891 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 892 enum aca_smu_type type, void *data) 893 { 894 u32 instlo; 895 896 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 897 instlo &= GENMASK(31, 1); 898 switch (instlo) { 899 case mmSMNAID_XCD0_MCA_SMU: 900 case mmSMNAID_XCD1_MCA_SMU: 901 case mmSMNXCD_XCD0_MCA_SMU: 902 return true; 903 default: 904 break; 905 } 906 907 return false; 908 } 909 910 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 911 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 912 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 913 }; 914 915 static const struct aca_info gfx_v9_4_3_aca_info = { 916 .hwip = ACA_HWIP_TYPE_SMU, 917 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 918 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 919 }; 920 921 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 922 { 923 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 924 adev->gfx.ras = &gfx_v9_4_3_ras; 925 926 adev->gfx.config.max_hw_contexts = 8; 927 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 928 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 929 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 930 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 931 adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG; 932 933 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 934 REG_GET_FIELD( 935 adev->gfx.config.gb_addr_config, 936 GB_ADDR_CONFIG, 937 NUM_PIPES); 938 939 adev->gfx.config.max_tile_pipes = 940 adev->gfx.config.gb_addr_config_fields.num_pipes; 941 942 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 943 REG_GET_FIELD( 944 adev->gfx.config.gb_addr_config, 945 GB_ADDR_CONFIG, 946 NUM_BANKS); 947 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 948 REG_GET_FIELD( 949 adev->gfx.config.gb_addr_config, 950 GB_ADDR_CONFIG, 951 MAX_COMPRESSED_FRAGS); 952 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 953 REG_GET_FIELD( 954 adev->gfx.config.gb_addr_config, 955 GB_ADDR_CONFIG, 956 NUM_RB_PER_SE); 957 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 958 REG_GET_FIELD( 959 adev->gfx.config.gb_addr_config, 960 GB_ADDR_CONFIG, 961 NUM_SHADER_ENGINES); 962 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 963 REG_GET_FIELD( 964 adev->gfx.config.gb_addr_config, 965 GB_ADDR_CONFIG, 966 PIPE_INTERLEAVE_SIZE)); 967 968 return 0; 969 } 970 971 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 972 int xcc_id, int mec, int pipe, int queue) 973 { 974 unsigned irq_type; 975 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 976 unsigned int hw_prio; 977 uint32_t xcc_doorbell_start; 978 979 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 980 ring_id]; 981 982 /* mec0 is me1 */ 983 ring->xcc_id = xcc_id; 984 ring->me = mec + 1; 985 ring->pipe = pipe; 986 ring->queue = queue; 987 988 ring->ring_obj = NULL; 989 ring->use_doorbell = true; 990 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 991 xcc_id * adev->doorbell_index.xcc_doorbell_range; 992 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 993 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 994 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 995 GFX9_MEC_HPD_SIZE; 996 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 997 sprintf(ring->name, "comp_%d.%d.%d.%d", 998 ring->xcc_id, ring->me, ring->pipe, ring->queue); 999 1000 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1001 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1002 + ring->pipe; 1003 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1004 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1005 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1006 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1007 hw_prio, NULL); 1008 } 1009 1010 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1011 { 1012 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1013 uint32_t *ptr, num_xcc, inst; 1014 1015 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1016 1017 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1018 if (!ptr) { 1019 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1020 adev->gfx.ip_dump_core = NULL; 1021 } else { 1022 adev->gfx.ip_dump_core = ptr; 1023 } 1024 1025 /* Allocate memory for compute queue registers for all the instances */ 1026 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1027 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1028 adev->gfx.mec.num_queue_per_pipe; 1029 1030 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1031 if (!ptr) { 1032 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1033 adev->gfx.ip_dump_compute_queues = NULL; 1034 } else { 1035 adev->gfx.ip_dump_compute_queues = ptr; 1036 } 1037 } 1038 1039 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1040 { 1041 int i, j, k, r, ring_id, xcc_id, num_xcc; 1042 struct amdgpu_device *adev = ip_block->adev; 1043 1044 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1045 case IP_VERSION(9, 4, 3): 1046 case IP_VERSION(9, 4, 4): 1047 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1048 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1049 if (adev->gfx.mec_fw_version >= 153) { 1050 adev->gfx.enable_cleaner_shader = true; 1051 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1052 if (r) { 1053 adev->gfx.enable_cleaner_shader = false; 1054 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1055 } 1056 } 1057 break; 1058 default: 1059 adev->gfx.enable_cleaner_shader = false; 1060 break; 1061 } 1062 1063 adev->gfx.mec.num_mec = 2; 1064 adev->gfx.mec.num_pipe_per_mec = 4; 1065 adev->gfx.mec.num_queue_per_pipe = 8; 1066 1067 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1068 1069 /* EOP Event */ 1070 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1071 if (r) 1072 return r; 1073 1074 /* Bad opcode Event */ 1075 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1076 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1077 &adev->gfx.bad_op_irq); 1078 if (r) 1079 return r; 1080 1081 /* Privileged reg */ 1082 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1083 &adev->gfx.priv_reg_irq); 1084 if (r) 1085 return r; 1086 1087 /* Privileged inst */ 1088 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1089 &adev->gfx.priv_inst_irq); 1090 if (r) 1091 return r; 1092 1093 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1094 1095 r = adev->gfx.rlc.funcs->init(adev); 1096 if (r) { 1097 DRM_ERROR("Failed to init rlc BOs!\n"); 1098 return r; 1099 } 1100 1101 r = gfx_v9_4_3_mec_init(adev); 1102 if (r) { 1103 DRM_ERROR("Failed to init MEC BOs!\n"); 1104 return r; 1105 } 1106 1107 /* set up the compute queues - allocate horizontally across pipes */ 1108 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1109 ring_id = 0; 1110 if (!adev->gfx.disable_kq) { 1111 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1112 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1113 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1114 k++) { 1115 if (!amdgpu_gfx_is_mec_queue_enabled( 1116 adev, xcc_id, i, k, j)) 1117 continue; 1118 1119 r = gfx_v9_4_3_compute_ring_init(adev, 1120 ring_id, 1121 xcc_id, 1122 i, k, j); 1123 if (r) 1124 return r; 1125 1126 ring_id++; 1127 } 1128 } 1129 } 1130 } 1131 1132 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1133 if (r) { 1134 DRM_ERROR("Failed to init KIQ BOs!\n"); 1135 return r; 1136 } 1137 1138 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1139 if (r) 1140 return r; 1141 1142 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1143 r = amdgpu_gfx_mqd_sw_init(adev, 1144 sizeof(struct v9_mqd_allocation), xcc_id); 1145 if (r) 1146 return r; 1147 } 1148 1149 adev->gfx.compute_supported_reset = 1150 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1151 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1152 case IP_VERSION(9, 4, 3): 1153 case IP_VERSION(9, 4, 4): 1154 if ((adev->gfx.mec_fw_version >= 155) && 1155 !amdgpu_sriov_vf(adev) && 1156 !adev->debug_disable_gpu_ring_reset) { 1157 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1158 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1159 } 1160 break; 1161 case IP_VERSION(9, 5, 0): 1162 if ((adev->gfx.mec_fw_version >= 21) && 1163 !amdgpu_sriov_vf(adev) && 1164 !adev->debug_disable_gpu_ring_reset) { 1165 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1166 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1167 } 1168 break; 1169 default: 1170 break; 1171 } 1172 r = gfx_v9_4_3_gpu_early_init(adev); 1173 if (r) 1174 return r; 1175 1176 r = amdgpu_gfx_ras_sw_init(adev); 1177 if (r) 1178 return r; 1179 1180 r = amdgpu_gfx_sysfs_init(adev); 1181 if (r) 1182 return r; 1183 1184 gfx_v9_4_3_alloc_ip_dump(adev); 1185 1186 return 0; 1187 } 1188 1189 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1190 { 1191 int i, num_xcc; 1192 struct amdgpu_device *adev = ip_block->adev; 1193 1194 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1195 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1196 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1197 1198 for (i = 0; i < num_xcc; i++) { 1199 amdgpu_gfx_mqd_sw_fini(adev, i); 1200 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1201 amdgpu_gfx_kiq_fini(adev, i); 1202 } 1203 1204 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1205 1206 gfx_v9_4_3_mec_fini(adev); 1207 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1208 gfx_v9_4_3_free_microcode(adev); 1209 amdgpu_gfx_sysfs_fini(adev); 1210 1211 kfree(adev->gfx.ip_dump_core); 1212 kfree(adev->gfx.ip_dump_compute_queues); 1213 1214 return 0; 1215 } 1216 1217 #define DEFAULT_SH_MEM_BASES (0x6000) 1218 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1219 int xcc_id) 1220 { 1221 int i; 1222 uint32_t sh_mem_config; 1223 uint32_t sh_mem_bases; 1224 uint32_t data; 1225 1226 /* 1227 * Configure apertures: 1228 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1229 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1230 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1231 */ 1232 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1233 1234 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1235 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1236 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1237 1238 mutex_lock(&adev->srbm_mutex); 1239 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1240 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1241 /* CP and shaders */ 1242 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1243 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1244 1245 /* Enable trap for each kfd vmid. */ 1246 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1247 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1248 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1249 } 1250 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1251 mutex_unlock(&adev->srbm_mutex); 1252 1253 /* 1254 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1255 * access. These should be enabled by FW for target VMIDs. 1256 */ 1257 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1258 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1259 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1260 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1261 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1262 } 1263 } 1264 1265 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1266 { 1267 int vmid; 1268 1269 /* 1270 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1271 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1272 * the driver can enable them for graphics. VMID0 should maintain 1273 * access so that HWS firmware can save/restore entries. 1274 */ 1275 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1276 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1277 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1278 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1279 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1280 } 1281 } 1282 1283 /* For ASICs that needs xnack chain and MEC version supports, set SG_CONFIG1 1284 * DISABLE_XNACK_CHECK_IN_RETRY_DISABLE bit and inform KFD to set xnack_chain 1285 * bit in SET_RESOURCES 1286 */ 1287 static void gfx_v9_4_3_xcc_init_sq(struct amdgpu_device *adev, int xcc_id) 1288 { 1289 uint32_t data; 1290 1291 if (!(adev->gmc.xnack_flags & AMDGPU_GMC_XNACK_FLAG_CHAIN)) 1292 return; 1293 1294 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1); 1295 data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1); 1296 WREG32_SOC15(GC, xcc_id, regSQ_CONFIG1, data); 1297 } 1298 1299 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1300 int xcc_id) 1301 { 1302 u32 tmp; 1303 int i; 1304 1305 /* XXX SH_MEM regs */ 1306 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1307 mutex_lock(&adev->srbm_mutex); 1308 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1309 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1310 /* CP and shaders */ 1311 if (i == 0) { 1312 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1313 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1314 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1315 !!adev->gmc.noretry); 1316 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1317 regSH_MEM_CONFIG, tmp); 1318 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1319 regSH_MEM_BASES, 0); 1320 } else { 1321 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1322 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1323 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1324 !!adev->gmc.noretry); 1325 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1326 regSH_MEM_CONFIG, tmp); 1327 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1328 (adev->gmc.private_aperture_start >> 1329 48)); 1330 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1331 (adev->gmc.shared_aperture_start >> 1332 48)); 1333 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1334 regSH_MEM_BASES, tmp); 1335 } 1336 } 1337 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1338 1339 mutex_unlock(&adev->srbm_mutex); 1340 1341 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1342 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1343 gfx_v9_4_3_xcc_init_sq(adev, xcc_id); 1344 } 1345 1346 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1347 { 1348 int i, num_xcc; 1349 1350 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1351 1352 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1353 adev->gfx.config.db_debug2 = 1354 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1355 1356 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1357 /* ToDo: GC 9.4.4 */ 1358 case IP_VERSION(9, 4, 3): 1359 if (adev->gfx.mec_fw_version >= 184 && 1360 (amdgpu_sriov_reg_access_sq_config(adev) || 1361 !amdgpu_sriov_vf(adev))) 1362 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1363 break; 1364 case IP_VERSION(9, 5, 0): 1365 if (adev->gfx.mec_fw_version >= 23) 1366 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 for (i = 0; i < num_xcc; i++) 1373 gfx_v9_4_3_xcc_constants_init(adev, i); 1374 } 1375 1376 static void 1377 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1378 int xcc_id) 1379 { 1380 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1381 } 1382 1383 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1384 { 1385 /* 1386 * Rlc save restore list is workable since v2_1. 1387 */ 1388 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1389 } 1390 1391 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1392 { 1393 uint32_t data; 1394 1395 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1396 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1397 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1398 } 1399 1400 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1401 { 1402 uint32_t rlc_setting; 1403 1404 /* if RLC is not enabled, do nothing */ 1405 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1406 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1407 return false; 1408 1409 return true; 1410 } 1411 1412 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1413 { 1414 uint32_t data; 1415 unsigned i; 1416 1417 data = RLC_SAFE_MODE__CMD_MASK; 1418 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1419 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1420 1421 /* wait for RLC_SAFE_MODE */ 1422 for (i = 0; i < adev->usec_timeout; i++) { 1423 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1424 break; 1425 udelay(1); 1426 } 1427 } 1428 1429 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1430 int xcc_id) 1431 { 1432 uint32_t data; 1433 1434 data = RLC_SAFE_MODE__CMD_MASK; 1435 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1436 } 1437 1438 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1439 { 1440 int xcc_id, num_xcc; 1441 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1442 1443 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1444 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1445 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1446 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1447 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1448 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1449 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1450 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1451 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1452 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1453 } 1454 adev->gfx.rlc.rlcg_reg_access_supported = true; 1455 } 1456 1457 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1458 { 1459 /* init spm vmid with 0xf */ 1460 if (adev->gfx.rlc.funcs->update_spm_vmid) 1461 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 1462 1463 return 0; 1464 } 1465 1466 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1467 int xcc_id) 1468 { 1469 u32 i, j, k; 1470 u32 mask; 1471 1472 mutex_lock(&adev->grbm_idx_mutex); 1473 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1474 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1475 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1476 xcc_id); 1477 for (k = 0; k < adev->usec_timeout; k++) { 1478 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1479 break; 1480 udelay(1); 1481 } 1482 if (k == adev->usec_timeout) { 1483 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1484 0xffffffff, 1485 0xffffffff, xcc_id); 1486 mutex_unlock(&adev->grbm_idx_mutex); 1487 drm_info(adev_to_drm(adev), "Timeout wait for RLC serdes %u,%u\n", 1488 i, j); 1489 return; 1490 } 1491 } 1492 } 1493 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1494 xcc_id); 1495 mutex_unlock(&adev->grbm_idx_mutex); 1496 1497 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1498 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1499 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1500 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1501 for (k = 0; k < adev->usec_timeout; k++) { 1502 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1503 break; 1504 udelay(1); 1505 } 1506 } 1507 1508 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1509 bool enable, int xcc_id) 1510 { 1511 u32 tmp; 1512 1513 /* These interrupts should be enabled to drive DS clock */ 1514 1515 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1516 1517 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1518 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1519 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1520 1521 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1522 } 1523 1524 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1525 { 1526 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1527 RLC_ENABLE_F32, 0); 1528 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1529 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1530 } 1531 1532 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1533 { 1534 int i, num_xcc; 1535 1536 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1537 for (i = 0; i < num_xcc; i++) 1538 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1539 } 1540 1541 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1542 { 1543 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1544 SOFT_RESET_RLC, 1); 1545 udelay(50); 1546 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1547 SOFT_RESET_RLC, 0); 1548 udelay(50); 1549 } 1550 1551 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1552 { 1553 int i, num_xcc; 1554 1555 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1556 for (i = 0; i < num_xcc; i++) 1557 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1558 } 1559 1560 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1561 { 1562 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1563 RLC_ENABLE_F32, 1); 1564 udelay(50); 1565 1566 /* carrizo do enable cp interrupt after cp inited */ 1567 if (!(adev->flags & AMD_IS_APU)) { 1568 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1569 udelay(50); 1570 } 1571 } 1572 1573 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1574 { 1575 #ifdef AMDGPU_RLC_DEBUG_RETRY 1576 u32 rlc_ucode_ver; 1577 #endif 1578 int i, num_xcc; 1579 1580 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1581 for (i = 0; i < num_xcc; i++) { 1582 gfx_v9_4_3_xcc_rlc_start(adev, i); 1583 #ifdef AMDGPU_RLC_DEBUG_RETRY 1584 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1585 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1586 if (rlc_ucode_ver == 0x108) { 1587 dev_info(adev->dev, 1588 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i\n", 1589 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1590 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1591 * default is 0x9C4 to create a 100us interval */ 1592 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1593 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1594 * to disable the page fault retry interrupts, default is 1595 * 0x100 (256) */ 1596 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1597 } 1598 #endif 1599 } 1600 } 1601 1602 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1603 int xcc_id) 1604 { 1605 const struct rlc_firmware_header_v2_0 *hdr; 1606 const __le32 *fw_data; 1607 unsigned i, fw_size; 1608 1609 if (!adev->gfx.rlc_fw) 1610 return -EINVAL; 1611 1612 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1613 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1614 1615 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1616 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1617 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1618 1619 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1620 RLCG_UCODE_LOADING_START_ADDRESS); 1621 for (i = 0; i < fw_size; i++) { 1622 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1623 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1624 msleep(1); 1625 } 1626 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1627 } 1628 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1629 1630 return 0; 1631 } 1632 1633 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1634 { 1635 int r; 1636 1637 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1638 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1639 /* legacy rlc firmware loading */ 1640 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1641 if (r) 1642 return r; 1643 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1644 } 1645 1646 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1647 /* disable CG */ 1648 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1649 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1650 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1651 1652 return 0; 1653 } 1654 1655 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1656 { 1657 int r, i, num_xcc; 1658 1659 if (amdgpu_sriov_vf(adev)) 1660 return 0; 1661 1662 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1663 for (i = 0; i < num_xcc; i++) { 1664 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1665 if (r) 1666 return r; 1667 } 1668 1669 return 0; 1670 } 1671 1672 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1673 int inst, struct amdgpu_ring *ring, unsigned int vmid) 1674 { 1675 u32 reg, pre_data, data; 1676 1677 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL); 1678 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1679 pre_data = RREG32_NO_KIQ(reg); 1680 else 1681 pre_data = RREG32(reg); 1682 1683 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1684 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1685 1686 if (pre_data != data) { 1687 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1688 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1689 } else 1690 WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1691 } 1692 } 1693 1694 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1695 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1696 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1697 }; 1698 1699 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1700 uint32_t offset, 1701 struct soc15_reg_rlcg *entries, int arr_size) 1702 { 1703 int i, inst; 1704 uint32_t reg; 1705 1706 if (!entries) 1707 return false; 1708 1709 for (i = 0; i < arr_size; i++) { 1710 const struct soc15_reg_rlcg *entry; 1711 1712 entry = &entries[i]; 1713 inst = adev->ip_map.logical_to_dev_inst ? 1714 adev->ip_map.logical_to_dev_inst( 1715 adev, entry->hwip, entry->instance) : 1716 entry->instance; 1717 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1718 entry->reg; 1719 if (offset == reg) 1720 return true; 1721 } 1722 1723 return false; 1724 } 1725 1726 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1727 { 1728 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1729 (void *)rlcg_access_gc_9_4_3, 1730 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1731 } 1732 1733 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1734 bool enable, int xcc_id) 1735 { 1736 if (enable) { 1737 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1738 } else { 1739 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1740 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1741 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1742 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1743 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1744 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1745 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1746 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1747 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1748 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1749 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1750 } 1751 udelay(50); 1752 } 1753 1754 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1755 int xcc_id) 1756 { 1757 const struct gfx_firmware_header_v1_0 *mec_hdr; 1758 const __le32 *fw_data; 1759 unsigned i; 1760 u32 tmp; 1761 u32 mec_ucode_addr_offset; 1762 u32 mec_ucode_data_offset; 1763 1764 if (!adev->gfx.mec_fw) 1765 return -EINVAL; 1766 1767 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1768 1769 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1770 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1771 1772 fw_data = (const __le32 *) 1773 (adev->gfx.mec_fw->data + 1774 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1775 tmp = 0; 1776 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1777 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1778 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1779 1780 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1781 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1782 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1783 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1784 1785 mec_ucode_addr_offset = 1786 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1787 mec_ucode_data_offset = 1788 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1789 1790 /* MEC1 */ 1791 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1792 for (i = 0; i < mec_hdr->jt_size; i++) 1793 WREG32(mec_ucode_data_offset, 1794 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1795 1796 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1797 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1798 1799 return 0; 1800 } 1801 1802 /* KIQ functions */ 1803 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1804 { 1805 uint32_t tmp; 1806 struct amdgpu_device *adev = ring->adev; 1807 1808 /* tell RLC which is KIQ queue */ 1809 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1810 tmp &= 0xffffff00; 1811 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1812 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1813 } 1814 1815 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1816 { 1817 struct amdgpu_device *adev = ring->adev; 1818 1819 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1820 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1821 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1822 mqd->cp_hqd_queue_priority = 1823 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1824 } 1825 } 1826 } 1827 1828 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1829 { 1830 struct amdgpu_device *adev = ring->adev; 1831 struct v9_mqd *mqd = ring->mqd_ptr; 1832 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1833 uint32_t tmp; 1834 1835 mqd->header = 0xC0310800; 1836 mqd->compute_pipelinestat_enable = 0x00000001; 1837 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1838 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1839 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1840 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1841 mqd->compute_misc_reserved = 0x00000003; 1842 1843 mqd->dynamic_cu_mask_addr_lo = 1844 lower_32_bits(ring->mqd_gpu_addr 1845 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1846 mqd->dynamic_cu_mask_addr_hi = 1847 upper_32_bits(ring->mqd_gpu_addr 1848 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1849 1850 eop_base_addr = ring->eop_gpu_addr >> 8; 1851 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1852 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1853 1854 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1855 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1856 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1857 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1858 1859 mqd->cp_hqd_eop_control = tmp; 1860 1861 /* enable doorbell? */ 1862 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1863 1864 if (ring->use_doorbell) { 1865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1866 DOORBELL_OFFSET, ring->doorbell_index); 1867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1868 DOORBELL_EN, 1); 1869 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1870 DOORBELL_SOURCE, 0); 1871 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1872 DOORBELL_HIT, 0); 1873 if (amdgpu_sriov_multi_vf_mode(adev)) 1874 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1875 DOORBELL_MODE, 1); 1876 } else { 1877 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1878 DOORBELL_EN, 0); 1879 } 1880 1881 mqd->cp_hqd_pq_doorbell_control = tmp; 1882 1883 /* disable the queue if it's active */ 1884 ring->wptr = 0; 1885 mqd->cp_hqd_dequeue_request = 0; 1886 mqd->cp_hqd_pq_rptr = 0; 1887 mqd->cp_hqd_pq_wptr_lo = 0; 1888 mqd->cp_hqd_pq_wptr_hi = 0; 1889 1890 /* set the pointer to the MQD */ 1891 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1892 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1893 1894 /* set MQD vmid to 0 */ 1895 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1896 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1897 mqd->cp_mqd_control = tmp; 1898 1899 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1900 hqd_gpu_addr = ring->gpu_addr >> 8; 1901 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1902 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1903 1904 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1905 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1906 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1907 (order_base_2(ring->ring_size / 4) - 1)); 1908 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1909 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1910 #ifdef __BIG_ENDIAN 1911 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1912 #endif 1913 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1914 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1915 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1916 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1917 mqd->cp_hqd_pq_control = tmp; 1918 1919 /* set the wb address whether it's enabled or not */ 1920 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1921 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1922 mqd->cp_hqd_pq_rptr_report_addr_hi = 1923 upper_32_bits(wb_gpu_addr) & 0xffff; 1924 1925 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1926 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1927 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1928 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1929 1930 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1931 ring->wptr = 0; 1932 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1933 1934 /* set the vmid for the queue */ 1935 mqd->cp_hqd_vmid = 0; 1936 1937 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1938 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1939 mqd->cp_hqd_persistent_state = tmp; 1940 1941 /* set MIN_IB_AVAIL_SIZE */ 1942 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1943 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1944 mqd->cp_hqd_ib_control = tmp; 1945 1946 /* set static priority for a queue/ring */ 1947 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1948 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1949 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); 1950 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 1951 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 1952 mqd->cp_hqd_quantum = tmp; 1953 1954 /* map_queues packet doesn't need activate the queue, 1955 * so only kiq need set this field. 1956 */ 1957 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1958 mqd->cp_hqd_active = 1; 1959 1960 return 0; 1961 } 1962 1963 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1964 int xcc_id) 1965 { 1966 struct amdgpu_device *adev = ring->adev; 1967 struct v9_mqd *mqd = ring->mqd_ptr; 1968 int j; 1969 1970 /* disable wptr polling */ 1971 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1972 1973 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1974 mqd->cp_hqd_eop_base_addr_lo); 1975 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1976 mqd->cp_hqd_eop_base_addr_hi); 1977 1978 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1979 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1980 mqd->cp_hqd_eop_control); 1981 1982 /* enable doorbell? */ 1983 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1984 mqd->cp_hqd_pq_doorbell_control); 1985 1986 /* disable the queue if it's active */ 1987 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1988 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1989 for (j = 0; j < adev->usec_timeout; j++) { 1990 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1991 break; 1992 udelay(1); 1993 } 1994 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1995 mqd->cp_hqd_dequeue_request); 1996 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1997 mqd->cp_hqd_pq_rptr); 1998 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1999 mqd->cp_hqd_pq_wptr_lo); 2000 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2001 mqd->cp_hqd_pq_wptr_hi); 2002 } 2003 2004 /* set the pointer to the MQD */ 2005 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 2006 mqd->cp_mqd_base_addr_lo); 2007 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 2008 mqd->cp_mqd_base_addr_hi); 2009 2010 /* set MQD vmid to 0 */ 2011 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 2012 mqd->cp_mqd_control); 2013 2014 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2015 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 2016 mqd->cp_hqd_pq_base_lo); 2017 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 2018 mqd->cp_hqd_pq_base_hi); 2019 2020 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2021 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 2022 mqd->cp_hqd_pq_control); 2023 2024 /* set the wb address whether it's enabled or not */ 2025 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2026 mqd->cp_hqd_pq_rptr_report_addr_lo); 2027 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2028 mqd->cp_hqd_pq_rptr_report_addr_hi); 2029 2030 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2031 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2032 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2033 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2034 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2035 2036 /* enable the doorbell if requested */ 2037 if (ring->use_doorbell) { 2038 WREG32_SOC15( 2039 GC, GET_INST(GC, xcc_id), 2040 regCP_MEC_DOORBELL_RANGE_LOWER, 2041 ((adev->doorbell_index.kiq + 2042 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2043 2) << 2); 2044 WREG32_SOC15( 2045 GC, GET_INST(GC, xcc_id), 2046 regCP_MEC_DOORBELL_RANGE_UPPER, 2047 ((adev->doorbell_index.userqueue_end + 2048 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2049 2) << 2); 2050 } 2051 2052 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2053 mqd->cp_hqd_pq_doorbell_control); 2054 2055 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2056 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2057 mqd->cp_hqd_pq_wptr_lo); 2058 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2059 mqd->cp_hqd_pq_wptr_hi); 2060 2061 /* set the vmid for the queue */ 2062 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2063 2064 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2065 mqd->cp_hqd_persistent_state); 2066 2067 /* activate the queue */ 2068 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2069 mqd->cp_hqd_active); 2070 2071 if (ring->use_doorbell) 2072 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2073 2074 return 0; 2075 } 2076 2077 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2078 int xcc_id) 2079 { 2080 struct amdgpu_device *adev = ring->adev; 2081 int j; 2082 2083 /* disable the queue if it's active */ 2084 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2085 2086 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2087 2088 for (j = 0; j < adev->usec_timeout; j++) { 2089 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2090 break; 2091 udelay(1); 2092 } 2093 2094 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2095 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2096 2097 /* Manual disable if dequeue request times out */ 2098 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2099 } 2100 2101 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2102 0); 2103 } 2104 2105 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2106 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2107 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2108 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2109 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2110 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2111 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2112 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2113 2114 return 0; 2115 } 2116 2117 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2118 { 2119 struct amdgpu_device *adev = ring->adev; 2120 struct v9_mqd *mqd = ring->mqd_ptr; 2121 struct v9_mqd *tmp_mqd; 2122 2123 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2124 2125 /* GPU could be in bad state during probe, driver trigger the reset 2126 * after load the SMU, in this case , the mqd is not be initialized. 2127 * driver need to re-init the mqd. 2128 * check mqd->cp_hqd_pq_control since this value should not be 0 2129 */ 2130 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2131 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2132 /* for GPU_RESET case , reset MQD to a clean status */ 2133 if (adev->gfx.kiq[xcc_id].mqd_backup) 2134 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2135 2136 /* reset ring buffer */ 2137 ring->wptr = 0; 2138 amdgpu_ring_clear_ring(ring); 2139 mutex_lock(&adev->srbm_mutex); 2140 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2141 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2142 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2143 mutex_unlock(&adev->srbm_mutex); 2144 } else { 2145 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2146 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2147 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2148 mutex_lock(&adev->srbm_mutex); 2149 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2150 amdgpu_ring_clear_ring(ring); 2151 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2152 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2153 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2154 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2155 mutex_unlock(&adev->srbm_mutex); 2156 2157 if (adev->gfx.kiq[xcc_id].mqd_backup) 2158 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2159 } 2160 2161 return 0; 2162 } 2163 2164 static void gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, 2165 bool restore) 2166 { 2167 struct amdgpu_device *adev = ring->adev; 2168 struct v9_mqd *mqd = ring->mqd_ptr; 2169 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2170 struct v9_mqd *tmp_mqd; 2171 2172 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2173 * is not be initialized before 2174 */ 2175 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2176 2177 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2178 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2179 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2180 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2181 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2182 mutex_lock(&adev->srbm_mutex); 2183 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2184 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2185 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2186 mutex_unlock(&adev->srbm_mutex); 2187 2188 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2189 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2190 } else { 2191 /* restore MQD to a clean status */ 2192 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2193 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2194 /* reset ring buffer */ 2195 ring->wptr = 0; 2196 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2197 amdgpu_ring_clear_ring(ring); 2198 } 2199 } 2200 2201 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2202 { 2203 struct amdgpu_ring *ring; 2204 int j; 2205 2206 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2207 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2208 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2209 mutex_lock(&adev->srbm_mutex); 2210 soc15_grbm_select(adev, ring->me, 2211 ring->pipe, 2212 ring->queue, 0, GET_INST(GC, xcc_id)); 2213 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2214 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2215 mutex_unlock(&adev->srbm_mutex); 2216 } 2217 } 2218 2219 return 0; 2220 } 2221 2222 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2223 { 2224 gfx_v9_4_3_xcc_kiq_init_queue(&adev->gfx.kiq[xcc_id].ring, xcc_id); 2225 return 0; 2226 } 2227 2228 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2229 { 2230 struct amdgpu_ring *ring; 2231 int i; 2232 2233 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2234 2235 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2236 ring = &adev->gfx.compute_ring[i + xcc_id * 2237 adev->gfx.num_compute_rings]; 2238 2239 gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2240 } 2241 2242 return amdgpu_gfx_enable_kcq(adev, xcc_id); 2243 } 2244 2245 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2246 { 2247 struct amdgpu_ring *ring; 2248 int r, j; 2249 2250 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2251 2252 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2253 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2254 2255 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2256 if (r) 2257 return r; 2258 } else { 2259 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2260 } 2261 2262 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2263 if (r) 2264 return r; 2265 2266 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2267 if (r) 2268 return r; 2269 2270 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2271 ring = &adev->gfx.compute_ring 2272 [j + xcc_id * adev->gfx.num_compute_rings]; 2273 r = amdgpu_ring_test_helper(ring); 2274 if (r) 2275 return r; 2276 } 2277 2278 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2279 2280 return 0; 2281 } 2282 2283 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2284 { 2285 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2286 2287 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2288 if (amdgpu_sriov_vf(adev)) { 2289 enum amdgpu_gfx_partition mode; 2290 2291 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2292 AMDGPU_XCP_FL_NONE); 2293 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2294 return -EINVAL; 2295 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2296 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2297 num_xcp = num_xcc / num_xcc_per_xcp; 2298 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2299 2300 } else { 2301 if (adev->in_suspend) 2302 amdgpu_xcp_restore_partition_mode(adev->xcp_mgr); 2303 else if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2304 AMDGPU_XCP_FL_NONE) == 2305 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2306 r = amdgpu_xcp_switch_partition_mode( 2307 adev->xcp_mgr, amdgpu_user_partt_mode); 2308 } 2309 if (r) 2310 return r; 2311 2312 for (i = 0; i < num_xcc; i++) { 2313 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2314 if (r) 2315 return r; 2316 } 2317 2318 return 0; 2319 } 2320 2321 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2322 { 2323 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2324 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2325 2326 if (amdgpu_sriov_vf(adev)) { 2327 /* must disable polling for SRIOV when hw finished, otherwise 2328 * CPC engine may still keep fetching WB address which is already 2329 * invalid after sw finished and trigger DMAR reading error in 2330 * hypervisor side. 2331 */ 2332 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2333 return; 2334 } 2335 2336 /* Use deinitialize sequence from CAIL when unbinding device 2337 * from driver, otherwise KIQ is hanging when binding back 2338 */ 2339 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2340 mutex_lock(&adev->srbm_mutex); 2341 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2342 adev->gfx.kiq[xcc_id].ring.pipe, 2343 adev->gfx.kiq[xcc_id].ring.queue, 0, 2344 GET_INST(GC, xcc_id)); 2345 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2346 xcc_id); 2347 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2348 mutex_unlock(&adev->srbm_mutex); 2349 } 2350 2351 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2352 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2353 } 2354 2355 static int gfx_v9_4_3_set_userq_eop_interrupts(struct amdgpu_device *adev, 2356 bool enable) 2357 { 2358 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2359 unsigned int irq_type; 2360 int m, p, xcc_id, r; 2361 2362 if (adev->gfx.disable_kq) { 2363 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 2364 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 2365 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 2366 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2367 + (m * adev->gfx.mec.num_pipe_per_mec) 2368 + p; 2369 2370 if (enable) 2371 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 2372 irq_type); 2373 else 2374 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 2375 irq_type); 2376 if (r) { 2377 if (!enable) 2378 return r; 2379 goto err_compute; 2380 } 2381 } 2382 } 2383 } 2384 } 2385 2386 return 0; 2387 2388 err_compute: 2389 for (p--; p >= 0; p--) { 2390 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2391 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2392 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2393 } 2394 for (m--; m >= 0; m--) { 2395 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 2396 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2397 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2398 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2399 } 2400 } 2401 for (xcc_id--; xcc_id >= 0; xcc_id--) { 2402 for (m = adev->gfx.mec.num_mec - 1; m <= 0; m--) { 2403 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 2404 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2405 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2406 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2407 } 2408 } 2409 } 2410 2411 return r; 2412 } 2413 2414 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2415 { 2416 int r; 2417 struct amdgpu_device *adev = ip_block->adev; 2418 2419 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2420 adev->gfx.cleaner_shader_ptr); 2421 2422 if (!amdgpu_sriov_vf(adev)) 2423 gfx_v9_4_3_init_golden_registers(adev); 2424 2425 gfx_v9_4_3_constants_init(adev); 2426 2427 r = adev->gfx.rlc.funcs->resume(adev); 2428 if (r) 2429 return r; 2430 2431 r = gfx_v9_4_3_cp_resume(adev); 2432 if (r) 2433 return r; 2434 2435 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2436 if (r) 2437 return r; 2438 2439 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2440 if (r) 2441 goto err_priv_inst; 2442 2443 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2444 if (r) 2445 goto err_bad_op; 2446 r = gfx_v9_4_3_set_userq_eop_interrupts(adev, true); 2447 if (r) 2448 goto err_bad_eop; 2449 2450 return 0; 2451 2452 err_bad_eop: 2453 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2454 err_bad_op: 2455 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2456 err_priv_inst: 2457 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2458 return r; 2459 } 2460 2461 static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool enable) 2462 { 2463 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2464 uint32_t ptl_state = enable ? 1 : 0; 2465 uint32_t fmt1, fmt2; 2466 int r; 2467 2468 if (!adev->psp.funcs) 2469 return -EOPNOTSUPP; 2470 2471 if (!ptl->hw_supported) { 2472 fmt1 = GFX_FTYPE_VECTOR; 2473 fmt2 = GFX_FTYPE_F8; 2474 } else { 2475 fmt1 = ptl->fmt1; 2476 fmt2 = ptl->fmt2; 2477 } 2478 2479 /* initialize PTL with default formats: GFX_FTYPE_VECTOR & GFX_FTYPE_F8 */ 2480 r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, 2481 &fmt1, &fmt2); 2482 if (r) 2483 return r; 2484 2485 ptl->hw_supported = true; 2486 2487 atomic_set(&ptl->disable_ref, 0); 2488 if (!enable && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2489 dev_dbg(adev->dev, 2490 "PTL disabled (amdgpu.ptl=%d)\ 2491 To enable, set amdgpu.ptl=1 via module param or kernel cmdline\n", 2492 amdgpu_ptl); 2493 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 2494 } 2495 2496 return 0; 2497 } 2498 2499 static int gfx_v9_4_3_ptl_hw_init(struct amdgpu_device *adev) 2500 { 2501 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2502 bool enable; 2503 2504 switch (amdgpu_ptl) { 2505 case 1: 2506 enable = true; 2507 break; 2508 case 2: 2509 /* Permanently disabled - cannot be re-enabled */ 2510 enable = false; 2511 ptl->permanently_disabled = true; 2512 break; 2513 case -1: 2514 case 0: 2515 default: 2516 enable = false; 2517 break; 2518 } 2519 2520 gfx_v9_4_3_perf_monitor_ptl_init(adev, enable ? 1 : 0); 2521 2522 return 0; 2523 } 2524 2525 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2526 { 2527 struct amdgpu_device *adev = ip_block->adev; 2528 int i, num_xcc; 2529 2530 if (adev->psp.ptl.hw_supported && !amdgpu_in_reset(adev)) 2531 gfx_v9_4_3_perf_monitor_ptl_init(adev, false); 2532 2533 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2534 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2535 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2536 gfx_v9_4_3_set_userq_eop_interrupts(adev, false); 2537 2538 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2539 for (i = 0; i < num_xcc; i++) { 2540 gfx_v9_4_3_xcc_fini(adev, i); 2541 } 2542 2543 return 0; 2544 } 2545 2546 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2547 { 2548 return gfx_v9_4_3_hw_fini(ip_block); 2549 } 2550 2551 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2552 { 2553 return gfx_v9_4_3_hw_init(ip_block); 2554 } 2555 2556 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2557 { 2558 struct amdgpu_device *adev = ip_block->adev; 2559 int i, num_xcc; 2560 u32 gc_ip_version; 2561 2562 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2563 gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 2564 2565 for (i = 0; i < num_xcc; i++) { 2566 if (gc_ip_version == IP_VERSION(9, 4, 4)) { 2567 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2568 GRBM_STATUS, SPI_BUSY)) 2569 return false; 2570 } else { 2571 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2572 GRBM_STATUS, GUI_ACTIVE)) 2573 return false; 2574 } 2575 } 2576 return true; 2577 } 2578 2579 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2580 { 2581 unsigned i; 2582 struct amdgpu_device *adev = ip_block->adev; 2583 2584 for (i = 0; i < adev->usec_timeout; i++) { 2585 if (gfx_v9_4_3_is_idle(ip_block)) 2586 return 0; 2587 udelay(1); 2588 } 2589 return -ETIMEDOUT; 2590 } 2591 2592 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2593 { 2594 u32 grbm_soft_reset = 0; 2595 u32 tmp; 2596 struct amdgpu_device *adev = ip_block->adev; 2597 2598 /* GRBM_STATUS */ 2599 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2600 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2601 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2602 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2603 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2604 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2605 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2606 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2607 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2608 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2609 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2610 } 2611 2612 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2613 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2614 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2615 } 2616 2617 /* GRBM_STATUS2 */ 2618 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2619 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2620 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2621 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2622 2623 2624 if (grbm_soft_reset) { 2625 /* stop the rlc */ 2626 adev->gfx.rlc.funcs->stop(adev); 2627 2628 /* Disable MEC parsing/prefetching */ 2629 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2630 2631 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2632 tmp |= grbm_soft_reset; 2633 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2634 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2635 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2636 2637 udelay(50); 2638 2639 tmp &= ~grbm_soft_reset; 2640 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2641 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2642 2643 /* Wait a little for things to settle down */ 2644 udelay(50); 2645 } 2646 return 0; 2647 } 2648 2649 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2650 uint32_t vmid, 2651 uint32_t gds_base, uint32_t gds_size, 2652 uint32_t gws_base, uint32_t gws_size, 2653 uint32_t oa_base, uint32_t oa_size) 2654 { 2655 struct amdgpu_device *adev = ring->adev; 2656 2657 /* GDS Base */ 2658 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2659 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2660 gds_base); 2661 2662 /* GDS Size */ 2663 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2664 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2665 gds_size); 2666 2667 /* GWS */ 2668 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2669 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2670 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2671 2672 /* OA */ 2673 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2674 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2675 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2676 } 2677 2678 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2679 { 2680 struct amdgpu_device *adev = ip_block->adev; 2681 2682 switch (amdgpu_user_queue) { 2683 case -1: 2684 case 0: 2685 default: 2686 adev->gfx.disable_kq = false; 2687 adev->gfx.disable_uq = true; 2688 break; 2689 case 2: 2690 adev->gfx.disable_kq = true; 2691 adev->gfx.disable_uq = true; 2692 break; 2693 } 2694 2695 if (adev->gfx.disable_kq) 2696 adev->gfx.num_compute_rings = 0; 2697 else 2698 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2699 AMDGPU_MAX_COMPUTE_RINGS); 2700 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2701 gfx_v9_4_3_set_ring_funcs(adev); 2702 gfx_v9_4_3_set_irq_funcs(adev); 2703 gfx_v9_4_3_set_gds_init(adev); 2704 gfx_v9_4_3_set_rlc_funcs(adev); 2705 2706 /* init rlcg reg access ctrl */ 2707 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2708 2709 amdgpu_init_rlc_reg_funcs(adev); 2710 2711 return gfx_v9_4_3_init_microcode(adev); 2712 } 2713 2714 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2715 { 2716 struct amdgpu_device *adev = ip_block->adev; 2717 2718 if (adev->gfx.ras && 2719 adev->gfx.ras->enable_watchdog_timer) 2720 adev->gfx.ras->enable_watchdog_timer(adev); 2721 2722 gfx_v9_4_3_ptl_hw_init(adev); 2723 2724 return 0; 2725 } 2726 2727 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2728 bool enable, int xcc_id) 2729 { 2730 uint32_t def, data; 2731 2732 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2733 return; 2734 2735 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2736 regRLC_CGTT_MGCG_OVERRIDE); 2737 2738 if (enable) 2739 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2740 else 2741 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2742 2743 if (def != data) 2744 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2745 regRLC_CGTT_MGCG_OVERRIDE, data); 2746 2747 } 2748 2749 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2750 bool enable, int xcc_id) 2751 { 2752 uint32_t def, data; 2753 2754 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2755 return; 2756 2757 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2758 regRLC_CGTT_MGCG_OVERRIDE); 2759 2760 if (enable) 2761 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2762 else 2763 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2764 2765 if (def != data) 2766 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2767 regRLC_CGTT_MGCG_OVERRIDE, data); 2768 } 2769 2770 static void 2771 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2772 bool enable, int xcc_id) 2773 { 2774 uint32_t data, def; 2775 2776 /* It is disabled by HW by default */ 2777 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2778 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2779 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2780 2781 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2782 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2783 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2784 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2785 2786 if (def != data) 2787 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2788 2789 /* MGLS is a global flag to control all MGLS in GFX */ 2790 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2791 /* 2 - RLC memory Light sleep */ 2792 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2793 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2794 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2795 if (def != data) 2796 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2797 } 2798 /* 3 - CP memory Light sleep */ 2799 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2800 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2801 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2802 if (def != data) 2803 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2804 } 2805 } 2806 } else { 2807 /* 1 - MGCG_OVERRIDE */ 2808 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2809 2810 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2811 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2812 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2813 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2814 2815 if (def != data) 2816 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2817 2818 /* 2 - disable MGLS in RLC */ 2819 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2820 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2821 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2822 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2823 } 2824 2825 /* 3 - disable MGLS in CP */ 2826 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2827 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2828 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2829 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2830 } 2831 } 2832 2833 } 2834 2835 static void 2836 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2837 bool enable, int xcc_id) 2838 { 2839 uint32_t def, data; 2840 2841 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2842 2843 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2844 /* unset CGCG override */ 2845 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2846 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2847 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2848 else 2849 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2850 /* update CGCG and CGLS override bits */ 2851 if (def != data) 2852 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2853 2854 /* CGCG Hysteresis: 400us */ 2855 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2856 2857 data = (0x2710 2858 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2859 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2860 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2861 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2862 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2863 if (def != data) 2864 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2865 2866 /* set IDLE_POLL_COUNT(0x33450100)*/ 2867 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2868 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2869 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2870 if (def != data) 2871 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2872 } else { 2873 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2874 /* reset CGCG/CGLS bits */ 2875 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2876 /* disable cgcg and cgls in FSM */ 2877 if (def != data) 2878 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2879 } 2880 2881 } 2882 2883 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2884 bool enable, int xcc_id) 2885 { 2886 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2887 2888 if (enable) { 2889 /* FGCG */ 2890 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2891 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2892 2893 /* CGCG/CGLS should be enabled after MGCG/MGLS 2894 * === MGCG + MGLS === 2895 */ 2896 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2897 xcc_id); 2898 /* === CGCG + CGLS === */ 2899 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2900 xcc_id); 2901 } else { 2902 /* CGCG/CGLS should be disabled before MGCG/MGLS 2903 * === CGCG + CGLS === 2904 */ 2905 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2906 xcc_id); 2907 /* === MGCG + MGLS === */ 2908 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2909 xcc_id); 2910 2911 /* FGCG */ 2912 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2913 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2914 } 2915 2916 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2917 2918 return 0; 2919 } 2920 2921 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2922 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2923 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2924 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2925 .init = gfx_v9_4_3_rlc_init, 2926 .resume = gfx_v9_4_3_rlc_resume, 2927 .stop = gfx_v9_4_3_rlc_stop, 2928 .reset = gfx_v9_4_3_rlc_reset, 2929 .start = gfx_v9_4_3_rlc_start, 2930 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2931 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2932 }; 2933 2934 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2935 enum amd_powergating_state state) 2936 { 2937 return 0; 2938 } 2939 2940 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2941 enum amd_clockgating_state state) 2942 { 2943 struct amdgpu_device *adev = ip_block->adev; 2944 int i, num_xcc; 2945 2946 if (amdgpu_sriov_vf(adev)) 2947 return 0; 2948 2949 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2950 for (i = 0; i < num_xcc; i++) 2951 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2952 adev, state == AMD_CG_STATE_GATE, i); 2953 2954 return 0; 2955 } 2956 2957 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2958 { 2959 struct amdgpu_device *adev = ip_block->adev; 2960 int data; 2961 2962 if (amdgpu_sriov_vf(adev)) 2963 *flags = 0; 2964 2965 /* AMD_CG_SUPPORT_GFX_MGCG */ 2966 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2967 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2968 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2969 2970 /* AMD_CG_SUPPORT_GFX_CGCG */ 2971 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2972 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2973 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2974 2975 /* AMD_CG_SUPPORT_GFX_CGLS */ 2976 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2977 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2978 2979 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2980 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2981 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2982 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2983 2984 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2985 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2986 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2987 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2988 } 2989 2990 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2991 { 2992 struct amdgpu_device *adev = ring->adev; 2993 u32 ref_and_mask, reg_mem_engine; 2994 2995 if (!adev->gfx.funcs->get_hdp_flush_mask) { 2996 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 2997 return; 2998 } 2999 3000 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 3001 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 3002 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 3003 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 3004 ref_and_mask, ref_and_mask, 0x20); 3005 } 3006 3007 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 3008 struct amdgpu_job *job, 3009 struct amdgpu_ib *ib, 3010 uint32_t flags) 3011 { 3012 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 3013 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 3014 3015 /* Currently, there is a high possibility to get wave ID mismatch 3016 * between ME and GDS, leading to a hw deadlock, because ME generates 3017 * different wave IDs than the GDS expects. This situation happens 3018 * randomly when at least 5 compute pipes use GDS ordered append. 3019 * The wave IDs generated by ME are also wrong after suspend/resume. 3020 * Those are probably bugs somewhere else in the kernel driver. 3021 * 3022 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 3023 * GDS to 0 for this ring (me/pipe). 3024 */ 3025 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 3026 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3027 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 3028 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 3029 } 3030 3031 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3032 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 3033 amdgpu_ring_write(ring, 3034 #ifdef __BIG_ENDIAN 3035 (2 << 0) | 3036 #endif 3037 lower_32_bits(ib->gpu_addr)); 3038 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3039 amdgpu_ring_write(ring, control); 3040 } 3041 3042 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3043 u64 seq, unsigned flags) 3044 { 3045 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3046 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3047 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 3048 3049 /* RELEASE_MEM - flush caches, send int */ 3050 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3051 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 3052 EOP_TC_NC_ACTION_EN) : 3053 (EOP_TCL1_ACTION_EN | 3054 EOP_TC_ACTION_EN | 3055 EOP_TC_WB_ACTION_EN | 3056 EOP_TC_MD_ACTION_EN)) | 3057 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3058 EVENT_INDEX(5))); 3059 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 3060 3061 /* 3062 * the address should be Qword aligned if 64bit write, Dword 3063 * aligned if only send 32bit data low (discard data high) 3064 */ 3065 if (write64bit) 3066 WARN_ON(addr & 0x7); 3067 else 3068 WARN_ON(addr & 0x3); 3069 amdgpu_ring_write(ring, lower_32_bits(addr)); 3070 amdgpu_ring_write(ring, upper_32_bits(addr)); 3071 amdgpu_ring_write(ring, lower_32_bits(seq)); 3072 amdgpu_ring_write(ring, upper_32_bits(seq)); 3073 amdgpu_ring_write(ring, 0); 3074 } 3075 3076 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3077 { 3078 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3079 uint32_t seq = ring->fence_drv.sync_seq; 3080 uint64_t addr = ring->fence_drv.gpu_addr; 3081 3082 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 3083 lower_32_bits(addr), upper_32_bits(addr), 3084 seq, 0xffffffff, 4); 3085 } 3086 3087 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 3088 unsigned vmid, uint64_t pd_addr) 3089 { 3090 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3091 } 3092 3093 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 3094 { 3095 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 3096 } 3097 3098 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 3099 { 3100 u64 wptr; 3101 3102 /* XXX check if swapping is necessary on BE */ 3103 if (ring->use_doorbell) 3104 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 3105 else 3106 BUG(); 3107 return wptr; 3108 } 3109 3110 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 3111 { 3112 struct amdgpu_device *adev = ring->adev; 3113 3114 /* XXX check if swapping is necessary on BE */ 3115 if (ring->use_doorbell) { 3116 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3117 WDOORBELL64(ring->doorbell_index, ring->wptr); 3118 } else { 3119 BUG(); /* only DOORBELL method supported on gfx9 now */ 3120 } 3121 } 3122 3123 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3124 u64 seq, unsigned int flags) 3125 { 3126 struct amdgpu_device *adev = ring->adev; 3127 3128 /* write fence seq to the "addr" */ 3129 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3130 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3131 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 3132 amdgpu_ring_write(ring, lower_32_bits(addr)); 3133 amdgpu_ring_write(ring, upper_32_bits(addr)); 3134 amdgpu_ring_write(ring, lower_32_bits(seq)); 3135 3136 if (flags & AMDGPU_FENCE_FLAG_INT) { 3137 /* set register to trigger INT */ 3138 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3139 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3140 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 3141 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 3142 amdgpu_ring_write(ring, 0); 3143 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3144 } 3145 } 3146 3147 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3148 uint32_t reg_val_offs) 3149 { 3150 struct amdgpu_device *adev = ring->adev; 3151 3152 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3153 3154 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3155 amdgpu_ring_write(ring, 0 | /* src: register*/ 3156 (5 << 8) | /* dst: memory */ 3157 (1 << 20)); /* write confirm */ 3158 amdgpu_ring_write(ring, reg); 3159 amdgpu_ring_write(ring, 0); 3160 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3161 reg_val_offs * 4)); 3162 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3163 reg_val_offs * 4)); 3164 } 3165 3166 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3167 uint32_t val) 3168 { 3169 uint32_t cmd = 0; 3170 3171 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3172 3173 switch (ring->funcs->type) { 3174 case AMDGPU_RING_TYPE_GFX: 3175 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3176 break; 3177 case AMDGPU_RING_TYPE_KIQ: 3178 cmd = (1 << 16); /* no inc addr */ 3179 break; 3180 default: 3181 cmd = WR_CONFIRM; 3182 break; 3183 } 3184 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3185 amdgpu_ring_write(ring, cmd); 3186 amdgpu_ring_write(ring, reg); 3187 amdgpu_ring_write(ring, 0); 3188 amdgpu_ring_write(ring, val); 3189 } 3190 3191 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3192 uint32_t val, uint32_t mask) 3193 { 3194 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3195 } 3196 3197 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3198 uint32_t reg0, uint32_t reg1, 3199 uint32_t ref, uint32_t mask) 3200 { 3201 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3202 ref, mask); 3203 } 3204 3205 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3206 unsigned vmid) 3207 { 3208 struct amdgpu_device *adev = ring->adev; 3209 uint32_t value = 0; 3210 3211 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3212 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3213 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3214 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3215 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3216 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3217 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3218 } 3219 3220 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3221 struct amdgpu_device *adev, int me, int pipe, 3222 enum amdgpu_interrupt_state state, int xcc_id) 3223 { 3224 u32 mec_int_cntl, mec_int_cntl_reg; 3225 3226 /* 3227 * amdgpu controls only the first MEC. That's why this function only 3228 * handles the setting of interrupts for this specific MEC. All other 3229 * pipes' interrupts are set by amdkfd. 3230 */ 3231 3232 if (me == 1) { 3233 switch (pipe) { 3234 case 0: 3235 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3236 break; 3237 case 1: 3238 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3239 break; 3240 case 2: 3241 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3242 break; 3243 case 3: 3244 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3245 break; 3246 default: 3247 DRM_DEBUG("invalid pipe %d\n", pipe); 3248 return; 3249 } 3250 } else { 3251 DRM_DEBUG("invalid me %d\n", me); 3252 return; 3253 } 3254 3255 switch (state) { 3256 case AMDGPU_IRQ_STATE_DISABLE: 3257 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3258 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3259 TIME_STAMP_INT_ENABLE, 0); 3260 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3261 break; 3262 case AMDGPU_IRQ_STATE_ENABLE: 3263 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3264 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3265 TIME_STAMP_INT_ENABLE, 1); 3266 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3267 break; 3268 default: 3269 break; 3270 } 3271 } 3272 3273 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3274 int xcc_id, int me, int pipe) 3275 { 3276 /* 3277 * amdgpu controls only the first MEC. That's why this function only 3278 * handles the setting of interrupts for this specific MEC. All other 3279 * pipes' interrupts are set by amdkfd. 3280 */ 3281 if (me != 1) 3282 return 0; 3283 3284 switch (pipe) { 3285 case 0: 3286 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3287 case 1: 3288 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3289 case 2: 3290 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3291 case 3: 3292 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3293 default: 3294 return 0; 3295 } 3296 } 3297 3298 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3299 struct amdgpu_irq_src *source, 3300 unsigned type, 3301 enum amdgpu_interrupt_state state) 3302 { 3303 u32 mec_int_cntl_reg, mec_int_cntl; 3304 int i, j, k, num_xcc; 3305 3306 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3307 switch (state) { 3308 case AMDGPU_IRQ_STATE_DISABLE: 3309 case AMDGPU_IRQ_STATE_ENABLE: 3310 for (i = 0; i < num_xcc; i++) { 3311 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3312 PRIV_REG_INT_ENABLE, 3313 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3314 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3315 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3316 /* MECs start at 1 */ 3317 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3318 3319 if (mec_int_cntl_reg) { 3320 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3321 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3322 PRIV_REG_INT_ENABLE, 3323 state == AMDGPU_IRQ_STATE_ENABLE ? 3324 1 : 0); 3325 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3326 } 3327 } 3328 } 3329 } 3330 break; 3331 default: 3332 break; 3333 } 3334 3335 return 0; 3336 } 3337 3338 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3339 struct amdgpu_irq_src *source, 3340 unsigned type, 3341 enum amdgpu_interrupt_state state) 3342 { 3343 u32 mec_int_cntl_reg, mec_int_cntl; 3344 int i, j, k, num_xcc; 3345 3346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3347 switch (state) { 3348 case AMDGPU_IRQ_STATE_DISABLE: 3349 case AMDGPU_IRQ_STATE_ENABLE: 3350 for (i = 0; i < num_xcc; i++) { 3351 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3352 OPCODE_ERROR_INT_ENABLE, 3353 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3354 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3355 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3356 /* MECs start at 1 */ 3357 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3358 3359 if (mec_int_cntl_reg) { 3360 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3361 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3362 OPCODE_ERROR_INT_ENABLE, 3363 state == AMDGPU_IRQ_STATE_ENABLE ? 3364 1 : 0); 3365 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3366 } 3367 } 3368 } 3369 } 3370 break; 3371 default: 3372 break; 3373 } 3374 3375 return 0; 3376 } 3377 3378 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3379 struct amdgpu_irq_src *source, 3380 unsigned type, 3381 enum amdgpu_interrupt_state state) 3382 { 3383 int i, num_xcc; 3384 3385 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3386 switch (state) { 3387 case AMDGPU_IRQ_STATE_DISABLE: 3388 case AMDGPU_IRQ_STATE_ENABLE: 3389 for (i = 0; i < num_xcc; i++) 3390 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3391 PRIV_INSTR_INT_ENABLE, 3392 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3393 break; 3394 default: 3395 break; 3396 } 3397 3398 return 0; 3399 } 3400 3401 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3402 struct amdgpu_irq_src *src, 3403 unsigned type, 3404 enum amdgpu_interrupt_state state) 3405 { 3406 int i, num_xcc; 3407 3408 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3409 for (i = 0; i < num_xcc; i++) { 3410 switch (type) { 3411 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3412 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3413 adev, 1, 0, state, i); 3414 break; 3415 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3416 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3417 adev, 1, 1, state, i); 3418 break; 3419 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3420 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3421 adev, 1, 2, state, i); 3422 break; 3423 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3424 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3425 adev, 1, 3, state, i); 3426 break; 3427 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3428 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3429 adev, 2, 0, state, i); 3430 break; 3431 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3432 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3433 adev, 2, 1, state, i); 3434 break; 3435 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3436 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3437 adev, 2, 2, state, i); 3438 break; 3439 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3440 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3441 adev, 2, 3, state, i); 3442 break; 3443 default: 3444 break; 3445 } 3446 } 3447 3448 return 0; 3449 } 3450 3451 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3452 struct amdgpu_irq_src *source, 3453 struct amdgpu_iv_entry *entry) 3454 { 3455 int i, xcc_id; 3456 u8 me_id, pipe_id, queue_id; 3457 struct amdgpu_ring *ring; 3458 3459 DRM_DEBUG("IH: CP EOP\n"); 3460 me_id = (entry->ring_id & 0x0c) >> 2; 3461 pipe_id = (entry->ring_id & 0x03) >> 0; 3462 queue_id = (entry->ring_id & 0x70) >> 4; 3463 3464 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3465 3466 if (xcc_id == -EINVAL) 3467 return -EINVAL; 3468 3469 switch (me_id) { 3470 case 0: 3471 case 1: 3472 case 2: 3473 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3474 ring = &adev->gfx.compute_ring 3475 [i + 3476 xcc_id * adev->gfx.num_compute_rings]; 3477 /* Per-queue interrupt is supported for MEC starting from VI. 3478 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3479 */ 3480 3481 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3482 amdgpu_fence_process(ring); 3483 } 3484 break; 3485 } 3486 return 0; 3487 } 3488 3489 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3490 struct amdgpu_iv_entry *entry) 3491 { 3492 u8 me_id, pipe_id, queue_id; 3493 struct amdgpu_ring *ring; 3494 int i, xcc_id; 3495 3496 me_id = (entry->ring_id & 0x0c) >> 2; 3497 pipe_id = (entry->ring_id & 0x03) >> 0; 3498 queue_id = (entry->ring_id & 0x70) >> 4; 3499 3500 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3501 3502 if (xcc_id == -EINVAL) 3503 return; 3504 3505 switch (me_id) { 3506 case 0: 3507 case 1: 3508 case 2: 3509 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3510 ring = &adev->gfx.compute_ring 3511 [i + 3512 xcc_id * adev->gfx.num_compute_rings]; 3513 if (ring->me == me_id && ring->pipe == pipe_id && 3514 ring->queue == queue_id) 3515 drm_sched_fault(&ring->sched); 3516 } 3517 break; 3518 } 3519 } 3520 3521 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3522 struct amdgpu_irq_src *source, 3523 struct amdgpu_iv_entry *entry) 3524 { 3525 DRM_ERROR("Illegal register access in command stream\n"); 3526 gfx_v9_4_3_fault(adev, entry); 3527 return 0; 3528 } 3529 3530 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3531 struct amdgpu_irq_src *source, 3532 struct amdgpu_iv_entry *entry) 3533 { 3534 DRM_ERROR("Illegal opcode in command stream\n"); 3535 gfx_v9_4_3_fault(adev, entry); 3536 return 0; 3537 } 3538 3539 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3540 struct amdgpu_irq_src *source, 3541 struct amdgpu_iv_entry *entry) 3542 { 3543 DRM_ERROR("Illegal instruction in command stream\n"); 3544 gfx_v9_4_3_fault(adev, entry); 3545 return 0; 3546 } 3547 3548 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3549 { 3550 const unsigned int cp_coher_cntl = 3551 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3552 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3553 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3554 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3555 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3556 3557 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3558 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3559 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3560 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3561 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3562 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3563 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3564 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3565 } 3566 3567 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3568 uint32_t pipe, bool enable) 3569 { 3570 struct amdgpu_device *adev = ring->adev; 3571 uint32_t val; 3572 uint32_t wcl_cs_reg; 3573 3574 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3575 val = enable ? 0x1 : 0x7f; 3576 3577 switch (pipe) { 3578 case 0: 3579 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3580 break; 3581 case 1: 3582 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3583 break; 3584 case 2: 3585 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3586 break; 3587 case 3: 3588 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3589 break; 3590 default: 3591 DRM_DEBUG("invalid pipe %d\n", pipe); 3592 return; 3593 } 3594 3595 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3596 3597 } 3598 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3599 { 3600 struct amdgpu_device *adev = ring->adev; 3601 uint32_t val; 3602 int i; 3603 3604 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3605 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3606 * around 25% of gpu resources. 3607 */ 3608 val = enable ? 0x1f : 0x07ffffff; 3609 amdgpu_ring_emit_wreg(ring, 3610 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3611 val); 3612 3613 /* Restrict waves for normal/low priority compute queues as well 3614 * to get best QoS for high priority compute jobs. 3615 * 3616 * amdgpu controls only 1st ME(0-3 CS pipes). 3617 */ 3618 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3619 if (i != ring->pipe) 3620 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3621 3622 } 3623 } 3624 3625 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3626 uint32_t pipe, uint32_t queue, 3627 uint32_t xcc_id) 3628 { 3629 int i, r; 3630 /* make sure dequeue is complete*/ 3631 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3632 mutex_lock(&adev->srbm_mutex); 3633 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3634 for (i = 0; i < adev->usec_timeout; i++) { 3635 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3636 break; 3637 udelay(1); 3638 } 3639 if (i >= adev->usec_timeout) 3640 r = -ETIMEDOUT; 3641 else 3642 r = 0; 3643 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3644 mutex_unlock(&adev->srbm_mutex); 3645 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3646 3647 return r; 3648 3649 } 3650 3651 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3652 { 3653 if (!!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3654 return true; 3655 else 3656 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3657 3658 return false; 3659 } 3660 3661 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3662 { 3663 struct amdgpu_device *adev = ring->adev; 3664 uint32_t reset_pipe, clean_pipe; 3665 int r; 3666 3667 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3668 return -EINVAL; 3669 3670 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3671 mutex_lock(&adev->srbm_mutex); 3672 3673 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3674 clean_pipe = reset_pipe; 3675 3676 if (ring->me == 1) { 3677 switch (ring->pipe) { 3678 case 0: 3679 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3680 MEC_ME1_PIPE0_RESET, 1); 3681 break; 3682 case 1: 3683 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3684 MEC_ME1_PIPE1_RESET, 1); 3685 break; 3686 case 2: 3687 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3688 MEC_ME1_PIPE2_RESET, 1); 3689 break; 3690 case 3: 3691 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3692 MEC_ME1_PIPE3_RESET, 1); 3693 break; 3694 default: 3695 break; 3696 } 3697 } else { 3698 if (ring->pipe) 3699 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3700 MEC_ME2_PIPE1_RESET, 1); 3701 else 3702 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3703 MEC_ME2_PIPE0_RESET, 1); 3704 } 3705 3706 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3707 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3708 mutex_unlock(&adev->srbm_mutex); 3709 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3710 3711 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3712 return r; 3713 } 3714 3715 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3716 unsigned int vmid, 3717 struct amdgpu_fence *timedout_fence) 3718 { 3719 struct amdgpu_device *adev = ring->adev; 3720 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3721 struct amdgpu_ring *kiq_ring = &kiq->ring; 3722 int reset_mode = AMDGPU_RESET_TYPE_PER_QUEUE; 3723 unsigned long flags; 3724 int r; 3725 3726 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3727 return -EINVAL; 3728 3729 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 3730 3731 spin_lock_irqsave(&kiq->ring_lock, flags); 3732 3733 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3734 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3735 return -ENOMEM; 3736 } 3737 3738 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3739 0, 0); 3740 amdgpu_ring_commit(kiq_ring); 3741 3742 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3743 3744 r = amdgpu_ring_test_ring(kiq_ring); 3745 if (r) { 3746 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3747 ring->name); 3748 goto pipe_reset; 3749 } 3750 3751 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3752 if (r) 3753 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3754 3755 pipe_reset: 3756 if (r) { 3757 if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3758 return -EOPNOTSUPP; 3759 r = gfx_v9_4_3_reset_hw_pipe(ring); 3760 reset_mode = AMDGPU_RESET_TYPE_PER_PIPE; 3761 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3762 r ? "failed" : "successfully"); 3763 if (r) 3764 return r; 3765 } 3766 3767 gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3768 3769 spin_lock_irqsave(&kiq->ring_lock, flags); 3770 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3771 if (r) { 3772 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3773 return -ENOMEM; 3774 } 3775 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3776 amdgpu_ring_commit(kiq_ring); 3777 r = amdgpu_ring_test_ring(kiq_ring); 3778 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3779 if (r) { 3780 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) 3781 goto pipe_reset; 3782 3783 dev_err(adev->dev, "fail to remap queue\n"); 3784 return r; 3785 } 3786 3787 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) { 3788 r = amdgpu_ring_test_ring(ring); 3789 if (r) 3790 goto pipe_reset; 3791 } 3792 3793 3794 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 3795 } 3796 3797 enum amdgpu_gfx_cp_ras_mem_id { 3798 AMDGPU_GFX_CP_MEM1 = 1, 3799 AMDGPU_GFX_CP_MEM2, 3800 AMDGPU_GFX_CP_MEM3, 3801 AMDGPU_GFX_CP_MEM4, 3802 AMDGPU_GFX_CP_MEM5, 3803 }; 3804 3805 enum amdgpu_gfx_gcea_ras_mem_id { 3806 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3807 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3808 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3809 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3810 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3811 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3812 AMDGPU_GFX_GCEA_MAM_DMEM0, 3813 AMDGPU_GFX_GCEA_MAM_DMEM1, 3814 AMDGPU_GFX_GCEA_MAM_DMEM2, 3815 AMDGPU_GFX_GCEA_MAM_DMEM3, 3816 AMDGPU_GFX_GCEA_MAM_AMEM0, 3817 AMDGPU_GFX_GCEA_MAM_AMEM1, 3818 AMDGPU_GFX_GCEA_MAM_AMEM2, 3819 AMDGPU_GFX_GCEA_MAM_AMEM3, 3820 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3821 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3822 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3823 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3824 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3825 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3826 }; 3827 3828 enum amdgpu_gfx_gc_cane_ras_mem_id { 3829 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3830 }; 3831 3832 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3833 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3834 }; 3835 3836 enum amdgpu_gfx_gds_ras_mem_id { 3837 AMDGPU_GFX_GDS_MEM0 = 0, 3838 }; 3839 3840 enum amdgpu_gfx_lds_ras_mem_id { 3841 AMDGPU_GFX_LDS_BANK0 = 0, 3842 AMDGPU_GFX_LDS_BANK1, 3843 AMDGPU_GFX_LDS_BANK2, 3844 AMDGPU_GFX_LDS_BANK3, 3845 AMDGPU_GFX_LDS_BANK4, 3846 AMDGPU_GFX_LDS_BANK5, 3847 AMDGPU_GFX_LDS_BANK6, 3848 AMDGPU_GFX_LDS_BANK7, 3849 AMDGPU_GFX_LDS_BANK8, 3850 AMDGPU_GFX_LDS_BANK9, 3851 AMDGPU_GFX_LDS_BANK10, 3852 AMDGPU_GFX_LDS_BANK11, 3853 AMDGPU_GFX_LDS_BANK12, 3854 AMDGPU_GFX_LDS_BANK13, 3855 AMDGPU_GFX_LDS_BANK14, 3856 AMDGPU_GFX_LDS_BANK15, 3857 AMDGPU_GFX_LDS_BANK16, 3858 AMDGPU_GFX_LDS_BANK17, 3859 AMDGPU_GFX_LDS_BANK18, 3860 AMDGPU_GFX_LDS_BANK19, 3861 AMDGPU_GFX_LDS_BANK20, 3862 AMDGPU_GFX_LDS_BANK21, 3863 AMDGPU_GFX_LDS_BANK22, 3864 AMDGPU_GFX_LDS_BANK23, 3865 AMDGPU_GFX_LDS_BANK24, 3866 AMDGPU_GFX_LDS_BANK25, 3867 AMDGPU_GFX_LDS_BANK26, 3868 AMDGPU_GFX_LDS_BANK27, 3869 AMDGPU_GFX_LDS_BANK28, 3870 AMDGPU_GFX_LDS_BANK29, 3871 AMDGPU_GFX_LDS_BANK30, 3872 AMDGPU_GFX_LDS_BANK31, 3873 AMDGPU_GFX_LDS_SP_BUFFER_A, 3874 AMDGPU_GFX_LDS_SP_BUFFER_B, 3875 }; 3876 3877 enum amdgpu_gfx_rlc_ras_mem_id { 3878 AMDGPU_GFX_RLC_GPMF32 = 1, 3879 AMDGPU_GFX_RLC_RLCVF32, 3880 AMDGPU_GFX_RLC_SCRATCH, 3881 AMDGPU_GFX_RLC_SRM_ARAM, 3882 AMDGPU_GFX_RLC_SRM_DRAM, 3883 AMDGPU_GFX_RLC_TCTAG, 3884 AMDGPU_GFX_RLC_SPM_SE, 3885 AMDGPU_GFX_RLC_SPM_GRBMT, 3886 }; 3887 3888 enum amdgpu_gfx_sp_ras_mem_id { 3889 AMDGPU_GFX_SP_SIMDID0 = 0, 3890 }; 3891 3892 enum amdgpu_gfx_spi_ras_mem_id { 3893 AMDGPU_GFX_SPI_MEM0 = 0, 3894 AMDGPU_GFX_SPI_MEM1, 3895 AMDGPU_GFX_SPI_MEM2, 3896 AMDGPU_GFX_SPI_MEM3, 3897 }; 3898 3899 enum amdgpu_gfx_sqc_ras_mem_id { 3900 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3901 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3902 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3903 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3904 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3905 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3906 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3907 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3908 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3909 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3910 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3911 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3912 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3913 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3914 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3915 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3916 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3917 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3918 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3919 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3920 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3921 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3922 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3923 }; 3924 3925 enum amdgpu_gfx_sq_ras_mem_id { 3926 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3927 AMDGPU_GFX_SQ_SGPR_MEM1, 3928 AMDGPU_GFX_SQ_SGPR_MEM2, 3929 AMDGPU_GFX_SQ_SGPR_MEM3, 3930 }; 3931 3932 enum amdgpu_gfx_ta_ras_mem_id { 3933 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3934 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3935 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3936 AMDGPU_GFX_TA_FSX_LFIFO, 3937 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3938 }; 3939 3940 enum amdgpu_gfx_tcc_ras_mem_id { 3941 AMDGPU_GFX_TCC_MEM1 = 1, 3942 }; 3943 3944 enum amdgpu_gfx_tca_ras_mem_id { 3945 AMDGPU_GFX_TCA_MEM1 = 1, 3946 }; 3947 3948 enum amdgpu_gfx_tci_ras_mem_id { 3949 AMDGPU_GFX_TCIW_MEM = 1, 3950 }; 3951 3952 enum amdgpu_gfx_tcp_ras_mem_id { 3953 AMDGPU_GFX_TCP_LFIFO0 = 1, 3954 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3955 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3956 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3957 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3958 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3959 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3960 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3961 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3962 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3963 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3964 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3965 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3966 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3967 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3968 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3969 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3970 AMDGPU_GFX_TCP_VM_FIFO, 3971 AMDGPU_GFX_TCP_DB_TAGRAM0, 3972 AMDGPU_GFX_TCP_DB_TAGRAM1, 3973 AMDGPU_GFX_TCP_DB_TAGRAM2, 3974 AMDGPU_GFX_TCP_DB_TAGRAM3, 3975 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3976 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3977 AMDGPU_GFX_TCP_CMD_FIFO, 3978 }; 3979 3980 enum amdgpu_gfx_td_ras_mem_id { 3981 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3982 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3983 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3984 }; 3985 3986 enum amdgpu_gfx_tcx_ras_mem_id { 3987 AMDGPU_GFX_TCX_FIFOD0 = 0, 3988 AMDGPU_GFX_TCX_FIFOD1, 3989 AMDGPU_GFX_TCX_FIFOD2, 3990 AMDGPU_GFX_TCX_FIFOD3, 3991 AMDGPU_GFX_TCX_FIFOD4, 3992 AMDGPU_GFX_TCX_FIFOD5, 3993 AMDGPU_GFX_TCX_FIFOD6, 3994 AMDGPU_GFX_TCX_FIFOD7, 3995 AMDGPU_GFX_TCX_FIFOB0, 3996 AMDGPU_GFX_TCX_FIFOB1, 3997 AMDGPU_GFX_TCX_FIFOB2, 3998 AMDGPU_GFX_TCX_FIFOB3, 3999 AMDGPU_GFX_TCX_FIFOB4, 4000 AMDGPU_GFX_TCX_FIFOB5, 4001 AMDGPU_GFX_TCX_FIFOB6, 4002 AMDGPU_GFX_TCX_FIFOB7, 4003 AMDGPU_GFX_TCX_FIFOA0, 4004 AMDGPU_GFX_TCX_FIFOA1, 4005 AMDGPU_GFX_TCX_FIFOA2, 4006 AMDGPU_GFX_TCX_FIFOA3, 4007 AMDGPU_GFX_TCX_FIFOA4, 4008 AMDGPU_GFX_TCX_FIFOA5, 4009 AMDGPU_GFX_TCX_FIFOA6, 4010 AMDGPU_GFX_TCX_FIFOA7, 4011 AMDGPU_GFX_TCX_CFIFO0, 4012 AMDGPU_GFX_TCX_CFIFO1, 4013 AMDGPU_GFX_TCX_CFIFO2, 4014 AMDGPU_GFX_TCX_CFIFO3, 4015 AMDGPU_GFX_TCX_CFIFO4, 4016 AMDGPU_GFX_TCX_CFIFO5, 4017 AMDGPU_GFX_TCX_CFIFO6, 4018 AMDGPU_GFX_TCX_CFIFO7, 4019 AMDGPU_GFX_TCX_FIFO_ACKB0, 4020 AMDGPU_GFX_TCX_FIFO_ACKB1, 4021 AMDGPU_GFX_TCX_FIFO_ACKB2, 4022 AMDGPU_GFX_TCX_FIFO_ACKB3, 4023 AMDGPU_GFX_TCX_FIFO_ACKB4, 4024 AMDGPU_GFX_TCX_FIFO_ACKB5, 4025 AMDGPU_GFX_TCX_FIFO_ACKB6, 4026 AMDGPU_GFX_TCX_FIFO_ACKB7, 4027 AMDGPU_GFX_TCX_FIFO_ACKD0, 4028 AMDGPU_GFX_TCX_FIFO_ACKD1, 4029 AMDGPU_GFX_TCX_FIFO_ACKD2, 4030 AMDGPU_GFX_TCX_FIFO_ACKD3, 4031 AMDGPU_GFX_TCX_FIFO_ACKD4, 4032 AMDGPU_GFX_TCX_FIFO_ACKD5, 4033 AMDGPU_GFX_TCX_FIFO_ACKD6, 4034 AMDGPU_GFX_TCX_FIFO_ACKD7, 4035 AMDGPU_GFX_TCX_DST_FIFOA0, 4036 AMDGPU_GFX_TCX_DST_FIFOA1, 4037 AMDGPU_GFX_TCX_DST_FIFOA2, 4038 AMDGPU_GFX_TCX_DST_FIFOA3, 4039 AMDGPU_GFX_TCX_DST_FIFOA4, 4040 AMDGPU_GFX_TCX_DST_FIFOA5, 4041 AMDGPU_GFX_TCX_DST_FIFOA6, 4042 AMDGPU_GFX_TCX_DST_FIFOA7, 4043 AMDGPU_GFX_TCX_DST_FIFOB0, 4044 AMDGPU_GFX_TCX_DST_FIFOB1, 4045 AMDGPU_GFX_TCX_DST_FIFOB2, 4046 AMDGPU_GFX_TCX_DST_FIFOB3, 4047 AMDGPU_GFX_TCX_DST_FIFOB4, 4048 AMDGPU_GFX_TCX_DST_FIFOB5, 4049 AMDGPU_GFX_TCX_DST_FIFOB6, 4050 AMDGPU_GFX_TCX_DST_FIFOB7, 4051 AMDGPU_GFX_TCX_DST_FIFOD0, 4052 AMDGPU_GFX_TCX_DST_FIFOD1, 4053 AMDGPU_GFX_TCX_DST_FIFOD2, 4054 AMDGPU_GFX_TCX_DST_FIFOD3, 4055 AMDGPU_GFX_TCX_DST_FIFOD4, 4056 AMDGPU_GFX_TCX_DST_FIFOD5, 4057 AMDGPU_GFX_TCX_DST_FIFOD6, 4058 AMDGPU_GFX_TCX_DST_FIFOD7, 4059 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 4060 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 4061 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 4062 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 4063 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 4064 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 4065 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 4066 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 4067 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 4068 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 4069 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 4070 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 4071 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 4072 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 4073 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 4074 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 4075 }; 4076 4077 enum amdgpu_gfx_atc_l2_ras_mem_id { 4078 AMDGPU_GFX_ATC_L2_MEM0 = 0, 4079 }; 4080 4081 enum amdgpu_gfx_utcl2_ras_mem_id { 4082 AMDGPU_GFX_UTCL2_MEM0 = 0, 4083 }; 4084 4085 enum amdgpu_gfx_vml2_ras_mem_id { 4086 AMDGPU_GFX_VML2_MEM0 = 0, 4087 }; 4088 4089 enum amdgpu_gfx_vml2_walker_ras_mem_id { 4090 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 4091 }; 4092 4093 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 4094 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 4095 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 4096 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 4097 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 4098 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 4099 }; 4100 4101 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 4102 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 4103 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 4104 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 4105 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 4106 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 4107 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 4108 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 4109 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 4110 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 4111 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 4112 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 4113 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 4114 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 4115 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 4116 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 4117 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 4118 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 4119 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 4120 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 4121 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 4122 }; 4123 4124 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 4125 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 4126 }; 4127 4128 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 4129 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 4130 }; 4131 4132 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 4133 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 4134 }; 4135 4136 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 4137 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 4138 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 4139 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 4140 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 4141 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 4142 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 4143 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 4144 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 4145 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 4146 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 4147 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 4148 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 4149 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 4150 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 4151 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 4152 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 4153 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 4154 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 4155 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 4156 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 4157 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 4158 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 4159 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 4160 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 4161 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 4162 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 4163 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 4164 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 4165 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 4166 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 4167 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 4168 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 4169 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 4170 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4171 }; 4172 4173 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4174 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4175 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4176 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4177 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4178 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4179 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4180 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4181 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4182 }; 4183 4184 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4185 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4186 }; 4187 4188 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4189 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4190 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4191 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4192 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4193 }; 4194 4195 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4196 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4197 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4198 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4199 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4200 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4201 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4202 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4203 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4204 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4205 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4206 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4207 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4208 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4209 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4210 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4211 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4212 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4213 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4214 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4215 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4216 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4217 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4218 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4219 }; 4220 4221 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4222 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4223 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4224 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4225 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4226 }; 4227 4228 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4229 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4230 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4231 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4232 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4233 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4234 }; 4235 4236 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4237 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4238 }; 4239 4240 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4241 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4242 }; 4243 4244 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4245 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4246 }; 4247 4248 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4249 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4250 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4251 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4252 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4253 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4254 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4255 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4256 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4257 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4258 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4259 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4260 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4261 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4262 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4263 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4264 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4265 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4266 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4267 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4268 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4269 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4270 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4271 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4272 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4273 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4274 }; 4275 4276 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4277 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4278 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4279 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4280 }; 4281 4282 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4283 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4284 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4285 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4286 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4287 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4288 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4289 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4290 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4291 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4292 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4293 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4294 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4295 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4296 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4297 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4298 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4299 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4300 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4301 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4302 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4303 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4304 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4305 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4306 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4307 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4308 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4309 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4310 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4311 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4312 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4313 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4314 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4315 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4316 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4317 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4318 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4319 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4320 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4321 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4322 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4323 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4324 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4325 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4326 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4327 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4328 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4329 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4330 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4331 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4332 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4333 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4334 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4335 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4336 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4337 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4338 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4339 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4340 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4341 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4342 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4343 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4344 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4345 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4346 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4347 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4348 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4349 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4350 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4351 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4352 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4353 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4354 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4355 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4356 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4357 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4358 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4359 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4360 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4361 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4362 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4363 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4364 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4365 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4366 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4367 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4368 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4369 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4370 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4371 }; 4372 4373 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4374 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4375 }; 4376 4377 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4378 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4379 }; 4380 4381 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4382 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4383 }; 4384 4385 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4386 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4387 }; 4388 4389 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4390 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4391 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4392 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4393 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4394 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4395 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4396 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4397 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4398 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4399 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4400 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4401 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4402 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4403 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4404 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4405 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4406 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4407 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4408 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4409 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4410 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4411 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4412 }; 4413 4414 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4415 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4416 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4417 AMDGPU_GFX_RLC_MEM, 1}, 4418 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4419 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4420 AMDGPU_GFX_CP_MEM, 1}, 4421 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4422 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4423 AMDGPU_GFX_CP_MEM, 1}, 4424 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4425 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4426 AMDGPU_GFX_CP_MEM, 1}, 4427 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4428 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4429 AMDGPU_GFX_GDS_MEM, 1}, 4430 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4431 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4432 AMDGPU_GFX_GC_CANE_MEM, 1}, 4433 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4434 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4435 AMDGPU_GFX_SPI_MEM, 1}, 4436 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4437 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4438 AMDGPU_GFX_SP_MEM, 4}, 4439 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4440 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4441 AMDGPU_GFX_SP_MEM, 4}, 4442 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4443 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4444 AMDGPU_GFX_SQ_MEM, 4}, 4445 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4446 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4447 AMDGPU_GFX_SQC_MEM, 4}, 4448 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4449 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4450 AMDGPU_GFX_TCX_MEM, 1}, 4451 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4452 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4453 AMDGPU_GFX_TCC_MEM, 1}, 4454 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4455 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4456 AMDGPU_GFX_TA_MEM, 4}, 4457 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4458 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4459 AMDGPU_GFX_TCI_MEM, 1}, 4460 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4461 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4462 AMDGPU_GFX_TCP_MEM, 4}, 4463 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4464 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4465 AMDGPU_GFX_TD_MEM, 4}, 4466 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4467 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4468 AMDGPU_GFX_GCEA_MEM, 1}, 4469 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4470 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4471 AMDGPU_GFX_LDS_MEM, 4}, 4472 }; 4473 4474 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4475 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4476 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4477 AMDGPU_GFX_RLC_MEM, 1}, 4478 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4479 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4480 AMDGPU_GFX_CP_MEM, 1}, 4481 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4482 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4483 AMDGPU_GFX_CP_MEM, 1}, 4484 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4485 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4486 AMDGPU_GFX_CP_MEM, 1}, 4487 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4488 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4489 AMDGPU_GFX_GDS_MEM, 1}, 4490 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4491 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4492 AMDGPU_GFX_GC_CANE_MEM, 1}, 4493 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4494 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4495 AMDGPU_GFX_SPI_MEM, 1}, 4496 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4497 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4498 AMDGPU_GFX_SP_MEM, 4}, 4499 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4500 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4501 AMDGPU_GFX_SP_MEM, 4}, 4502 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4503 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4504 AMDGPU_GFX_SQ_MEM, 4}, 4505 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4506 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4507 AMDGPU_GFX_SQC_MEM, 4}, 4508 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4509 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4510 AMDGPU_GFX_TCX_MEM, 1}, 4511 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4512 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4513 AMDGPU_GFX_TCC_MEM, 1}, 4514 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4515 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4516 AMDGPU_GFX_TA_MEM, 4}, 4517 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4518 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4519 AMDGPU_GFX_TCI_MEM, 1}, 4520 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4521 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4522 AMDGPU_GFX_TCP_MEM, 4}, 4523 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4524 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4525 AMDGPU_GFX_TD_MEM, 4}, 4526 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4527 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4528 AMDGPU_GFX_TCA_MEM, 1}, 4529 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4530 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4531 AMDGPU_GFX_GCEA_MEM, 1}, 4532 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4533 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4534 AMDGPU_GFX_LDS_MEM, 4}, 4535 }; 4536 4537 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4538 void *ras_error_status, int xcc_id) 4539 { 4540 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4541 unsigned long ce_count = 0, ue_count = 0; 4542 uint32_t i, j, k; 4543 4544 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4545 struct amdgpu_smuio_mcm_config_info mcm_info = { 4546 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4547 .die_id = xcc_id & 0x01 ? 1 : 0, 4548 }; 4549 4550 mutex_lock(&adev->grbm_idx_mutex); 4551 4552 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4553 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4554 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4555 /* no need to select if instance number is 1 */ 4556 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4557 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4558 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4559 4560 amdgpu_ras_inst_query_ras_error_count(adev, 4561 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4562 1, 4563 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4564 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4565 GET_INST(GC, xcc_id), 4566 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4567 &ce_count); 4568 4569 amdgpu_ras_inst_query_ras_error_count(adev, 4570 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4571 1, 4572 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4573 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4574 GET_INST(GC, xcc_id), 4575 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4576 &ue_count); 4577 } 4578 } 4579 } 4580 4581 /* handle extra register entries of UE */ 4582 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4583 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4584 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4585 /* no need to select if instance number is 1 */ 4586 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4587 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4588 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4589 4590 amdgpu_ras_inst_query_ras_error_count(adev, 4591 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4592 1, 4593 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4594 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4595 GET_INST(GC, xcc_id), 4596 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4597 &ue_count); 4598 } 4599 } 4600 } 4601 4602 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4603 xcc_id); 4604 mutex_unlock(&adev->grbm_idx_mutex); 4605 4606 /* the caller should make sure initialize value of 4607 * err_data->ue_count and err_data->ce_count 4608 */ 4609 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4610 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4611 } 4612 4613 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4614 void *ras_error_status, int xcc_id) 4615 { 4616 uint32_t i, j, k; 4617 4618 mutex_lock(&adev->grbm_idx_mutex); 4619 4620 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4621 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4622 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4623 /* no need to select if instance number is 1 */ 4624 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4625 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4626 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4627 4628 amdgpu_ras_inst_reset_ras_error_count(adev, 4629 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4630 1, 4631 GET_INST(GC, xcc_id)); 4632 4633 amdgpu_ras_inst_reset_ras_error_count(adev, 4634 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4635 1, 4636 GET_INST(GC, xcc_id)); 4637 } 4638 } 4639 } 4640 4641 /* handle extra register entries of UE */ 4642 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4643 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4644 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4645 /* no need to select if instance number is 1 */ 4646 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4647 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4648 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4649 4650 amdgpu_ras_inst_reset_ras_error_count(adev, 4651 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4652 1, 4653 GET_INST(GC, xcc_id)); 4654 } 4655 } 4656 } 4657 4658 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4659 xcc_id); 4660 mutex_unlock(&adev->grbm_idx_mutex); 4661 } 4662 4663 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4664 void *ras_error_status, int xcc_id) 4665 { 4666 uint32_t i; 4667 uint32_t data; 4668 4669 if (amdgpu_sriov_vf(adev)) 4670 return; 4671 4672 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4673 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4674 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4675 4676 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4677 (amdgpu_watchdog_timer.period < 1 || 4678 amdgpu_watchdog_timer.period > 0x23)) { 4679 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4680 amdgpu_watchdog_timer.period = 0x23; 4681 } 4682 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4683 amdgpu_watchdog_timer.period); 4684 4685 mutex_lock(&adev->grbm_idx_mutex); 4686 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4687 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4688 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4689 } 4690 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4691 xcc_id); 4692 mutex_unlock(&adev->grbm_idx_mutex); 4693 } 4694 4695 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4696 void *ras_error_status) 4697 { 4698 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4699 gfx_v9_4_3_inst_query_ras_err_count); 4700 } 4701 4702 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4703 { 4704 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4705 } 4706 4707 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4708 { 4709 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4710 } 4711 4712 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4713 { 4714 /* Header itself is a NOP packet */ 4715 if (num_nop == 1) { 4716 amdgpu_ring_write(ring, ring->funcs->nop); 4717 return; 4718 } 4719 4720 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4721 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4722 4723 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4724 amdgpu_ring_insert_nop(ring, num_nop - 1); 4725 } 4726 4727 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4728 { 4729 struct amdgpu_device *adev = ip_block->adev; 4730 uint32_t i, j, k; 4731 uint32_t xcc_id, xcc_offset, inst_offset; 4732 uint32_t num_xcc, reg, num_inst; 4733 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4734 4735 if (!adev->gfx.ip_dump_core) 4736 return; 4737 4738 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4739 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4740 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4741 xcc_offset = xcc_id * reg_count; 4742 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4743 for (i = 0; i < reg_count; i++) 4744 drm_printf(p, "%-50s \t 0x%08x\n", 4745 gc_reg_list_9_4_3[i].reg_name, 4746 adev->gfx.ip_dump_core[xcc_offset + i]); 4747 } 4748 4749 /* print compute queue registers for all instances */ 4750 if (!adev->gfx.ip_dump_compute_queues) 4751 return; 4752 4753 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4754 adev->gfx.mec.num_queue_per_pipe; 4755 4756 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4757 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4758 num_xcc, 4759 adev->gfx.mec.num_mec, 4760 adev->gfx.mec.num_pipe_per_mec, 4761 adev->gfx.mec.num_queue_per_pipe); 4762 4763 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4764 xcc_offset = xcc_id * reg_count * num_inst; 4765 inst_offset = 0; 4766 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4767 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4768 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4769 drm_printf(p, 4770 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4771 xcc_id, i, j, k); 4772 for (reg = 0; reg < reg_count; reg++) { 4773 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4774 regCP_MEC_ME1_HEADER_DUMP) 4775 drm_printf(p, 4776 "%-50s \t 0x%08x\n", 4777 "regCP_MEC_ME2_HEADER_DUMP", 4778 adev->gfx.ip_dump_compute_queues 4779 [xcc_offset + inst_offset + 4780 reg]); 4781 else 4782 drm_printf(p, 4783 "%-50s \t 0x%08x\n", 4784 gc_cp_reg_list_9_4_3[reg].reg_name, 4785 adev->gfx.ip_dump_compute_queues 4786 [xcc_offset + inst_offset + 4787 reg]); 4788 } 4789 inst_offset += reg_count; 4790 } 4791 } 4792 } 4793 } 4794 } 4795 4796 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4797 { 4798 struct amdgpu_device *adev = ip_block->adev; 4799 uint32_t i, j, k; 4800 uint32_t num_xcc, reg, num_inst; 4801 uint32_t xcc_id, xcc_offset, inst_offset; 4802 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4803 4804 if (!adev->gfx.ip_dump_core) 4805 return; 4806 4807 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4808 4809 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4810 xcc_offset = xcc_id * reg_count; 4811 for (i = 0; i < reg_count; i++) 4812 adev->gfx.ip_dump_core[xcc_offset + i] = 4813 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4814 GET_INST(GC, xcc_id))); 4815 } 4816 4817 /* dump compute queue registers for all instances */ 4818 if (!adev->gfx.ip_dump_compute_queues) 4819 return; 4820 4821 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4822 adev->gfx.mec.num_queue_per_pipe; 4823 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4824 mutex_lock(&adev->srbm_mutex); 4825 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4826 xcc_offset = xcc_id * reg_count * num_inst; 4827 inst_offset = 0; 4828 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4829 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4830 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4831 /* ME0 is for GFX so start from 1 for CP */ 4832 soc15_grbm_select(adev, 1 + i, j, k, 0, 4833 GET_INST(GC, xcc_id)); 4834 4835 for (reg = 0; reg < reg_count; reg++) { 4836 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4837 regCP_MEC_ME1_HEADER_DUMP) 4838 adev->gfx.ip_dump_compute_queues 4839 [xcc_offset + 4840 inst_offset + reg] = 4841 RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), 4842 regCP_MEC_ME2_HEADER_DUMP)); 4843 else 4844 adev->gfx.ip_dump_compute_queues 4845 [xcc_offset + 4846 inst_offset + reg] = 4847 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4848 gc_cp_reg_list_9_4_3[reg], 4849 GET_INST(GC, xcc_id))); 4850 } 4851 inst_offset += reg_count; 4852 } 4853 } 4854 } 4855 } 4856 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4857 mutex_unlock(&adev->srbm_mutex); 4858 } 4859 4860 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4861 { 4862 /* Emit the cleaner shader */ 4863 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4864 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4865 } 4866 4867 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4868 .name = "gfx_v9_4_3", 4869 .early_init = gfx_v9_4_3_early_init, 4870 .late_init = gfx_v9_4_3_late_init, 4871 .sw_init = gfx_v9_4_3_sw_init, 4872 .sw_fini = gfx_v9_4_3_sw_fini, 4873 .hw_init = gfx_v9_4_3_hw_init, 4874 .hw_fini = gfx_v9_4_3_hw_fini, 4875 .suspend = gfx_v9_4_3_suspend, 4876 .resume = gfx_v9_4_3_resume, 4877 .is_idle = gfx_v9_4_3_is_idle, 4878 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4879 .soft_reset = gfx_v9_4_3_soft_reset, 4880 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4881 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4882 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4883 .dump_ip_state = gfx_v9_4_3_ip_dump, 4884 .print_ip_state = gfx_v9_4_3_ip_print, 4885 }; 4886 4887 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4888 .type = AMDGPU_RING_TYPE_COMPUTE, 4889 .align_mask = 0xff, 4890 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4891 .support_64bit_ptrs = true, 4892 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4893 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4894 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4895 .emit_frame_size = 4896 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4897 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4898 5 + /* hdp invalidate */ 4899 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4900 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4901 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4902 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4903 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4904 7 + /* gfx_v9_4_3_emit_mem_sync */ 4905 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4906 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4907 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4908 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4909 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4910 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4911 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4912 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4913 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4914 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4915 .test_ring = gfx_v9_4_3_ring_test_ring, 4916 .test_ib = gfx_v9_4_3_ring_test_ib, 4917 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4918 .pad_ib = amdgpu_ring_generic_pad_ib, 4919 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4920 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4921 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4922 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4923 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4924 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4925 .reset = gfx_v9_4_3_reset_kcq, 4926 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4927 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4928 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4929 }; 4930 4931 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4932 .type = AMDGPU_RING_TYPE_KIQ, 4933 .align_mask = 0xff, 4934 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4935 .support_64bit_ptrs = true, 4936 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4937 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4938 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4939 .emit_frame_size = 4940 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4941 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4942 5 + /* hdp invalidate */ 4943 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4944 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4945 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4946 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4947 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4948 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4949 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4950 .test_ring = gfx_v9_4_3_ring_test_ring, 4951 .insert_nop = amdgpu_ring_insert_nop, 4952 .pad_ib = amdgpu_ring_generic_pad_ib, 4953 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4954 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4955 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4956 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4957 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4958 }; 4959 4960 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4961 { 4962 int i, j, num_xcc; 4963 4964 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4965 for (i = 0; i < num_xcc; i++) { 4966 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4967 4968 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4969 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4970 = &gfx_v9_4_3_ring_funcs_compute; 4971 } 4972 } 4973 4974 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4975 .set = gfx_v9_4_3_set_eop_interrupt_state, 4976 .process = gfx_v9_4_3_eop_irq, 4977 }; 4978 4979 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4980 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4981 .process = gfx_v9_4_3_priv_reg_irq, 4982 }; 4983 4984 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4985 .set = gfx_v9_4_3_set_bad_op_fault_state, 4986 .process = gfx_v9_4_3_bad_op_irq, 4987 }; 4988 4989 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4990 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4991 .process = gfx_v9_4_3_priv_inst_irq, 4992 }; 4993 4994 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4995 { 4996 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4997 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4998 4999 adev->gfx.priv_reg_irq.num_types = 1; 5000 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 5001 5002 adev->gfx.bad_op_irq.num_types = 1; 5003 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 5004 5005 adev->gfx.priv_inst_irq.num_types = 1; 5006 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 5007 } 5008 5009 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 5010 { 5011 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 5012 } 5013 5014 5015 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 5016 { 5017 /* 9.4.3 variants removed all the GDS internal memory, 5018 * only support GWS opcode in kernel, like barrier 5019 * semaphore.etc */ 5020 5021 /* init asic gds info */ 5022 adev->gds.gds_size = 0; 5023 adev->gds.gds_compute_max_wave_id = 0; 5024 adev->gds.gws_size = 64; 5025 adev->gds.oa_size = 16; 5026 } 5027 5028 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 5029 u32 bitmap, int xcc_id) 5030 { 5031 u32 data; 5032 5033 if (!bitmap) 5034 return; 5035 5036 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 5037 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 5038 5039 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 5040 } 5041 5042 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 5043 { 5044 u32 data, mask; 5045 5046 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 5047 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 5048 5049 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 5050 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 5051 5052 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 5053 5054 return (~data) & mask; 5055 } 5056 5057 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 5058 struct amdgpu_cu_info *cu_info) 5059 { 5060 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 5061 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 5062 unsigned disable_masks[4 * 4]; 5063 bool is_symmetric_cus; 5064 5065 if (!adev || !cu_info) 5066 return -EINVAL; 5067 5068 /* 5069 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 5070 */ 5071 if (adev->gfx.config.max_shader_engines * 5072 adev->gfx.config.max_sh_per_se > 16) 5073 return -EINVAL; 5074 5075 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 5076 adev->gfx.config.max_shader_engines, 5077 adev->gfx.config.max_sh_per_se); 5078 5079 mutex_lock(&adev->grbm_idx_mutex); 5080 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 5081 is_symmetric_cus = true; 5082 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5083 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5084 mask = 1; 5085 ao_bitmap = 0; 5086 counter = 0; 5087 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 5088 gfx_v9_4_3_set_user_cu_inactive_bitmap( 5089 adev, 5090 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 5091 xcc_id); 5092 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 5093 5094 cu_info->bitmap[xcc_id][i][j] = bitmap; 5095 5096 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5097 if (bitmap & mask) { 5098 if (counter < adev->gfx.config.max_cu_per_sh) 5099 ao_bitmap |= mask; 5100 counter++; 5101 } 5102 mask <<= 1; 5103 } 5104 active_cu_number += counter; 5105 if (i < 2 && j < 2) 5106 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5107 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5108 } 5109 if (i && is_symmetric_cus && prev_counter != counter) 5110 is_symmetric_cus = false; 5111 prev_counter = counter; 5112 } 5113 if (is_symmetric_cus) { 5114 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 5115 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 5116 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 5117 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 5118 } 5119 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 5120 xcc_id); 5121 } 5122 mutex_unlock(&adev->grbm_idx_mutex); 5123 5124 cu_info->number = active_cu_number; 5125 cu_info->ao_cu_mask = ao_cu_mask; 5126 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5127 5128 return 0; 5129 } 5130 5131 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 5132 .type = AMD_IP_BLOCK_TYPE_GFX, 5133 .major = 9, 5134 .minor = 4, 5135 .rev = 3, 5136 .funcs = &gfx_v9_4_3_ip_funcs, 5137 }; 5138 5139 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 5140 { 5141 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5142 uint32_t tmp_mask; 5143 int i, r; 5144 5145 /* TODO : Initialize golden regs */ 5146 /* gfx_v9_4_3_init_golden_registers(adev); */ 5147 5148 tmp_mask = inst_mask; 5149 for_each_inst(i, tmp_mask) 5150 gfx_v9_4_3_xcc_constants_init(adev, i); 5151 5152 if (!amdgpu_sriov_vf(adev)) { 5153 tmp_mask = inst_mask; 5154 for_each_inst(i, tmp_mask) { 5155 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 5156 if (r) 5157 return r; 5158 } 5159 } 5160 5161 tmp_mask = inst_mask; 5162 for_each_inst(i, tmp_mask) { 5163 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 5164 if (r) 5165 return r; 5166 } 5167 5168 return 0; 5169 } 5170 5171 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 5172 { 5173 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5174 int i; 5175 5176 for_each_inst(i, inst_mask) 5177 gfx_v9_4_3_xcc_fini(adev, i); 5178 5179 return 0; 5180 } 5181 5182 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5183 .suspend = &gfx_v9_4_3_xcp_suspend, 5184 .resume = &gfx_v9_4_3_xcp_resume 5185 }; 5186 5187 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5188 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5189 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5190 }; 5191 5192 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5193 { 5194 int r; 5195 5196 r = amdgpu_ras_block_late_init(adev, ras_block); 5197 if (r) 5198 return r; 5199 5200 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5201 &gfx_v9_4_3_aca_info, 5202 NULL); 5203 if (r) 5204 goto late_fini; 5205 5206 return 0; 5207 5208 late_fini: 5209 amdgpu_ras_block_late_fini(adev, ras_block); 5210 5211 return r; 5212 } 5213 5214 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5215 .ras_block = { 5216 .hw_ops = &gfx_v9_4_3_ras_ops, 5217 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5218 }, 5219 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5220 }; 5221