1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 #include "amdgpu_aca.h" 42 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 47 48 #define GFX9_MEC_HPD_SIZE 4096 49 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 50 51 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 52 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 53 54 #define mmSMNAID_XCD0_MCA_SMU 0x36430400 /* SMN AID XCD0 */ 55 #define mmSMNAID_XCD1_MCA_SMU 0x38430400 /* SMN AID XCD1 */ 56 #define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */ 57 58 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 59 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 60 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 61 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 62 63 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 64 (offset & 0xFFFF) 65 66 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 67 68 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 69 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 70 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 71 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 72 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 73 struct amdgpu_cu_info *cu_info); 74 75 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 76 uint64_t queue_mask) 77 { 78 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 79 amdgpu_ring_write(kiq_ring, 80 PACKET3_SET_RESOURCES_VMID_MASK(0) | 81 /* vmid_mask:0* queue_type:0 (KIQ) */ 82 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 83 amdgpu_ring_write(kiq_ring, 84 lower_32_bits(queue_mask)); /* queue mask lo */ 85 amdgpu_ring_write(kiq_ring, 86 upper_32_bits(queue_mask)); /* queue mask hi */ 87 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 88 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 89 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 90 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 91 } 92 93 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 94 struct amdgpu_ring *ring) 95 { 96 struct amdgpu_device *adev = kiq_ring->adev; 97 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 98 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 99 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 100 101 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 102 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 103 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 104 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 105 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 106 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 107 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 108 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 109 /*queue_type: normal compute queue */ 110 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 111 /* alloc format: all_on_one_pipe */ 112 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 113 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 114 /* num_queues: must be 1 */ 115 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 116 amdgpu_ring_write(kiq_ring, 117 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 118 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 119 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 120 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 121 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 122 } 123 124 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 125 struct amdgpu_ring *ring, 126 enum amdgpu_unmap_queues_action action, 127 u64 gpu_addr, u64 seq) 128 { 129 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 130 131 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 132 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 133 PACKET3_UNMAP_QUEUES_ACTION(action) | 134 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 135 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 136 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 137 amdgpu_ring_write(kiq_ring, 138 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 139 140 if (action == PREEMPT_QUEUES_NO_UNMAP) { 141 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 142 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 143 amdgpu_ring_write(kiq_ring, seq); 144 } else { 145 amdgpu_ring_write(kiq_ring, 0); 146 amdgpu_ring_write(kiq_ring, 0); 147 amdgpu_ring_write(kiq_ring, 0); 148 } 149 } 150 151 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 152 struct amdgpu_ring *ring, 153 u64 addr, 154 u64 seq) 155 { 156 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 157 158 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 159 amdgpu_ring_write(kiq_ring, 160 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 161 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 162 PACKET3_QUERY_STATUS_COMMAND(2)); 163 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 164 amdgpu_ring_write(kiq_ring, 165 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 166 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 167 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 168 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 169 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 170 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 171 } 172 173 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 174 uint16_t pasid, uint32_t flush_type, 175 bool all_hub) 176 { 177 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 178 amdgpu_ring_write(kiq_ring, 179 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 180 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 181 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 182 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 183 } 184 185 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 186 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 187 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 188 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 189 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 190 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 191 .set_resources_size = 8, 192 .map_queues_size = 7, 193 .unmap_queues_size = 6, 194 .query_status_size = 7, 195 .invalidate_tlbs_size = 2, 196 }; 197 198 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 199 { 200 int i, num_xcc; 201 202 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 203 for (i = 0; i < num_xcc; i++) 204 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 205 } 206 207 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 208 { 209 int i, num_xcc, dev_inst; 210 211 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 212 for (i = 0; i < num_xcc; i++) { 213 dev_inst = GET_INST(GC, i); 214 215 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 216 GOLDEN_GB_ADDR_CONFIG); 217 /* Golden settings applied by driver for ASIC with rev_id 0 */ 218 if (adev->rev_id == 0) { 219 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 220 REDUCE_FIFO_DEPTH_BY_2, 2); 221 } else { 222 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 223 SPARE, 0x1); 224 } 225 } 226 } 227 228 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 229 { 230 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 231 232 /* If it is an XCC reg, normalize the reg to keep 233 lower 16 bits in local xcc */ 234 235 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 236 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 237 return normalized_reg; 238 else 239 return reg; 240 } 241 242 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 243 bool wc, uint32_t reg, uint32_t val) 244 { 245 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 246 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 247 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 248 WRITE_DATA_DST_SEL(0) | 249 (wc ? WR_CONFIRM : 0)); 250 amdgpu_ring_write(ring, reg); 251 amdgpu_ring_write(ring, 0); 252 amdgpu_ring_write(ring, val); 253 } 254 255 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 256 int mem_space, int opt, uint32_t addr0, 257 uint32_t addr1, uint32_t ref, uint32_t mask, 258 uint32_t inv) 259 { 260 /* Only do the normalization on regspace */ 261 if (mem_space == 0) { 262 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 263 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 264 } 265 266 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 267 amdgpu_ring_write(ring, 268 /* memory (1) or register (0) */ 269 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 270 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 271 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 272 WAIT_REG_MEM_ENGINE(eng_sel))); 273 274 if (mem_space) 275 BUG_ON(addr0 & 0x3); /* Dword align */ 276 amdgpu_ring_write(ring, addr0); 277 amdgpu_ring_write(ring, addr1); 278 amdgpu_ring_write(ring, ref); 279 amdgpu_ring_write(ring, mask); 280 amdgpu_ring_write(ring, inv); /* poll interval */ 281 } 282 283 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 284 { 285 uint32_t scratch_reg0_offset, xcc_offset; 286 struct amdgpu_device *adev = ring->adev; 287 uint32_t tmp = 0; 288 unsigned i; 289 int r; 290 291 /* Use register offset which is local to XCC in the packet */ 292 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 293 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 294 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 295 tmp = RREG32(scratch_reg0_offset); 296 297 r = amdgpu_ring_alloc(ring, 3); 298 if (r) 299 return r; 300 301 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 302 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 303 amdgpu_ring_write(ring, 0xDEADBEEF); 304 amdgpu_ring_commit(ring); 305 306 for (i = 0; i < adev->usec_timeout; i++) { 307 tmp = RREG32(scratch_reg0_offset); 308 if (tmp == 0xDEADBEEF) 309 break; 310 udelay(1); 311 } 312 313 if (i >= adev->usec_timeout) 314 r = -ETIMEDOUT; 315 return r; 316 } 317 318 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 319 { 320 struct amdgpu_device *adev = ring->adev; 321 struct amdgpu_ib ib; 322 struct dma_fence *f = NULL; 323 324 unsigned index; 325 uint64_t gpu_addr; 326 uint32_t tmp; 327 long r; 328 329 r = amdgpu_device_wb_get(adev, &index); 330 if (r) 331 return r; 332 333 gpu_addr = adev->wb.gpu_addr + (index * 4); 334 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 335 memset(&ib, 0, sizeof(ib)); 336 337 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 338 if (r) 339 goto err1; 340 341 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 342 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 343 ib.ptr[2] = lower_32_bits(gpu_addr); 344 ib.ptr[3] = upper_32_bits(gpu_addr); 345 ib.ptr[4] = 0xDEADBEEF; 346 ib.length_dw = 5; 347 348 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 349 if (r) 350 goto err2; 351 352 r = dma_fence_wait_timeout(f, false, timeout); 353 if (r == 0) { 354 r = -ETIMEDOUT; 355 goto err2; 356 } else if (r < 0) { 357 goto err2; 358 } 359 360 tmp = adev->wb.wb[index]; 361 if (tmp == 0xDEADBEEF) 362 r = 0; 363 else 364 r = -EINVAL; 365 366 err2: 367 amdgpu_ib_free(adev, &ib, NULL); 368 dma_fence_put(f); 369 err1: 370 amdgpu_device_wb_free(adev, index); 371 return r; 372 } 373 374 375 /* This value might differs per partition */ 376 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 377 { 378 uint64_t clock; 379 380 mutex_lock(&adev->gfx.gpu_clock_mutex); 381 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 382 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 383 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 384 mutex_unlock(&adev->gfx.gpu_clock_mutex); 385 386 return clock; 387 } 388 389 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 390 { 391 amdgpu_ucode_release(&adev->gfx.pfp_fw); 392 amdgpu_ucode_release(&adev->gfx.me_fw); 393 amdgpu_ucode_release(&adev->gfx.ce_fw); 394 amdgpu_ucode_release(&adev->gfx.rlc_fw); 395 amdgpu_ucode_release(&adev->gfx.mec_fw); 396 amdgpu_ucode_release(&adev->gfx.mec2_fw); 397 398 kfree(adev->gfx.rlc.register_list_format); 399 } 400 401 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 402 const char *chip_name) 403 { 404 int err; 405 const struct rlc_firmware_header_v2_0 *rlc_hdr; 406 uint16_t version_major; 407 uint16_t version_minor; 408 409 410 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 411 "amdgpu/%s_rlc.bin", chip_name); 412 if (err) 413 goto out; 414 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 415 416 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 417 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 418 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 419 out: 420 if (err) 421 amdgpu_ucode_release(&adev->gfx.rlc_fw); 422 423 return err; 424 } 425 426 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 427 { 428 return true; 429 } 430 431 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 432 { 433 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 434 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 435 } 436 437 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 438 const char *chip_name) 439 { 440 int err; 441 442 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 443 "amdgpu/%s_mec.bin", chip_name); 444 if (err) 445 goto out; 446 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 447 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 448 449 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 450 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 451 452 gfx_v9_4_3_check_if_need_gfxoff(adev); 453 454 out: 455 if (err) 456 amdgpu_ucode_release(&adev->gfx.mec_fw); 457 return err; 458 } 459 460 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 461 { 462 char ucode_prefix[15]; 463 int r; 464 465 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 466 467 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 468 if (r) 469 return r; 470 471 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 472 if (r) 473 return r; 474 475 return r; 476 } 477 478 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 479 { 480 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 481 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 482 } 483 484 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 485 { 486 int r, i, num_xcc; 487 u32 *hpd; 488 const __le32 *fw_data; 489 unsigned fw_size; 490 u32 *fw; 491 size_t mec_hpd_size; 492 493 const struct gfx_firmware_header_v1_0 *mec_hdr; 494 495 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 496 for (i = 0; i < num_xcc; i++) 497 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 498 AMDGPU_MAX_COMPUTE_QUEUES); 499 500 /* take ownership of the relevant compute queues */ 501 amdgpu_gfx_compute_queue_acquire(adev); 502 mec_hpd_size = 503 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 504 if (mec_hpd_size) { 505 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 506 AMDGPU_GEM_DOMAIN_VRAM | 507 AMDGPU_GEM_DOMAIN_GTT, 508 &adev->gfx.mec.hpd_eop_obj, 509 &adev->gfx.mec.hpd_eop_gpu_addr, 510 (void **)&hpd); 511 if (r) { 512 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 513 gfx_v9_4_3_mec_fini(adev); 514 return r; 515 } 516 517 if (amdgpu_emu_mode == 1) { 518 for (i = 0; i < mec_hpd_size / 4; i++) { 519 memset((void *)(hpd + i), 0, 4); 520 if (i % 50 == 0) 521 msleep(1); 522 } 523 } else { 524 memset(hpd, 0, mec_hpd_size); 525 } 526 527 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 528 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 529 } 530 531 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 532 533 fw_data = (const __le32 *) 534 (adev->gfx.mec_fw->data + 535 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 536 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 537 538 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 539 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 540 &adev->gfx.mec.mec_fw_obj, 541 &adev->gfx.mec.mec_fw_gpu_addr, 542 (void **)&fw); 543 if (r) { 544 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 545 gfx_v9_4_3_mec_fini(adev); 546 return r; 547 } 548 549 memcpy(fw, fw_data, fw_size); 550 551 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 552 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 553 554 return 0; 555 } 556 557 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 558 u32 sh_num, u32 instance, int xcc_id) 559 { 560 u32 data; 561 562 if (instance == 0xffffffff) 563 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 564 INSTANCE_BROADCAST_WRITES, 1); 565 else 566 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 567 INSTANCE_INDEX, instance); 568 569 if (se_num == 0xffffffff) 570 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 571 SE_BROADCAST_WRITES, 1); 572 else 573 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 574 575 if (sh_num == 0xffffffff) 576 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 577 SH_BROADCAST_WRITES, 1); 578 else 579 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 580 581 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 582 } 583 584 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 585 { 586 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 587 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 588 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 589 (address << SQ_IND_INDEX__INDEX__SHIFT) | 590 (SQ_IND_INDEX__FORCE_READ_MASK)); 591 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 592 } 593 594 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 595 uint32_t wave, uint32_t thread, 596 uint32_t regno, uint32_t num, uint32_t *out) 597 { 598 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 599 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 600 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 601 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 602 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 603 (SQ_IND_INDEX__FORCE_READ_MASK) | 604 (SQ_IND_INDEX__AUTO_INCR_MASK)); 605 while (num--) 606 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 607 } 608 609 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 610 uint32_t xcc_id, uint32_t simd, uint32_t wave, 611 uint32_t *dst, int *no_fields) 612 { 613 /* type 1 wave data */ 614 dst[(*no_fields)++] = 1; 615 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 616 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 617 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 618 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 619 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 620 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 621 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 622 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 623 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 624 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 625 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 626 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 627 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 628 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 629 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 630 } 631 632 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 633 uint32_t wave, uint32_t start, 634 uint32_t size, uint32_t *dst) 635 { 636 wave_read_regs(adev, xcc_id, simd, wave, 0, 637 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 638 } 639 640 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 641 uint32_t wave, uint32_t thread, 642 uint32_t start, uint32_t size, 643 uint32_t *dst) 644 { 645 wave_read_regs(adev, xcc_id, simd, wave, thread, 646 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 647 } 648 649 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 650 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 651 { 652 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 653 } 654 655 656 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 657 int num_xccs_per_xcp) 658 { 659 int ret, i, num_xcc; 660 u32 tmp = 0; 661 662 if (adev->psp.funcs) { 663 ret = psp_spatial_partition(&adev->psp, 664 NUM_XCC(adev->gfx.xcc_mask) / 665 num_xccs_per_xcp); 666 if (ret) 667 return ret; 668 } else { 669 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 670 671 for (i = 0; i < num_xcc; i++) { 672 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 673 num_xccs_per_xcp); 674 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 675 i % num_xccs_per_xcp); 676 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 677 tmp); 678 } 679 ret = 0; 680 } 681 682 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 683 684 return ret; 685 } 686 687 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 688 { 689 int xcc; 690 691 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 692 if (!xcc) { 693 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 694 return -EINVAL; 695 } 696 697 return xcc - 1; 698 } 699 700 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 701 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 702 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 703 .read_wave_data = &gfx_v9_4_3_read_wave_data, 704 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 705 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 706 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 707 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 708 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 709 }; 710 711 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 712 struct aca_bank *bank, enum aca_smu_type type, 713 void *data) 714 { 715 struct aca_bank_info info; 716 u64 misc0; 717 u32 instlo; 718 int ret; 719 720 ret = aca_bank_info_decode(bank, &info); 721 if (ret) 722 return ret; 723 724 /* NOTE: overwrite info.die_id with xcd id for gfx */ 725 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 726 instlo &= GENMASK(31, 1); 727 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 728 729 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 730 731 switch (type) { 732 case ACA_SMU_TYPE_UE: 733 ret = aca_error_cache_log_bank_error(handle, &info, 734 ACA_ERROR_TYPE_UE, 1ULL); 735 break; 736 case ACA_SMU_TYPE_CE: 737 ret = aca_error_cache_log_bank_error(handle, &info, 738 ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0)); 739 break; 740 default: 741 return -EINVAL; 742 } 743 744 return ret; 745 } 746 747 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 748 enum aca_smu_type type, void *data) 749 { 750 u32 instlo; 751 752 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 753 instlo &= GENMASK(31, 1); 754 switch (instlo) { 755 case mmSMNAID_XCD0_MCA_SMU: 756 case mmSMNAID_XCD1_MCA_SMU: 757 case mmSMNXCD_XCD0_MCA_SMU: 758 return true; 759 default: 760 break; 761 } 762 763 return false; 764 } 765 766 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 767 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 768 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 769 }; 770 771 static const struct aca_info gfx_v9_4_3_aca_info = { 772 .hwip = ACA_HWIP_TYPE_SMU, 773 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 774 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 775 }; 776 777 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 778 { 779 u32 gb_addr_config; 780 781 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 782 adev->gfx.ras = &gfx_v9_4_3_ras; 783 784 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 785 case IP_VERSION(9, 4, 3): 786 case IP_VERSION(9, 4, 4): 787 adev->gfx.config.max_hw_contexts = 8; 788 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 789 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 790 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 791 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 792 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 793 break; 794 default: 795 BUG(); 796 break; 797 } 798 799 adev->gfx.config.gb_addr_config = gb_addr_config; 800 801 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 802 REG_GET_FIELD( 803 adev->gfx.config.gb_addr_config, 804 GB_ADDR_CONFIG, 805 NUM_PIPES); 806 807 adev->gfx.config.max_tile_pipes = 808 adev->gfx.config.gb_addr_config_fields.num_pipes; 809 810 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 811 REG_GET_FIELD( 812 adev->gfx.config.gb_addr_config, 813 GB_ADDR_CONFIG, 814 NUM_BANKS); 815 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 816 REG_GET_FIELD( 817 adev->gfx.config.gb_addr_config, 818 GB_ADDR_CONFIG, 819 MAX_COMPRESSED_FRAGS); 820 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 821 REG_GET_FIELD( 822 adev->gfx.config.gb_addr_config, 823 GB_ADDR_CONFIG, 824 NUM_RB_PER_SE); 825 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 826 REG_GET_FIELD( 827 adev->gfx.config.gb_addr_config, 828 GB_ADDR_CONFIG, 829 NUM_SHADER_ENGINES); 830 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 831 REG_GET_FIELD( 832 adev->gfx.config.gb_addr_config, 833 GB_ADDR_CONFIG, 834 PIPE_INTERLEAVE_SIZE)); 835 836 return 0; 837 } 838 839 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 840 int xcc_id, int mec, int pipe, int queue) 841 { 842 unsigned irq_type; 843 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 844 unsigned int hw_prio; 845 uint32_t xcc_doorbell_start; 846 847 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 848 ring_id]; 849 850 /* mec0 is me1 */ 851 ring->xcc_id = xcc_id; 852 ring->me = mec + 1; 853 ring->pipe = pipe; 854 ring->queue = queue; 855 856 ring->ring_obj = NULL; 857 ring->use_doorbell = true; 858 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 859 xcc_id * adev->doorbell_index.xcc_doorbell_range; 860 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 861 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 862 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 863 GFX9_MEC_HPD_SIZE; 864 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 865 sprintf(ring->name, "comp_%d.%d.%d.%d", 866 ring->xcc_id, ring->me, ring->pipe, ring->queue); 867 868 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 869 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 870 + ring->pipe; 871 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 872 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 873 /* type-2 packets are deprecated on MEC, use type-3 instead */ 874 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 875 hw_prio, NULL); 876 } 877 878 static int gfx_v9_4_3_sw_init(void *handle) 879 { 880 int i, j, k, r, ring_id, xcc_id, num_xcc; 881 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 882 883 adev->gfx.mec.num_mec = 2; 884 adev->gfx.mec.num_pipe_per_mec = 4; 885 adev->gfx.mec.num_queue_per_pipe = 8; 886 887 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 888 889 /* EOP Event */ 890 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 891 if (r) 892 return r; 893 894 /* Privileged reg */ 895 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 896 &adev->gfx.priv_reg_irq); 897 if (r) 898 return r; 899 900 /* Privileged inst */ 901 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 902 &adev->gfx.priv_inst_irq); 903 if (r) 904 return r; 905 906 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 907 908 r = adev->gfx.rlc.funcs->init(adev); 909 if (r) { 910 DRM_ERROR("Failed to init rlc BOs!\n"); 911 return r; 912 } 913 914 r = gfx_v9_4_3_mec_init(adev); 915 if (r) { 916 DRM_ERROR("Failed to init MEC BOs!\n"); 917 return r; 918 } 919 920 /* set up the compute queues - allocate horizontally across pipes */ 921 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 922 ring_id = 0; 923 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 924 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 925 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 926 k++) { 927 if (!amdgpu_gfx_is_mec_queue_enabled( 928 adev, xcc_id, i, k, j)) 929 continue; 930 931 r = gfx_v9_4_3_compute_ring_init(adev, 932 ring_id, 933 xcc_id, 934 i, k, j); 935 if (r) 936 return r; 937 938 ring_id++; 939 } 940 } 941 } 942 943 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 944 if (r) { 945 DRM_ERROR("Failed to init KIQ BOs!\n"); 946 return r; 947 } 948 949 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 950 if (r) 951 return r; 952 953 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 954 r = amdgpu_gfx_mqd_sw_init(adev, 955 sizeof(struct v9_mqd_allocation), xcc_id); 956 if (r) 957 return r; 958 } 959 960 r = gfx_v9_4_3_gpu_early_init(adev); 961 if (r) 962 return r; 963 964 r = amdgpu_gfx_ras_sw_init(adev); 965 if (r) 966 return r; 967 968 969 if (!amdgpu_sriov_vf(adev)) 970 r = amdgpu_gfx_sysfs_init(adev); 971 972 return r; 973 } 974 975 static int gfx_v9_4_3_sw_fini(void *handle) 976 { 977 int i, num_xcc; 978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 979 980 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 981 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 982 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 983 984 for (i = 0; i < num_xcc; i++) { 985 amdgpu_gfx_mqd_sw_fini(adev, i); 986 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 987 amdgpu_gfx_kiq_fini(adev, i); 988 } 989 990 gfx_v9_4_3_mec_fini(adev); 991 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 992 gfx_v9_4_3_free_microcode(adev); 993 if (!amdgpu_sriov_vf(adev)) 994 amdgpu_gfx_sysfs_fini(adev); 995 996 return 0; 997 } 998 999 #define DEFAULT_SH_MEM_BASES (0x6000) 1000 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1001 int xcc_id) 1002 { 1003 int i; 1004 uint32_t sh_mem_config; 1005 uint32_t sh_mem_bases; 1006 uint32_t data; 1007 1008 /* 1009 * Configure apertures: 1010 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1011 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1012 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1013 */ 1014 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1015 1016 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1017 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1018 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1019 1020 mutex_lock(&adev->srbm_mutex); 1021 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1022 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1023 /* CP and shaders */ 1024 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1025 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1026 1027 /* Enable trap for each kfd vmid. */ 1028 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1029 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1030 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1031 } 1032 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1033 mutex_unlock(&adev->srbm_mutex); 1034 1035 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1036 acccess. These should be enabled by FW for target VMIDs. */ 1037 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1038 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1039 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1040 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1041 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1042 } 1043 } 1044 1045 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1046 { 1047 int vmid; 1048 1049 /* 1050 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1051 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1052 * the driver can enable them for graphics. VMID0 should maintain 1053 * access so that HWS firmware can save/restore entries. 1054 */ 1055 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1056 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1057 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1058 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1059 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1060 } 1061 } 1062 1063 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1064 int xcc_id) 1065 { 1066 u32 tmp; 1067 int i; 1068 1069 /* XXX SH_MEM regs */ 1070 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1071 mutex_lock(&adev->srbm_mutex); 1072 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1073 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1074 /* CP and shaders */ 1075 if (i == 0) { 1076 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1077 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1078 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1079 !!adev->gmc.noretry); 1080 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1081 regSH_MEM_CONFIG, tmp); 1082 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1083 regSH_MEM_BASES, 0); 1084 } else { 1085 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1086 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1087 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1088 !!adev->gmc.noretry); 1089 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1090 regSH_MEM_CONFIG, tmp); 1091 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1092 (adev->gmc.private_aperture_start >> 1093 48)); 1094 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1095 (adev->gmc.shared_aperture_start >> 1096 48)); 1097 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1098 regSH_MEM_BASES, tmp); 1099 } 1100 } 1101 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1102 1103 mutex_unlock(&adev->srbm_mutex); 1104 1105 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1106 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1107 } 1108 1109 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1110 { 1111 int i, num_xcc; 1112 1113 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1114 1115 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1116 adev->gfx.config.db_debug2 = 1117 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1118 1119 for (i = 0; i < num_xcc; i++) 1120 gfx_v9_4_3_xcc_constants_init(adev, i); 1121 } 1122 1123 static void 1124 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1125 int xcc_id) 1126 { 1127 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1128 } 1129 1130 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1131 { 1132 /* 1133 * Rlc save restore list is workable since v2_1. 1134 * And it's needed by gfxoff feature. 1135 */ 1136 if (adev->gfx.rlc.is_rlc_v2_1) 1137 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1138 } 1139 1140 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1141 { 1142 uint32_t data; 1143 1144 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1145 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1146 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1147 } 1148 1149 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1150 { 1151 uint32_t rlc_setting; 1152 1153 /* if RLC is not enabled, do nothing */ 1154 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1155 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1156 return false; 1157 1158 return true; 1159 } 1160 1161 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1162 { 1163 uint32_t data; 1164 unsigned i; 1165 1166 data = RLC_SAFE_MODE__CMD_MASK; 1167 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1168 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1169 1170 /* wait for RLC_SAFE_MODE */ 1171 for (i = 0; i < adev->usec_timeout; i++) { 1172 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1173 break; 1174 udelay(1); 1175 } 1176 } 1177 1178 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1179 int xcc_id) 1180 { 1181 uint32_t data; 1182 1183 data = RLC_SAFE_MODE__CMD_MASK; 1184 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1185 } 1186 1187 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1188 { 1189 int xcc_id, num_xcc; 1190 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1191 1192 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1193 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1194 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1195 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1196 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1197 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1198 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1199 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1200 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1201 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1202 } 1203 adev->gfx.rlc.rlcg_reg_access_supported = true; 1204 } 1205 1206 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1207 { 1208 /* init spm vmid with 0xf */ 1209 if (adev->gfx.rlc.funcs->update_spm_vmid) 1210 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1211 1212 return 0; 1213 } 1214 1215 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1216 int xcc_id) 1217 { 1218 u32 i, j, k; 1219 u32 mask; 1220 1221 mutex_lock(&adev->grbm_idx_mutex); 1222 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1223 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1224 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1225 xcc_id); 1226 for (k = 0; k < adev->usec_timeout; k++) { 1227 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1228 break; 1229 udelay(1); 1230 } 1231 if (k == adev->usec_timeout) { 1232 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1233 0xffffffff, 1234 0xffffffff, xcc_id); 1235 mutex_unlock(&adev->grbm_idx_mutex); 1236 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1237 i, j); 1238 return; 1239 } 1240 } 1241 } 1242 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1243 xcc_id); 1244 mutex_unlock(&adev->grbm_idx_mutex); 1245 1246 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1247 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1248 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1249 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1250 for (k = 0; k < adev->usec_timeout; k++) { 1251 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1252 break; 1253 udelay(1); 1254 } 1255 } 1256 1257 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1258 bool enable, int xcc_id) 1259 { 1260 u32 tmp; 1261 1262 /* These interrupts should be enabled to drive DS clock */ 1263 1264 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1265 1266 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1267 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1268 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1269 1270 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1271 } 1272 1273 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1274 { 1275 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1276 RLC_ENABLE_F32, 0); 1277 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1278 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1279 } 1280 1281 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1282 { 1283 int i, num_xcc; 1284 1285 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1286 for (i = 0; i < num_xcc; i++) 1287 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1288 } 1289 1290 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1291 { 1292 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1293 SOFT_RESET_RLC, 1); 1294 udelay(50); 1295 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1296 SOFT_RESET_RLC, 0); 1297 udelay(50); 1298 } 1299 1300 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1301 { 1302 int i, num_xcc; 1303 1304 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1305 for (i = 0; i < num_xcc; i++) 1306 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1307 } 1308 1309 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1310 { 1311 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1312 RLC_ENABLE_F32, 1); 1313 udelay(50); 1314 1315 /* carrizo do enable cp interrupt after cp inited */ 1316 if (!(adev->flags & AMD_IS_APU)) { 1317 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1318 udelay(50); 1319 } 1320 } 1321 1322 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1323 { 1324 #ifdef AMDGPU_RLC_DEBUG_RETRY 1325 u32 rlc_ucode_ver; 1326 #endif 1327 int i, num_xcc; 1328 1329 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1330 for (i = 0; i < num_xcc; i++) { 1331 gfx_v9_4_3_xcc_rlc_start(adev, i); 1332 #ifdef AMDGPU_RLC_DEBUG_RETRY 1333 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1334 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1335 if (rlc_ucode_ver == 0x108) { 1336 dev_info(adev->dev, 1337 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1338 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1339 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1340 * default is 0x9C4 to create a 100us interval */ 1341 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1342 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1343 * to disable the page fault retry interrupts, default is 1344 * 0x100 (256) */ 1345 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1346 } 1347 #endif 1348 } 1349 } 1350 1351 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1352 int xcc_id) 1353 { 1354 const struct rlc_firmware_header_v2_0 *hdr; 1355 const __le32 *fw_data; 1356 unsigned i, fw_size; 1357 1358 if (!adev->gfx.rlc_fw) 1359 return -EINVAL; 1360 1361 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1362 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1363 1364 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1365 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1366 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1367 1368 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1369 RLCG_UCODE_LOADING_START_ADDRESS); 1370 for (i = 0; i < fw_size; i++) { 1371 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1372 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1373 msleep(1); 1374 } 1375 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1376 } 1377 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1378 1379 return 0; 1380 } 1381 1382 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1383 { 1384 int r; 1385 1386 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1387 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1388 /* legacy rlc firmware loading */ 1389 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1390 if (r) 1391 return r; 1392 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1393 } 1394 1395 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1396 /* disable CG */ 1397 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1398 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1399 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1400 1401 return 0; 1402 } 1403 1404 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1405 { 1406 int r, i, num_xcc; 1407 1408 if (amdgpu_sriov_vf(adev)) 1409 return 0; 1410 1411 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1412 for (i = 0; i < num_xcc; i++) { 1413 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1414 if (r) 1415 return r; 1416 } 1417 1418 return 0; 1419 } 1420 1421 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1422 unsigned vmid) 1423 { 1424 u32 reg, pre_data, data; 1425 1426 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1427 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1428 pre_data = RREG32_NO_KIQ(reg); 1429 else 1430 pre_data = RREG32(reg); 1431 1432 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1433 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1434 1435 if (pre_data != data) { 1436 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1437 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1438 } else 1439 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1440 } 1441 } 1442 1443 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1444 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1445 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1446 }; 1447 1448 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1449 uint32_t offset, 1450 struct soc15_reg_rlcg *entries, int arr_size) 1451 { 1452 int i, inst; 1453 uint32_t reg; 1454 1455 if (!entries) 1456 return false; 1457 1458 for (i = 0; i < arr_size; i++) { 1459 const struct soc15_reg_rlcg *entry; 1460 1461 entry = &entries[i]; 1462 inst = adev->ip_map.logical_to_dev_inst ? 1463 adev->ip_map.logical_to_dev_inst( 1464 adev, entry->hwip, entry->instance) : 1465 entry->instance; 1466 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1467 entry->reg; 1468 if (offset == reg) 1469 return true; 1470 } 1471 1472 return false; 1473 } 1474 1475 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1476 { 1477 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1478 (void *)rlcg_access_gc_9_4_3, 1479 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1480 } 1481 1482 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1483 bool enable, int xcc_id) 1484 { 1485 if (enable) { 1486 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1487 } else { 1488 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1489 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1490 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1491 } 1492 udelay(50); 1493 } 1494 1495 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1496 int xcc_id) 1497 { 1498 const struct gfx_firmware_header_v1_0 *mec_hdr; 1499 const __le32 *fw_data; 1500 unsigned i; 1501 u32 tmp; 1502 u32 mec_ucode_addr_offset; 1503 u32 mec_ucode_data_offset; 1504 1505 if (!adev->gfx.mec_fw) 1506 return -EINVAL; 1507 1508 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1509 1510 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1511 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1512 1513 fw_data = (const __le32 *) 1514 (adev->gfx.mec_fw->data + 1515 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1516 tmp = 0; 1517 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1518 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1519 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1520 1521 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1522 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1523 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1524 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1525 1526 mec_ucode_addr_offset = 1527 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1528 mec_ucode_data_offset = 1529 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1530 1531 /* MEC1 */ 1532 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1533 for (i = 0; i < mec_hdr->jt_size; i++) 1534 WREG32(mec_ucode_data_offset, 1535 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1536 1537 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1538 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1539 1540 return 0; 1541 } 1542 1543 /* KIQ functions */ 1544 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1545 { 1546 uint32_t tmp; 1547 struct amdgpu_device *adev = ring->adev; 1548 1549 /* tell RLC which is KIQ queue */ 1550 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1551 tmp &= 0xffffff00; 1552 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1553 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1554 tmp |= 0x80; 1555 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1556 } 1557 1558 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1559 { 1560 struct amdgpu_device *adev = ring->adev; 1561 1562 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1563 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1564 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1565 mqd->cp_hqd_queue_priority = 1566 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1567 } 1568 } 1569 } 1570 1571 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1572 { 1573 struct amdgpu_device *adev = ring->adev; 1574 struct v9_mqd *mqd = ring->mqd_ptr; 1575 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1576 uint32_t tmp; 1577 1578 mqd->header = 0xC0310800; 1579 mqd->compute_pipelinestat_enable = 0x00000001; 1580 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1581 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1582 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1583 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1584 mqd->compute_misc_reserved = 0x00000003; 1585 1586 mqd->dynamic_cu_mask_addr_lo = 1587 lower_32_bits(ring->mqd_gpu_addr 1588 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1589 mqd->dynamic_cu_mask_addr_hi = 1590 upper_32_bits(ring->mqd_gpu_addr 1591 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1592 1593 eop_base_addr = ring->eop_gpu_addr >> 8; 1594 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1595 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1596 1597 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1598 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1599 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1600 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1601 1602 mqd->cp_hqd_eop_control = tmp; 1603 1604 /* enable doorbell? */ 1605 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1606 1607 if (ring->use_doorbell) { 1608 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1609 DOORBELL_OFFSET, ring->doorbell_index); 1610 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1611 DOORBELL_EN, 1); 1612 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1613 DOORBELL_SOURCE, 0); 1614 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1615 DOORBELL_HIT, 0); 1616 } else { 1617 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1618 DOORBELL_EN, 0); 1619 } 1620 1621 mqd->cp_hqd_pq_doorbell_control = tmp; 1622 1623 /* disable the queue if it's active */ 1624 ring->wptr = 0; 1625 mqd->cp_hqd_dequeue_request = 0; 1626 mqd->cp_hqd_pq_rptr = 0; 1627 mqd->cp_hqd_pq_wptr_lo = 0; 1628 mqd->cp_hqd_pq_wptr_hi = 0; 1629 1630 /* set the pointer to the MQD */ 1631 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1632 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1633 1634 /* set MQD vmid to 0 */ 1635 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1636 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1637 mqd->cp_mqd_control = tmp; 1638 1639 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1640 hqd_gpu_addr = ring->gpu_addr >> 8; 1641 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1642 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1643 1644 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1645 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1646 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1647 (order_base_2(ring->ring_size / 4) - 1)); 1648 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1649 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1650 #ifdef __BIG_ENDIAN 1651 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1652 #endif 1653 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1654 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1655 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1656 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1657 mqd->cp_hqd_pq_control = tmp; 1658 1659 /* set the wb address whether it's enabled or not */ 1660 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1661 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1662 mqd->cp_hqd_pq_rptr_report_addr_hi = 1663 upper_32_bits(wb_gpu_addr) & 0xffff; 1664 1665 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1666 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1667 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1668 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1669 1670 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1671 ring->wptr = 0; 1672 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1673 1674 /* set the vmid for the queue */ 1675 mqd->cp_hqd_vmid = 0; 1676 1677 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1678 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1679 mqd->cp_hqd_persistent_state = tmp; 1680 1681 /* set MIN_IB_AVAIL_SIZE */ 1682 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1683 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1684 mqd->cp_hqd_ib_control = tmp; 1685 1686 /* set static priority for a queue/ring */ 1687 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1688 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1689 1690 /* map_queues packet doesn't need activate the queue, 1691 * so only kiq need set this field. 1692 */ 1693 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1694 mqd->cp_hqd_active = 1; 1695 1696 return 0; 1697 } 1698 1699 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1700 int xcc_id) 1701 { 1702 struct amdgpu_device *adev = ring->adev; 1703 struct v9_mqd *mqd = ring->mqd_ptr; 1704 int j; 1705 1706 /* disable wptr polling */ 1707 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1708 1709 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1710 mqd->cp_hqd_eop_base_addr_lo); 1711 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1712 mqd->cp_hqd_eop_base_addr_hi); 1713 1714 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1715 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1716 mqd->cp_hqd_eop_control); 1717 1718 /* enable doorbell? */ 1719 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1720 mqd->cp_hqd_pq_doorbell_control); 1721 1722 /* disable the queue if it's active */ 1723 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1724 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1725 for (j = 0; j < adev->usec_timeout; j++) { 1726 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1727 break; 1728 udelay(1); 1729 } 1730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1731 mqd->cp_hqd_dequeue_request); 1732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1733 mqd->cp_hqd_pq_rptr); 1734 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1735 mqd->cp_hqd_pq_wptr_lo); 1736 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1737 mqd->cp_hqd_pq_wptr_hi); 1738 } 1739 1740 /* set the pointer to the MQD */ 1741 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1742 mqd->cp_mqd_base_addr_lo); 1743 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1744 mqd->cp_mqd_base_addr_hi); 1745 1746 /* set MQD vmid to 0 */ 1747 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1748 mqd->cp_mqd_control); 1749 1750 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1751 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1752 mqd->cp_hqd_pq_base_lo); 1753 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1754 mqd->cp_hqd_pq_base_hi); 1755 1756 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1757 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1758 mqd->cp_hqd_pq_control); 1759 1760 /* set the wb address whether it's enabled or not */ 1761 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1762 mqd->cp_hqd_pq_rptr_report_addr_lo); 1763 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1764 mqd->cp_hqd_pq_rptr_report_addr_hi); 1765 1766 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1767 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1768 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1769 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1770 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1771 1772 /* enable the doorbell if requested */ 1773 if (ring->use_doorbell) { 1774 WREG32_SOC15( 1775 GC, GET_INST(GC, xcc_id), 1776 regCP_MEC_DOORBELL_RANGE_LOWER, 1777 ((adev->doorbell_index.kiq + 1778 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1779 2) << 2); 1780 WREG32_SOC15( 1781 GC, GET_INST(GC, xcc_id), 1782 regCP_MEC_DOORBELL_RANGE_UPPER, 1783 ((adev->doorbell_index.userqueue_end + 1784 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1785 2) << 2); 1786 } 1787 1788 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1789 mqd->cp_hqd_pq_doorbell_control); 1790 1791 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1792 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1793 mqd->cp_hqd_pq_wptr_lo); 1794 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1795 mqd->cp_hqd_pq_wptr_hi); 1796 1797 /* set the vmid for the queue */ 1798 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1799 1800 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1801 mqd->cp_hqd_persistent_state); 1802 1803 /* activate the queue */ 1804 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1805 mqd->cp_hqd_active); 1806 1807 if (ring->use_doorbell) 1808 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1809 1810 return 0; 1811 } 1812 1813 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1814 int xcc_id) 1815 { 1816 struct amdgpu_device *adev = ring->adev; 1817 int j; 1818 1819 /* disable the queue if it's active */ 1820 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1821 1822 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1823 1824 for (j = 0; j < adev->usec_timeout; j++) { 1825 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1826 break; 1827 udelay(1); 1828 } 1829 1830 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1831 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1832 1833 /* Manual disable if dequeue request times out */ 1834 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1835 } 1836 1837 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1838 0); 1839 } 1840 1841 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1842 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1843 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 1844 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1845 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1846 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1847 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1848 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1849 1850 return 0; 1851 } 1852 1853 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1854 { 1855 struct amdgpu_device *adev = ring->adev; 1856 struct v9_mqd *mqd = ring->mqd_ptr; 1857 struct v9_mqd *tmp_mqd; 1858 1859 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1860 1861 /* GPU could be in bad state during probe, driver trigger the reset 1862 * after load the SMU, in this case , the mqd is not be initialized. 1863 * driver need to re-init the mqd. 1864 * check mqd->cp_hqd_pq_control since this value should not be 0 1865 */ 1866 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1867 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1868 /* for GPU_RESET case , reset MQD to a clean status */ 1869 if (adev->gfx.kiq[xcc_id].mqd_backup) 1870 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1871 1872 /* reset ring buffer */ 1873 ring->wptr = 0; 1874 amdgpu_ring_clear_ring(ring); 1875 mutex_lock(&adev->srbm_mutex); 1876 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1877 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1878 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1879 mutex_unlock(&adev->srbm_mutex); 1880 } else { 1881 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1882 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1883 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1884 mutex_lock(&adev->srbm_mutex); 1885 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1886 amdgpu_ring_clear_ring(ring); 1887 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1888 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1889 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1890 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1891 mutex_unlock(&adev->srbm_mutex); 1892 1893 if (adev->gfx.kiq[xcc_id].mqd_backup) 1894 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1895 } 1896 1897 return 0; 1898 } 1899 1900 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1901 { 1902 struct amdgpu_device *adev = ring->adev; 1903 struct v9_mqd *mqd = ring->mqd_ptr; 1904 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1905 struct v9_mqd *tmp_mqd; 1906 1907 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1908 * is not be initialized before 1909 */ 1910 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1911 1912 if (!tmp_mqd->cp_hqd_pq_control || 1913 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1914 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1915 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1916 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1917 mutex_lock(&adev->srbm_mutex); 1918 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1919 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1920 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1921 mutex_unlock(&adev->srbm_mutex); 1922 1923 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1924 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1925 } else { 1926 /* restore MQD to a clean status */ 1927 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1928 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1929 /* reset ring buffer */ 1930 ring->wptr = 0; 1931 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1932 amdgpu_ring_clear_ring(ring); 1933 } 1934 1935 return 0; 1936 } 1937 1938 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1939 { 1940 struct amdgpu_ring *ring; 1941 int j; 1942 1943 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1944 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1945 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1946 mutex_lock(&adev->srbm_mutex); 1947 soc15_grbm_select(adev, ring->me, 1948 ring->pipe, 1949 ring->queue, 0, GET_INST(GC, xcc_id)); 1950 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1951 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1952 mutex_unlock(&adev->srbm_mutex); 1953 } 1954 } 1955 1956 return 0; 1957 } 1958 1959 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1960 { 1961 struct amdgpu_ring *ring; 1962 int r; 1963 1964 ring = &adev->gfx.kiq[xcc_id].ring; 1965 1966 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1967 if (unlikely(r != 0)) 1968 return r; 1969 1970 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1971 if (unlikely(r != 0)) { 1972 amdgpu_bo_unreserve(ring->mqd_obj); 1973 return r; 1974 } 1975 1976 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1977 amdgpu_bo_kunmap(ring->mqd_obj); 1978 ring->mqd_ptr = NULL; 1979 amdgpu_bo_unreserve(ring->mqd_obj); 1980 return 0; 1981 } 1982 1983 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1984 { 1985 struct amdgpu_ring *ring = NULL; 1986 int r = 0, i; 1987 1988 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1989 1990 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1991 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1992 1993 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1994 if (unlikely(r != 0)) 1995 goto done; 1996 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1997 if (!r) { 1998 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1999 amdgpu_bo_kunmap(ring->mqd_obj); 2000 ring->mqd_ptr = NULL; 2001 } 2002 amdgpu_bo_unreserve(ring->mqd_obj); 2003 if (r) 2004 goto done; 2005 } 2006 2007 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2008 done: 2009 return r; 2010 } 2011 2012 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2013 { 2014 struct amdgpu_ring *ring; 2015 int r, j; 2016 2017 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2018 2019 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2020 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2021 2022 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2023 if (r) 2024 return r; 2025 } 2026 2027 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2028 if (r) 2029 return r; 2030 2031 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2032 if (r) 2033 return r; 2034 2035 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2036 ring = &adev->gfx.compute_ring 2037 [j + xcc_id * adev->gfx.num_compute_rings]; 2038 r = amdgpu_ring_test_helper(ring); 2039 if (r) 2040 return r; 2041 } 2042 2043 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2044 2045 return 0; 2046 } 2047 2048 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2049 { 2050 int r = 0, i, num_xcc; 2051 2052 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2053 AMDGPU_XCP_FL_NONE) == 2054 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2055 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 2056 amdgpu_user_partt_mode); 2057 2058 if (r) 2059 return r; 2060 2061 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2062 for (i = 0; i < num_xcc; i++) { 2063 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2064 if (r) 2065 return r; 2066 } 2067 2068 return 0; 2069 } 2070 2071 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 2072 int xcc_id) 2073 { 2074 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 2075 } 2076 2077 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2078 { 2079 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2080 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2081 2082 if (amdgpu_sriov_vf(adev)) { 2083 /* must disable polling for SRIOV when hw finished, otherwise 2084 * CPC engine may still keep fetching WB address which is already 2085 * invalid after sw finished and trigger DMAR reading error in 2086 * hypervisor side. 2087 */ 2088 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2089 return; 2090 } 2091 2092 /* Use deinitialize sequence from CAIL when unbinding device 2093 * from driver, otherwise KIQ is hanging when binding back 2094 */ 2095 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2096 mutex_lock(&adev->srbm_mutex); 2097 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2098 adev->gfx.kiq[xcc_id].ring.pipe, 2099 adev->gfx.kiq[xcc_id].ring.queue, 0, 2100 GET_INST(GC, xcc_id)); 2101 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2102 xcc_id); 2103 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2104 mutex_unlock(&adev->srbm_mutex); 2105 } 2106 2107 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2108 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 2109 } 2110 2111 static int gfx_v9_4_3_hw_init(void *handle) 2112 { 2113 int r; 2114 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2115 2116 if (!amdgpu_sriov_vf(adev)) 2117 gfx_v9_4_3_init_golden_registers(adev); 2118 2119 gfx_v9_4_3_constants_init(adev); 2120 2121 r = adev->gfx.rlc.funcs->resume(adev); 2122 if (r) 2123 return r; 2124 2125 r = gfx_v9_4_3_cp_resume(adev); 2126 if (r) 2127 return r; 2128 2129 return r; 2130 } 2131 2132 static int gfx_v9_4_3_hw_fini(void *handle) 2133 { 2134 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2135 int i, num_xcc; 2136 2137 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2138 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2139 2140 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2141 for (i = 0; i < num_xcc; i++) { 2142 gfx_v9_4_3_xcc_fini(adev, i); 2143 } 2144 2145 return 0; 2146 } 2147 2148 static int gfx_v9_4_3_suspend(void *handle) 2149 { 2150 return gfx_v9_4_3_hw_fini(handle); 2151 } 2152 2153 static int gfx_v9_4_3_resume(void *handle) 2154 { 2155 return gfx_v9_4_3_hw_init(handle); 2156 } 2157 2158 static bool gfx_v9_4_3_is_idle(void *handle) 2159 { 2160 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2161 int i, num_xcc; 2162 2163 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2164 for (i = 0; i < num_xcc; i++) { 2165 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2166 GRBM_STATUS, GUI_ACTIVE)) 2167 return false; 2168 } 2169 return true; 2170 } 2171 2172 static int gfx_v9_4_3_wait_for_idle(void *handle) 2173 { 2174 unsigned i; 2175 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2176 2177 for (i = 0; i < adev->usec_timeout; i++) { 2178 if (gfx_v9_4_3_is_idle(handle)) 2179 return 0; 2180 udelay(1); 2181 } 2182 return -ETIMEDOUT; 2183 } 2184 2185 static int gfx_v9_4_3_soft_reset(void *handle) 2186 { 2187 u32 grbm_soft_reset = 0; 2188 u32 tmp; 2189 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2190 2191 /* GRBM_STATUS */ 2192 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2193 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2194 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2195 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2196 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2197 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2198 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2199 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2200 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2201 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2202 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2203 } 2204 2205 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2206 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2207 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2208 } 2209 2210 /* GRBM_STATUS2 */ 2211 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2212 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2213 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2214 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2215 2216 2217 if (grbm_soft_reset) { 2218 /* stop the rlc */ 2219 adev->gfx.rlc.funcs->stop(adev); 2220 2221 /* Disable MEC parsing/prefetching */ 2222 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2223 2224 if (grbm_soft_reset) { 2225 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2226 tmp |= grbm_soft_reset; 2227 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2228 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2229 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2230 2231 udelay(50); 2232 2233 tmp &= ~grbm_soft_reset; 2234 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2235 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2236 } 2237 2238 /* Wait a little for things to settle down */ 2239 udelay(50); 2240 } 2241 return 0; 2242 } 2243 2244 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2245 uint32_t vmid, 2246 uint32_t gds_base, uint32_t gds_size, 2247 uint32_t gws_base, uint32_t gws_size, 2248 uint32_t oa_base, uint32_t oa_size) 2249 { 2250 struct amdgpu_device *adev = ring->adev; 2251 2252 /* GDS Base */ 2253 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2254 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2255 gds_base); 2256 2257 /* GDS Size */ 2258 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2259 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2260 gds_size); 2261 2262 /* GWS */ 2263 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2264 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2265 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2266 2267 /* OA */ 2268 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2269 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2270 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2271 } 2272 2273 static int gfx_v9_4_3_early_init(void *handle) 2274 { 2275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2276 2277 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2278 AMDGPU_MAX_COMPUTE_RINGS); 2279 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2280 gfx_v9_4_3_set_ring_funcs(adev); 2281 gfx_v9_4_3_set_irq_funcs(adev); 2282 gfx_v9_4_3_set_gds_init(adev); 2283 gfx_v9_4_3_set_rlc_funcs(adev); 2284 2285 /* init rlcg reg access ctrl */ 2286 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2287 2288 return gfx_v9_4_3_init_microcode(adev); 2289 } 2290 2291 static int gfx_v9_4_3_late_init(void *handle) 2292 { 2293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2294 int r; 2295 2296 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2297 if (r) 2298 return r; 2299 2300 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2301 if (r) 2302 return r; 2303 2304 if (adev->gfx.ras && 2305 adev->gfx.ras->enable_watchdog_timer) 2306 adev->gfx.ras->enable_watchdog_timer(adev); 2307 2308 return 0; 2309 } 2310 2311 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2312 bool enable, int xcc_id) 2313 { 2314 uint32_t def, data; 2315 2316 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2317 return; 2318 2319 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2320 regRLC_CGTT_MGCG_OVERRIDE); 2321 2322 if (enable) 2323 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2324 else 2325 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2326 2327 if (def != data) 2328 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2329 regRLC_CGTT_MGCG_OVERRIDE, data); 2330 2331 } 2332 2333 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2334 bool enable, int xcc_id) 2335 { 2336 uint32_t def, data; 2337 2338 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2339 return; 2340 2341 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2342 regRLC_CGTT_MGCG_OVERRIDE); 2343 2344 if (enable) 2345 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2346 else 2347 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2348 2349 if (def != data) 2350 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2351 regRLC_CGTT_MGCG_OVERRIDE, data); 2352 } 2353 2354 static void 2355 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2356 bool enable, int xcc_id) 2357 { 2358 uint32_t data, def; 2359 2360 /* It is disabled by HW by default */ 2361 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2362 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2363 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2364 2365 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2366 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2367 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2368 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2369 2370 if (def != data) 2371 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2372 2373 /* MGLS is a global flag to control all MGLS in GFX */ 2374 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2375 /* 2 - RLC memory Light sleep */ 2376 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2377 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2378 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2379 if (def != data) 2380 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2381 } 2382 /* 3 - CP memory Light sleep */ 2383 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2384 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2385 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2386 if (def != data) 2387 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2388 } 2389 } 2390 } else { 2391 /* 1 - MGCG_OVERRIDE */ 2392 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2393 2394 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2395 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2396 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2397 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2398 2399 if (def != data) 2400 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2401 2402 /* 2 - disable MGLS in RLC */ 2403 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2404 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2405 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2406 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2407 } 2408 2409 /* 3 - disable MGLS in CP */ 2410 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2411 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2412 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2413 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2414 } 2415 } 2416 2417 } 2418 2419 static void 2420 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2421 bool enable, int xcc_id) 2422 { 2423 uint32_t def, data; 2424 2425 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2426 2427 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2428 /* unset CGCG override */ 2429 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2430 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2431 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2432 else 2433 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2434 /* update CGCG and CGLS override bits */ 2435 if (def != data) 2436 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2437 2438 /* CGCG Hysteresis: 400us */ 2439 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2440 2441 data = (0x2710 2442 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2443 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2444 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2445 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2446 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2447 if (def != data) 2448 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2449 2450 /* set IDLE_POLL_COUNT(0x33450100)*/ 2451 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2452 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2453 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2454 if (def != data) 2455 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2456 } else { 2457 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2458 /* reset CGCG/CGLS bits */ 2459 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2460 /* disable cgcg and cgls in FSM */ 2461 if (def != data) 2462 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2463 } 2464 2465 } 2466 2467 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2468 bool enable, int xcc_id) 2469 { 2470 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2471 2472 if (enable) { 2473 /* FGCG */ 2474 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2475 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2476 2477 /* CGCG/CGLS should be enabled after MGCG/MGLS 2478 * === MGCG + MGLS === 2479 */ 2480 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2481 xcc_id); 2482 /* === CGCG + CGLS === */ 2483 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2484 xcc_id); 2485 } else { 2486 /* CGCG/CGLS should be disabled before MGCG/MGLS 2487 * === CGCG + CGLS === 2488 */ 2489 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2490 xcc_id); 2491 /* === MGCG + MGLS === */ 2492 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2493 xcc_id); 2494 2495 /* FGCG */ 2496 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2497 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2498 } 2499 2500 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2501 2502 return 0; 2503 } 2504 2505 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2506 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2507 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2508 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2509 .init = gfx_v9_4_3_rlc_init, 2510 .resume = gfx_v9_4_3_rlc_resume, 2511 .stop = gfx_v9_4_3_rlc_stop, 2512 .reset = gfx_v9_4_3_rlc_reset, 2513 .start = gfx_v9_4_3_rlc_start, 2514 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2515 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2516 }; 2517 2518 static int gfx_v9_4_3_set_powergating_state(void *handle, 2519 enum amd_powergating_state state) 2520 { 2521 return 0; 2522 } 2523 2524 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2525 enum amd_clockgating_state state) 2526 { 2527 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2528 int i, num_xcc; 2529 2530 if (amdgpu_sriov_vf(adev)) 2531 return 0; 2532 2533 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2534 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2535 case IP_VERSION(9, 4, 3): 2536 case IP_VERSION(9, 4, 4): 2537 for (i = 0; i < num_xcc; i++) 2538 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2539 adev, state == AMD_CG_STATE_GATE, i); 2540 break; 2541 default: 2542 break; 2543 } 2544 return 0; 2545 } 2546 2547 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2548 { 2549 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2550 int data; 2551 2552 if (amdgpu_sriov_vf(adev)) 2553 *flags = 0; 2554 2555 /* AMD_CG_SUPPORT_GFX_MGCG */ 2556 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2557 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2558 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2559 2560 /* AMD_CG_SUPPORT_GFX_CGCG */ 2561 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2562 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2563 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2564 2565 /* AMD_CG_SUPPORT_GFX_CGLS */ 2566 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2567 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2568 2569 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2570 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2571 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2572 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2573 2574 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2575 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2576 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2577 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2578 } 2579 2580 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2581 { 2582 struct amdgpu_device *adev = ring->adev; 2583 u32 ref_and_mask, reg_mem_engine; 2584 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2585 2586 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2587 switch (ring->me) { 2588 case 1: 2589 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2590 break; 2591 case 2: 2592 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2593 break; 2594 default: 2595 return; 2596 } 2597 reg_mem_engine = 0; 2598 } else { 2599 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2600 reg_mem_engine = 1; /* pfp */ 2601 } 2602 2603 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2604 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2605 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2606 ref_and_mask, ref_and_mask, 0x20); 2607 } 2608 2609 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2610 struct amdgpu_job *job, 2611 struct amdgpu_ib *ib, 2612 uint32_t flags) 2613 { 2614 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2615 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2616 2617 /* Currently, there is a high possibility to get wave ID mismatch 2618 * between ME and GDS, leading to a hw deadlock, because ME generates 2619 * different wave IDs than the GDS expects. This situation happens 2620 * randomly when at least 5 compute pipes use GDS ordered append. 2621 * The wave IDs generated by ME are also wrong after suspend/resume. 2622 * Those are probably bugs somewhere else in the kernel driver. 2623 * 2624 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2625 * GDS to 0 for this ring (me/pipe). 2626 */ 2627 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2628 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2629 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2630 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2631 } 2632 2633 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2634 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2635 amdgpu_ring_write(ring, 2636 #ifdef __BIG_ENDIAN 2637 (2 << 0) | 2638 #endif 2639 lower_32_bits(ib->gpu_addr)); 2640 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2641 amdgpu_ring_write(ring, control); 2642 } 2643 2644 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2645 u64 seq, unsigned flags) 2646 { 2647 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2648 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2649 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2650 2651 /* RELEASE_MEM - flush caches, send int */ 2652 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2653 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2654 EOP_TC_NC_ACTION_EN) : 2655 (EOP_TCL1_ACTION_EN | 2656 EOP_TC_ACTION_EN | 2657 EOP_TC_WB_ACTION_EN | 2658 EOP_TC_MD_ACTION_EN)) | 2659 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2660 EVENT_INDEX(5))); 2661 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2662 2663 /* 2664 * the address should be Qword aligned if 64bit write, Dword 2665 * aligned if only send 32bit data low (discard data high) 2666 */ 2667 if (write64bit) 2668 BUG_ON(addr & 0x7); 2669 else 2670 BUG_ON(addr & 0x3); 2671 amdgpu_ring_write(ring, lower_32_bits(addr)); 2672 amdgpu_ring_write(ring, upper_32_bits(addr)); 2673 amdgpu_ring_write(ring, lower_32_bits(seq)); 2674 amdgpu_ring_write(ring, upper_32_bits(seq)); 2675 amdgpu_ring_write(ring, 0); 2676 } 2677 2678 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2679 { 2680 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2681 uint32_t seq = ring->fence_drv.sync_seq; 2682 uint64_t addr = ring->fence_drv.gpu_addr; 2683 2684 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2685 lower_32_bits(addr), upper_32_bits(addr), 2686 seq, 0xffffffff, 4); 2687 } 2688 2689 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2690 unsigned vmid, uint64_t pd_addr) 2691 { 2692 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2693 } 2694 2695 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2696 { 2697 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2698 } 2699 2700 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2701 { 2702 u64 wptr; 2703 2704 /* XXX check if swapping is necessary on BE */ 2705 if (ring->use_doorbell) 2706 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2707 else 2708 BUG(); 2709 return wptr; 2710 } 2711 2712 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2713 { 2714 struct amdgpu_device *adev = ring->adev; 2715 2716 /* XXX check if swapping is necessary on BE */ 2717 if (ring->use_doorbell) { 2718 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2719 WDOORBELL64(ring->doorbell_index, ring->wptr); 2720 } else { 2721 BUG(); /* only DOORBELL method supported on gfx9 now */ 2722 } 2723 } 2724 2725 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2726 u64 seq, unsigned int flags) 2727 { 2728 struct amdgpu_device *adev = ring->adev; 2729 2730 /* we only allocate 32bit for each seq wb address */ 2731 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2732 2733 /* write fence seq to the "addr" */ 2734 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2735 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2736 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2737 amdgpu_ring_write(ring, lower_32_bits(addr)); 2738 amdgpu_ring_write(ring, upper_32_bits(addr)); 2739 amdgpu_ring_write(ring, lower_32_bits(seq)); 2740 2741 if (flags & AMDGPU_FENCE_FLAG_INT) { 2742 /* set register to trigger INT */ 2743 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2744 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2745 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2746 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2747 amdgpu_ring_write(ring, 0); 2748 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2749 } 2750 } 2751 2752 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2753 uint32_t reg_val_offs) 2754 { 2755 struct amdgpu_device *adev = ring->adev; 2756 2757 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2758 2759 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2760 amdgpu_ring_write(ring, 0 | /* src: register*/ 2761 (5 << 8) | /* dst: memory */ 2762 (1 << 20)); /* write confirm */ 2763 amdgpu_ring_write(ring, reg); 2764 amdgpu_ring_write(ring, 0); 2765 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2766 reg_val_offs * 4)); 2767 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2768 reg_val_offs * 4)); 2769 } 2770 2771 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2772 uint32_t val) 2773 { 2774 uint32_t cmd = 0; 2775 2776 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 2777 2778 switch (ring->funcs->type) { 2779 case AMDGPU_RING_TYPE_GFX: 2780 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2781 break; 2782 case AMDGPU_RING_TYPE_KIQ: 2783 cmd = (1 << 16); /* no inc addr */ 2784 break; 2785 default: 2786 cmd = WR_CONFIRM; 2787 break; 2788 } 2789 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2790 amdgpu_ring_write(ring, cmd); 2791 amdgpu_ring_write(ring, reg); 2792 amdgpu_ring_write(ring, 0); 2793 amdgpu_ring_write(ring, val); 2794 } 2795 2796 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2797 uint32_t val, uint32_t mask) 2798 { 2799 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2800 } 2801 2802 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2803 uint32_t reg0, uint32_t reg1, 2804 uint32_t ref, uint32_t mask) 2805 { 2806 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2807 ref, mask); 2808 } 2809 2810 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2811 struct amdgpu_device *adev, int me, int pipe, 2812 enum amdgpu_interrupt_state state, int xcc_id) 2813 { 2814 u32 mec_int_cntl, mec_int_cntl_reg; 2815 2816 /* 2817 * amdgpu controls only the first MEC. That's why this function only 2818 * handles the setting of interrupts for this specific MEC. All other 2819 * pipes' interrupts are set by amdkfd. 2820 */ 2821 2822 if (me == 1) { 2823 switch (pipe) { 2824 case 0: 2825 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2826 break; 2827 case 1: 2828 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2829 break; 2830 case 2: 2831 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2832 break; 2833 case 3: 2834 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2835 break; 2836 default: 2837 DRM_DEBUG("invalid pipe %d\n", pipe); 2838 return; 2839 } 2840 } else { 2841 DRM_DEBUG("invalid me %d\n", me); 2842 return; 2843 } 2844 2845 switch (state) { 2846 case AMDGPU_IRQ_STATE_DISABLE: 2847 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2848 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2849 TIME_STAMP_INT_ENABLE, 0); 2850 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2851 break; 2852 case AMDGPU_IRQ_STATE_ENABLE: 2853 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2854 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2855 TIME_STAMP_INT_ENABLE, 1); 2856 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2857 break; 2858 default: 2859 break; 2860 } 2861 } 2862 2863 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2864 struct amdgpu_irq_src *source, 2865 unsigned type, 2866 enum amdgpu_interrupt_state state) 2867 { 2868 int i, num_xcc; 2869 2870 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2871 switch (state) { 2872 case AMDGPU_IRQ_STATE_DISABLE: 2873 case AMDGPU_IRQ_STATE_ENABLE: 2874 for (i = 0; i < num_xcc; i++) 2875 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2876 PRIV_REG_INT_ENABLE, 2877 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2878 break; 2879 default: 2880 break; 2881 } 2882 2883 return 0; 2884 } 2885 2886 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2887 struct amdgpu_irq_src *source, 2888 unsigned type, 2889 enum amdgpu_interrupt_state state) 2890 { 2891 int i, num_xcc; 2892 2893 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2894 switch (state) { 2895 case AMDGPU_IRQ_STATE_DISABLE: 2896 case AMDGPU_IRQ_STATE_ENABLE: 2897 for (i = 0; i < num_xcc; i++) 2898 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2899 PRIV_INSTR_INT_ENABLE, 2900 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2901 break; 2902 default: 2903 break; 2904 } 2905 2906 return 0; 2907 } 2908 2909 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2910 struct amdgpu_irq_src *src, 2911 unsigned type, 2912 enum amdgpu_interrupt_state state) 2913 { 2914 int i, num_xcc; 2915 2916 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2917 for (i = 0; i < num_xcc; i++) { 2918 switch (type) { 2919 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2920 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2921 adev, 1, 0, state, i); 2922 break; 2923 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2924 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2925 adev, 1, 1, state, i); 2926 break; 2927 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2928 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2929 adev, 1, 2, state, i); 2930 break; 2931 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2932 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2933 adev, 1, 3, state, i); 2934 break; 2935 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2936 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2937 adev, 2, 0, state, i); 2938 break; 2939 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2940 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2941 adev, 2, 1, state, i); 2942 break; 2943 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2944 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2945 adev, 2, 2, state, i); 2946 break; 2947 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2948 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2949 adev, 2, 3, state, i); 2950 break; 2951 default: 2952 break; 2953 } 2954 } 2955 2956 return 0; 2957 } 2958 2959 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2960 struct amdgpu_irq_src *source, 2961 struct amdgpu_iv_entry *entry) 2962 { 2963 int i, xcc_id; 2964 u8 me_id, pipe_id, queue_id; 2965 struct amdgpu_ring *ring; 2966 2967 DRM_DEBUG("IH: CP EOP\n"); 2968 me_id = (entry->ring_id & 0x0c) >> 2; 2969 pipe_id = (entry->ring_id & 0x03) >> 0; 2970 queue_id = (entry->ring_id & 0x70) >> 4; 2971 2972 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2973 2974 if (xcc_id == -EINVAL) 2975 return -EINVAL; 2976 2977 switch (me_id) { 2978 case 0: 2979 case 1: 2980 case 2: 2981 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2982 ring = &adev->gfx.compute_ring 2983 [i + 2984 xcc_id * adev->gfx.num_compute_rings]; 2985 /* Per-queue interrupt is supported for MEC starting from VI. 2986 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2987 */ 2988 2989 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2990 amdgpu_fence_process(ring); 2991 } 2992 break; 2993 } 2994 return 0; 2995 } 2996 2997 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2998 struct amdgpu_iv_entry *entry) 2999 { 3000 u8 me_id, pipe_id, queue_id; 3001 struct amdgpu_ring *ring; 3002 int i, xcc_id; 3003 3004 me_id = (entry->ring_id & 0x0c) >> 2; 3005 pipe_id = (entry->ring_id & 0x03) >> 0; 3006 queue_id = (entry->ring_id & 0x70) >> 4; 3007 3008 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3009 3010 if (xcc_id == -EINVAL) 3011 return; 3012 3013 switch (me_id) { 3014 case 0: 3015 case 1: 3016 case 2: 3017 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3018 ring = &adev->gfx.compute_ring 3019 [i + 3020 xcc_id * adev->gfx.num_compute_rings]; 3021 if (ring->me == me_id && ring->pipe == pipe_id && 3022 ring->queue == queue_id) 3023 drm_sched_fault(&ring->sched); 3024 } 3025 break; 3026 } 3027 } 3028 3029 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3030 struct amdgpu_irq_src *source, 3031 struct amdgpu_iv_entry *entry) 3032 { 3033 DRM_ERROR("Illegal register access in command stream\n"); 3034 gfx_v9_4_3_fault(adev, entry); 3035 return 0; 3036 } 3037 3038 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3039 struct amdgpu_irq_src *source, 3040 struct amdgpu_iv_entry *entry) 3041 { 3042 DRM_ERROR("Illegal instruction in command stream\n"); 3043 gfx_v9_4_3_fault(adev, entry); 3044 return 0; 3045 } 3046 3047 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3048 { 3049 const unsigned int cp_coher_cntl = 3050 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3051 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3052 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3053 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3054 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3055 3056 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3057 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3058 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3059 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3060 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3061 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3062 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3063 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3064 } 3065 3066 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3067 uint32_t pipe, bool enable) 3068 { 3069 struct amdgpu_device *adev = ring->adev; 3070 uint32_t val; 3071 uint32_t wcl_cs_reg; 3072 3073 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3074 val = enable ? 0x1 : 0x7f; 3075 3076 switch (pipe) { 3077 case 0: 3078 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3079 break; 3080 case 1: 3081 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3082 break; 3083 case 2: 3084 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3085 break; 3086 case 3: 3087 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3088 break; 3089 default: 3090 DRM_DEBUG("invalid pipe %d\n", pipe); 3091 return; 3092 } 3093 3094 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3095 3096 } 3097 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3098 { 3099 struct amdgpu_device *adev = ring->adev; 3100 uint32_t val; 3101 int i; 3102 3103 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3104 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3105 * around 25% of gpu resources. 3106 */ 3107 val = enable ? 0x1f : 0x07ffffff; 3108 amdgpu_ring_emit_wreg(ring, 3109 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3110 val); 3111 3112 /* Restrict waves for normal/low priority compute queues as well 3113 * to get best QoS for high priority compute jobs. 3114 * 3115 * amdgpu controls only 1st ME(0-3 CS pipes). 3116 */ 3117 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3118 if (i != ring->pipe) 3119 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3120 3121 } 3122 } 3123 3124 enum amdgpu_gfx_cp_ras_mem_id { 3125 AMDGPU_GFX_CP_MEM1 = 1, 3126 AMDGPU_GFX_CP_MEM2, 3127 AMDGPU_GFX_CP_MEM3, 3128 AMDGPU_GFX_CP_MEM4, 3129 AMDGPU_GFX_CP_MEM5, 3130 }; 3131 3132 enum amdgpu_gfx_gcea_ras_mem_id { 3133 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3134 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3135 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3136 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3137 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3138 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3139 AMDGPU_GFX_GCEA_MAM_DMEM0, 3140 AMDGPU_GFX_GCEA_MAM_DMEM1, 3141 AMDGPU_GFX_GCEA_MAM_DMEM2, 3142 AMDGPU_GFX_GCEA_MAM_DMEM3, 3143 AMDGPU_GFX_GCEA_MAM_AMEM0, 3144 AMDGPU_GFX_GCEA_MAM_AMEM1, 3145 AMDGPU_GFX_GCEA_MAM_AMEM2, 3146 AMDGPU_GFX_GCEA_MAM_AMEM3, 3147 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3148 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3149 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3150 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3151 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3152 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3153 }; 3154 3155 enum amdgpu_gfx_gc_cane_ras_mem_id { 3156 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3157 }; 3158 3159 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3160 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3161 }; 3162 3163 enum amdgpu_gfx_gds_ras_mem_id { 3164 AMDGPU_GFX_GDS_MEM0 = 0, 3165 }; 3166 3167 enum amdgpu_gfx_lds_ras_mem_id { 3168 AMDGPU_GFX_LDS_BANK0 = 0, 3169 AMDGPU_GFX_LDS_BANK1, 3170 AMDGPU_GFX_LDS_BANK2, 3171 AMDGPU_GFX_LDS_BANK3, 3172 AMDGPU_GFX_LDS_BANK4, 3173 AMDGPU_GFX_LDS_BANK5, 3174 AMDGPU_GFX_LDS_BANK6, 3175 AMDGPU_GFX_LDS_BANK7, 3176 AMDGPU_GFX_LDS_BANK8, 3177 AMDGPU_GFX_LDS_BANK9, 3178 AMDGPU_GFX_LDS_BANK10, 3179 AMDGPU_GFX_LDS_BANK11, 3180 AMDGPU_GFX_LDS_BANK12, 3181 AMDGPU_GFX_LDS_BANK13, 3182 AMDGPU_GFX_LDS_BANK14, 3183 AMDGPU_GFX_LDS_BANK15, 3184 AMDGPU_GFX_LDS_BANK16, 3185 AMDGPU_GFX_LDS_BANK17, 3186 AMDGPU_GFX_LDS_BANK18, 3187 AMDGPU_GFX_LDS_BANK19, 3188 AMDGPU_GFX_LDS_BANK20, 3189 AMDGPU_GFX_LDS_BANK21, 3190 AMDGPU_GFX_LDS_BANK22, 3191 AMDGPU_GFX_LDS_BANK23, 3192 AMDGPU_GFX_LDS_BANK24, 3193 AMDGPU_GFX_LDS_BANK25, 3194 AMDGPU_GFX_LDS_BANK26, 3195 AMDGPU_GFX_LDS_BANK27, 3196 AMDGPU_GFX_LDS_BANK28, 3197 AMDGPU_GFX_LDS_BANK29, 3198 AMDGPU_GFX_LDS_BANK30, 3199 AMDGPU_GFX_LDS_BANK31, 3200 AMDGPU_GFX_LDS_SP_BUFFER_A, 3201 AMDGPU_GFX_LDS_SP_BUFFER_B, 3202 }; 3203 3204 enum amdgpu_gfx_rlc_ras_mem_id { 3205 AMDGPU_GFX_RLC_GPMF32 = 1, 3206 AMDGPU_GFX_RLC_RLCVF32, 3207 AMDGPU_GFX_RLC_SCRATCH, 3208 AMDGPU_GFX_RLC_SRM_ARAM, 3209 AMDGPU_GFX_RLC_SRM_DRAM, 3210 AMDGPU_GFX_RLC_TCTAG, 3211 AMDGPU_GFX_RLC_SPM_SE, 3212 AMDGPU_GFX_RLC_SPM_GRBMT, 3213 }; 3214 3215 enum amdgpu_gfx_sp_ras_mem_id { 3216 AMDGPU_GFX_SP_SIMDID0 = 0, 3217 }; 3218 3219 enum amdgpu_gfx_spi_ras_mem_id { 3220 AMDGPU_GFX_SPI_MEM0 = 0, 3221 AMDGPU_GFX_SPI_MEM1, 3222 AMDGPU_GFX_SPI_MEM2, 3223 AMDGPU_GFX_SPI_MEM3, 3224 }; 3225 3226 enum amdgpu_gfx_sqc_ras_mem_id { 3227 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3228 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3229 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3230 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3231 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3232 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3233 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3234 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3235 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3236 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3237 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3238 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3239 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3240 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3241 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3242 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3243 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3244 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3245 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3246 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3247 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3248 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3249 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3250 }; 3251 3252 enum amdgpu_gfx_sq_ras_mem_id { 3253 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3254 AMDGPU_GFX_SQ_SGPR_MEM1, 3255 AMDGPU_GFX_SQ_SGPR_MEM2, 3256 AMDGPU_GFX_SQ_SGPR_MEM3, 3257 }; 3258 3259 enum amdgpu_gfx_ta_ras_mem_id { 3260 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3261 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3262 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3263 AMDGPU_GFX_TA_FSX_LFIFO, 3264 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3265 }; 3266 3267 enum amdgpu_gfx_tcc_ras_mem_id { 3268 AMDGPU_GFX_TCC_MEM1 = 1, 3269 }; 3270 3271 enum amdgpu_gfx_tca_ras_mem_id { 3272 AMDGPU_GFX_TCA_MEM1 = 1, 3273 }; 3274 3275 enum amdgpu_gfx_tci_ras_mem_id { 3276 AMDGPU_GFX_TCIW_MEM = 1, 3277 }; 3278 3279 enum amdgpu_gfx_tcp_ras_mem_id { 3280 AMDGPU_GFX_TCP_LFIFO0 = 1, 3281 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3282 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3283 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3284 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3285 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3286 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3287 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3288 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3289 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3290 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3291 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3292 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3293 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3294 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3295 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3296 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3297 AMDGPU_GFX_TCP_VM_FIFO, 3298 AMDGPU_GFX_TCP_DB_TAGRAM0, 3299 AMDGPU_GFX_TCP_DB_TAGRAM1, 3300 AMDGPU_GFX_TCP_DB_TAGRAM2, 3301 AMDGPU_GFX_TCP_DB_TAGRAM3, 3302 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3303 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3304 AMDGPU_GFX_TCP_CMD_FIFO, 3305 }; 3306 3307 enum amdgpu_gfx_td_ras_mem_id { 3308 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3309 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3310 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3311 }; 3312 3313 enum amdgpu_gfx_tcx_ras_mem_id { 3314 AMDGPU_GFX_TCX_FIFOD0 = 0, 3315 AMDGPU_GFX_TCX_FIFOD1, 3316 AMDGPU_GFX_TCX_FIFOD2, 3317 AMDGPU_GFX_TCX_FIFOD3, 3318 AMDGPU_GFX_TCX_FIFOD4, 3319 AMDGPU_GFX_TCX_FIFOD5, 3320 AMDGPU_GFX_TCX_FIFOD6, 3321 AMDGPU_GFX_TCX_FIFOD7, 3322 AMDGPU_GFX_TCX_FIFOB0, 3323 AMDGPU_GFX_TCX_FIFOB1, 3324 AMDGPU_GFX_TCX_FIFOB2, 3325 AMDGPU_GFX_TCX_FIFOB3, 3326 AMDGPU_GFX_TCX_FIFOB4, 3327 AMDGPU_GFX_TCX_FIFOB5, 3328 AMDGPU_GFX_TCX_FIFOB6, 3329 AMDGPU_GFX_TCX_FIFOB7, 3330 AMDGPU_GFX_TCX_FIFOA0, 3331 AMDGPU_GFX_TCX_FIFOA1, 3332 AMDGPU_GFX_TCX_FIFOA2, 3333 AMDGPU_GFX_TCX_FIFOA3, 3334 AMDGPU_GFX_TCX_FIFOA4, 3335 AMDGPU_GFX_TCX_FIFOA5, 3336 AMDGPU_GFX_TCX_FIFOA6, 3337 AMDGPU_GFX_TCX_FIFOA7, 3338 AMDGPU_GFX_TCX_CFIFO0, 3339 AMDGPU_GFX_TCX_CFIFO1, 3340 AMDGPU_GFX_TCX_CFIFO2, 3341 AMDGPU_GFX_TCX_CFIFO3, 3342 AMDGPU_GFX_TCX_CFIFO4, 3343 AMDGPU_GFX_TCX_CFIFO5, 3344 AMDGPU_GFX_TCX_CFIFO6, 3345 AMDGPU_GFX_TCX_CFIFO7, 3346 AMDGPU_GFX_TCX_FIFO_ACKB0, 3347 AMDGPU_GFX_TCX_FIFO_ACKB1, 3348 AMDGPU_GFX_TCX_FIFO_ACKB2, 3349 AMDGPU_GFX_TCX_FIFO_ACKB3, 3350 AMDGPU_GFX_TCX_FIFO_ACKB4, 3351 AMDGPU_GFX_TCX_FIFO_ACKB5, 3352 AMDGPU_GFX_TCX_FIFO_ACKB6, 3353 AMDGPU_GFX_TCX_FIFO_ACKB7, 3354 AMDGPU_GFX_TCX_FIFO_ACKD0, 3355 AMDGPU_GFX_TCX_FIFO_ACKD1, 3356 AMDGPU_GFX_TCX_FIFO_ACKD2, 3357 AMDGPU_GFX_TCX_FIFO_ACKD3, 3358 AMDGPU_GFX_TCX_FIFO_ACKD4, 3359 AMDGPU_GFX_TCX_FIFO_ACKD5, 3360 AMDGPU_GFX_TCX_FIFO_ACKD6, 3361 AMDGPU_GFX_TCX_FIFO_ACKD7, 3362 AMDGPU_GFX_TCX_DST_FIFOA0, 3363 AMDGPU_GFX_TCX_DST_FIFOA1, 3364 AMDGPU_GFX_TCX_DST_FIFOA2, 3365 AMDGPU_GFX_TCX_DST_FIFOA3, 3366 AMDGPU_GFX_TCX_DST_FIFOA4, 3367 AMDGPU_GFX_TCX_DST_FIFOA5, 3368 AMDGPU_GFX_TCX_DST_FIFOA6, 3369 AMDGPU_GFX_TCX_DST_FIFOA7, 3370 AMDGPU_GFX_TCX_DST_FIFOB0, 3371 AMDGPU_GFX_TCX_DST_FIFOB1, 3372 AMDGPU_GFX_TCX_DST_FIFOB2, 3373 AMDGPU_GFX_TCX_DST_FIFOB3, 3374 AMDGPU_GFX_TCX_DST_FIFOB4, 3375 AMDGPU_GFX_TCX_DST_FIFOB5, 3376 AMDGPU_GFX_TCX_DST_FIFOB6, 3377 AMDGPU_GFX_TCX_DST_FIFOB7, 3378 AMDGPU_GFX_TCX_DST_FIFOD0, 3379 AMDGPU_GFX_TCX_DST_FIFOD1, 3380 AMDGPU_GFX_TCX_DST_FIFOD2, 3381 AMDGPU_GFX_TCX_DST_FIFOD3, 3382 AMDGPU_GFX_TCX_DST_FIFOD4, 3383 AMDGPU_GFX_TCX_DST_FIFOD5, 3384 AMDGPU_GFX_TCX_DST_FIFOD6, 3385 AMDGPU_GFX_TCX_DST_FIFOD7, 3386 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3387 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3388 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3389 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3390 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3391 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3392 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3393 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3394 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3395 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3396 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3397 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3398 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3399 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3400 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3401 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3402 }; 3403 3404 enum amdgpu_gfx_atc_l2_ras_mem_id { 3405 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3406 }; 3407 3408 enum amdgpu_gfx_utcl2_ras_mem_id { 3409 AMDGPU_GFX_UTCL2_MEM0 = 0, 3410 }; 3411 3412 enum amdgpu_gfx_vml2_ras_mem_id { 3413 AMDGPU_GFX_VML2_MEM0 = 0, 3414 }; 3415 3416 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3417 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3418 }; 3419 3420 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3421 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3422 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3423 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3424 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3425 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3426 }; 3427 3428 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3429 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3430 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3431 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3432 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3433 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3434 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3435 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3436 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3437 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3438 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3439 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3440 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3441 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3442 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3443 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3444 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3445 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3446 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3447 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3448 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3449 }; 3450 3451 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3452 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3453 }; 3454 3455 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3456 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3457 }; 3458 3459 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3460 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3461 }; 3462 3463 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3464 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3465 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3466 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3467 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3468 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3469 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3470 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3471 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3472 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3473 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3474 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3475 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3476 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3477 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3478 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3479 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3480 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3481 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3482 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3483 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3484 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3485 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3486 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3487 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3488 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3489 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3490 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3491 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3492 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3493 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3494 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3495 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3496 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3497 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3498 }; 3499 3500 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3501 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3502 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3503 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3504 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3505 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3506 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3507 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3508 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3509 }; 3510 3511 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3512 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3513 }; 3514 3515 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3516 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3517 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3518 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3519 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3520 }; 3521 3522 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3523 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3524 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3525 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3526 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3527 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3528 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3529 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3530 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3531 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3532 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3533 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3534 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3535 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3536 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3537 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3538 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3539 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3540 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3541 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3542 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3543 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3544 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3545 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3546 }; 3547 3548 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3549 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3550 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3551 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3552 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3553 }; 3554 3555 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3556 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3557 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3558 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3559 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3560 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3561 }; 3562 3563 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3564 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3565 }; 3566 3567 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3568 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3569 }; 3570 3571 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3572 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3573 }; 3574 3575 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3576 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3577 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3578 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3579 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3580 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3581 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3582 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3583 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3584 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3585 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3586 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3587 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3588 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3589 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3590 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3591 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3592 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3593 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3594 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3595 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3596 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3597 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3598 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3599 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3600 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3601 }; 3602 3603 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3604 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3605 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3606 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3607 }; 3608 3609 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3610 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3611 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3612 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3613 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3614 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3615 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3616 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3617 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3618 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3619 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3620 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3621 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3622 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3623 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3624 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3625 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3626 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3627 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3628 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3629 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3630 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3631 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3632 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3633 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3634 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3635 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3636 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3637 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3638 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3639 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3640 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3641 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3642 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3643 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3644 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3645 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3646 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3647 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3648 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3649 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3650 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3651 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3652 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3653 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3654 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3655 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3656 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3657 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3658 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3659 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3660 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3661 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3662 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3663 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3664 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3665 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3666 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3667 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3668 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3669 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3670 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3671 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3672 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3673 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3674 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3675 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3676 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3677 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3678 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3679 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3680 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3681 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3682 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3683 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3684 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3685 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3686 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3687 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3688 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3689 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3690 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3691 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3692 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3693 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3694 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3695 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3696 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3697 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3698 }; 3699 3700 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3701 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3702 }; 3703 3704 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3705 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3706 }; 3707 3708 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3709 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3710 }; 3711 3712 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3713 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3714 }; 3715 3716 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3717 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3718 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3719 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3720 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3721 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3722 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3723 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3724 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3725 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3726 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3727 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3728 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3729 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3730 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3731 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3732 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3733 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3734 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3735 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3736 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3737 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3738 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3739 }; 3740 3741 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3742 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3743 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3744 AMDGPU_GFX_RLC_MEM, 1}, 3745 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3746 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3747 AMDGPU_GFX_CP_MEM, 1}, 3748 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3749 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3750 AMDGPU_GFX_CP_MEM, 1}, 3751 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3752 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3753 AMDGPU_GFX_CP_MEM, 1}, 3754 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3755 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3756 AMDGPU_GFX_GDS_MEM, 1}, 3757 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3758 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3759 AMDGPU_GFX_GC_CANE_MEM, 1}, 3760 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3761 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3762 AMDGPU_GFX_SPI_MEM, 1}, 3763 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3764 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3765 AMDGPU_GFX_SP_MEM, 4}, 3766 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3767 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3768 AMDGPU_GFX_SP_MEM, 4}, 3769 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3770 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3771 AMDGPU_GFX_SQ_MEM, 4}, 3772 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3773 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3774 AMDGPU_GFX_SQC_MEM, 4}, 3775 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3776 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3777 AMDGPU_GFX_TCX_MEM, 1}, 3778 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3779 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3780 AMDGPU_GFX_TCC_MEM, 1}, 3781 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3782 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3783 AMDGPU_GFX_TA_MEM, 4}, 3784 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3785 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3786 AMDGPU_GFX_TCI_MEM, 1}, 3787 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3788 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3789 AMDGPU_GFX_TCP_MEM, 4}, 3790 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3791 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3792 AMDGPU_GFX_TD_MEM, 4}, 3793 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3794 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3795 AMDGPU_GFX_GCEA_MEM, 1}, 3796 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3797 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3798 AMDGPU_GFX_LDS_MEM, 4}, 3799 }; 3800 3801 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3802 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3803 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3804 AMDGPU_GFX_RLC_MEM, 1}, 3805 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3806 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3807 AMDGPU_GFX_CP_MEM, 1}, 3808 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3809 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3810 AMDGPU_GFX_CP_MEM, 1}, 3811 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3812 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3813 AMDGPU_GFX_CP_MEM, 1}, 3814 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3815 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3816 AMDGPU_GFX_GDS_MEM, 1}, 3817 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3818 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3819 AMDGPU_GFX_GC_CANE_MEM, 1}, 3820 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3821 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3822 AMDGPU_GFX_SPI_MEM, 1}, 3823 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3824 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3825 AMDGPU_GFX_SP_MEM, 4}, 3826 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3827 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3828 AMDGPU_GFX_SP_MEM, 4}, 3829 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3830 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3831 AMDGPU_GFX_SQ_MEM, 4}, 3832 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3833 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3834 AMDGPU_GFX_SQC_MEM, 4}, 3835 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3836 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3837 AMDGPU_GFX_TCX_MEM, 1}, 3838 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3839 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3840 AMDGPU_GFX_TCC_MEM, 1}, 3841 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3842 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3843 AMDGPU_GFX_TA_MEM, 4}, 3844 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3845 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3846 AMDGPU_GFX_TCI_MEM, 1}, 3847 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3848 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3849 AMDGPU_GFX_TCP_MEM, 4}, 3850 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3851 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3852 AMDGPU_GFX_TD_MEM, 4}, 3853 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3854 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3855 AMDGPU_GFX_TCA_MEM, 1}, 3856 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3857 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3858 AMDGPU_GFX_GCEA_MEM, 1}, 3859 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3860 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3861 AMDGPU_GFX_LDS_MEM, 4}, 3862 }; 3863 3864 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3865 void *ras_error_status, int xcc_id) 3866 { 3867 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3868 unsigned long ce_count = 0, ue_count = 0; 3869 uint32_t i, j, k; 3870 3871 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 3872 struct amdgpu_smuio_mcm_config_info mcm_info = { 3873 .socket_id = adev->smuio.funcs->get_socket_id(adev), 3874 .die_id = xcc_id & 0x01 ? 1 : 0, 3875 }; 3876 3877 mutex_lock(&adev->grbm_idx_mutex); 3878 3879 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3880 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3881 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3882 /* no need to select if instance number is 1 */ 3883 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3884 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3885 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3886 3887 amdgpu_ras_inst_query_ras_error_count(adev, 3888 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3889 1, 3890 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3891 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3892 GET_INST(GC, xcc_id), 3893 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3894 &ce_count); 3895 3896 amdgpu_ras_inst_query_ras_error_count(adev, 3897 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3898 1, 3899 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3900 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3901 GET_INST(GC, xcc_id), 3902 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3903 &ue_count); 3904 } 3905 } 3906 } 3907 3908 /* handle extra register entries of UE */ 3909 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3910 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3911 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3912 /* no need to select if instance number is 1 */ 3913 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3914 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3915 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3916 3917 amdgpu_ras_inst_query_ras_error_count(adev, 3918 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3919 1, 3920 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3921 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3922 GET_INST(GC, xcc_id), 3923 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3924 &ue_count); 3925 } 3926 } 3927 } 3928 3929 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3930 xcc_id); 3931 mutex_unlock(&adev->grbm_idx_mutex); 3932 3933 /* the caller should make sure initialize value of 3934 * err_data->ue_count and err_data->ce_count 3935 */ 3936 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count); 3937 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, ce_count); 3938 } 3939 3940 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3941 void *ras_error_status, int xcc_id) 3942 { 3943 uint32_t i, j, k; 3944 3945 mutex_lock(&adev->grbm_idx_mutex); 3946 3947 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3948 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3949 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3950 /* no need to select if instance number is 1 */ 3951 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3952 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3953 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3954 3955 amdgpu_ras_inst_reset_ras_error_count(adev, 3956 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3957 1, 3958 GET_INST(GC, xcc_id)); 3959 3960 amdgpu_ras_inst_reset_ras_error_count(adev, 3961 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3962 1, 3963 GET_INST(GC, xcc_id)); 3964 } 3965 } 3966 } 3967 3968 /* handle extra register entries of UE */ 3969 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3970 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3971 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3972 /* no need to select if instance number is 1 */ 3973 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3974 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3975 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3976 3977 amdgpu_ras_inst_reset_ras_error_count(adev, 3978 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3979 1, 3980 GET_INST(GC, xcc_id)); 3981 } 3982 } 3983 } 3984 3985 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3986 xcc_id); 3987 mutex_unlock(&adev->grbm_idx_mutex); 3988 } 3989 3990 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 3991 void *ras_error_status, int xcc_id) 3992 { 3993 uint32_t i; 3994 uint32_t data; 3995 3996 if (amdgpu_sriov_vf(adev)) 3997 return; 3998 3999 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4000 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4001 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4002 4003 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4004 (amdgpu_watchdog_timer.period < 1 || 4005 amdgpu_watchdog_timer.period > 0x23)) { 4006 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4007 amdgpu_watchdog_timer.period = 0x23; 4008 } 4009 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4010 amdgpu_watchdog_timer.period); 4011 4012 mutex_lock(&adev->grbm_idx_mutex); 4013 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4014 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4015 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4016 } 4017 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4018 xcc_id); 4019 mutex_unlock(&adev->grbm_idx_mutex); 4020 } 4021 4022 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4023 void *ras_error_status) 4024 { 4025 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4026 gfx_v9_4_3_inst_query_ras_err_count); 4027 } 4028 4029 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4030 { 4031 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4032 } 4033 4034 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4035 { 4036 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4037 } 4038 4039 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4040 .name = "gfx_v9_4_3", 4041 .early_init = gfx_v9_4_3_early_init, 4042 .late_init = gfx_v9_4_3_late_init, 4043 .sw_init = gfx_v9_4_3_sw_init, 4044 .sw_fini = gfx_v9_4_3_sw_fini, 4045 .hw_init = gfx_v9_4_3_hw_init, 4046 .hw_fini = gfx_v9_4_3_hw_fini, 4047 .suspend = gfx_v9_4_3_suspend, 4048 .resume = gfx_v9_4_3_resume, 4049 .is_idle = gfx_v9_4_3_is_idle, 4050 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4051 .soft_reset = gfx_v9_4_3_soft_reset, 4052 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4053 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4054 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4055 .dump_ip_state = NULL, 4056 .print_ip_state = NULL, 4057 }; 4058 4059 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4060 .type = AMDGPU_RING_TYPE_COMPUTE, 4061 .align_mask = 0xff, 4062 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4063 .support_64bit_ptrs = true, 4064 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4065 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4066 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4067 .emit_frame_size = 4068 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4069 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4070 5 + /* hdp invalidate */ 4071 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4072 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4073 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4074 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4075 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4076 7 + /* gfx_v9_4_3_emit_mem_sync */ 4077 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4078 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4079 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4080 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4081 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4082 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4083 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4084 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4085 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4086 .test_ring = gfx_v9_4_3_ring_test_ring, 4087 .test_ib = gfx_v9_4_3_ring_test_ib, 4088 .insert_nop = amdgpu_ring_insert_nop, 4089 .pad_ib = amdgpu_ring_generic_pad_ib, 4090 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4091 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4092 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4093 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4094 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4095 }; 4096 4097 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4098 .type = AMDGPU_RING_TYPE_KIQ, 4099 .align_mask = 0xff, 4100 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4101 .support_64bit_ptrs = true, 4102 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4103 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4104 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4105 .emit_frame_size = 4106 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4107 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4108 5 + /* hdp invalidate */ 4109 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4110 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4111 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4112 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4113 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4114 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4115 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4116 .test_ring = gfx_v9_4_3_ring_test_ring, 4117 .insert_nop = amdgpu_ring_insert_nop, 4118 .pad_ib = amdgpu_ring_generic_pad_ib, 4119 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4120 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4121 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4122 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4123 }; 4124 4125 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4126 { 4127 int i, j, num_xcc; 4128 4129 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4130 for (i = 0; i < num_xcc; i++) { 4131 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4132 4133 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4134 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4135 = &gfx_v9_4_3_ring_funcs_compute; 4136 } 4137 } 4138 4139 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4140 .set = gfx_v9_4_3_set_eop_interrupt_state, 4141 .process = gfx_v9_4_3_eop_irq, 4142 }; 4143 4144 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4145 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4146 .process = gfx_v9_4_3_priv_reg_irq, 4147 }; 4148 4149 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4150 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4151 .process = gfx_v9_4_3_priv_inst_irq, 4152 }; 4153 4154 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4155 { 4156 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4157 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4158 4159 adev->gfx.priv_reg_irq.num_types = 1; 4160 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4161 4162 adev->gfx.priv_inst_irq.num_types = 1; 4163 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4164 } 4165 4166 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4167 { 4168 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4169 } 4170 4171 4172 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4173 { 4174 /* init asci gds info */ 4175 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4176 case IP_VERSION(9, 4, 3): 4177 case IP_VERSION(9, 4, 4): 4178 /* 9.4.3 removed all the GDS internal memory, 4179 * only support GWS opcode in kernel, like barrier 4180 * semaphore.etc */ 4181 adev->gds.gds_size = 0; 4182 break; 4183 default: 4184 adev->gds.gds_size = 0x10000; 4185 break; 4186 } 4187 4188 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4189 case IP_VERSION(9, 4, 3): 4190 case IP_VERSION(9, 4, 4): 4191 /* deprecated for 9.4.3, no usage at all */ 4192 adev->gds.gds_compute_max_wave_id = 0; 4193 break; 4194 default: 4195 /* this really depends on the chip */ 4196 adev->gds.gds_compute_max_wave_id = 0x7ff; 4197 break; 4198 } 4199 4200 adev->gds.gws_size = 64; 4201 adev->gds.oa_size = 16; 4202 } 4203 4204 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4205 u32 bitmap, int xcc_id) 4206 { 4207 u32 data; 4208 4209 if (!bitmap) 4210 return; 4211 4212 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4213 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4214 4215 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4216 } 4217 4218 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4219 { 4220 u32 data, mask; 4221 4222 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4223 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4224 4225 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4226 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4227 4228 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4229 4230 return (~data) & mask; 4231 } 4232 4233 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4234 struct amdgpu_cu_info *cu_info) 4235 { 4236 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4237 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4238 unsigned disable_masks[4 * 4]; 4239 bool is_symmetric_cus; 4240 4241 if (!adev || !cu_info) 4242 return -EINVAL; 4243 4244 /* 4245 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4246 */ 4247 if (adev->gfx.config.max_shader_engines * 4248 adev->gfx.config.max_sh_per_se > 16) 4249 return -EINVAL; 4250 4251 amdgpu_gfx_parse_disable_cu(disable_masks, 4252 adev->gfx.config.max_shader_engines, 4253 adev->gfx.config.max_sh_per_se); 4254 4255 mutex_lock(&adev->grbm_idx_mutex); 4256 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4257 is_symmetric_cus = true; 4258 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4259 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4260 mask = 1; 4261 ao_bitmap = 0; 4262 counter = 0; 4263 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4264 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4265 adev, 4266 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4267 xcc_id); 4268 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4269 4270 cu_info->bitmap[xcc_id][i][j] = bitmap; 4271 4272 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4273 if (bitmap & mask) { 4274 if (counter < adev->gfx.config.max_cu_per_sh) 4275 ao_bitmap |= mask; 4276 counter++; 4277 } 4278 mask <<= 1; 4279 } 4280 active_cu_number += counter; 4281 if (i < 2 && j < 2) 4282 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4283 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4284 } 4285 if (i && is_symmetric_cus && prev_counter != counter) 4286 is_symmetric_cus = false; 4287 prev_counter = counter; 4288 } 4289 if (is_symmetric_cus) { 4290 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4291 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4292 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4293 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4294 } 4295 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4296 xcc_id); 4297 } 4298 mutex_unlock(&adev->grbm_idx_mutex); 4299 4300 cu_info->number = active_cu_number; 4301 cu_info->ao_cu_mask = ao_cu_mask; 4302 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4303 4304 return 0; 4305 } 4306 4307 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4308 .type = AMD_IP_BLOCK_TYPE_GFX, 4309 .major = 9, 4310 .minor = 4, 4311 .rev = 3, 4312 .funcs = &gfx_v9_4_3_ip_funcs, 4313 }; 4314 4315 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4316 { 4317 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4318 uint32_t tmp_mask; 4319 int i, r; 4320 4321 /* TODO : Initialize golden regs */ 4322 /* gfx_v9_4_3_init_golden_registers(adev); */ 4323 4324 tmp_mask = inst_mask; 4325 for_each_inst(i, tmp_mask) 4326 gfx_v9_4_3_xcc_constants_init(adev, i); 4327 4328 if (!amdgpu_sriov_vf(adev)) { 4329 tmp_mask = inst_mask; 4330 for_each_inst(i, tmp_mask) { 4331 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4332 if (r) 4333 return r; 4334 } 4335 } 4336 4337 tmp_mask = inst_mask; 4338 for_each_inst(i, tmp_mask) { 4339 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4340 if (r) 4341 return r; 4342 } 4343 4344 return 0; 4345 } 4346 4347 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4348 { 4349 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4350 int i; 4351 4352 for_each_inst(i, inst_mask) 4353 gfx_v9_4_3_xcc_fini(adev, i); 4354 4355 return 0; 4356 } 4357 4358 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4359 .suspend = &gfx_v9_4_3_xcp_suspend, 4360 .resume = &gfx_v9_4_3_xcp_resume 4361 }; 4362 4363 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4364 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4365 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4366 }; 4367 4368 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 4369 { 4370 int r; 4371 4372 r = amdgpu_ras_block_late_init(adev, ras_block); 4373 if (r) 4374 return r; 4375 4376 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 4377 &gfx_v9_4_3_aca_info, 4378 NULL); 4379 if (r) 4380 goto late_fini; 4381 4382 return 0; 4383 4384 late_fini: 4385 amdgpu_ras_block_late_fini(adev, ras_block); 4386 4387 return r; 4388 } 4389 4390 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4391 .ras_block = { 4392 .hw_ops = &gfx_v9_4_3_ras_ops, 4393 .ras_late_init = &gfx_v9_4_3_ras_late_init, 4394 }, 4395 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4396 }; 4397