1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* SE status registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 110 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 111 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 113 }; 114 115 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 116 /* compute queue registers */ 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 162 }; 163 164 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 165 166 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 167 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 168 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 169 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 170 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 171 struct amdgpu_cu_info *cu_info); 172 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 173 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 174 175 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 176 uint64_t queue_mask) 177 { 178 struct amdgpu_device *adev = kiq_ring->adev; 179 u64 shader_mc_addr; 180 181 /* Cleaner shader MC address */ 182 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 183 184 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 185 amdgpu_ring_write(kiq_ring, 186 PACKET3_SET_RESOURCES_VMID_MASK(0) | 187 /* vmid_mask:0* queue_type:0 (KIQ) */ 188 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 189 amdgpu_ring_write(kiq_ring, 190 lower_32_bits(queue_mask)); /* queue mask lo */ 191 amdgpu_ring_write(kiq_ring, 192 upper_32_bits(queue_mask)); /* queue mask hi */ 193 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 194 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 195 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 196 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 197 } 198 199 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 200 struct amdgpu_ring *ring) 201 { 202 struct amdgpu_device *adev = kiq_ring->adev; 203 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 204 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 205 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 206 207 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 208 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 209 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 210 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 211 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 212 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 213 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 214 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 215 /*queue_type: normal compute queue */ 216 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 217 /* alloc format: all_on_one_pipe */ 218 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 219 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 220 /* num_queues: must be 1 */ 221 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 222 amdgpu_ring_write(kiq_ring, 223 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 224 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 225 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 226 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 227 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 228 } 229 230 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 231 struct amdgpu_ring *ring, 232 enum amdgpu_unmap_queues_action action, 233 u64 gpu_addr, u64 seq) 234 { 235 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 236 237 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 238 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 239 PACKET3_UNMAP_QUEUES_ACTION(action) | 240 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 241 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 242 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 243 amdgpu_ring_write(kiq_ring, 244 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 245 246 if (action == PREEMPT_QUEUES_NO_UNMAP) { 247 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 248 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 249 amdgpu_ring_write(kiq_ring, seq); 250 } else { 251 amdgpu_ring_write(kiq_ring, 0); 252 amdgpu_ring_write(kiq_ring, 0); 253 amdgpu_ring_write(kiq_ring, 0); 254 } 255 } 256 257 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 258 struct amdgpu_ring *ring, 259 u64 addr, 260 u64 seq) 261 { 262 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 263 264 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 267 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 268 PACKET3_QUERY_STATUS_COMMAND(2)); 269 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 270 amdgpu_ring_write(kiq_ring, 271 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 272 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 273 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 274 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 275 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 276 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 277 } 278 279 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 280 uint16_t pasid, uint32_t flush_type, 281 bool all_hub) 282 { 283 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 284 amdgpu_ring_write(kiq_ring, 285 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 286 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 287 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 288 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 289 } 290 291 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 292 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 293 uint32_t xcc_id, uint32_t vmid) 294 { 295 struct amdgpu_device *adev = kiq_ring->adev; 296 unsigned i; 297 298 /* enter save mode */ 299 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 300 mutex_lock(&adev->srbm_mutex); 301 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 302 303 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 305 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 306 /* wait till dequeue take effects */ 307 for (i = 0; i < adev->usec_timeout; i++) { 308 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 309 break; 310 udelay(1); 311 } 312 if (i >= adev->usec_timeout) 313 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 314 } else { 315 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 316 } 317 318 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 319 mutex_unlock(&adev->srbm_mutex); 320 /* exit safe mode */ 321 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 322 } 323 324 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 325 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 326 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 327 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 328 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 329 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 330 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 331 .set_resources_size = 8, 332 .map_queues_size = 7, 333 .unmap_queues_size = 6, 334 .query_status_size = 7, 335 .invalidate_tlbs_size = 2, 336 }; 337 338 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 339 { 340 int i, num_xcc; 341 342 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 343 for (i = 0; i < num_xcc; i++) 344 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 345 } 346 347 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 348 { 349 int i, num_xcc, dev_inst; 350 351 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 352 for (i = 0; i < num_xcc; i++) { 353 dev_inst = GET_INST(GC, i); 354 355 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 356 GOLDEN_GB_ADDR_CONFIG); 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 358 } 359 } 360 361 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 362 { 363 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 364 365 /* If it is an XCC reg, normalize the reg to keep 366 lower 16 bits in local xcc */ 367 368 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 369 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 370 return normalized_reg; 371 else 372 return reg; 373 } 374 375 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 376 bool wc, uint32_t reg, uint32_t val) 377 { 378 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 379 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 380 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 381 WRITE_DATA_DST_SEL(0) | 382 (wc ? WR_CONFIRM : 0)); 383 amdgpu_ring_write(ring, reg); 384 amdgpu_ring_write(ring, 0); 385 amdgpu_ring_write(ring, val); 386 } 387 388 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 389 int mem_space, int opt, uint32_t addr0, 390 uint32_t addr1, uint32_t ref, uint32_t mask, 391 uint32_t inv) 392 { 393 /* Only do the normalization on regspace */ 394 if (mem_space == 0) { 395 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 396 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 397 } 398 399 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 400 amdgpu_ring_write(ring, 401 /* memory (1) or register (0) */ 402 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 403 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 404 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 405 WAIT_REG_MEM_ENGINE(eng_sel))); 406 407 if (mem_space) 408 WARN_ON(addr0 & 0x3); /* Dword align */ 409 amdgpu_ring_write(ring, addr0); 410 amdgpu_ring_write(ring, addr1); 411 amdgpu_ring_write(ring, ref); 412 amdgpu_ring_write(ring, mask); 413 amdgpu_ring_write(ring, inv); /* poll interval */ 414 } 415 416 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 417 { 418 uint32_t scratch_reg0_offset, xcc_offset; 419 struct amdgpu_device *adev = ring->adev; 420 uint32_t tmp = 0; 421 unsigned i; 422 int r; 423 424 /* Use register offset which is local to XCC in the packet */ 425 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 426 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 427 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 428 tmp = RREG32(scratch_reg0_offset); 429 430 r = amdgpu_ring_alloc(ring, 3); 431 if (r) 432 return r; 433 434 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 435 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 436 amdgpu_ring_write(ring, 0xDEADBEEF); 437 amdgpu_ring_commit(ring); 438 439 for (i = 0; i < adev->usec_timeout; i++) { 440 tmp = RREG32(scratch_reg0_offset); 441 if (tmp == 0xDEADBEEF) 442 break; 443 udelay(1); 444 } 445 446 if (i >= adev->usec_timeout) 447 r = -ETIMEDOUT; 448 return r; 449 } 450 451 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 452 { 453 struct amdgpu_device *adev = ring->adev; 454 struct amdgpu_ib ib; 455 struct dma_fence *f = NULL; 456 457 unsigned index; 458 uint64_t gpu_addr; 459 uint32_t tmp; 460 long r; 461 462 r = amdgpu_device_wb_get(adev, &index); 463 if (r) 464 return r; 465 466 gpu_addr = adev->wb.gpu_addr + (index * 4); 467 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 468 memset(&ib, 0, sizeof(ib)); 469 470 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 471 if (r) 472 goto err1; 473 474 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 475 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 476 ib.ptr[2] = lower_32_bits(gpu_addr); 477 ib.ptr[3] = upper_32_bits(gpu_addr); 478 ib.ptr[4] = 0xDEADBEEF; 479 ib.length_dw = 5; 480 481 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 482 if (r) 483 goto err2; 484 485 r = dma_fence_wait_timeout(f, false, timeout); 486 if (r == 0) { 487 r = -ETIMEDOUT; 488 goto err2; 489 } else if (r < 0) { 490 goto err2; 491 } 492 493 tmp = adev->wb.wb[index]; 494 if (tmp == 0xDEADBEEF) 495 r = 0; 496 else 497 r = -EINVAL; 498 499 err2: 500 amdgpu_ib_free(&ib, NULL); 501 dma_fence_put(f); 502 err1: 503 amdgpu_device_wb_free(adev, index); 504 return r; 505 } 506 507 508 /* This value might differs per partition */ 509 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 510 { 511 uint64_t clock; 512 513 mutex_lock(&adev->gfx.gpu_clock_mutex); 514 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 515 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 516 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 517 mutex_unlock(&adev->gfx.gpu_clock_mutex); 518 519 return clock; 520 } 521 522 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 523 { 524 amdgpu_ucode_release(&adev->gfx.pfp_fw); 525 amdgpu_ucode_release(&adev->gfx.me_fw); 526 amdgpu_ucode_release(&adev->gfx.ce_fw); 527 amdgpu_ucode_release(&adev->gfx.rlc_fw); 528 amdgpu_ucode_release(&adev->gfx.mec_fw); 529 amdgpu_ucode_release(&adev->gfx.mec2_fw); 530 531 kfree(adev->gfx.rlc.register_list_format); 532 } 533 534 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 535 const char *chip_name) 536 { 537 int err; 538 const struct rlc_firmware_header_v2_0 *rlc_hdr; 539 uint16_t version_major; 540 uint16_t version_minor; 541 542 543 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 544 AMDGPU_UCODE_REQUIRED, 545 "amdgpu/%s_rlc.bin", chip_name); 546 if (err) 547 goto out; 548 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 549 550 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 551 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 552 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 553 out: 554 if (err) 555 amdgpu_ucode_release(&adev->gfx.rlc_fw); 556 557 return err; 558 } 559 560 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 561 const char *chip_name) 562 { 563 int err; 564 565 if (amdgpu_sriov_vf(adev)) { 566 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 567 AMDGPU_UCODE_REQUIRED, 568 "amdgpu/%s_sjt_mec.bin", chip_name); 569 570 if (err) 571 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 572 AMDGPU_UCODE_REQUIRED, 573 "amdgpu/%s_mec.bin", chip_name); 574 } else 575 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 576 AMDGPU_UCODE_REQUIRED, 577 "amdgpu/%s_mec.bin", chip_name); 578 if (err) 579 goto out; 580 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 581 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 582 583 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 584 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 585 586 out: 587 if (err) 588 amdgpu_ucode_release(&adev->gfx.mec_fw); 589 return err; 590 } 591 592 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 593 { 594 char ucode_prefix[15]; 595 int r; 596 597 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 598 599 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 600 if (r) 601 return r; 602 603 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 604 if (r) 605 return r; 606 607 return r; 608 } 609 610 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 611 { 612 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 613 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 614 } 615 616 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 617 { 618 int r, i, num_xcc; 619 u32 *hpd; 620 const __le32 *fw_data; 621 unsigned fw_size; 622 u32 *fw; 623 size_t mec_hpd_size; 624 625 const struct gfx_firmware_header_v1_0 *mec_hdr; 626 627 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 628 for (i = 0; i < num_xcc; i++) 629 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 630 AMDGPU_MAX_COMPUTE_QUEUES); 631 632 /* take ownership of the relevant compute queues */ 633 amdgpu_gfx_compute_queue_acquire(adev); 634 mec_hpd_size = 635 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 636 if (mec_hpd_size) { 637 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 638 AMDGPU_GEM_DOMAIN_VRAM | 639 AMDGPU_GEM_DOMAIN_GTT, 640 &adev->gfx.mec.hpd_eop_obj, 641 &adev->gfx.mec.hpd_eop_gpu_addr, 642 (void **)&hpd); 643 if (r) { 644 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 645 gfx_v9_4_3_mec_fini(adev); 646 return r; 647 } 648 649 if (amdgpu_emu_mode == 1) { 650 for (i = 0; i < mec_hpd_size / 4; i++) { 651 memset((void *)(hpd + i), 0, 4); 652 if (i % 50 == 0) 653 msleep(1); 654 } 655 } else { 656 memset(hpd, 0, mec_hpd_size); 657 } 658 659 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 660 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 661 } 662 663 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 664 665 fw_data = (const __le32 *) 666 (adev->gfx.mec_fw->data + 667 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 668 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 669 670 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 671 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 672 &adev->gfx.mec.mec_fw_obj, 673 &adev->gfx.mec.mec_fw_gpu_addr, 674 (void **)&fw); 675 if (r) { 676 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 677 gfx_v9_4_3_mec_fini(adev); 678 return r; 679 } 680 681 memcpy(fw, fw_data, fw_size); 682 683 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 684 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 685 686 return 0; 687 } 688 689 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 690 u32 sh_num, u32 instance, int xcc_id) 691 { 692 u32 data; 693 694 if (instance == 0xffffffff) 695 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 696 INSTANCE_BROADCAST_WRITES, 1); 697 else 698 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 699 INSTANCE_INDEX, instance); 700 701 if (se_num == 0xffffffff) 702 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 703 SE_BROADCAST_WRITES, 1); 704 else 705 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 706 707 if (sh_num == 0xffffffff) 708 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 709 SH_BROADCAST_WRITES, 1); 710 else 711 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 712 713 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 714 } 715 716 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 717 { 718 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 719 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 720 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 721 (address << SQ_IND_INDEX__INDEX__SHIFT) | 722 (SQ_IND_INDEX__FORCE_READ_MASK)); 723 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 724 } 725 726 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 727 uint32_t wave, uint32_t thread, 728 uint32_t regno, uint32_t num, uint32_t *out) 729 { 730 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 731 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 732 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 733 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 734 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 735 (SQ_IND_INDEX__FORCE_READ_MASK) | 736 (SQ_IND_INDEX__AUTO_INCR_MASK)); 737 while (num--) 738 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 739 } 740 741 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 742 uint32_t xcc_id, uint32_t simd, uint32_t wave, 743 uint32_t *dst, int *no_fields) 744 { 745 /* type 1 wave data */ 746 dst[(*no_fields)++] = 1; 747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 761 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 762 } 763 764 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 765 uint32_t wave, uint32_t start, 766 uint32_t size, uint32_t *dst) 767 { 768 wave_read_regs(adev, xcc_id, simd, wave, 0, 769 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 770 } 771 772 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 773 uint32_t wave, uint32_t thread, 774 uint32_t start, uint32_t size, 775 uint32_t *dst) 776 { 777 wave_read_regs(adev, xcc_id, simd, wave, thread, 778 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 779 } 780 781 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 782 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 783 { 784 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 785 } 786 787 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 788 { 789 u32 xcp_ctl; 790 791 /* Value is expected to be the same on all, fetch from first instance */ 792 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 793 794 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 795 } 796 797 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 798 int num_xccs_per_xcp) 799 { 800 int ret, i, num_xcc; 801 u32 tmp = 0; 802 803 if (adev->psp.funcs) { 804 ret = psp_spatial_partition(&adev->psp, 805 NUM_XCC(adev->gfx.xcc_mask) / 806 num_xccs_per_xcp); 807 if (ret) 808 return ret; 809 } else { 810 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 811 812 for (i = 0; i < num_xcc; i++) { 813 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 814 num_xccs_per_xcp); 815 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 816 i % num_xccs_per_xcp); 817 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 818 tmp); 819 } 820 ret = 0; 821 } 822 823 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 824 825 return ret; 826 } 827 828 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 829 { 830 int xcc; 831 832 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 833 if (!xcc) { 834 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 835 return -EINVAL; 836 } 837 838 return xcc - 1; 839 } 840 841 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 842 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 843 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 844 .read_wave_data = &gfx_v9_4_3_read_wave_data, 845 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 846 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 847 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 848 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 849 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 850 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 851 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 852 }; 853 854 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 855 struct aca_bank *bank, enum aca_smu_type type, 856 void *data) 857 { 858 struct aca_bank_info info; 859 u64 misc0; 860 u32 instlo; 861 int ret; 862 863 ret = aca_bank_info_decode(bank, &info); 864 if (ret) 865 return ret; 866 867 /* NOTE: overwrite info.die_id with xcd id for gfx */ 868 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 869 instlo &= GENMASK(31, 1); 870 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 871 872 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 873 874 switch (type) { 875 case ACA_SMU_TYPE_UE: 876 bank->aca_err_type = ACA_ERROR_TYPE_UE; 877 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL); 878 break; 879 case ACA_SMU_TYPE_CE: 880 bank->aca_err_type = ACA_ERROR_TYPE_CE; 881 ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 882 ACA_REG__MISC0__ERRCNT(misc0)); 883 break; 884 default: 885 return -EINVAL; 886 } 887 888 return ret; 889 } 890 891 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 892 enum aca_smu_type type, void *data) 893 { 894 u32 instlo; 895 896 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 897 instlo &= GENMASK(31, 1); 898 switch (instlo) { 899 case mmSMNAID_XCD0_MCA_SMU: 900 case mmSMNAID_XCD1_MCA_SMU: 901 case mmSMNXCD_XCD0_MCA_SMU: 902 return true; 903 default: 904 break; 905 } 906 907 return false; 908 } 909 910 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 911 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 912 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 913 }; 914 915 static const struct aca_info gfx_v9_4_3_aca_info = { 916 .hwip = ACA_HWIP_TYPE_SMU, 917 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 918 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 919 }; 920 921 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 922 { 923 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 924 adev->gfx.ras = &gfx_v9_4_3_ras; 925 926 adev->gfx.config.max_hw_contexts = 8; 927 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 928 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 929 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 930 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 931 adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG; 932 933 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 934 REG_GET_FIELD( 935 adev->gfx.config.gb_addr_config, 936 GB_ADDR_CONFIG, 937 NUM_PIPES); 938 939 adev->gfx.config.max_tile_pipes = 940 adev->gfx.config.gb_addr_config_fields.num_pipes; 941 942 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 943 REG_GET_FIELD( 944 adev->gfx.config.gb_addr_config, 945 GB_ADDR_CONFIG, 946 NUM_BANKS); 947 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 948 REG_GET_FIELD( 949 adev->gfx.config.gb_addr_config, 950 GB_ADDR_CONFIG, 951 MAX_COMPRESSED_FRAGS); 952 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 953 REG_GET_FIELD( 954 adev->gfx.config.gb_addr_config, 955 GB_ADDR_CONFIG, 956 NUM_RB_PER_SE); 957 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 958 REG_GET_FIELD( 959 adev->gfx.config.gb_addr_config, 960 GB_ADDR_CONFIG, 961 NUM_SHADER_ENGINES); 962 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 963 REG_GET_FIELD( 964 adev->gfx.config.gb_addr_config, 965 GB_ADDR_CONFIG, 966 PIPE_INTERLEAVE_SIZE)); 967 968 return 0; 969 } 970 971 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 972 int xcc_id, int mec, int pipe, int queue) 973 { 974 unsigned irq_type; 975 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 976 unsigned int hw_prio; 977 uint32_t xcc_doorbell_start; 978 979 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 980 ring_id]; 981 982 /* mec0 is me1 */ 983 ring->xcc_id = xcc_id; 984 ring->me = mec + 1; 985 ring->pipe = pipe; 986 ring->queue = queue; 987 988 ring->ring_obj = NULL; 989 ring->use_doorbell = true; 990 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 991 xcc_id * adev->doorbell_index.xcc_doorbell_range; 992 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 993 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 994 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 995 GFX9_MEC_HPD_SIZE; 996 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 997 sprintf(ring->name, "comp_%d.%d.%d.%d", 998 ring->xcc_id, ring->me, ring->pipe, ring->queue); 999 1000 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1001 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1002 + ring->pipe; 1003 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1004 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1005 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1006 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1007 hw_prio, NULL); 1008 } 1009 1010 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1011 { 1012 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1013 uint32_t *ptr, num_xcc, inst; 1014 1015 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1016 1017 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1018 if (!ptr) { 1019 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1020 adev->gfx.ip_dump_core = NULL; 1021 } else { 1022 adev->gfx.ip_dump_core = ptr; 1023 } 1024 1025 /* Allocate memory for compute queue registers for all the instances */ 1026 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1027 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1028 adev->gfx.mec.num_queue_per_pipe; 1029 1030 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1031 if (!ptr) { 1032 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1033 adev->gfx.ip_dump_compute_queues = NULL; 1034 } else { 1035 adev->gfx.ip_dump_compute_queues = ptr; 1036 } 1037 } 1038 1039 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1040 { 1041 int i, j, k, r, ring_id, xcc_id, num_xcc; 1042 struct amdgpu_device *adev = ip_block->adev; 1043 1044 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1045 case IP_VERSION(9, 4, 3): 1046 case IP_VERSION(9, 4, 4): 1047 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1048 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1049 if (adev->gfx.mec_fw_version >= 153) { 1050 adev->gfx.enable_cleaner_shader = true; 1051 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1052 if (r) { 1053 adev->gfx.enable_cleaner_shader = false; 1054 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1055 } 1056 } 1057 break; 1058 default: 1059 adev->gfx.enable_cleaner_shader = false; 1060 break; 1061 } 1062 1063 adev->gfx.mec.num_mec = 2; 1064 adev->gfx.mec.num_pipe_per_mec = 4; 1065 adev->gfx.mec.num_queue_per_pipe = 8; 1066 1067 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1068 1069 /* EOP Event */ 1070 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1071 if (r) 1072 return r; 1073 1074 /* Bad opcode Event */ 1075 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1076 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1077 &adev->gfx.bad_op_irq); 1078 if (r) 1079 return r; 1080 1081 /* Privileged reg */ 1082 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1083 &adev->gfx.priv_reg_irq); 1084 if (r) 1085 return r; 1086 1087 /* Privileged inst */ 1088 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1089 &adev->gfx.priv_inst_irq); 1090 if (r) 1091 return r; 1092 1093 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1094 1095 r = adev->gfx.rlc.funcs->init(adev); 1096 if (r) { 1097 DRM_ERROR("Failed to init rlc BOs!\n"); 1098 return r; 1099 } 1100 1101 r = gfx_v9_4_3_mec_init(adev); 1102 if (r) { 1103 DRM_ERROR("Failed to init MEC BOs!\n"); 1104 return r; 1105 } 1106 1107 /* set up the compute queues - allocate horizontally across pipes */ 1108 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1109 ring_id = 0; 1110 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1111 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1112 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1113 k++) { 1114 if (!amdgpu_gfx_is_mec_queue_enabled( 1115 adev, xcc_id, i, k, j)) 1116 continue; 1117 1118 r = gfx_v9_4_3_compute_ring_init(adev, 1119 ring_id, 1120 xcc_id, 1121 i, k, j); 1122 if (r) 1123 return r; 1124 1125 ring_id++; 1126 } 1127 } 1128 } 1129 1130 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1131 if (r) { 1132 DRM_ERROR("Failed to init KIQ BOs!\n"); 1133 return r; 1134 } 1135 1136 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1137 if (r) 1138 return r; 1139 1140 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1141 r = amdgpu_gfx_mqd_sw_init(adev, 1142 sizeof(struct v9_mqd_allocation), xcc_id); 1143 if (r) 1144 return r; 1145 } 1146 1147 adev->gfx.compute_supported_reset = 1148 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1149 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1150 case IP_VERSION(9, 4, 3): 1151 case IP_VERSION(9, 4, 4): 1152 if ((adev->gfx.mec_fw_version >= 155) && 1153 !amdgpu_sriov_vf(adev) && 1154 !adev->debug_disable_gpu_ring_reset) { 1155 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1156 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1157 } 1158 break; 1159 case IP_VERSION(9, 5, 0): 1160 if ((adev->gfx.mec_fw_version >= 21) && 1161 !amdgpu_sriov_vf(adev) && 1162 !adev->debug_disable_gpu_ring_reset) { 1163 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1164 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1165 } 1166 break; 1167 default: 1168 break; 1169 } 1170 r = gfx_v9_4_3_gpu_early_init(adev); 1171 if (r) 1172 return r; 1173 1174 r = amdgpu_gfx_ras_sw_init(adev); 1175 if (r) 1176 return r; 1177 1178 r = amdgpu_gfx_sysfs_init(adev); 1179 if (r) 1180 return r; 1181 1182 gfx_v9_4_3_alloc_ip_dump(adev); 1183 1184 return 0; 1185 } 1186 1187 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1188 { 1189 int i, num_xcc; 1190 struct amdgpu_device *adev = ip_block->adev; 1191 1192 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1193 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1194 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1195 1196 for (i = 0; i < num_xcc; i++) { 1197 amdgpu_gfx_mqd_sw_fini(adev, i); 1198 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1199 amdgpu_gfx_kiq_fini(adev, i); 1200 } 1201 1202 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1203 1204 gfx_v9_4_3_mec_fini(adev); 1205 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1206 gfx_v9_4_3_free_microcode(adev); 1207 amdgpu_gfx_sysfs_fini(adev); 1208 1209 kfree(adev->gfx.ip_dump_core); 1210 kfree(adev->gfx.ip_dump_compute_queues); 1211 1212 return 0; 1213 } 1214 1215 #define DEFAULT_SH_MEM_BASES (0x6000) 1216 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1217 int xcc_id) 1218 { 1219 int i; 1220 uint32_t sh_mem_config; 1221 uint32_t sh_mem_bases; 1222 uint32_t data; 1223 1224 /* 1225 * Configure apertures: 1226 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1227 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1228 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1229 */ 1230 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1231 1232 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1233 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1234 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1235 1236 mutex_lock(&adev->srbm_mutex); 1237 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1238 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1239 /* CP and shaders */ 1240 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1241 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1242 1243 /* Enable trap for each kfd vmid. */ 1244 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1245 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1246 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1247 } 1248 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1249 mutex_unlock(&adev->srbm_mutex); 1250 1251 /* 1252 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1253 * access. These should be enabled by FW for target VMIDs. 1254 */ 1255 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1256 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1257 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1258 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1259 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1260 } 1261 } 1262 1263 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1264 { 1265 int vmid; 1266 1267 /* 1268 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1269 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1270 * the driver can enable them for graphics. VMID0 should maintain 1271 * access so that HWS firmware can save/restore entries. 1272 */ 1273 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1274 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1275 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1276 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1277 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1278 } 1279 } 1280 1281 /* For ASICs that needs xnack chain and MEC version supports, set SG_CONFIG1 1282 * DISABLE_XNACK_CHECK_IN_RETRY_DISABLE bit and inform KFD to set xnack_chain 1283 * bit in SET_RESOURCES 1284 */ 1285 static void gfx_v9_4_3_xcc_init_sq(struct amdgpu_device *adev, int xcc_id) 1286 { 1287 uint32_t data; 1288 1289 if (!(adev->gmc.xnack_flags & AMDGPU_GMC_XNACK_FLAG_CHAIN)) 1290 return; 1291 1292 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1); 1293 data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1); 1294 WREG32_SOC15(GC, xcc_id, regSQ_CONFIG1, data); 1295 } 1296 1297 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1298 int xcc_id) 1299 { 1300 u32 tmp; 1301 int i; 1302 1303 /* XXX SH_MEM regs */ 1304 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1305 mutex_lock(&adev->srbm_mutex); 1306 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1307 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1308 /* CP and shaders */ 1309 if (i == 0) { 1310 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1311 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1312 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1313 !!adev->gmc.noretry); 1314 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1315 regSH_MEM_CONFIG, tmp); 1316 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1317 regSH_MEM_BASES, 0); 1318 } else { 1319 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1320 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1321 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1322 !!adev->gmc.noretry); 1323 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1324 regSH_MEM_CONFIG, tmp); 1325 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1326 (adev->gmc.private_aperture_start >> 1327 48)); 1328 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1329 (adev->gmc.shared_aperture_start >> 1330 48)); 1331 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1332 regSH_MEM_BASES, tmp); 1333 } 1334 } 1335 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1336 1337 mutex_unlock(&adev->srbm_mutex); 1338 1339 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1340 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1341 gfx_v9_4_3_xcc_init_sq(adev, xcc_id); 1342 } 1343 1344 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1345 { 1346 int i, num_xcc; 1347 1348 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1349 1350 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1351 adev->gfx.config.db_debug2 = 1352 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1353 1354 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1355 /* ToDo: GC 9.4.4 */ 1356 case IP_VERSION(9, 4, 3): 1357 if (adev->gfx.mec_fw_version >= 184 && 1358 (amdgpu_sriov_reg_access_sq_config(adev) || 1359 !amdgpu_sriov_vf(adev))) 1360 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1361 break; 1362 case IP_VERSION(9, 5, 0): 1363 if (adev->gfx.mec_fw_version >= 23) 1364 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1365 break; 1366 default: 1367 break; 1368 } 1369 1370 for (i = 0; i < num_xcc; i++) 1371 gfx_v9_4_3_xcc_constants_init(adev, i); 1372 } 1373 1374 static void 1375 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1376 int xcc_id) 1377 { 1378 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1379 } 1380 1381 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1382 { 1383 /* 1384 * Rlc save restore list is workable since v2_1. 1385 */ 1386 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1387 } 1388 1389 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1390 { 1391 uint32_t data; 1392 1393 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1394 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1395 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1396 } 1397 1398 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1399 { 1400 uint32_t rlc_setting; 1401 1402 /* if RLC is not enabled, do nothing */ 1403 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1404 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1405 return false; 1406 1407 return true; 1408 } 1409 1410 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1411 { 1412 uint32_t data; 1413 unsigned i; 1414 1415 data = RLC_SAFE_MODE__CMD_MASK; 1416 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1417 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1418 1419 /* wait for RLC_SAFE_MODE */ 1420 for (i = 0; i < adev->usec_timeout; i++) { 1421 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1422 break; 1423 udelay(1); 1424 } 1425 } 1426 1427 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1428 int xcc_id) 1429 { 1430 uint32_t data; 1431 1432 data = RLC_SAFE_MODE__CMD_MASK; 1433 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1434 } 1435 1436 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1437 { 1438 int xcc_id, num_xcc; 1439 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1440 1441 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1442 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1443 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1444 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1445 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1446 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1447 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1448 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1449 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1450 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1451 } 1452 adev->gfx.rlc.rlcg_reg_access_supported = true; 1453 } 1454 1455 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1456 { 1457 /* init spm vmid with 0xf */ 1458 if (adev->gfx.rlc.funcs->update_spm_vmid) 1459 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 1460 1461 return 0; 1462 } 1463 1464 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1465 int xcc_id) 1466 { 1467 u32 i, j, k; 1468 u32 mask; 1469 1470 mutex_lock(&adev->grbm_idx_mutex); 1471 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1472 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1473 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1474 xcc_id); 1475 for (k = 0; k < adev->usec_timeout; k++) { 1476 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1477 break; 1478 udelay(1); 1479 } 1480 if (k == adev->usec_timeout) { 1481 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1482 0xffffffff, 1483 0xffffffff, xcc_id); 1484 mutex_unlock(&adev->grbm_idx_mutex); 1485 drm_info(adev_to_drm(adev), "Timeout wait for RLC serdes %u,%u\n", 1486 i, j); 1487 return; 1488 } 1489 } 1490 } 1491 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1492 xcc_id); 1493 mutex_unlock(&adev->grbm_idx_mutex); 1494 1495 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1496 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1497 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1498 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1499 for (k = 0; k < adev->usec_timeout; k++) { 1500 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1501 break; 1502 udelay(1); 1503 } 1504 } 1505 1506 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1507 bool enable, int xcc_id) 1508 { 1509 u32 tmp; 1510 1511 /* These interrupts should be enabled to drive DS clock */ 1512 1513 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1514 1515 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1516 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1517 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1518 1519 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1520 } 1521 1522 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1523 { 1524 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1525 RLC_ENABLE_F32, 0); 1526 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1527 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1528 } 1529 1530 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1531 { 1532 int i, num_xcc; 1533 1534 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1535 for (i = 0; i < num_xcc; i++) 1536 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1537 } 1538 1539 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1540 { 1541 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1542 SOFT_RESET_RLC, 1); 1543 udelay(50); 1544 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1545 SOFT_RESET_RLC, 0); 1546 udelay(50); 1547 } 1548 1549 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1550 { 1551 int i, num_xcc; 1552 1553 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1554 for (i = 0; i < num_xcc; i++) 1555 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1556 } 1557 1558 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1559 { 1560 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1561 RLC_ENABLE_F32, 1); 1562 udelay(50); 1563 1564 /* carrizo do enable cp interrupt after cp inited */ 1565 if (!(adev->flags & AMD_IS_APU)) { 1566 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1567 udelay(50); 1568 } 1569 } 1570 1571 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1572 { 1573 #ifdef AMDGPU_RLC_DEBUG_RETRY 1574 u32 rlc_ucode_ver; 1575 #endif 1576 int i, num_xcc; 1577 1578 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1579 for (i = 0; i < num_xcc; i++) { 1580 gfx_v9_4_3_xcc_rlc_start(adev, i); 1581 #ifdef AMDGPU_RLC_DEBUG_RETRY 1582 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1583 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1584 if (rlc_ucode_ver == 0x108) { 1585 dev_info(adev->dev, 1586 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i\n", 1587 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1588 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1589 * default is 0x9C4 to create a 100us interval */ 1590 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1591 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1592 * to disable the page fault retry interrupts, default is 1593 * 0x100 (256) */ 1594 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1595 } 1596 #endif 1597 } 1598 } 1599 1600 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1601 int xcc_id) 1602 { 1603 const struct rlc_firmware_header_v2_0 *hdr; 1604 const __le32 *fw_data; 1605 unsigned i, fw_size; 1606 1607 if (!adev->gfx.rlc_fw) 1608 return -EINVAL; 1609 1610 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1611 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1612 1613 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1614 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1615 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1616 1617 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1618 RLCG_UCODE_LOADING_START_ADDRESS); 1619 for (i = 0; i < fw_size; i++) { 1620 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1621 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1622 msleep(1); 1623 } 1624 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1625 } 1626 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1627 1628 return 0; 1629 } 1630 1631 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1632 { 1633 int r; 1634 1635 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1636 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1637 /* legacy rlc firmware loading */ 1638 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1639 if (r) 1640 return r; 1641 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1642 } 1643 1644 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1645 /* disable CG */ 1646 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1647 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1648 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1649 1650 return 0; 1651 } 1652 1653 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1654 { 1655 int r, i, num_xcc; 1656 1657 if (amdgpu_sriov_vf(adev)) 1658 return 0; 1659 1660 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1661 for (i = 0; i < num_xcc; i++) { 1662 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1663 if (r) 1664 return r; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1671 int inst, struct amdgpu_ring *ring, unsigned int vmid) 1672 { 1673 u32 reg, pre_data, data; 1674 1675 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL); 1676 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1677 pre_data = RREG32_NO_KIQ(reg); 1678 else 1679 pre_data = RREG32(reg); 1680 1681 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1682 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1683 1684 if (pre_data != data) { 1685 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1686 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1687 } else 1688 WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1689 } 1690 } 1691 1692 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1693 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1694 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1695 }; 1696 1697 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1698 uint32_t offset, 1699 struct soc15_reg_rlcg *entries, int arr_size) 1700 { 1701 int i, inst; 1702 uint32_t reg; 1703 1704 if (!entries) 1705 return false; 1706 1707 for (i = 0; i < arr_size; i++) { 1708 const struct soc15_reg_rlcg *entry; 1709 1710 entry = &entries[i]; 1711 inst = adev->ip_map.logical_to_dev_inst ? 1712 adev->ip_map.logical_to_dev_inst( 1713 adev, entry->hwip, entry->instance) : 1714 entry->instance; 1715 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1716 entry->reg; 1717 if (offset == reg) 1718 return true; 1719 } 1720 1721 return false; 1722 } 1723 1724 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1725 { 1726 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1727 (void *)rlcg_access_gc_9_4_3, 1728 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1729 } 1730 1731 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1732 bool enable, int xcc_id) 1733 { 1734 if (enable) { 1735 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1736 } else { 1737 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1738 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1739 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1740 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1741 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1742 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1743 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1744 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1745 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1746 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1747 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1748 } 1749 udelay(50); 1750 } 1751 1752 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1753 int xcc_id) 1754 { 1755 const struct gfx_firmware_header_v1_0 *mec_hdr; 1756 const __le32 *fw_data; 1757 unsigned i; 1758 u32 tmp; 1759 u32 mec_ucode_addr_offset; 1760 u32 mec_ucode_data_offset; 1761 1762 if (!adev->gfx.mec_fw) 1763 return -EINVAL; 1764 1765 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1766 1767 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1768 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1769 1770 fw_data = (const __le32 *) 1771 (adev->gfx.mec_fw->data + 1772 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1773 tmp = 0; 1774 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1775 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1776 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1777 1778 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1779 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1780 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1781 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1782 1783 mec_ucode_addr_offset = 1784 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1785 mec_ucode_data_offset = 1786 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1787 1788 /* MEC1 */ 1789 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1790 for (i = 0; i < mec_hdr->jt_size; i++) 1791 WREG32(mec_ucode_data_offset, 1792 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1793 1794 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1795 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1796 1797 return 0; 1798 } 1799 1800 /* KIQ functions */ 1801 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1802 { 1803 uint32_t tmp; 1804 struct amdgpu_device *adev = ring->adev; 1805 1806 /* tell RLC which is KIQ queue */ 1807 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1808 tmp &= 0xffffff00; 1809 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1810 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1811 } 1812 1813 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1814 { 1815 struct amdgpu_device *adev = ring->adev; 1816 1817 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1818 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1819 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1820 mqd->cp_hqd_queue_priority = 1821 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1822 } 1823 } 1824 } 1825 1826 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1827 { 1828 struct amdgpu_device *adev = ring->adev; 1829 struct v9_mqd *mqd = ring->mqd_ptr; 1830 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1831 uint32_t tmp; 1832 1833 mqd->header = 0xC0310800; 1834 mqd->compute_pipelinestat_enable = 0x00000001; 1835 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1836 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1837 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1838 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1839 mqd->compute_misc_reserved = 0x00000003; 1840 1841 mqd->dynamic_cu_mask_addr_lo = 1842 lower_32_bits(ring->mqd_gpu_addr 1843 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1844 mqd->dynamic_cu_mask_addr_hi = 1845 upper_32_bits(ring->mqd_gpu_addr 1846 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1847 1848 eop_base_addr = ring->eop_gpu_addr >> 8; 1849 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1850 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1851 1852 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1853 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1854 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1855 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1856 1857 mqd->cp_hqd_eop_control = tmp; 1858 1859 /* enable doorbell? */ 1860 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1861 1862 if (ring->use_doorbell) { 1863 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1864 DOORBELL_OFFSET, ring->doorbell_index); 1865 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1866 DOORBELL_EN, 1); 1867 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1868 DOORBELL_SOURCE, 0); 1869 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1870 DOORBELL_HIT, 0); 1871 if (amdgpu_sriov_multi_vf_mode(adev)) 1872 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1873 DOORBELL_MODE, 1); 1874 } else { 1875 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1876 DOORBELL_EN, 0); 1877 } 1878 1879 mqd->cp_hqd_pq_doorbell_control = tmp; 1880 1881 /* disable the queue if it's active */ 1882 ring->wptr = 0; 1883 mqd->cp_hqd_dequeue_request = 0; 1884 mqd->cp_hqd_pq_rptr = 0; 1885 mqd->cp_hqd_pq_wptr_lo = 0; 1886 mqd->cp_hqd_pq_wptr_hi = 0; 1887 1888 /* set the pointer to the MQD */ 1889 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1890 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1891 1892 /* set MQD vmid to 0 */ 1893 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1894 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1895 mqd->cp_mqd_control = tmp; 1896 1897 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1898 hqd_gpu_addr = ring->gpu_addr >> 8; 1899 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1900 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1901 1902 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1903 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1904 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1905 (order_base_2(ring->ring_size / 4) - 1)); 1906 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1907 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1908 #ifdef __BIG_ENDIAN 1909 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1910 #endif 1911 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1912 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1913 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1914 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1915 mqd->cp_hqd_pq_control = tmp; 1916 1917 /* set the wb address whether it's enabled or not */ 1918 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1919 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1920 mqd->cp_hqd_pq_rptr_report_addr_hi = 1921 upper_32_bits(wb_gpu_addr) & 0xffff; 1922 1923 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1924 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1925 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1926 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1927 1928 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1929 ring->wptr = 0; 1930 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1931 1932 /* set the vmid for the queue */ 1933 mqd->cp_hqd_vmid = 0; 1934 1935 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1936 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1937 mqd->cp_hqd_persistent_state = tmp; 1938 1939 /* set MIN_IB_AVAIL_SIZE */ 1940 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1941 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1942 mqd->cp_hqd_ib_control = tmp; 1943 1944 /* set static priority for a queue/ring */ 1945 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1946 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1947 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); 1948 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 1949 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 1950 mqd->cp_hqd_quantum = tmp; 1951 1952 /* map_queues packet doesn't need activate the queue, 1953 * so only kiq need set this field. 1954 */ 1955 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1956 mqd->cp_hqd_active = 1; 1957 1958 return 0; 1959 } 1960 1961 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1962 int xcc_id) 1963 { 1964 struct amdgpu_device *adev = ring->adev; 1965 struct v9_mqd *mqd = ring->mqd_ptr; 1966 int j; 1967 1968 /* disable wptr polling */ 1969 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1970 1971 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1972 mqd->cp_hqd_eop_base_addr_lo); 1973 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1974 mqd->cp_hqd_eop_base_addr_hi); 1975 1976 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1977 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1978 mqd->cp_hqd_eop_control); 1979 1980 /* enable doorbell? */ 1981 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1982 mqd->cp_hqd_pq_doorbell_control); 1983 1984 /* disable the queue if it's active */ 1985 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1986 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1987 for (j = 0; j < adev->usec_timeout; j++) { 1988 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1989 break; 1990 udelay(1); 1991 } 1992 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1993 mqd->cp_hqd_dequeue_request); 1994 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1995 mqd->cp_hqd_pq_rptr); 1996 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1997 mqd->cp_hqd_pq_wptr_lo); 1998 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1999 mqd->cp_hqd_pq_wptr_hi); 2000 } 2001 2002 /* set the pointer to the MQD */ 2003 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 2004 mqd->cp_mqd_base_addr_lo); 2005 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 2006 mqd->cp_mqd_base_addr_hi); 2007 2008 /* set MQD vmid to 0 */ 2009 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 2010 mqd->cp_mqd_control); 2011 2012 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2013 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 2014 mqd->cp_hqd_pq_base_lo); 2015 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 2016 mqd->cp_hqd_pq_base_hi); 2017 2018 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2019 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 2020 mqd->cp_hqd_pq_control); 2021 2022 /* set the wb address whether it's enabled or not */ 2023 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2024 mqd->cp_hqd_pq_rptr_report_addr_lo); 2025 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2026 mqd->cp_hqd_pq_rptr_report_addr_hi); 2027 2028 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2029 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2030 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2031 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2032 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2033 2034 /* enable the doorbell if requested */ 2035 if (ring->use_doorbell) { 2036 WREG32_SOC15( 2037 GC, GET_INST(GC, xcc_id), 2038 regCP_MEC_DOORBELL_RANGE_LOWER, 2039 ((adev->doorbell_index.kiq + 2040 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2041 2) << 2); 2042 WREG32_SOC15( 2043 GC, GET_INST(GC, xcc_id), 2044 regCP_MEC_DOORBELL_RANGE_UPPER, 2045 ((adev->doorbell_index.userqueue_end + 2046 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2047 2) << 2); 2048 } 2049 2050 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2051 mqd->cp_hqd_pq_doorbell_control); 2052 2053 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2054 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2055 mqd->cp_hqd_pq_wptr_lo); 2056 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2057 mqd->cp_hqd_pq_wptr_hi); 2058 2059 /* set the vmid for the queue */ 2060 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2061 2062 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2063 mqd->cp_hqd_persistent_state); 2064 2065 /* activate the queue */ 2066 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2067 mqd->cp_hqd_active); 2068 2069 if (ring->use_doorbell) 2070 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2071 2072 return 0; 2073 } 2074 2075 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2076 int xcc_id) 2077 { 2078 struct amdgpu_device *adev = ring->adev; 2079 int j; 2080 2081 /* disable the queue if it's active */ 2082 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2083 2084 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2085 2086 for (j = 0; j < adev->usec_timeout; j++) { 2087 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2088 break; 2089 udelay(1); 2090 } 2091 2092 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2093 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2094 2095 /* Manual disable if dequeue request times out */ 2096 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2097 } 2098 2099 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2100 0); 2101 } 2102 2103 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2104 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2105 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2106 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2107 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2108 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2109 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2110 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2111 2112 return 0; 2113 } 2114 2115 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2116 { 2117 struct amdgpu_device *adev = ring->adev; 2118 struct v9_mqd *mqd = ring->mqd_ptr; 2119 struct v9_mqd *tmp_mqd; 2120 2121 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2122 2123 /* GPU could be in bad state during probe, driver trigger the reset 2124 * after load the SMU, in this case , the mqd is not be initialized. 2125 * driver need to re-init the mqd. 2126 * check mqd->cp_hqd_pq_control since this value should not be 0 2127 */ 2128 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2129 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2130 /* for GPU_RESET case , reset MQD to a clean status */ 2131 if (adev->gfx.kiq[xcc_id].mqd_backup) 2132 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2133 2134 /* reset ring buffer */ 2135 ring->wptr = 0; 2136 amdgpu_ring_clear_ring(ring); 2137 mutex_lock(&adev->srbm_mutex); 2138 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2139 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2140 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2141 mutex_unlock(&adev->srbm_mutex); 2142 } else { 2143 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2144 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2145 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2146 mutex_lock(&adev->srbm_mutex); 2147 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2148 amdgpu_ring_clear_ring(ring); 2149 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2150 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2151 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2152 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2153 mutex_unlock(&adev->srbm_mutex); 2154 2155 if (adev->gfx.kiq[xcc_id].mqd_backup) 2156 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2157 } 2158 2159 return 0; 2160 } 2161 2162 static void gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, 2163 bool restore) 2164 { 2165 struct amdgpu_device *adev = ring->adev; 2166 struct v9_mqd *mqd = ring->mqd_ptr; 2167 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2168 struct v9_mqd *tmp_mqd; 2169 2170 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2171 * is not be initialized before 2172 */ 2173 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2174 2175 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2176 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2177 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2178 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2179 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2180 mutex_lock(&adev->srbm_mutex); 2181 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2182 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2183 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2184 mutex_unlock(&adev->srbm_mutex); 2185 2186 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2187 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2188 } else { 2189 /* restore MQD to a clean status */ 2190 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2191 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2192 /* reset ring buffer */ 2193 ring->wptr = 0; 2194 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2195 amdgpu_ring_clear_ring(ring); 2196 } 2197 } 2198 2199 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2200 { 2201 struct amdgpu_ring *ring; 2202 int j; 2203 2204 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2205 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2206 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2207 mutex_lock(&adev->srbm_mutex); 2208 soc15_grbm_select(adev, ring->me, 2209 ring->pipe, 2210 ring->queue, 0, GET_INST(GC, xcc_id)); 2211 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2212 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2213 mutex_unlock(&adev->srbm_mutex); 2214 } 2215 } 2216 2217 return 0; 2218 } 2219 2220 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2221 { 2222 gfx_v9_4_3_xcc_kiq_init_queue(&adev->gfx.kiq[xcc_id].ring, xcc_id); 2223 return 0; 2224 } 2225 2226 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2227 { 2228 struct amdgpu_ring *ring; 2229 int i; 2230 2231 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2232 2233 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2234 ring = &adev->gfx.compute_ring[i + xcc_id * 2235 adev->gfx.num_compute_rings]; 2236 2237 gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2238 } 2239 2240 return amdgpu_gfx_enable_kcq(adev, xcc_id); 2241 } 2242 2243 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2244 { 2245 struct amdgpu_ring *ring; 2246 int r, j; 2247 2248 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2249 2250 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2251 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2252 2253 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2254 if (r) 2255 return r; 2256 } else { 2257 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2258 } 2259 2260 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2261 if (r) 2262 return r; 2263 2264 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2265 if (r) 2266 return r; 2267 2268 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2269 ring = &adev->gfx.compute_ring 2270 [j + xcc_id * adev->gfx.num_compute_rings]; 2271 r = amdgpu_ring_test_helper(ring); 2272 if (r) 2273 return r; 2274 } 2275 2276 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2277 2278 return 0; 2279 } 2280 2281 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2282 { 2283 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2284 2285 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2286 if (amdgpu_sriov_vf(adev)) { 2287 enum amdgpu_gfx_partition mode; 2288 2289 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2290 AMDGPU_XCP_FL_NONE); 2291 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2292 return -EINVAL; 2293 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2294 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2295 num_xcp = num_xcc / num_xcc_per_xcp; 2296 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2297 2298 } else { 2299 if (adev->in_suspend) 2300 amdgpu_xcp_restore_partition_mode(adev->xcp_mgr); 2301 else if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2302 AMDGPU_XCP_FL_NONE) == 2303 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2304 r = amdgpu_xcp_switch_partition_mode( 2305 adev->xcp_mgr, amdgpu_user_partt_mode); 2306 } 2307 if (r) 2308 return r; 2309 2310 for (i = 0; i < num_xcc; i++) { 2311 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2312 if (r) 2313 return r; 2314 } 2315 2316 return 0; 2317 } 2318 2319 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2320 { 2321 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2322 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2323 2324 if (amdgpu_sriov_vf(adev)) { 2325 /* must disable polling for SRIOV when hw finished, otherwise 2326 * CPC engine may still keep fetching WB address which is already 2327 * invalid after sw finished and trigger DMAR reading error in 2328 * hypervisor side. 2329 */ 2330 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2331 return; 2332 } 2333 2334 /* Use deinitialize sequence from CAIL when unbinding device 2335 * from driver, otherwise KIQ is hanging when binding back 2336 */ 2337 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2338 mutex_lock(&adev->srbm_mutex); 2339 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2340 adev->gfx.kiq[xcc_id].ring.pipe, 2341 adev->gfx.kiq[xcc_id].ring.queue, 0, 2342 GET_INST(GC, xcc_id)); 2343 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2344 xcc_id); 2345 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2346 mutex_unlock(&adev->srbm_mutex); 2347 } 2348 2349 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2350 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2351 } 2352 2353 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2354 { 2355 int r; 2356 struct amdgpu_device *adev = ip_block->adev; 2357 2358 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2359 adev->gfx.cleaner_shader_ptr); 2360 2361 if (!amdgpu_sriov_vf(adev)) 2362 gfx_v9_4_3_init_golden_registers(adev); 2363 2364 gfx_v9_4_3_constants_init(adev); 2365 2366 r = adev->gfx.rlc.funcs->resume(adev); 2367 if (r) 2368 return r; 2369 2370 r = gfx_v9_4_3_cp_resume(adev); 2371 if (r) 2372 return r; 2373 2374 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2375 if (r) 2376 return r; 2377 2378 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2379 if (r) 2380 goto err_priv_inst; 2381 2382 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2383 if (r) 2384 goto err_bad_op; 2385 2386 return 0; 2387 2388 err_bad_op: 2389 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2390 err_priv_inst: 2391 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2392 return r; 2393 } 2394 2395 static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool enable) 2396 { 2397 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2398 uint32_t ptl_state = enable ? 1 : 0; 2399 uint32_t fmt1, fmt2; 2400 int r; 2401 2402 if (!adev->psp.funcs) 2403 return -EOPNOTSUPP; 2404 2405 if (!ptl->hw_supported) { 2406 fmt1 = GFX_FTYPE_VECTOR; 2407 fmt2 = GFX_FTYPE_F8; 2408 } else { 2409 fmt1 = ptl->fmt1; 2410 fmt2 = ptl->fmt2; 2411 } 2412 2413 /* initialize PTL with default formats: GFX_FTYPE_VECTOR & GFX_FTYPE_F8 */ 2414 r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, 2415 &fmt1, &fmt2); 2416 if (r) 2417 return r; 2418 2419 ptl->hw_supported = true; 2420 2421 atomic_set(&ptl->disable_ref, 0); 2422 if (!enable && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2423 dev_dbg(adev->dev, 2424 "PTL disabled (amdgpu.ptl=%d)\ 2425 To enable, set amdgpu.ptl=1 via module param or kernel cmdline\n", 2426 amdgpu_ptl); 2427 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 2428 } 2429 2430 return 0; 2431 } 2432 2433 static int gfx_v9_4_3_ptl_hw_init(struct amdgpu_device *adev) 2434 { 2435 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2436 bool enable; 2437 2438 switch (amdgpu_ptl) { 2439 case 1: 2440 enable = true; 2441 break; 2442 case 2: 2443 /* Permanently disabled - cannot be re-enabled */ 2444 enable = false; 2445 ptl->permanently_disabled = true; 2446 break; 2447 case -1: 2448 case 0: 2449 default: 2450 enable = false; 2451 break; 2452 } 2453 2454 gfx_v9_4_3_perf_monitor_ptl_init(adev, enable ? 1 : 0); 2455 2456 return 0; 2457 } 2458 2459 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2460 { 2461 struct amdgpu_device *adev = ip_block->adev; 2462 int i, num_xcc; 2463 2464 if (adev->psp.ptl.hw_supported && !amdgpu_in_reset(adev)) 2465 gfx_v9_4_3_perf_monitor_ptl_init(adev, false); 2466 2467 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2468 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2469 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2470 2471 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2472 for (i = 0; i < num_xcc; i++) { 2473 gfx_v9_4_3_xcc_fini(adev, i); 2474 } 2475 2476 return 0; 2477 } 2478 2479 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2480 { 2481 return gfx_v9_4_3_hw_fini(ip_block); 2482 } 2483 2484 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2485 { 2486 return gfx_v9_4_3_hw_init(ip_block); 2487 } 2488 2489 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2490 { 2491 struct amdgpu_device *adev = ip_block->adev; 2492 int i, num_xcc; 2493 u32 gc_ip_version; 2494 2495 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2496 gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 2497 2498 for (i = 0; i < num_xcc; i++) { 2499 if (gc_ip_version == IP_VERSION(9, 4, 4)) { 2500 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2501 GRBM_STATUS, SPI_BUSY)) 2502 return false; 2503 } else { 2504 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2505 GRBM_STATUS, GUI_ACTIVE)) 2506 return false; 2507 } 2508 } 2509 return true; 2510 } 2511 2512 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2513 { 2514 unsigned i; 2515 struct amdgpu_device *adev = ip_block->adev; 2516 2517 for (i = 0; i < adev->usec_timeout; i++) { 2518 if (gfx_v9_4_3_is_idle(ip_block)) 2519 return 0; 2520 udelay(1); 2521 } 2522 return -ETIMEDOUT; 2523 } 2524 2525 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2526 { 2527 u32 grbm_soft_reset = 0; 2528 u32 tmp; 2529 struct amdgpu_device *adev = ip_block->adev; 2530 2531 /* GRBM_STATUS */ 2532 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2533 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2534 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2535 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2536 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2537 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2538 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2539 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2540 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2541 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2542 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2543 } 2544 2545 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2546 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2547 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2548 } 2549 2550 /* GRBM_STATUS2 */ 2551 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2552 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2553 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2554 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2555 2556 2557 if (grbm_soft_reset) { 2558 /* stop the rlc */ 2559 adev->gfx.rlc.funcs->stop(adev); 2560 2561 /* Disable MEC parsing/prefetching */ 2562 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2563 2564 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2565 tmp |= grbm_soft_reset; 2566 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2567 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2568 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2569 2570 udelay(50); 2571 2572 tmp &= ~grbm_soft_reset; 2573 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2574 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2575 2576 /* Wait a little for things to settle down */ 2577 udelay(50); 2578 } 2579 return 0; 2580 } 2581 2582 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2583 uint32_t vmid, 2584 uint32_t gds_base, uint32_t gds_size, 2585 uint32_t gws_base, uint32_t gws_size, 2586 uint32_t oa_base, uint32_t oa_size) 2587 { 2588 struct amdgpu_device *adev = ring->adev; 2589 2590 /* GDS Base */ 2591 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2592 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2593 gds_base); 2594 2595 /* GDS Size */ 2596 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2597 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2598 gds_size); 2599 2600 /* GWS */ 2601 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2602 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2603 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2604 2605 /* OA */ 2606 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2607 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2608 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2609 } 2610 2611 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2612 { 2613 struct amdgpu_device *adev = ip_block->adev; 2614 2615 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2616 AMDGPU_MAX_COMPUTE_RINGS); 2617 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2618 gfx_v9_4_3_set_ring_funcs(adev); 2619 gfx_v9_4_3_set_irq_funcs(adev); 2620 gfx_v9_4_3_set_gds_init(adev); 2621 gfx_v9_4_3_set_rlc_funcs(adev); 2622 2623 /* init rlcg reg access ctrl */ 2624 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2625 2626 return gfx_v9_4_3_init_microcode(adev); 2627 } 2628 2629 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2630 { 2631 struct amdgpu_device *adev = ip_block->adev; 2632 2633 if (adev->gfx.ras && 2634 adev->gfx.ras->enable_watchdog_timer) 2635 adev->gfx.ras->enable_watchdog_timer(adev); 2636 2637 gfx_v9_4_3_ptl_hw_init(adev); 2638 2639 return 0; 2640 } 2641 2642 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2643 bool enable, int xcc_id) 2644 { 2645 uint32_t def, data; 2646 2647 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2648 return; 2649 2650 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2651 regRLC_CGTT_MGCG_OVERRIDE); 2652 2653 if (enable) 2654 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2655 else 2656 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2657 2658 if (def != data) 2659 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2660 regRLC_CGTT_MGCG_OVERRIDE, data); 2661 2662 } 2663 2664 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2665 bool enable, int xcc_id) 2666 { 2667 uint32_t def, data; 2668 2669 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2670 return; 2671 2672 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2673 regRLC_CGTT_MGCG_OVERRIDE); 2674 2675 if (enable) 2676 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2677 else 2678 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2679 2680 if (def != data) 2681 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2682 regRLC_CGTT_MGCG_OVERRIDE, data); 2683 } 2684 2685 static void 2686 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2687 bool enable, int xcc_id) 2688 { 2689 uint32_t data, def; 2690 2691 /* It is disabled by HW by default */ 2692 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2693 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2694 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2695 2696 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2697 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2698 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2699 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2700 2701 if (def != data) 2702 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2703 2704 /* MGLS is a global flag to control all MGLS in GFX */ 2705 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2706 /* 2 - RLC memory Light sleep */ 2707 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2708 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2709 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2710 if (def != data) 2711 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2712 } 2713 /* 3 - CP memory Light sleep */ 2714 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2715 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2716 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2717 if (def != data) 2718 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2719 } 2720 } 2721 } else { 2722 /* 1 - MGCG_OVERRIDE */ 2723 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2724 2725 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2726 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2727 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2728 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2729 2730 if (def != data) 2731 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2732 2733 /* 2 - disable MGLS in RLC */ 2734 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2735 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2736 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2737 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2738 } 2739 2740 /* 3 - disable MGLS in CP */ 2741 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2742 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2743 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2744 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2745 } 2746 } 2747 2748 } 2749 2750 static void 2751 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2752 bool enable, int xcc_id) 2753 { 2754 uint32_t def, data; 2755 2756 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2757 2758 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2759 /* unset CGCG override */ 2760 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2761 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2762 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2763 else 2764 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2765 /* update CGCG and CGLS override bits */ 2766 if (def != data) 2767 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2768 2769 /* CGCG Hysteresis: 400us */ 2770 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2771 2772 data = (0x2710 2773 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2774 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2775 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2776 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2777 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2778 if (def != data) 2779 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2780 2781 /* set IDLE_POLL_COUNT(0x33450100)*/ 2782 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2783 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2784 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2785 if (def != data) 2786 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2787 } else { 2788 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2789 /* reset CGCG/CGLS bits */ 2790 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2791 /* disable cgcg and cgls in FSM */ 2792 if (def != data) 2793 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2794 } 2795 2796 } 2797 2798 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2799 bool enable, int xcc_id) 2800 { 2801 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2802 2803 if (enable) { 2804 /* FGCG */ 2805 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2806 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2807 2808 /* CGCG/CGLS should be enabled after MGCG/MGLS 2809 * === MGCG + MGLS === 2810 */ 2811 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2812 xcc_id); 2813 /* === CGCG + CGLS === */ 2814 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2815 xcc_id); 2816 } else { 2817 /* CGCG/CGLS should be disabled before MGCG/MGLS 2818 * === CGCG + CGLS === 2819 */ 2820 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2821 xcc_id); 2822 /* === MGCG + MGLS === */ 2823 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2824 xcc_id); 2825 2826 /* FGCG */ 2827 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2828 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2829 } 2830 2831 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2832 2833 return 0; 2834 } 2835 2836 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2837 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2838 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2839 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2840 .init = gfx_v9_4_3_rlc_init, 2841 .resume = gfx_v9_4_3_rlc_resume, 2842 .stop = gfx_v9_4_3_rlc_stop, 2843 .reset = gfx_v9_4_3_rlc_reset, 2844 .start = gfx_v9_4_3_rlc_start, 2845 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2846 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2847 }; 2848 2849 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2850 enum amd_powergating_state state) 2851 { 2852 return 0; 2853 } 2854 2855 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2856 enum amd_clockgating_state state) 2857 { 2858 struct amdgpu_device *adev = ip_block->adev; 2859 int i, num_xcc; 2860 2861 if (amdgpu_sriov_vf(adev)) 2862 return 0; 2863 2864 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2865 for (i = 0; i < num_xcc; i++) 2866 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2867 adev, state == AMD_CG_STATE_GATE, i); 2868 2869 return 0; 2870 } 2871 2872 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2873 { 2874 struct amdgpu_device *adev = ip_block->adev; 2875 int data; 2876 2877 if (amdgpu_sriov_vf(adev)) 2878 *flags = 0; 2879 2880 /* AMD_CG_SUPPORT_GFX_MGCG */ 2881 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2882 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2883 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2884 2885 /* AMD_CG_SUPPORT_GFX_CGCG */ 2886 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2887 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2888 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2889 2890 /* AMD_CG_SUPPORT_GFX_CGLS */ 2891 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2892 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2893 2894 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2895 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2896 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2897 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2898 2899 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2900 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2901 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2902 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2903 } 2904 2905 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2906 { 2907 struct amdgpu_device *adev = ring->adev; 2908 u32 ref_and_mask, reg_mem_engine; 2909 2910 if (!adev->gfx.funcs->get_hdp_flush_mask) { 2911 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 2912 return; 2913 } 2914 2915 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 2916 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2917 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2918 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2919 ref_and_mask, ref_and_mask, 0x20); 2920 } 2921 2922 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2923 struct amdgpu_job *job, 2924 struct amdgpu_ib *ib, 2925 uint32_t flags) 2926 { 2927 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2928 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2929 2930 /* Currently, there is a high possibility to get wave ID mismatch 2931 * between ME and GDS, leading to a hw deadlock, because ME generates 2932 * different wave IDs than the GDS expects. This situation happens 2933 * randomly when at least 5 compute pipes use GDS ordered append. 2934 * The wave IDs generated by ME are also wrong after suspend/resume. 2935 * Those are probably bugs somewhere else in the kernel driver. 2936 * 2937 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2938 * GDS to 0 for this ring (me/pipe). 2939 */ 2940 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2941 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2942 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2943 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2944 } 2945 2946 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2947 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 2948 amdgpu_ring_write(ring, 2949 #ifdef __BIG_ENDIAN 2950 (2 << 0) | 2951 #endif 2952 lower_32_bits(ib->gpu_addr)); 2953 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2954 amdgpu_ring_write(ring, control); 2955 } 2956 2957 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2958 u64 seq, unsigned flags) 2959 { 2960 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2961 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2962 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2963 2964 /* RELEASE_MEM - flush caches, send int */ 2965 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2966 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2967 EOP_TC_NC_ACTION_EN) : 2968 (EOP_TCL1_ACTION_EN | 2969 EOP_TC_ACTION_EN | 2970 EOP_TC_WB_ACTION_EN | 2971 EOP_TC_MD_ACTION_EN)) | 2972 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2973 EVENT_INDEX(5))); 2974 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2975 2976 /* 2977 * the address should be Qword aligned if 64bit write, Dword 2978 * aligned if only send 32bit data low (discard data high) 2979 */ 2980 if (write64bit) 2981 WARN_ON(addr & 0x7); 2982 else 2983 WARN_ON(addr & 0x3); 2984 amdgpu_ring_write(ring, lower_32_bits(addr)); 2985 amdgpu_ring_write(ring, upper_32_bits(addr)); 2986 amdgpu_ring_write(ring, lower_32_bits(seq)); 2987 amdgpu_ring_write(ring, upper_32_bits(seq)); 2988 amdgpu_ring_write(ring, 0); 2989 } 2990 2991 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2992 { 2993 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2994 uint32_t seq = ring->fence_drv.sync_seq; 2995 uint64_t addr = ring->fence_drv.gpu_addr; 2996 2997 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2998 lower_32_bits(addr), upper_32_bits(addr), 2999 seq, 0xffffffff, 4); 3000 } 3001 3002 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 3003 unsigned vmid, uint64_t pd_addr) 3004 { 3005 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3006 } 3007 3008 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 3009 { 3010 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 3011 } 3012 3013 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 3014 { 3015 u64 wptr; 3016 3017 /* XXX check if swapping is necessary on BE */ 3018 if (ring->use_doorbell) 3019 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 3020 else 3021 BUG(); 3022 return wptr; 3023 } 3024 3025 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 3026 { 3027 struct amdgpu_device *adev = ring->adev; 3028 3029 /* XXX check if swapping is necessary on BE */ 3030 if (ring->use_doorbell) { 3031 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3032 WDOORBELL64(ring->doorbell_index, ring->wptr); 3033 } else { 3034 BUG(); /* only DOORBELL method supported on gfx9 now */ 3035 } 3036 } 3037 3038 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3039 u64 seq, unsigned int flags) 3040 { 3041 struct amdgpu_device *adev = ring->adev; 3042 3043 /* write fence seq to the "addr" */ 3044 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3045 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3046 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 3047 amdgpu_ring_write(ring, lower_32_bits(addr)); 3048 amdgpu_ring_write(ring, upper_32_bits(addr)); 3049 amdgpu_ring_write(ring, lower_32_bits(seq)); 3050 3051 if (flags & AMDGPU_FENCE_FLAG_INT) { 3052 /* set register to trigger INT */ 3053 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3054 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3055 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 3056 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 3057 amdgpu_ring_write(ring, 0); 3058 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3059 } 3060 } 3061 3062 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3063 uint32_t reg_val_offs) 3064 { 3065 struct amdgpu_device *adev = ring->adev; 3066 3067 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3068 3069 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3070 amdgpu_ring_write(ring, 0 | /* src: register*/ 3071 (5 << 8) | /* dst: memory */ 3072 (1 << 20)); /* write confirm */ 3073 amdgpu_ring_write(ring, reg); 3074 amdgpu_ring_write(ring, 0); 3075 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3076 reg_val_offs * 4)); 3077 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3078 reg_val_offs * 4)); 3079 } 3080 3081 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3082 uint32_t val) 3083 { 3084 uint32_t cmd = 0; 3085 3086 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3087 3088 switch (ring->funcs->type) { 3089 case AMDGPU_RING_TYPE_GFX: 3090 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3091 break; 3092 case AMDGPU_RING_TYPE_KIQ: 3093 cmd = (1 << 16); /* no inc addr */ 3094 break; 3095 default: 3096 cmd = WR_CONFIRM; 3097 break; 3098 } 3099 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3100 amdgpu_ring_write(ring, cmd); 3101 amdgpu_ring_write(ring, reg); 3102 amdgpu_ring_write(ring, 0); 3103 amdgpu_ring_write(ring, val); 3104 } 3105 3106 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3107 uint32_t val, uint32_t mask) 3108 { 3109 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3110 } 3111 3112 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3113 uint32_t reg0, uint32_t reg1, 3114 uint32_t ref, uint32_t mask) 3115 { 3116 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3117 ref, mask); 3118 } 3119 3120 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3121 unsigned vmid) 3122 { 3123 struct amdgpu_device *adev = ring->adev; 3124 uint32_t value = 0; 3125 3126 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3127 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3128 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3129 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3130 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3131 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3132 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3133 } 3134 3135 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3136 struct amdgpu_device *adev, int me, int pipe, 3137 enum amdgpu_interrupt_state state, int xcc_id) 3138 { 3139 u32 mec_int_cntl, mec_int_cntl_reg; 3140 3141 /* 3142 * amdgpu controls only the first MEC. That's why this function only 3143 * handles the setting of interrupts for this specific MEC. All other 3144 * pipes' interrupts are set by amdkfd. 3145 */ 3146 3147 if (me == 1) { 3148 switch (pipe) { 3149 case 0: 3150 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3151 break; 3152 case 1: 3153 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3154 break; 3155 case 2: 3156 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3157 break; 3158 case 3: 3159 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3160 break; 3161 default: 3162 DRM_DEBUG("invalid pipe %d\n", pipe); 3163 return; 3164 } 3165 } else { 3166 DRM_DEBUG("invalid me %d\n", me); 3167 return; 3168 } 3169 3170 switch (state) { 3171 case AMDGPU_IRQ_STATE_DISABLE: 3172 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3173 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3174 TIME_STAMP_INT_ENABLE, 0); 3175 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3176 break; 3177 case AMDGPU_IRQ_STATE_ENABLE: 3178 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3179 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3180 TIME_STAMP_INT_ENABLE, 1); 3181 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3182 break; 3183 default: 3184 break; 3185 } 3186 } 3187 3188 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3189 int xcc_id, int me, int pipe) 3190 { 3191 /* 3192 * amdgpu controls only the first MEC. That's why this function only 3193 * handles the setting of interrupts for this specific MEC. All other 3194 * pipes' interrupts are set by amdkfd. 3195 */ 3196 if (me != 1) 3197 return 0; 3198 3199 switch (pipe) { 3200 case 0: 3201 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3202 case 1: 3203 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3204 case 2: 3205 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3206 case 3: 3207 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3208 default: 3209 return 0; 3210 } 3211 } 3212 3213 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3214 struct amdgpu_irq_src *source, 3215 unsigned type, 3216 enum amdgpu_interrupt_state state) 3217 { 3218 u32 mec_int_cntl_reg, mec_int_cntl; 3219 int i, j, k, num_xcc; 3220 3221 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3222 switch (state) { 3223 case AMDGPU_IRQ_STATE_DISABLE: 3224 case AMDGPU_IRQ_STATE_ENABLE: 3225 for (i = 0; i < num_xcc; i++) { 3226 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3227 PRIV_REG_INT_ENABLE, 3228 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3229 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3230 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3231 /* MECs start at 1 */ 3232 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3233 3234 if (mec_int_cntl_reg) { 3235 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3236 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3237 PRIV_REG_INT_ENABLE, 3238 state == AMDGPU_IRQ_STATE_ENABLE ? 3239 1 : 0); 3240 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3241 } 3242 } 3243 } 3244 } 3245 break; 3246 default: 3247 break; 3248 } 3249 3250 return 0; 3251 } 3252 3253 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3254 struct amdgpu_irq_src *source, 3255 unsigned type, 3256 enum amdgpu_interrupt_state state) 3257 { 3258 u32 mec_int_cntl_reg, mec_int_cntl; 3259 int i, j, k, num_xcc; 3260 3261 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3262 switch (state) { 3263 case AMDGPU_IRQ_STATE_DISABLE: 3264 case AMDGPU_IRQ_STATE_ENABLE: 3265 for (i = 0; i < num_xcc; i++) { 3266 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3267 OPCODE_ERROR_INT_ENABLE, 3268 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3269 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3270 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3271 /* MECs start at 1 */ 3272 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3273 3274 if (mec_int_cntl_reg) { 3275 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3276 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3277 OPCODE_ERROR_INT_ENABLE, 3278 state == AMDGPU_IRQ_STATE_ENABLE ? 3279 1 : 0); 3280 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3281 } 3282 } 3283 } 3284 } 3285 break; 3286 default: 3287 break; 3288 } 3289 3290 return 0; 3291 } 3292 3293 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3294 struct amdgpu_irq_src *source, 3295 unsigned type, 3296 enum amdgpu_interrupt_state state) 3297 { 3298 int i, num_xcc; 3299 3300 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3301 switch (state) { 3302 case AMDGPU_IRQ_STATE_DISABLE: 3303 case AMDGPU_IRQ_STATE_ENABLE: 3304 for (i = 0; i < num_xcc; i++) 3305 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3306 PRIV_INSTR_INT_ENABLE, 3307 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3308 break; 3309 default: 3310 break; 3311 } 3312 3313 return 0; 3314 } 3315 3316 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3317 struct amdgpu_irq_src *src, 3318 unsigned type, 3319 enum amdgpu_interrupt_state state) 3320 { 3321 int i, num_xcc; 3322 3323 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3324 for (i = 0; i < num_xcc; i++) { 3325 switch (type) { 3326 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3327 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3328 adev, 1, 0, state, i); 3329 break; 3330 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3331 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3332 adev, 1, 1, state, i); 3333 break; 3334 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3335 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3336 adev, 1, 2, state, i); 3337 break; 3338 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3339 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3340 adev, 1, 3, state, i); 3341 break; 3342 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3343 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3344 adev, 2, 0, state, i); 3345 break; 3346 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3347 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3348 adev, 2, 1, state, i); 3349 break; 3350 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3351 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3352 adev, 2, 2, state, i); 3353 break; 3354 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3355 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3356 adev, 2, 3, state, i); 3357 break; 3358 default: 3359 break; 3360 } 3361 } 3362 3363 return 0; 3364 } 3365 3366 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3367 struct amdgpu_irq_src *source, 3368 struct amdgpu_iv_entry *entry) 3369 { 3370 int i, xcc_id; 3371 u8 me_id, pipe_id, queue_id; 3372 struct amdgpu_ring *ring; 3373 3374 DRM_DEBUG("IH: CP EOP\n"); 3375 me_id = (entry->ring_id & 0x0c) >> 2; 3376 pipe_id = (entry->ring_id & 0x03) >> 0; 3377 queue_id = (entry->ring_id & 0x70) >> 4; 3378 3379 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3380 3381 if (xcc_id == -EINVAL) 3382 return -EINVAL; 3383 3384 switch (me_id) { 3385 case 0: 3386 case 1: 3387 case 2: 3388 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3389 ring = &adev->gfx.compute_ring 3390 [i + 3391 xcc_id * adev->gfx.num_compute_rings]; 3392 /* Per-queue interrupt is supported for MEC starting from VI. 3393 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3394 */ 3395 3396 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3397 amdgpu_fence_process(ring); 3398 } 3399 break; 3400 } 3401 return 0; 3402 } 3403 3404 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3405 struct amdgpu_iv_entry *entry) 3406 { 3407 u8 me_id, pipe_id, queue_id; 3408 struct amdgpu_ring *ring; 3409 int i, xcc_id; 3410 3411 me_id = (entry->ring_id & 0x0c) >> 2; 3412 pipe_id = (entry->ring_id & 0x03) >> 0; 3413 queue_id = (entry->ring_id & 0x70) >> 4; 3414 3415 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3416 3417 if (xcc_id == -EINVAL) 3418 return; 3419 3420 switch (me_id) { 3421 case 0: 3422 case 1: 3423 case 2: 3424 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3425 ring = &adev->gfx.compute_ring 3426 [i + 3427 xcc_id * adev->gfx.num_compute_rings]; 3428 if (ring->me == me_id && ring->pipe == pipe_id && 3429 ring->queue == queue_id) 3430 drm_sched_fault(&ring->sched); 3431 } 3432 break; 3433 } 3434 } 3435 3436 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3437 struct amdgpu_irq_src *source, 3438 struct amdgpu_iv_entry *entry) 3439 { 3440 DRM_ERROR("Illegal register access in command stream\n"); 3441 gfx_v9_4_3_fault(adev, entry); 3442 return 0; 3443 } 3444 3445 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3446 struct amdgpu_irq_src *source, 3447 struct amdgpu_iv_entry *entry) 3448 { 3449 DRM_ERROR("Illegal opcode in command stream\n"); 3450 gfx_v9_4_3_fault(adev, entry); 3451 return 0; 3452 } 3453 3454 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3455 struct amdgpu_irq_src *source, 3456 struct amdgpu_iv_entry *entry) 3457 { 3458 DRM_ERROR("Illegal instruction in command stream\n"); 3459 gfx_v9_4_3_fault(adev, entry); 3460 return 0; 3461 } 3462 3463 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3464 { 3465 const unsigned int cp_coher_cntl = 3466 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3467 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3468 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3469 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3470 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3471 3472 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3473 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3474 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3475 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3476 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3477 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3478 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3479 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3480 } 3481 3482 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3483 uint32_t pipe, bool enable) 3484 { 3485 struct amdgpu_device *adev = ring->adev; 3486 uint32_t val; 3487 uint32_t wcl_cs_reg; 3488 3489 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3490 val = enable ? 0x1 : 0x7f; 3491 3492 switch (pipe) { 3493 case 0: 3494 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3495 break; 3496 case 1: 3497 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3498 break; 3499 case 2: 3500 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3501 break; 3502 case 3: 3503 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3504 break; 3505 default: 3506 DRM_DEBUG("invalid pipe %d\n", pipe); 3507 return; 3508 } 3509 3510 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3511 3512 } 3513 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3514 { 3515 struct amdgpu_device *adev = ring->adev; 3516 uint32_t val; 3517 int i; 3518 3519 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3520 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3521 * around 25% of gpu resources. 3522 */ 3523 val = enable ? 0x1f : 0x07ffffff; 3524 amdgpu_ring_emit_wreg(ring, 3525 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3526 val); 3527 3528 /* Restrict waves for normal/low priority compute queues as well 3529 * to get best QoS for high priority compute jobs. 3530 * 3531 * amdgpu controls only 1st ME(0-3 CS pipes). 3532 */ 3533 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3534 if (i != ring->pipe) 3535 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3536 3537 } 3538 } 3539 3540 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3541 uint32_t pipe, uint32_t queue, 3542 uint32_t xcc_id) 3543 { 3544 int i, r; 3545 /* make sure dequeue is complete*/ 3546 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3547 mutex_lock(&adev->srbm_mutex); 3548 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3549 for (i = 0; i < adev->usec_timeout; i++) { 3550 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3551 break; 3552 udelay(1); 3553 } 3554 if (i >= adev->usec_timeout) 3555 r = -ETIMEDOUT; 3556 else 3557 r = 0; 3558 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3559 mutex_unlock(&adev->srbm_mutex); 3560 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3561 3562 return r; 3563 3564 } 3565 3566 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3567 { 3568 if (!!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3569 return true; 3570 else 3571 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3572 3573 return false; 3574 } 3575 3576 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3577 { 3578 struct amdgpu_device *adev = ring->adev; 3579 uint32_t reset_pipe, clean_pipe; 3580 int r; 3581 3582 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3583 return -EINVAL; 3584 3585 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3586 mutex_lock(&adev->srbm_mutex); 3587 3588 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3589 clean_pipe = reset_pipe; 3590 3591 if (ring->me == 1) { 3592 switch (ring->pipe) { 3593 case 0: 3594 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3595 MEC_ME1_PIPE0_RESET, 1); 3596 break; 3597 case 1: 3598 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3599 MEC_ME1_PIPE1_RESET, 1); 3600 break; 3601 case 2: 3602 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3603 MEC_ME1_PIPE2_RESET, 1); 3604 break; 3605 case 3: 3606 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3607 MEC_ME1_PIPE3_RESET, 1); 3608 break; 3609 default: 3610 break; 3611 } 3612 } else { 3613 if (ring->pipe) 3614 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3615 MEC_ME2_PIPE1_RESET, 1); 3616 else 3617 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3618 MEC_ME2_PIPE0_RESET, 1); 3619 } 3620 3621 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3622 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3623 mutex_unlock(&adev->srbm_mutex); 3624 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3625 3626 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3627 return r; 3628 } 3629 3630 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3631 unsigned int vmid, 3632 struct amdgpu_fence *timedout_fence) 3633 { 3634 struct amdgpu_device *adev = ring->adev; 3635 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3636 struct amdgpu_ring *kiq_ring = &kiq->ring; 3637 int reset_mode = AMDGPU_RESET_TYPE_PER_QUEUE; 3638 unsigned long flags; 3639 int r; 3640 3641 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3642 return -EINVAL; 3643 3644 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 3645 3646 spin_lock_irqsave(&kiq->ring_lock, flags); 3647 3648 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3649 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3650 return -ENOMEM; 3651 } 3652 3653 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3654 0, 0); 3655 amdgpu_ring_commit(kiq_ring); 3656 3657 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3658 3659 r = amdgpu_ring_test_ring(kiq_ring); 3660 if (r) { 3661 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3662 ring->name); 3663 goto pipe_reset; 3664 } 3665 3666 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3667 if (r) 3668 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3669 3670 pipe_reset: 3671 if (r) { 3672 if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3673 return -EOPNOTSUPP; 3674 r = gfx_v9_4_3_reset_hw_pipe(ring); 3675 reset_mode = AMDGPU_RESET_TYPE_PER_PIPE; 3676 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3677 r ? "failed" : "successfully"); 3678 if (r) 3679 return r; 3680 } 3681 3682 gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3683 3684 spin_lock_irqsave(&kiq->ring_lock, flags); 3685 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3686 if (r) { 3687 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3688 return -ENOMEM; 3689 } 3690 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3691 amdgpu_ring_commit(kiq_ring); 3692 r = amdgpu_ring_test_ring(kiq_ring); 3693 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3694 if (r) { 3695 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) 3696 goto pipe_reset; 3697 3698 dev_err(adev->dev, "fail to remap queue\n"); 3699 return r; 3700 } 3701 3702 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) { 3703 r = amdgpu_ring_test_ring(ring); 3704 if (r) 3705 goto pipe_reset; 3706 } 3707 3708 3709 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 3710 } 3711 3712 enum amdgpu_gfx_cp_ras_mem_id { 3713 AMDGPU_GFX_CP_MEM1 = 1, 3714 AMDGPU_GFX_CP_MEM2, 3715 AMDGPU_GFX_CP_MEM3, 3716 AMDGPU_GFX_CP_MEM4, 3717 AMDGPU_GFX_CP_MEM5, 3718 }; 3719 3720 enum amdgpu_gfx_gcea_ras_mem_id { 3721 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3722 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3723 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3724 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3725 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3726 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3727 AMDGPU_GFX_GCEA_MAM_DMEM0, 3728 AMDGPU_GFX_GCEA_MAM_DMEM1, 3729 AMDGPU_GFX_GCEA_MAM_DMEM2, 3730 AMDGPU_GFX_GCEA_MAM_DMEM3, 3731 AMDGPU_GFX_GCEA_MAM_AMEM0, 3732 AMDGPU_GFX_GCEA_MAM_AMEM1, 3733 AMDGPU_GFX_GCEA_MAM_AMEM2, 3734 AMDGPU_GFX_GCEA_MAM_AMEM3, 3735 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3736 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3737 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3738 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3739 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3740 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3741 }; 3742 3743 enum amdgpu_gfx_gc_cane_ras_mem_id { 3744 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3745 }; 3746 3747 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3748 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3749 }; 3750 3751 enum amdgpu_gfx_gds_ras_mem_id { 3752 AMDGPU_GFX_GDS_MEM0 = 0, 3753 }; 3754 3755 enum amdgpu_gfx_lds_ras_mem_id { 3756 AMDGPU_GFX_LDS_BANK0 = 0, 3757 AMDGPU_GFX_LDS_BANK1, 3758 AMDGPU_GFX_LDS_BANK2, 3759 AMDGPU_GFX_LDS_BANK3, 3760 AMDGPU_GFX_LDS_BANK4, 3761 AMDGPU_GFX_LDS_BANK5, 3762 AMDGPU_GFX_LDS_BANK6, 3763 AMDGPU_GFX_LDS_BANK7, 3764 AMDGPU_GFX_LDS_BANK8, 3765 AMDGPU_GFX_LDS_BANK9, 3766 AMDGPU_GFX_LDS_BANK10, 3767 AMDGPU_GFX_LDS_BANK11, 3768 AMDGPU_GFX_LDS_BANK12, 3769 AMDGPU_GFX_LDS_BANK13, 3770 AMDGPU_GFX_LDS_BANK14, 3771 AMDGPU_GFX_LDS_BANK15, 3772 AMDGPU_GFX_LDS_BANK16, 3773 AMDGPU_GFX_LDS_BANK17, 3774 AMDGPU_GFX_LDS_BANK18, 3775 AMDGPU_GFX_LDS_BANK19, 3776 AMDGPU_GFX_LDS_BANK20, 3777 AMDGPU_GFX_LDS_BANK21, 3778 AMDGPU_GFX_LDS_BANK22, 3779 AMDGPU_GFX_LDS_BANK23, 3780 AMDGPU_GFX_LDS_BANK24, 3781 AMDGPU_GFX_LDS_BANK25, 3782 AMDGPU_GFX_LDS_BANK26, 3783 AMDGPU_GFX_LDS_BANK27, 3784 AMDGPU_GFX_LDS_BANK28, 3785 AMDGPU_GFX_LDS_BANK29, 3786 AMDGPU_GFX_LDS_BANK30, 3787 AMDGPU_GFX_LDS_BANK31, 3788 AMDGPU_GFX_LDS_SP_BUFFER_A, 3789 AMDGPU_GFX_LDS_SP_BUFFER_B, 3790 }; 3791 3792 enum amdgpu_gfx_rlc_ras_mem_id { 3793 AMDGPU_GFX_RLC_GPMF32 = 1, 3794 AMDGPU_GFX_RLC_RLCVF32, 3795 AMDGPU_GFX_RLC_SCRATCH, 3796 AMDGPU_GFX_RLC_SRM_ARAM, 3797 AMDGPU_GFX_RLC_SRM_DRAM, 3798 AMDGPU_GFX_RLC_TCTAG, 3799 AMDGPU_GFX_RLC_SPM_SE, 3800 AMDGPU_GFX_RLC_SPM_GRBMT, 3801 }; 3802 3803 enum amdgpu_gfx_sp_ras_mem_id { 3804 AMDGPU_GFX_SP_SIMDID0 = 0, 3805 }; 3806 3807 enum amdgpu_gfx_spi_ras_mem_id { 3808 AMDGPU_GFX_SPI_MEM0 = 0, 3809 AMDGPU_GFX_SPI_MEM1, 3810 AMDGPU_GFX_SPI_MEM2, 3811 AMDGPU_GFX_SPI_MEM3, 3812 }; 3813 3814 enum amdgpu_gfx_sqc_ras_mem_id { 3815 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3816 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3817 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3818 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3819 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3820 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3821 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3822 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3823 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3824 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3825 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3826 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3827 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3828 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3829 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3830 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3831 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3832 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3833 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3834 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3835 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3836 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3837 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3838 }; 3839 3840 enum amdgpu_gfx_sq_ras_mem_id { 3841 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3842 AMDGPU_GFX_SQ_SGPR_MEM1, 3843 AMDGPU_GFX_SQ_SGPR_MEM2, 3844 AMDGPU_GFX_SQ_SGPR_MEM3, 3845 }; 3846 3847 enum amdgpu_gfx_ta_ras_mem_id { 3848 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3849 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3850 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3851 AMDGPU_GFX_TA_FSX_LFIFO, 3852 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3853 }; 3854 3855 enum amdgpu_gfx_tcc_ras_mem_id { 3856 AMDGPU_GFX_TCC_MEM1 = 1, 3857 }; 3858 3859 enum amdgpu_gfx_tca_ras_mem_id { 3860 AMDGPU_GFX_TCA_MEM1 = 1, 3861 }; 3862 3863 enum amdgpu_gfx_tci_ras_mem_id { 3864 AMDGPU_GFX_TCIW_MEM = 1, 3865 }; 3866 3867 enum amdgpu_gfx_tcp_ras_mem_id { 3868 AMDGPU_GFX_TCP_LFIFO0 = 1, 3869 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3870 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3871 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3872 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3873 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3874 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3875 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3876 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3877 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3878 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3879 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3880 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3881 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3882 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3883 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3884 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3885 AMDGPU_GFX_TCP_VM_FIFO, 3886 AMDGPU_GFX_TCP_DB_TAGRAM0, 3887 AMDGPU_GFX_TCP_DB_TAGRAM1, 3888 AMDGPU_GFX_TCP_DB_TAGRAM2, 3889 AMDGPU_GFX_TCP_DB_TAGRAM3, 3890 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3891 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3892 AMDGPU_GFX_TCP_CMD_FIFO, 3893 }; 3894 3895 enum amdgpu_gfx_td_ras_mem_id { 3896 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3897 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3898 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3899 }; 3900 3901 enum amdgpu_gfx_tcx_ras_mem_id { 3902 AMDGPU_GFX_TCX_FIFOD0 = 0, 3903 AMDGPU_GFX_TCX_FIFOD1, 3904 AMDGPU_GFX_TCX_FIFOD2, 3905 AMDGPU_GFX_TCX_FIFOD3, 3906 AMDGPU_GFX_TCX_FIFOD4, 3907 AMDGPU_GFX_TCX_FIFOD5, 3908 AMDGPU_GFX_TCX_FIFOD6, 3909 AMDGPU_GFX_TCX_FIFOD7, 3910 AMDGPU_GFX_TCX_FIFOB0, 3911 AMDGPU_GFX_TCX_FIFOB1, 3912 AMDGPU_GFX_TCX_FIFOB2, 3913 AMDGPU_GFX_TCX_FIFOB3, 3914 AMDGPU_GFX_TCX_FIFOB4, 3915 AMDGPU_GFX_TCX_FIFOB5, 3916 AMDGPU_GFX_TCX_FIFOB6, 3917 AMDGPU_GFX_TCX_FIFOB7, 3918 AMDGPU_GFX_TCX_FIFOA0, 3919 AMDGPU_GFX_TCX_FIFOA1, 3920 AMDGPU_GFX_TCX_FIFOA2, 3921 AMDGPU_GFX_TCX_FIFOA3, 3922 AMDGPU_GFX_TCX_FIFOA4, 3923 AMDGPU_GFX_TCX_FIFOA5, 3924 AMDGPU_GFX_TCX_FIFOA6, 3925 AMDGPU_GFX_TCX_FIFOA7, 3926 AMDGPU_GFX_TCX_CFIFO0, 3927 AMDGPU_GFX_TCX_CFIFO1, 3928 AMDGPU_GFX_TCX_CFIFO2, 3929 AMDGPU_GFX_TCX_CFIFO3, 3930 AMDGPU_GFX_TCX_CFIFO4, 3931 AMDGPU_GFX_TCX_CFIFO5, 3932 AMDGPU_GFX_TCX_CFIFO6, 3933 AMDGPU_GFX_TCX_CFIFO7, 3934 AMDGPU_GFX_TCX_FIFO_ACKB0, 3935 AMDGPU_GFX_TCX_FIFO_ACKB1, 3936 AMDGPU_GFX_TCX_FIFO_ACKB2, 3937 AMDGPU_GFX_TCX_FIFO_ACKB3, 3938 AMDGPU_GFX_TCX_FIFO_ACKB4, 3939 AMDGPU_GFX_TCX_FIFO_ACKB5, 3940 AMDGPU_GFX_TCX_FIFO_ACKB6, 3941 AMDGPU_GFX_TCX_FIFO_ACKB7, 3942 AMDGPU_GFX_TCX_FIFO_ACKD0, 3943 AMDGPU_GFX_TCX_FIFO_ACKD1, 3944 AMDGPU_GFX_TCX_FIFO_ACKD2, 3945 AMDGPU_GFX_TCX_FIFO_ACKD3, 3946 AMDGPU_GFX_TCX_FIFO_ACKD4, 3947 AMDGPU_GFX_TCX_FIFO_ACKD5, 3948 AMDGPU_GFX_TCX_FIFO_ACKD6, 3949 AMDGPU_GFX_TCX_FIFO_ACKD7, 3950 AMDGPU_GFX_TCX_DST_FIFOA0, 3951 AMDGPU_GFX_TCX_DST_FIFOA1, 3952 AMDGPU_GFX_TCX_DST_FIFOA2, 3953 AMDGPU_GFX_TCX_DST_FIFOA3, 3954 AMDGPU_GFX_TCX_DST_FIFOA4, 3955 AMDGPU_GFX_TCX_DST_FIFOA5, 3956 AMDGPU_GFX_TCX_DST_FIFOA6, 3957 AMDGPU_GFX_TCX_DST_FIFOA7, 3958 AMDGPU_GFX_TCX_DST_FIFOB0, 3959 AMDGPU_GFX_TCX_DST_FIFOB1, 3960 AMDGPU_GFX_TCX_DST_FIFOB2, 3961 AMDGPU_GFX_TCX_DST_FIFOB3, 3962 AMDGPU_GFX_TCX_DST_FIFOB4, 3963 AMDGPU_GFX_TCX_DST_FIFOB5, 3964 AMDGPU_GFX_TCX_DST_FIFOB6, 3965 AMDGPU_GFX_TCX_DST_FIFOB7, 3966 AMDGPU_GFX_TCX_DST_FIFOD0, 3967 AMDGPU_GFX_TCX_DST_FIFOD1, 3968 AMDGPU_GFX_TCX_DST_FIFOD2, 3969 AMDGPU_GFX_TCX_DST_FIFOD3, 3970 AMDGPU_GFX_TCX_DST_FIFOD4, 3971 AMDGPU_GFX_TCX_DST_FIFOD5, 3972 AMDGPU_GFX_TCX_DST_FIFOD6, 3973 AMDGPU_GFX_TCX_DST_FIFOD7, 3974 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3975 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3976 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3977 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3978 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3979 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3980 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3981 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3982 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3983 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3984 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3985 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3986 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3987 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3988 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3989 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3990 }; 3991 3992 enum amdgpu_gfx_atc_l2_ras_mem_id { 3993 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3994 }; 3995 3996 enum amdgpu_gfx_utcl2_ras_mem_id { 3997 AMDGPU_GFX_UTCL2_MEM0 = 0, 3998 }; 3999 4000 enum amdgpu_gfx_vml2_ras_mem_id { 4001 AMDGPU_GFX_VML2_MEM0 = 0, 4002 }; 4003 4004 enum amdgpu_gfx_vml2_walker_ras_mem_id { 4005 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 4006 }; 4007 4008 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 4009 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 4010 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 4011 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 4012 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 4013 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 4014 }; 4015 4016 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 4017 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 4018 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 4019 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 4020 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 4021 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 4022 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 4023 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 4024 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 4025 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 4026 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 4027 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 4028 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 4029 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 4030 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 4031 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 4032 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 4033 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 4034 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 4035 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 4036 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 4037 }; 4038 4039 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 4040 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 4041 }; 4042 4043 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 4044 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 4045 }; 4046 4047 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 4048 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 4049 }; 4050 4051 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 4052 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 4053 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 4054 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 4055 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 4056 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 4057 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 4058 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 4059 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 4060 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 4061 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 4062 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 4063 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 4064 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 4065 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 4066 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 4067 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 4068 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 4069 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 4070 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 4071 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 4072 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 4073 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 4074 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 4075 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 4076 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 4077 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 4078 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 4079 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 4080 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 4081 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 4082 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 4083 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 4084 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 4085 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4086 }; 4087 4088 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4089 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4090 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4091 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4092 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4093 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4094 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4095 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4096 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4097 }; 4098 4099 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4100 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4101 }; 4102 4103 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4104 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4105 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4106 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4107 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4108 }; 4109 4110 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4111 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4112 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4113 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4114 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4115 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4116 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4117 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4118 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4119 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4120 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4121 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4122 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4123 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4124 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4125 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4126 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4127 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4128 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4129 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4130 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4131 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4132 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4133 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4134 }; 4135 4136 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4137 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4138 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4139 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4140 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4141 }; 4142 4143 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4144 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4145 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4146 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4147 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4148 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4149 }; 4150 4151 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4152 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4153 }; 4154 4155 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4156 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4157 }; 4158 4159 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4160 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4161 }; 4162 4163 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4164 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4165 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4166 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4167 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4168 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4169 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4170 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4171 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4172 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4173 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4174 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4175 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4176 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4177 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4178 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4179 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4180 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4181 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4182 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4183 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4184 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4185 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4186 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4187 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4188 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4189 }; 4190 4191 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4192 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4193 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4194 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4195 }; 4196 4197 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4198 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4199 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4200 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4201 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4202 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4203 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4204 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4205 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4206 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4207 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4208 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4209 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4210 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4211 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4212 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4213 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4214 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4215 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4216 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4217 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4218 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4219 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4220 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4221 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4222 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4223 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4224 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4225 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4226 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4227 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4228 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4229 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4230 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4231 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4232 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4233 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4234 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4235 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4236 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4237 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4238 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4239 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4240 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4241 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4242 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4243 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4244 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4245 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4246 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4247 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4248 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4249 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4250 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4251 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4252 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4253 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4254 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4255 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4256 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4257 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4258 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4259 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4260 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4261 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4262 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4263 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4264 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4265 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4266 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4267 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4268 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4269 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4270 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4271 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4272 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4273 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4274 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4275 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4276 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4277 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4278 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4279 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4280 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4281 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4282 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4283 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4284 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4285 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4286 }; 4287 4288 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4289 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4290 }; 4291 4292 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4293 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4294 }; 4295 4296 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4297 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4298 }; 4299 4300 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4301 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4302 }; 4303 4304 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4305 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4306 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4307 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4308 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4309 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4310 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4311 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4312 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4313 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4314 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4315 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4316 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4317 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4318 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4319 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4320 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4321 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4322 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4323 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4324 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4325 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4326 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4327 }; 4328 4329 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4330 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4331 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4332 AMDGPU_GFX_RLC_MEM, 1}, 4333 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4334 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4335 AMDGPU_GFX_CP_MEM, 1}, 4336 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4337 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4338 AMDGPU_GFX_CP_MEM, 1}, 4339 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4340 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4341 AMDGPU_GFX_CP_MEM, 1}, 4342 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4343 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4344 AMDGPU_GFX_GDS_MEM, 1}, 4345 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4346 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4347 AMDGPU_GFX_GC_CANE_MEM, 1}, 4348 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4349 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4350 AMDGPU_GFX_SPI_MEM, 1}, 4351 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4352 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4353 AMDGPU_GFX_SP_MEM, 4}, 4354 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4355 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4356 AMDGPU_GFX_SP_MEM, 4}, 4357 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4358 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4359 AMDGPU_GFX_SQ_MEM, 4}, 4360 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4361 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4362 AMDGPU_GFX_SQC_MEM, 4}, 4363 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4364 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4365 AMDGPU_GFX_TCX_MEM, 1}, 4366 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4367 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4368 AMDGPU_GFX_TCC_MEM, 1}, 4369 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4370 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4371 AMDGPU_GFX_TA_MEM, 4}, 4372 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4373 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4374 AMDGPU_GFX_TCI_MEM, 1}, 4375 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4376 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4377 AMDGPU_GFX_TCP_MEM, 4}, 4378 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4379 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4380 AMDGPU_GFX_TD_MEM, 4}, 4381 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4382 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4383 AMDGPU_GFX_GCEA_MEM, 1}, 4384 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4385 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4386 AMDGPU_GFX_LDS_MEM, 4}, 4387 }; 4388 4389 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4390 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4391 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4392 AMDGPU_GFX_RLC_MEM, 1}, 4393 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4394 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4395 AMDGPU_GFX_CP_MEM, 1}, 4396 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4397 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4398 AMDGPU_GFX_CP_MEM, 1}, 4399 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4400 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4401 AMDGPU_GFX_CP_MEM, 1}, 4402 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4403 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4404 AMDGPU_GFX_GDS_MEM, 1}, 4405 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4406 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4407 AMDGPU_GFX_GC_CANE_MEM, 1}, 4408 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4409 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4410 AMDGPU_GFX_SPI_MEM, 1}, 4411 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4412 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4413 AMDGPU_GFX_SP_MEM, 4}, 4414 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4415 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4416 AMDGPU_GFX_SP_MEM, 4}, 4417 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4418 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4419 AMDGPU_GFX_SQ_MEM, 4}, 4420 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4421 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4422 AMDGPU_GFX_SQC_MEM, 4}, 4423 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4424 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4425 AMDGPU_GFX_TCX_MEM, 1}, 4426 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4427 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4428 AMDGPU_GFX_TCC_MEM, 1}, 4429 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4430 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4431 AMDGPU_GFX_TA_MEM, 4}, 4432 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4433 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4434 AMDGPU_GFX_TCI_MEM, 1}, 4435 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4436 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4437 AMDGPU_GFX_TCP_MEM, 4}, 4438 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4439 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4440 AMDGPU_GFX_TD_MEM, 4}, 4441 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4442 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4443 AMDGPU_GFX_TCA_MEM, 1}, 4444 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4445 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4446 AMDGPU_GFX_GCEA_MEM, 1}, 4447 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4448 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4449 AMDGPU_GFX_LDS_MEM, 4}, 4450 }; 4451 4452 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4453 void *ras_error_status, int xcc_id) 4454 { 4455 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4456 unsigned long ce_count = 0, ue_count = 0; 4457 uint32_t i, j, k; 4458 4459 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4460 struct amdgpu_smuio_mcm_config_info mcm_info = { 4461 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4462 .die_id = xcc_id & 0x01 ? 1 : 0, 4463 }; 4464 4465 mutex_lock(&adev->grbm_idx_mutex); 4466 4467 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4468 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4469 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4470 /* no need to select if instance number is 1 */ 4471 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4472 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4473 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4474 4475 amdgpu_ras_inst_query_ras_error_count(adev, 4476 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4477 1, 4478 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4479 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4480 GET_INST(GC, xcc_id), 4481 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4482 &ce_count); 4483 4484 amdgpu_ras_inst_query_ras_error_count(adev, 4485 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4486 1, 4487 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4488 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4489 GET_INST(GC, xcc_id), 4490 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4491 &ue_count); 4492 } 4493 } 4494 } 4495 4496 /* handle extra register entries of UE */ 4497 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4498 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4499 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4500 /* no need to select if instance number is 1 */ 4501 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4502 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4503 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4504 4505 amdgpu_ras_inst_query_ras_error_count(adev, 4506 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4507 1, 4508 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4509 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4510 GET_INST(GC, xcc_id), 4511 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4512 &ue_count); 4513 } 4514 } 4515 } 4516 4517 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4518 xcc_id); 4519 mutex_unlock(&adev->grbm_idx_mutex); 4520 4521 /* the caller should make sure initialize value of 4522 * err_data->ue_count and err_data->ce_count 4523 */ 4524 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4525 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4526 } 4527 4528 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4529 void *ras_error_status, int xcc_id) 4530 { 4531 uint32_t i, j, k; 4532 4533 mutex_lock(&adev->grbm_idx_mutex); 4534 4535 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4536 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4537 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4538 /* no need to select if instance number is 1 */ 4539 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4540 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4541 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4542 4543 amdgpu_ras_inst_reset_ras_error_count(adev, 4544 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4545 1, 4546 GET_INST(GC, xcc_id)); 4547 4548 amdgpu_ras_inst_reset_ras_error_count(adev, 4549 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4550 1, 4551 GET_INST(GC, xcc_id)); 4552 } 4553 } 4554 } 4555 4556 /* handle extra register entries of UE */ 4557 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4558 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4559 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4560 /* no need to select if instance number is 1 */ 4561 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4562 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4563 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4564 4565 amdgpu_ras_inst_reset_ras_error_count(adev, 4566 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4567 1, 4568 GET_INST(GC, xcc_id)); 4569 } 4570 } 4571 } 4572 4573 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4574 xcc_id); 4575 mutex_unlock(&adev->grbm_idx_mutex); 4576 } 4577 4578 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4579 void *ras_error_status, int xcc_id) 4580 { 4581 uint32_t i; 4582 uint32_t data; 4583 4584 if (amdgpu_sriov_vf(adev)) 4585 return; 4586 4587 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4588 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4589 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4590 4591 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4592 (amdgpu_watchdog_timer.period < 1 || 4593 amdgpu_watchdog_timer.period > 0x23)) { 4594 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4595 amdgpu_watchdog_timer.period = 0x23; 4596 } 4597 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4598 amdgpu_watchdog_timer.period); 4599 4600 mutex_lock(&adev->grbm_idx_mutex); 4601 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4602 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4603 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4604 } 4605 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4606 xcc_id); 4607 mutex_unlock(&adev->grbm_idx_mutex); 4608 } 4609 4610 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4611 void *ras_error_status) 4612 { 4613 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4614 gfx_v9_4_3_inst_query_ras_err_count); 4615 } 4616 4617 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4618 { 4619 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4620 } 4621 4622 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4623 { 4624 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4625 } 4626 4627 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4628 { 4629 /* Header itself is a NOP packet */ 4630 if (num_nop == 1) { 4631 amdgpu_ring_write(ring, ring->funcs->nop); 4632 return; 4633 } 4634 4635 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4636 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4637 4638 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4639 amdgpu_ring_insert_nop(ring, num_nop - 1); 4640 } 4641 4642 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4643 { 4644 struct amdgpu_device *adev = ip_block->adev; 4645 uint32_t i, j, k; 4646 uint32_t xcc_id, xcc_offset, inst_offset; 4647 uint32_t num_xcc, reg, num_inst; 4648 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4649 4650 if (!adev->gfx.ip_dump_core) 4651 return; 4652 4653 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4654 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4655 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4656 xcc_offset = xcc_id * reg_count; 4657 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4658 for (i = 0; i < reg_count; i++) 4659 drm_printf(p, "%-50s \t 0x%08x\n", 4660 gc_reg_list_9_4_3[i].reg_name, 4661 adev->gfx.ip_dump_core[xcc_offset + i]); 4662 } 4663 4664 /* print compute queue registers for all instances */ 4665 if (!adev->gfx.ip_dump_compute_queues) 4666 return; 4667 4668 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4669 adev->gfx.mec.num_queue_per_pipe; 4670 4671 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4672 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4673 num_xcc, 4674 adev->gfx.mec.num_mec, 4675 adev->gfx.mec.num_pipe_per_mec, 4676 adev->gfx.mec.num_queue_per_pipe); 4677 4678 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4679 xcc_offset = xcc_id * reg_count * num_inst; 4680 inst_offset = 0; 4681 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4682 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4683 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4684 drm_printf(p, 4685 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4686 xcc_id, i, j, k); 4687 for (reg = 0; reg < reg_count; reg++) { 4688 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4689 regCP_MEC_ME1_HEADER_DUMP) 4690 drm_printf(p, 4691 "%-50s \t 0x%08x\n", 4692 "regCP_MEC_ME2_HEADER_DUMP", 4693 adev->gfx.ip_dump_compute_queues 4694 [xcc_offset + inst_offset + 4695 reg]); 4696 else 4697 drm_printf(p, 4698 "%-50s \t 0x%08x\n", 4699 gc_cp_reg_list_9_4_3[reg].reg_name, 4700 adev->gfx.ip_dump_compute_queues 4701 [xcc_offset + inst_offset + 4702 reg]); 4703 } 4704 inst_offset += reg_count; 4705 } 4706 } 4707 } 4708 } 4709 } 4710 4711 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4712 { 4713 struct amdgpu_device *adev = ip_block->adev; 4714 uint32_t i, j, k; 4715 uint32_t num_xcc, reg, num_inst; 4716 uint32_t xcc_id, xcc_offset, inst_offset; 4717 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4718 4719 if (!adev->gfx.ip_dump_core) 4720 return; 4721 4722 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4723 4724 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4725 xcc_offset = xcc_id * reg_count; 4726 for (i = 0; i < reg_count; i++) 4727 adev->gfx.ip_dump_core[xcc_offset + i] = 4728 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4729 GET_INST(GC, xcc_id))); 4730 } 4731 4732 /* dump compute queue registers for all instances */ 4733 if (!adev->gfx.ip_dump_compute_queues) 4734 return; 4735 4736 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4737 adev->gfx.mec.num_queue_per_pipe; 4738 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4739 mutex_lock(&adev->srbm_mutex); 4740 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4741 xcc_offset = xcc_id * reg_count * num_inst; 4742 inst_offset = 0; 4743 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4744 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4745 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4746 /* ME0 is for GFX so start from 1 for CP */ 4747 soc15_grbm_select(adev, 1 + i, j, k, 0, 4748 GET_INST(GC, xcc_id)); 4749 4750 for (reg = 0; reg < reg_count; reg++) { 4751 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 4752 regCP_MEC_ME1_HEADER_DUMP) 4753 adev->gfx.ip_dump_compute_queues 4754 [xcc_offset + 4755 inst_offset + reg] = 4756 RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), 4757 regCP_MEC_ME2_HEADER_DUMP)); 4758 else 4759 adev->gfx.ip_dump_compute_queues 4760 [xcc_offset + 4761 inst_offset + reg] = 4762 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4763 gc_cp_reg_list_9_4_3[reg], 4764 GET_INST(GC, xcc_id))); 4765 } 4766 inst_offset += reg_count; 4767 } 4768 } 4769 } 4770 } 4771 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4772 mutex_unlock(&adev->srbm_mutex); 4773 } 4774 4775 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4776 { 4777 /* Emit the cleaner shader */ 4778 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4779 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4780 } 4781 4782 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4783 .name = "gfx_v9_4_3", 4784 .early_init = gfx_v9_4_3_early_init, 4785 .late_init = gfx_v9_4_3_late_init, 4786 .sw_init = gfx_v9_4_3_sw_init, 4787 .sw_fini = gfx_v9_4_3_sw_fini, 4788 .hw_init = gfx_v9_4_3_hw_init, 4789 .hw_fini = gfx_v9_4_3_hw_fini, 4790 .suspend = gfx_v9_4_3_suspend, 4791 .resume = gfx_v9_4_3_resume, 4792 .is_idle = gfx_v9_4_3_is_idle, 4793 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4794 .soft_reset = gfx_v9_4_3_soft_reset, 4795 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4796 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4797 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4798 .dump_ip_state = gfx_v9_4_3_ip_dump, 4799 .print_ip_state = gfx_v9_4_3_ip_print, 4800 }; 4801 4802 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4803 .type = AMDGPU_RING_TYPE_COMPUTE, 4804 .align_mask = 0xff, 4805 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4806 .support_64bit_ptrs = true, 4807 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4808 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4809 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4810 .emit_frame_size = 4811 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4812 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4813 5 + /* hdp invalidate */ 4814 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4815 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4816 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4817 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4818 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4819 7 + /* gfx_v9_4_3_emit_mem_sync */ 4820 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4821 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4822 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4823 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4824 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4825 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4826 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4827 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4828 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4829 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4830 .test_ring = gfx_v9_4_3_ring_test_ring, 4831 .test_ib = gfx_v9_4_3_ring_test_ib, 4832 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4833 .pad_ib = amdgpu_ring_generic_pad_ib, 4834 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4835 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4836 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4837 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4838 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4839 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4840 .reset = gfx_v9_4_3_reset_kcq, 4841 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4842 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4843 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4844 }; 4845 4846 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4847 .type = AMDGPU_RING_TYPE_KIQ, 4848 .align_mask = 0xff, 4849 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4850 .support_64bit_ptrs = true, 4851 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4852 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4853 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4854 .emit_frame_size = 4855 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4856 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4857 5 + /* hdp invalidate */ 4858 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4859 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4860 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4861 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4862 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4863 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4864 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4865 .test_ring = gfx_v9_4_3_ring_test_ring, 4866 .insert_nop = amdgpu_ring_insert_nop, 4867 .pad_ib = amdgpu_ring_generic_pad_ib, 4868 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4869 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4870 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4871 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4872 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4873 }; 4874 4875 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4876 { 4877 int i, j, num_xcc; 4878 4879 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4880 for (i = 0; i < num_xcc; i++) { 4881 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4882 4883 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4884 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4885 = &gfx_v9_4_3_ring_funcs_compute; 4886 } 4887 } 4888 4889 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4890 .set = gfx_v9_4_3_set_eop_interrupt_state, 4891 .process = gfx_v9_4_3_eop_irq, 4892 }; 4893 4894 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4895 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4896 .process = gfx_v9_4_3_priv_reg_irq, 4897 }; 4898 4899 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4900 .set = gfx_v9_4_3_set_bad_op_fault_state, 4901 .process = gfx_v9_4_3_bad_op_irq, 4902 }; 4903 4904 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4905 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4906 .process = gfx_v9_4_3_priv_inst_irq, 4907 }; 4908 4909 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4910 { 4911 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4912 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4913 4914 adev->gfx.priv_reg_irq.num_types = 1; 4915 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4916 4917 adev->gfx.bad_op_irq.num_types = 1; 4918 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4919 4920 adev->gfx.priv_inst_irq.num_types = 1; 4921 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4922 } 4923 4924 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4925 { 4926 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4927 } 4928 4929 4930 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4931 { 4932 /* 9.4.3 variants removed all the GDS internal memory, 4933 * only support GWS opcode in kernel, like barrier 4934 * semaphore.etc */ 4935 4936 /* init asic gds info */ 4937 adev->gds.gds_size = 0; 4938 adev->gds.gds_compute_max_wave_id = 0; 4939 adev->gds.gws_size = 64; 4940 adev->gds.oa_size = 16; 4941 } 4942 4943 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4944 u32 bitmap, int xcc_id) 4945 { 4946 u32 data; 4947 4948 if (!bitmap) 4949 return; 4950 4951 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4952 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4953 4954 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4955 } 4956 4957 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4958 { 4959 u32 data, mask; 4960 4961 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4962 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4963 4964 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4965 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4966 4967 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4968 4969 return (~data) & mask; 4970 } 4971 4972 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4973 struct amdgpu_cu_info *cu_info) 4974 { 4975 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4976 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4977 unsigned disable_masks[4 * 4]; 4978 bool is_symmetric_cus; 4979 4980 if (!adev || !cu_info) 4981 return -EINVAL; 4982 4983 /* 4984 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4985 */ 4986 if (adev->gfx.config.max_shader_engines * 4987 adev->gfx.config.max_sh_per_se > 16) 4988 return -EINVAL; 4989 4990 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4991 adev->gfx.config.max_shader_engines, 4992 adev->gfx.config.max_sh_per_se); 4993 4994 mutex_lock(&adev->grbm_idx_mutex); 4995 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4996 is_symmetric_cus = true; 4997 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4998 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4999 mask = 1; 5000 ao_bitmap = 0; 5001 counter = 0; 5002 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 5003 gfx_v9_4_3_set_user_cu_inactive_bitmap( 5004 adev, 5005 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 5006 xcc_id); 5007 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 5008 5009 cu_info->bitmap[xcc_id][i][j] = bitmap; 5010 5011 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5012 if (bitmap & mask) { 5013 if (counter < adev->gfx.config.max_cu_per_sh) 5014 ao_bitmap |= mask; 5015 counter++; 5016 } 5017 mask <<= 1; 5018 } 5019 active_cu_number += counter; 5020 if (i < 2 && j < 2) 5021 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5022 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5023 } 5024 if (i && is_symmetric_cus && prev_counter != counter) 5025 is_symmetric_cus = false; 5026 prev_counter = counter; 5027 } 5028 if (is_symmetric_cus) { 5029 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 5030 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 5031 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 5032 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 5033 } 5034 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 5035 xcc_id); 5036 } 5037 mutex_unlock(&adev->grbm_idx_mutex); 5038 5039 cu_info->number = active_cu_number; 5040 cu_info->ao_cu_mask = ao_cu_mask; 5041 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5042 5043 return 0; 5044 } 5045 5046 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 5047 .type = AMD_IP_BLOCK_TYPE_GFX, 5048 .major = 9, 5049 .minor = 4, 5050 .rev = 3, 5051 .funcs = &gfx_v9_4_3_ip_funcs, 5052 }; 5053 5054 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 5055 { 5056 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5057 uint32_t tmp_mask; 5058 int i, r; 5059 5060 /* TODO : Initialize golden regs */ 5061 /* gfx_v9_4_3_init_golden_registers(adev); */ 5062 5063 tmp_mask = inst_mask; 5064 for_each_inst(i, tmp_mask) 5065 gfx_v9_4_3_xcc_constants_init(adev, i); 5066 5067 if (!amdgpu_sriov_vf(adev)) { 5068 tmp_mask = inst_mask; 5069 for_each_inst(i, tmp_mask) { 5070 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 5071 if (r) 5072 return r; 5073 } 5074 } 5075 5076 tmp_mask = inst_mask; 5077 for_each_inst(i, tmp_mask) { 5078 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 5079 if (r) 5080 return r; 5081 } 5082 5083 return 0; 5084 } 5085 5086 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 5087 { 5088 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5089 int i; 5090 5091 for_each_inst(i, inst_mask) 5092 gfx_v9_4_3_xcc_fini(adev, i); 5093 5094 return 0; 5095 } 5096 5097 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5098 .suspend = &gfx_v9_4_3_xcp_suspend, 5099 .resume = &gfx_v9_4_3_xcp_resume 5100 }; 5101 5102 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5103 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5104 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5105 }; 5106 5107 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5108 { 5109 int r; 5110 5111 r = amdgpu_ras_block_late_init(adev, ras_block); 5112 if (r) 5113 return r; 5114 5115 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5116 &gfx_v9_4_3_aca_info, 5117 NULL); 5118 if (r) 5119 goto late_fini; 5120 5121 return 0; 5122 5123 late_fini: 5124 amdgpu_ras_block_late_fini(adev, ras_block); 5125 5126 return r; 5127 } 5128 5129 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5130 .ras_block = { 5131 .hw_ops = &gfx_v9_4_3_ras_ops, 5132 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5133 }, 5134 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5135 }; 5136