1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 51 52 #define GFX9_MEC_HPD_SIZE 4096 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 56 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 57 58 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 59 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 60 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 61 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 62 63 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 64 (offset & 0xFFFF) 65 66 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 67 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 69 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 78 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 84 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 97 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 102 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 103 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 107 /* SE status registers */ 108 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 109 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 110 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 111 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 112 }; 113 114 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 115 /* compute queue registers */ 116 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 117 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 118 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 161 }; 162 163 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 164 165 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 166 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 167 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 168 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 169 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 170 struct amdgpu_cu_info *cu_info); 171 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 172 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 173 174 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 175 uint64_t queue_mask) 176 { 177 struct amdgpu_device *adev = kiq_ring->adev; 178 u64 shader_mc_addr; 179 180 /* Cleaner shader MC address */ 181 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 182 183 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 184 amdgpu_ring_write(kiq_ring, 185 PACKET3_SET_RESOURCES_VMID_MASK(0) | 186 /* vmid_mask:0* queue_type:0 (KIQ) */ 187 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 188 amdgpu_ring_write(kiq_ring, 189 lower_32_bits(queue_mask)); /* queue mask lo */ 190 amdgpu_ring_write(kiq_ring, 191 upper_32_bits(queue_mask)); /* queue mask hi */ 192 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 193 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 194 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 195 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 196 } 197 198 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 199 struct amdgpu_ring *ring) 200 { 201 struct amdgpu_device *adev = kiq_ring->adev; 202 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 203 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 204 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 205 206 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 207 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 208 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 209 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 210 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 211 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 212 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 213 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 214 /*queue_type: normal compute queue */ 215 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 216 /* alloc format: all_on_one_pipe */ 217 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 218 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 219 /* num_queues: must be 1 */ 220 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 221 amdgpu_ring_write(kiq_ring, 222 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 223 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 224 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 225 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 226 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 227 } 228 229 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 230 struct amdgpu_ring *ring, 231 enum amdgpu_unmap_queues_action action, 232 u64 gpu_addr, u64 seq) 233 { 234 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 235 236 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 237 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 238 PACKET3_UNMAP_QUEUES_ACTION(action) | 239 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 240 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 241 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 242 amdgpu_ring_write(kiq_ring, 243 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 244 245 if (action == PREEMPT_QUEUES_NO_UNMAP) { 246 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 247 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 248 amdgpu_ring_write(kiq_ring, seq); 249 } else { 250 amdgpu_ring_write(kiq_ring, 0); 251 amdgpu_ring_write(kiq_ring, 0); 252 amdgpu_ring_write(kiq_ring, 0); 253 } 254 } 255 256 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 257 struct amdgpu_ring *ring, 258 u64 addr, 259 u64 seq) 260 { 261 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 262 263 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 264 amdgpu_ring_write(kiq_ring, 265 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 266 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 267 PACKET3_QUERY_STATUS_COMMAND(2)); 268 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 269 amdgpu_ring_write(kiq_ring, 270 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 271 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 272 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 273 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 274 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 275 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 276 } 277 278 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 279 uint16_t pasid, uint32_t flush_type, 280 bool all_hub) 281 { 282 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 283 amdgpu_ring_write(kiq_ring, 284 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 285 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 286 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 287 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 288 } 289 290 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 291 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 292 uint32_t xcc_id, uint32_t vmid) 293 { 294 struct amdgpu_device *adev = kiq_ring->adev; 295 unsigned i; 296 297 /* enter save mode */ 298 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 299 mutex_lock(&adev->srbm_mutex); 300 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 301 302 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 303 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 304 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 305 /* wait till dequeue take effects */ 306 for (i = 0; i < adev->usec_timeout; i++) { 307 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 308 break; 309 udelay(1); 310 } 311 if (i >= adev->usec_timeout) 312 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 313 } else { 314 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 315 } 316 317 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 318 mutex_unlock(&adev->srbm_mutex); 319 /* exit safe mode */ 320 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 321 } 322 323 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 324 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 325 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 326 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 327 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 328 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 329 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 330 .set_resources_size = 8, 331 .map_queues_size = 7, 332 .unmap_queues_size = 6, 333 .query_status_size = 7, 334 .invalidate_tlbs_size = 2, 335 }; 336 337 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 338 { 339 int i, num_xcc; 340 341 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 342 for (i = 0; i < num_xcc; i++) 343 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 344 } 345 346 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 347 { 348 int i, num_xcc, dev_inst; 349 350 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 351 for (i = 0; i < num_xcc; i++) { 352 dev_inst = GET_INST(GC, i); 353 354 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 355 GOLDEN_GB_ADDR_CONFIG); 356 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 357 } 358 } 359 360 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 361 { 362 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 363 364 /* If it is an XCC reg, normalize the reg to keep 365 lower 16 bits in local xcc */ 366 367 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 368 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 369 return normalized_reg; 370 else 371 return reg; 372 } 373 374 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 375 bool wc, uint32_t reg, uint32_t val) 376 { 377 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 378 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 379 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 380 WRITE_DATA_DST_SEL(0) | 381 (wc ? WR_CONFIRM : 0)); 382 amdgpu_ring_write(ring, reg); 383 amdgpu_ring_write(ring, 0); 384 amdgpu_ring_write(ring, val); 385 } 386 387 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 388 int mem_space, int opt, uint32_t addr0, 389 uint32_t addr1, uint32_t ref, uint32_t mask, 390 uint32_t inv) 391 { 392 /* Only do the normalization on regspace */ 393 if (mem_space == 0) { 394 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 395 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 396 } 397 398 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 399 amdgpu_ring_write(ring, 400 /* memory (1) or register (0) */ 401 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 402 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 403 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 404 WAIT_REG_MEM_ENGINE(eng_sel))); 405 406 if (mem_space) 407 WARN_ON(addr0 & 0x3); /* Dword align */ 408 amdgpu_ring_write(ring, addr0); 409 amdgpu_ring_write(ring, addr1); 410 amdgpu_ring_write(ring, ref); 411 amdgpu_ring_write(ring, mask); 412 amdgpu_ring_write(ring, inv); /* poll interval */ 413 } 414 415 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 416 { 417 uint32_t scratch_reg0_offset, xcc_offset; 418 struct amdgpu_device *adev = ring->adev; 419 uint32_t tmp = 0; 420 unsigned i; 421 int r; 422 423 /* Use register offset which is local to XCC in the packet */ 424 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 425 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 426 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 427 tmp = RREG32(scratch_reg0_offset); 428 429 r = amdgpu_ring_alloc(ring, 3); 430 if (r) 431 return r; 432 433 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 434 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 435 amdgpu_ring_write(ring, 0xDEADBEEF); 436 amdgpu_ring_commit(ring); 437 438 for (i = 0; i < adev->usec_timeout; i++) { 439 tmp = RREG32(scratch_reg0_offset); 440 if (tmp == 0xDEADBEEF) 441 break; 442 udelay(1); 443 } 444 445 if (i >= adev->usec_timeout) 446 r = -ETIMEDOUT; 447 return r; 448 } 449 450 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 451 { 452 struct amdgpu_device *adev = ring->adev; 453 struct amdgpu_ib ib; 454 struct dma_fence *f = NULL; 455 456 unsigned index; 457 uint64_t gpu_addr; 458 uint32_t tmp; 459 long r; 460 461 r = amdgpu_wb_get(adev, &index); 462 if (r) 463 return r; 464 465 gpu_addr = adev->wb.gpu_addr + (index * 4); 466 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 467 memset(&ib, 0, sizeof(ib)); 468 469 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 470 if (r) 471 goto err1; 472 473 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 474 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 475 ib.ptr[2] = lower_32_bits(gpu_addr); 476 ib.ptr[3] = upper_32_bits(gpu_addr); 477 ib.ptr[4] = 0xDEADBEEF; 478 ib.length_dw = 5; 479 480 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 481 if (r) 482 goto err2; 483 484 r = dma_fence_wait_timeout(f, false, timeout); 485 if (r == 0) { 486 r = -ETIMEDOUT; 487 goto err2; 488 } else if (r < 0) { 489 goto err2; 490 } 491 492 tmp = adev->wb.wb[index]; 493 if (tmp == 0xDEADBEEF) 494 r = 0; 495 else 496 r = -EINVAL; 497 498 err2: 499 amdgpu_ib_free(&ib, NULL); 500 dma_fence_put(f); 501 err1: 502 amdgpu_wb_free(adev, index); 503 return r; 504 } 505 506 507 /* This value might differs per partition */ 508 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 509 { 510 uint64_t clock; 511 512 mutex_lock(&adev->gfx.gpu_clock_mutex); 513 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 514 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 515 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 516 mutex_unlock(&adev->gfx.gpu_clock_mutex); 517 518 return clock; 519 } 520 521 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 522 { 523 amdgpu_ucode_release(&adev->gfx.pfp_fw); 524 amdgpu_ucode_release(&adev->gfx.me_fw); 525 amdgpu_ucode_release(&adev->gfx.ce_fw); 526 amdgpu_ucode_release(&adev->gfx.rlc_fw); 527 amdgpu_ucode_release(&adev->gfx.mec_fw); 528 amdgpu_ucode_release(&adev->gfx.mec2_fw); 529 530 kfree(adev->gfx.rlc.register_list_format); 531 } 532 533 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 534 const char *chip_name) 535 { 536 int err; 537 const struct rlc_firmware_header_v2_0 *rlc_hdr; 538 uint16_t version_major; 539 uint16_t version_minor; 540 541 542 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 543 AMDGPU_UCODE_REQUIRED, 544 "amdgpu/%s_rlc.bin", chip_name); 545 if (err) 546 goto out; 547 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 548 549 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 550 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 551 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 552 out: 553 if (err) 554 amdgpu_ucode_release(&adev->gfx.rlc_fw); 555 556 return err; 557 } 558 559 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 560 const char *chip_name) 561 { 562 int err; 563 564 if (amdgpu_sriov_vf(adev)) { 565 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 566 AMDGPU_UCODE_REQUIRED, 567 "amdgpu/%s_sjt_mec.bin", chip_name); 568 569 if (err) 570 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 571 AMDGPU_UCODE_REQUIRED, 572 "amdgpu/%s_mec.bin", chip_name); 573 } else 574 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 575 AMDGPU_UCODE_REQUIRED, 576 "amdgpu/%s_mec.bin", chip_name); 577 if (err) 578 goto out; 579 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 580 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 581 582 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 583 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 584 585 out: 586 if (err) 587 amdgpu_ucode_release(&adev->gfx.mec_fw); 588 return err; 589 } 590 591 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 592 { 593 char ucode_prefix[15]; 594 int r; 595 596 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 597 598 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 599 if (r) 600 return r; 601 602 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 603 if (r) 604 return r; 605 606 return r; 607 } 608 609 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 610 { 611 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 612 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 613 } 614 615 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 616 { 617 int r, i, num_xcc; 618 u32 *hpd; 619 const __le32 *fw_data; 620 unsigned fw_size; 621 u32 *fw; 622 size_t mec_hpd_size; 623 624 const struct gfx_firmware_header_v1_0 *mec_hdr; 625 626 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 627 for (i = 0; i < num_xcc; i++) 628 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 629 AMDGPU_MAX_COMPUTE_QUEUES); 630 631 /* take ownership of the relevant compute queues */ 632 amdgpu_gfx_compute_queue_acquire(adev); 633 mec_hpd_size = 634 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 635 if (mec_hpd_size) { 636 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 637 AMDGPU_GEM_DOMAIN_VRAM | 638 AMDGPU_GEM_DOMAIN_GTT, 639 &adev->gfx.mec.hpd_eop_obj, 640 &adev->gfx.mec.hpd_eop_gpu_addr, 641 (void **)&hpd); 642 if (r) { 643 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 644 gfx_v9_4_3_mec_fini(adev); 645 return r; 646 } 647 648 if (amdgpu_emu_mode == 1) { 649 for (i = 0; i < mec_hpd_size / 4; i++) { 650 memset((void *)(hpd + i), 0, 4); 651 if (i % 50 == 0) 652 msleep(1); 653 } 654 } else { 655 memset(hpd, 0, mec_hpd_size); 656 } 657 658 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 659 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 660 } 661 662 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 663 664 fw_data = (const __le32 *) 665 (adev->gfx.mec_fw->data + 666 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 667 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 668 669 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 670 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 671 &adev->gfx.mec.mec_fw_obj, 672 &adev->gfx.mec.mec_fw_gpu_addr, 673 (void **)&fw); 674 if (r) { 675 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 676 gfx_v9_4_3_mec_fini(adev); 677 return r; 678 } 679 680 memcpy(fw, fw_data, fw_size); 681 682 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 683 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 684 685 return 0; 686 } 687 688 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 689 u32 sh_num, u32 instance, int xcc_id) 690 { 691 u32 data; 692 693 if (instance == 0xffffffff) 694 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 695 INSTANCE_BROADCAST_WRITES, 1); 696 else 697 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 698 INSTANCE_INDEX, instance); 699 700 if (se_num == 0xffffffff) 701 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 702 SE_BROADCAST_WRITES, 1); 703 else 704 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 705 706 if (sh_num == 0xffffffff) 707 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 708 SH_BROADCAST_WRITES, 1); 709 else 710 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 711 712 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 713 } 714 715 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 716 { 717 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 718 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 719 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 720 (address << SQ_IND_INDEX__INDEX__SHIFT) | 721 (SQ_IND_INDEX__FORCE_READ_MASK)); 722 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 723 } 724 725 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 726 uint32_t wave, uint32_t thread, 727 uint32_t regno, uint32_t num, uint32_t *out) 728 { 729 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 730 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 731 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 732 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 733 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 734 (SQ_IND_INDEX__FORCE_READ_MASK) | 735 (SQ_IND_INDEX__AUTO_INCR_MASK)); 736 while (num--) 737 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 738 } 739 740 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 741 uint32_t xcc_id, uint32_t simd, uint32_t wave, 742 uint32_t *dst, int *no_fields) 743 { 744 /* type 1 wave data */ 745 dst[(*no_fields)++] = 1; 746 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 747 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 748 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 749 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 750 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 751 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 752 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 753 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 754 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 755 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 756 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 757 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 758 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 759 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 760 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 761 } 762 763 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 764 uint32_t wave, uint32_t start, 765 uint32_t size, uint32_t *dst) 766 { 767 wave_read_regs(adev, xcc_id, simd, wave, 0, 768 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 769 } 770 771 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 772 uint32_t wave, uint32_t thread, 773 uint32_t start, uint32_t size, 774 uint32_t *dst) 775 { 776 wave_read_regs(adev, xcc_id, simd, wave, thread, 777 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 778 } 779 780 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 781 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 782 { 783 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 784 } 785 786 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 787 { 788 u32 xcp_ctl; 789 790 /* Value is expected to be the same on all, fetch from first instance */ 791 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 792 793 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 794 } 795 796 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 797 int num_xccs_per_xcp) 798 { 799 int ret, i, num_xcc; 800 u32 tmp = 0; 801 802 if (adev->psp.funcs) { 803 ret = psp_spatial_partition(&adev->psp, 804 NUM_XCC(adev->gfx.xcc_mask) / 805 num_xccs_per_xcp); 806 if (ret) 807 return ret; 808 } else { 809 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 810 811 for (i = 0; i < num_xcc; i++) { 812 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 813 num_xccs_per_xcp); 814 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 815 i % num_xccs_per_xcp); 816 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 817 tmp); 818 } 819 ret = 0; 820 } 821 822 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 823 824 return ret; 825 } 826 827 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 828 { 829 int xcc; 830 831 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 832 if (!xcc) { 833 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 834 return -EINVAL; 835 } 836 837 return xcc - 1; 838 } 839 840 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 841 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 842 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 843 .read_wave_data = &gfx_v9_4_3_read_wave_data, 844 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 845 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 846 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 847 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 848 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 849 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 850 .get_hdp_flush_mask = &amdgpu_gfx_get_hdp_flush_mask, 851 }; 852 853 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 854 { 855 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 856 adev->gfx.ras = &gfx_v9_4_3_ras; 857 858 adev->gfx.config.max_hw_contexts = 8; 859 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 860 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 861 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 862 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 863 adev->gfx.config.gb_addr_config = GOLDEN_GB_ADDR_CONFIG; 864 865 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 866 REG_GET_FIELD( 867 adev->gfx.config.gb_addr_config, 868 GB_ADDR_CONFIG, 869 NUM_PIPES); 870 871 adev->gfx.config.max_tile_pipes = 872 adev->gfx.config.gb_addr_config_fields.num_pipes; 873 874 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 875 REG_GET_FIELD( 876 adev->gfx.config.gb_addr_config, 877 GB_ADDR_CONFIG, 878 NUM_BANKS); 879 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 880 REG_GET_FIELD( 881 adev->gfx.config.gb_addr_config, 882 GB_ADDR_CONFIG, 883 MAX_COMPRESSED_FRAGS); 884 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 885 REG_GET_FIELD( 886 adev->gfx.config.gb_addr_config, 887 GB_ADDR_CONFIG, 888 NUM_RB_PER_SE); 889 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 890 REG_GET_FIELD( 891 adev->gfx.config.gb_addr_config, 892 GB_ADDR_CONFIG, 893 NUM_SHADER_ENGINES); 894 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 895 REG_GET_FIELD( 896 adev->gfx.config.gb_addr_config, 897 GB_ADDR_CONFIG, 898 PIPE_INTERLEAVE_SIZE)); 899 900 return 0; 901 } 902 903 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 904 int xcc_id, int mec, int pipe, int queue) 905 { 906 unsigned irq_type; 907 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 908 unsigned int hw_prio; 909 uint32_t xcc_doorbell_start; 910 911 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 912 ring_id]; 913 914 /* mec0 is me1 */ 915 ring->xcc_id = xcc_id; 916 ring->me = mec + 1; 917 ring->pipe = pipe; 918 ring->queue = queue; 919 920 ring->ring_obj = NULL; 921 ring->use_doorbell = true; 922 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 923 xcc_id * adev->doorbell_index.xcc_doorbell_range; 924 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 925 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 926 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 927 GFX9_MEC_HPD_SIZE; 928 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 929 sprintf(ring->name, "comp_%d.%d.%d.%d", 930 ring->xcc_id, ring->me, ring->pipe, ring->queue); 931 932 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 933 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 934 + ring->pipe; 935 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 936 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 937 /* type-2 packets are deprecated on MEC, use type-3 instead */ 938 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 939 hw_prio, NULL); 940 } 941 942 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 943 { 944 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 945 uint32_t *ptr, num_xcc, inst; 946 947 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 948 949 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 950 if (!ptr) { 951 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 952 adev->gfx.ip_dump_core = NULL; 953 } else { 954 adev->gfx.ip_dump_core = ptr; 955 } 956 957 /* Allocate memory for compute queue registers for all the instances */ 958 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 959 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 960 adev->gfx.mec.num_queue_per_pipe; 961 962 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 963 if (!ptr) { 964 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 965 adev->gfx.ip_dump_compute_queues = NULL; 966 } else { 967 adev->gfx.ip_dump_compute_queues = ptr; 968 } 969 } 970 971 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 972 { 973 int i, j, k, r, ring_id, xcc_id, num_xcc; 974 struct amdgpu_device *adev = ip_block->adev; 975 976 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 977 case IP_VERSION(9, 4, 3): 978 case IP_VERSION(9, 4, 4): 979 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 980 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 981 if (adev->gfx.mec_fw_version >= 153) { 982 adev->gfx.enable_cleaner_shader = true; 983 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 984 if (r) { 985 adev->gfx.enable_cleaner_shader = false; 986 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 987 } 988 } 989 break; 990 default: 991 adev->gfx.enable_cleaner_shader = false; 992 break; 993 } 994 995 adev->gfx.mec.num_mec = 2; 996 adev->gfx.mec.num_pipe_per_mec = 4; 997 adev->gfx.mec.num_queue_per_pipe = 8; 998 999 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1000 1001 /* EOP Event */ 1002 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1003 if (r) 1004 return r; 1005 1006 /* Bad opcode Event */ 1007 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1008 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1009 &adev->gfx.bad_op_irq); 1010 if (r) 1011 return r; 1012 1013 /* Privileged reg */ 1014 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1015 &adev->gfx.priv_reg_irq); 1016 if (r) 1017 return r; 1018 1019 /* Privileged inst */ 1020 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1021 &adev->gfx.priv_inst_irq); 1022 if (r) 1023 return r; 1024 1025 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1026 1027 r = adev->gfx.rlc.funcs->init(adev); 1028 if (r) { 1029 DRM_ERROR("Failed to init rlc BOs!\n"); 1030 return r; 1031 } 1032 1033 r = gfx_v9_4_3_mec_init(adev); 1034 if (r) { 1035 DRM_ERROR("Failed to init MEC BOs!\n"); 1036 return r; 1037 } 1038 1039 /* set up the compute queues - allocate horizontally across pipes */ 1040 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1041 ring_id = 0; 1042 if (!adev->gfx.disable_kq) { 1043 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1044 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1045 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1046 k++) { 1047 if (!amdgpu_gfx_is_mec_queue_enabled( 1048 adev, xcc_id, i, k, j)) 1049 continue; 1050 1051 r = gfx_v9_4_3_compute_ring_init(adev, 1052 ring_id, 1053 xcc_id, 1054 i, k, j); 1055 if (r) 1056 return r; 1057 1058 ring_id++; 1059 } 1060 } 1061 } 1062 } 1063 1064 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1065 if (r) { 1066 DRM_ERROR("Failed to init KIQ BOs!\n"); 1067 return r; 1068 } 1069 1070 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1071 if (r) 1072 return r; 1073 1074 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1075 r = amdgpu_gfx_mqd_sw_init(adev, 1076 sizeof(struct v9_mqd_allocation), xcc_id); 1077 if (r) 1078 return r; 1079 } 1080 1081 adev->gfx.compute_supported_reset = 1082 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1083 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1084 case IP_VERSION(9, 4, 3): 1085 case IP_VERSION(9, 4, 4): 1086 if ((adev->gfx.mec_fw_version >= 155) && 1087 !amdgpu_sriov_vf(adev) && 1088 !adev->debug_disable_gpu_ring_reset) { 1089 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1090 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1091 } 1092 break; 1093 case IP_VERSION(9, 5, 0): 1094 if ((adev->gfx.mec_fw_version >= 21) && 1095 !amdgpu_sriov_vf(adev) && 1096 !adev->debug_disable_gpu_ring_reset) { 1097 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1098 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1099 } 1100 break; 1101 default: 1102 break; 1103 } 1104 r = gfx_v9_4_3_gpu_early_init(adev); 1105 if (r) 1106 return r; 1107 1108 r = amdgpu_gfx_ras_sw_init(adev); 1109 if (r) 1110 return r; 1111 1112 r = amdgpu_gfx_sysfs_init(adev); 1113 if (r) 1114 return r; 1115 1116 gfx_v9_4_3_alloc_ip_dump(adev); 1117 1118 return 0; 1119 } 1120 1121 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1122 { 1123 int i, num_xcc; 1124 struct amdgpu_device *adev = ip_block->adev; 1125 1126 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1127 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1128 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1129 1130 for (i = 0; i < num_xcc; i++) { 1131 amdgpu_gfx_mqd_sw_fini(adev, i); 1132 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1133 amdgpu_gfx_kiq_fini(adev, i); 1134 } 1135 1136 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1137 1138 gfx_v9_4_3_mec_fini(adev); 1139 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1140 gfx_v9_4_3_free_microcode(adev); 1141 amdgpu_gfx_sysfs_fini(adev); 1142 1143 kfree(adev->gfx.ip_dump_core); 1144 kfree(adev->gfx.ip_dump_compute_queues); 1145 1146 return 0; 1147 } 1148 1149 #define DEFAULT_SH_MEM_BASES (0x6000) 1150 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1151 int xcc_id) 1152 { 1153 int i; 1154 uint32_t sh_mem_config; 1155 uint32_t sh_mem_bases; 1156 uint32_t data; 1157 1158 /* 1159 * Configure apertures: 1160 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1161 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1162 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1163 */ 1164 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1165 1166 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1167 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1168 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1169 1170 mutex_lock(&adev->srbm_mutex); 1171 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1172 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1173 /* CP and shaders */ 1174 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1175 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1176 1177 /* Enable trap for each kfd vmid. */ 1178 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1179 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1180 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1181 } 1182 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1183 mutex_unlock(&adev->srbm_mutex); 1184 1185 /* 1186 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1187 * access. These should be enabled by FW for target VMIDs. 1188 */ 1189 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1190 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1191 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1192 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1193 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1194 } 1195 } 1196 1197 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1198 { 1199 int vmid; 1200 1201 /* 1202 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1203 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1204 * the driver can enable them for graphics. VMID0 should maintain 1205 * access so that HWS firmware can save/restore entries. 1206 */ 1207 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1208 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1209 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1210 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1211 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1212 } 1213 } 1214 1215 /* For ASICs that needs xnack chain and MEC version supports, set SG_CONFIG1 1216 * DISABLE_XNACK_CHECK_IN_RETRY_DISABLE bit and inform KFD to set xnack_chain 1217 * bit in SET_RESOURCES 1218 */ 1219 static void gfx_v9_4_3_xcc_init_sq(struct amdgpu_device *adev, int xcc_id) 1220 { 1221 uint32_t data; 1222 1223 if (!(adev->gmc.xnack_flags & AMDGPU_GMC_XNACK_FLAG_CHAIN)) 1224 return; 1225 1226 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_CONFIG1); 1227 data = REG_SET_FIELD(data, SQ_CONFIG1, DISABLE_XNACK_CHECK_IN_RETRY_DISABLE, 1); 1228 WREG32_SOC15(GC, xcc_id, regSQ_CONFIG1, data); 1229 } 1230 1231 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1232 int xcc_id) 1233 { 1234 u32 tmp; 1235 int i; 1236 1237 /* XXX SH_MEM regs */ 1238 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1239 mutex_lock(&adev->srbm_mutex); 1240 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1241 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1242 /* CP and shaders */ 1243 if (i == 0) { 1244 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1245 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1246 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1247 !!adev->gmc.noretry); 1248 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1249 regSH_MEM_CONFIG, tmp); 1250 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1251 regSH_MEM_BASES, 0); 1252 } else { 1253 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1254 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1255 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1256 !!adev->gmc.noretry); 1257 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1258 regSH_MEM_CONFIG, tmp); 1259 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1260 (adev->gmc.private_aperture_start >> 1261 48)); 1262 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1263 (adev->gmc.shared_aperture_start >> 1264 48)); 1265 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1266 regSH_MEM_BASES, tmp); 1267 } 1268 } 1269 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1270 1271 mutex_unlock(&adev->srbm_mutex); 1272 1273 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1274 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1275 gfx_v9_4_3_xcc_init_sq(adev, xcc_id); 1276 } 1277 1278 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1279 { 1280 int i, num_xcc; 1281 1282 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1283 1284 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1285 adev->gfx.config.db_debug2 = 1286 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1287 1288 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1289 /* ToDo: GC 9.4.4 */ 1290 case IP_VERSION(9, 4, 3): 1291 if (adev->gfx.mec_fw_version >= 184 && 1292 (amdgpu_sriov_reg_access_sq_config(adev) || 1293 !amdgpu_sriov_vf(adev))) 1294 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1295 break; 1296 case IP_VERSION(9, 5, 0): 1297 if (adev->gfx.mec_fw_version >= 23) 1298 adev->gmc.xnack_flags |= AMDGPU_GMC_XNACK_FLAG_CHAIN; 1299 break; 1300 default: 1301 break; 1302 } 1303 1304 for (i = 0; i < num_xcc; i++) 1305 gfx_v9_4_3_xcc_constants_init(adev, i); 1306 } 1307 1308 static void 1309 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1310 int xcc_id) 1311 { 1312 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1313 } 1314 1315 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1316 { 1317 /* 1318 * Rlc save restore list is workable since v2_1. 1319 */ 1320 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1321 } 1322 1323 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1324 { 1325 uint32_t data; 1326 1327 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1328 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1329 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1330 } 1331 1332 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1333 { 1334 uint32_t rlc_setting; 1335 1336 /* if RLC is not enabled, do nothing */ 1337 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1338 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1339 return false; 1340 1341 return true; 1342 } 1343 1344 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1345 { 1346 uint32_t data; 1347 unsigned i; 1348 1349 data = RLC_SAFE_MODE__CMD_MASK; 1350 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1351 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1352 1353 /* wait for RLC_SAFE_MODE */ 1354 for (i = 0; i < adev->usec_timeout; i++) { 1355 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1356 break; 1357 udelay(1); 1358 } 1359 } 1360 1361 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1362 int xcc_id) 1363 { 1364 uint32_t data; 1365 1366 data = RLC_SAFE_MODE__CMD_MASK; 1367 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1368 } 1369 1370 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1371 { 1372 int xcc_id, num_xcc; 1373 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1374 1375 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1376 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1377 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1378 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1379 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1380 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1381 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1382 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1383 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1384 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1385 } 1386 adev->gfx.rlc.rlcg_reg_access_supported = true; 1387 } 1388 1389 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1390 { 1391 /* init spm vmid with 0xf */ 1392 if (adev->gfx.rlc.funcs->update_spm_vmid) 1393 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0, NULL, 0xf); 1394 1395 return 0; 1396 } 1397 1398 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1399 int xcc_id) 1400 { 1401 u32 i, j, k; 1402 u32 mask; 1403 1404 mutex_lock(&adev->grbm_idx_mutex); 1405 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1406 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1407 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1408 xcc_id); 1409 for (k = 0; k < adev->usec_timeout; k++) { 1410 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1411 break; 1412 udelay(1); 1413 } 1414 if (k == adev->usec_timeout) { 1415 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1416 0xffffffff, 1417 0xffffffff, xcc_id); 1418 mutex_unlock(&adev->grbm_idx_mutex); 1419 drm_info(adev_to_drm(adev), "Timeout wait for RLC serdes %u,%u\n", 1420 i, j); 1421 return; 1422 } 1423 } 1424 } 1425 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1426 xcc_id); 1427 mutex_unlock(&adev->grbm_idx_mutex); 1428 1429 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1430 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1431 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1432 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1433 for (k = 0; k < adev->usec_timeout; k++) { 1434 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1435 break; 1436 udelay(1); 1437 } 1438 } 1439 1440 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1441 bool enable, int xcc_id) 1442 { 1443 u32 tmp; 1444 1445 /* These interrupts should be enabled to drive DS clock */ 1446 1447 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1448 1449 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1450 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1451 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1452 1453 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1454 } 1455 1456 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1457 { 1458 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1459 RLC_ENABLE_F32, 0); 1460 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1461 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1462 } 1463 1464 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1465 { 1466 int i, num_xcc; 1467 1468 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1469 for (i = 0; i < num_xcc; i++) 1470 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1471 } 1472 1473 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1474 { 1475 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1476 SOFT_RESET_RLC, 1); 1477 udelay(50); 1478 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1479 SOFT_RESET_RLC, 0); 1480 udelay(50); 1481 } 1482 1483 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1484 { 1485 int i, num_xcc; 1486 1487 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1488 for (i = 0; i < num_xcc; i++) 1489 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1490 } 1491 1492 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1493 { 1494 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1495 RLC_ENABLE_F32, 1); 1496 udelay(50); 1497 1498 /* carrizo do enable cp interrupt after cp inited */ 1499 if (!(adev->flags & AMD_IS_APU)) { 1500 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1501 udelay(50); 1502 } 1503 } 1504 1505 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1506 { 1507 #ifdef AMDGPU_RLC_DEBUG_RETRY 1508 u32 rlc_ucode_ver; 1509 #endif 1510 int i, num_xcc; 1511 1512 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1513 for (i = 0; i < num_xcc; i++) { 1514 gfx_v9_4_3_xcc_rlc_start(adev, i); 1515 #ifdef AMDGPU_RLC_DEBUG_RETRY 1516 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1517 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1518 if (rlc_ucode_ver == 0x108) { 1519 dev_info(adev->dev, 1520 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i\n", 1521 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1522 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1523 * default is 0x9C4 to create a 100us interval */ 1524 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1525 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1526 * to disable the page fault retry interrupts, default is 1527 * 0x100 (256) */ 1528 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1529 } 1530 #endif 1531 } 1532 } 1533 1534 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1535 int xcc_id) 1536 { 1537 const struct rlc_firmware_header_v2_0 *hdr; 1538 const __le32 *fw_data; 1539 unsigned i, fw_size; 1540 1541 if (!adev->gfx.rlc_fw) 1542 return -EINVAL; 1543 1544 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1545 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1546 1547 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1548 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1549 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1550 1551 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1552 RLCG_UCODE_LOADING_START_ADDRESS); 1553 for (i = 0; i < fw_size; i++) { 1554 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1555 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1556 msleep(1); 1557 } 1558 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1559 } 1560 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1561 1562 return 0; 1563 } 1564 1565 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1566 { 1567 int r; 1568 1569 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1570 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1571 /* legacy rlc firmware loading */ 1572 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1573 if (r) 1574 return r; 1575 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1576 } 1577 1578 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1579 /* disable CG */ 1580 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1581 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1582 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1583 1584 return 0; 1585 } 1586 1587 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1588 { 1589 int r, i, num_xcc; 1590 1591 if (amdgpu_sriov_vf(adev)) 1592 return 0; 1593 1594 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1595 for (i = 0; i < num_xcc; i++) { 1596 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1597 if (r) 1598 return r; 1599 } 1600 1601 return 0; 1602 } 1603 1604 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, 1605 int inst, struct amdgpu_ring *ring, unsigned int vmid) 1606 { 1607 u32 reg, pre_data, data; 1608 1609 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL); 1610 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1611 pre_data = RREG32_NO_KIQ(reg); 1612 else 1613 pre_data = RREG32(reg); 1614 1615 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1616 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1617 1618 if (pre_data != data) { 1619 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1620 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1621 } else 1622 WREG32_SOC15(GC, GET_INST(GC, inst), regRLC_SPM_MC_CNTL, data); 1623 } 1624 } 1625 1626 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1627 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1628 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1629 }; 1630 1631 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1632 uint32_t offset, 1633 struct soc15_reg_rlcg *entries, int arr_size) 1634 { 1635 int i, inst; 1636 uint32_t reg; 1637 1638 if (!entries) 1639 return false; 1640 1641 for (i = 0; i < arr_size; i++) { 1642 const struct soc15_reg_rlcg *entry; 1643 1644 entry = &entries[i]; 1645 inst = adev->ip_map.logical_to_dev_inst ? 1646 adev->ip_map.logical_to_dev_inst( 1647 adev, entry->hwip, entry->instance) : 1648 entry->instance; 1649 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1650 entry->reg; 1651 if (offset == reg) 1652 return true; 1653 } 1654 1655 return false; 1656 } 1657 1658 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1659 { 1660 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1661 (void *)rlcg_access_gc_9_4_3, 1662 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1663 } 1664 1665 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1666 bool enable, int xcc_id) 1667 { 1668 if (enable) { 1669 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1670 } else { 1671 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1672 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1673 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1674 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1675 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1676 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1677 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1678 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1679 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1680 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1681 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1682 } 1683 udelay(50); 1684 } 1685 1686 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1687 int xcc_id) 1688 { 1689 const struct gfx_firmware_header_v1_0 *mec_hdr; 1690 const __le32 *fw_data; 1691 unsigned i; 1692 u32 tmp; 1693 u32 mec_ucode_addr_offset; 1694 u32 mec_ucode_data_offset; 1695 1696 if (!adev->gfx.mec_fw) 1697 return -EINVAL; 1698 1699 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1700 1701 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1702 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1703 1704 fw_data = (const __le32 *) 1705 (adev->gfx.mec_fw->data + 1706 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1707 tmp = 0; 1708 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1709 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1710 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1711 1712 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1713 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1714 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1715 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1716 1717 mec_ucode_addr_offset = 1718 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1719 mec_ucode_data_offset = 1720 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1721 1722 /* MEC1 */ 1723 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1724 for (i = 0; i < mec_hdr->jt_size; i++) 1725 WREG32(mec_ucode_data_offset, 1726 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1727 1728 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1729 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1730 1731 return 0; 1732 } 1733 1734 /* KIQ functions */ 1735 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1736 { 1737 uint32_t tmp; 1738 struct amdgpu_device *adev = ring->adev; 1739 1740 /* tell RLC which is KIQ queue */ 1741 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1742 tmp &= 0xffffff00; 1743 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1744 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1745 } 1746 1747 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1748 { 1749 struct amdgpu_device *adev = ring->adev; 1750 1751 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1752 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1753 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1754 mqd->cp_hqd_queue_priority = 1755 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1756 } 1757 } 1758 } 1759 1760 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1761 { 1762 struct amdgpu_device *adev = ring->adev; 1763 struct v9_mqd *mqd = ring->mqd_ptr; 1764 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1765 uint32_t tmp; 1766 1767 mqd->header = 0xC0310800; 1768 mqd->compute_pipelinestat_enable = 0x00000001; 1769 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1770 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1771 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1772 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1773 mqd->compute_misc_reserved = 0x00000003; 1774 1775 mqd->dynamic_cu_mask_addr_lo = 1776 lower_32_bits(ring->mqd_gpu_addr 1777 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1778 mqd->dynamic_cu_mask_addr_hi = 1779 upper_32_bits(ring->mqd_gpu_addr 1780 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1781 1782 eop_base_addr = ring->eop_gpu_addr >> 8; 1783 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1784 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1785 1786 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1787 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1788 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1789 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1790 1791 mqd->cp_hqd_eop_control = tmp; 1792 1793 /* enable doorbell? */ 1794 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1795 1796 if (ring->use_doorbell) { 1797 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1798 DOORBELL_OFFSET, ring->doorbell_index); 1799 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1800 DOORBELL_EN, 1); 1801 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1802 DOORBELL_SOURCE, 0); 1803 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1804 DOORBELL_HIT, 0); 1805 if (amdgpu_sriov_multi_vf_mode(adev)) 1806 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1807 DOORBELL_MODE, 1); 1808 } else { 1809 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1810 DOORBELL_EN, 0); 1811 } 1812 1813 mqd->cp_hqd_pq_doorbell_control = tmp; 1814 1815 /* disable the queue if it's active */ 1816 ring->wptr = 0; 1817 mqd->cp_hqd_dequeue_request = 0; 1818 mqd->cp_hqd_pq_rptr = 0; 1819 mqd->cp_hqd_pq_wptr_lo = 0; 1820 mqd->cp_hqd_pq_wptr_hi = 0; 1821 1822 /* set the pointer to the MQD */ 1823 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1824 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1825 1826 /* set MQD vmid to 0 */ 1827 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1828 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1829 mqd->cp_mqd_control = tmp; 1830 1831 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1832 hqd_gpu_addr = ring->gpu_addr >> 8; 1833 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1834 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1835 1836 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1837 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1838 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1839 (order_base_2(ring->ring_size / 4) - 1)); 1840 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1841 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1842 #ifdef __BIG_ENDIAN 1843 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1844 #endif 1845 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1846 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1847 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1848 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1849 mqd->cp_hqd_pq_control = tmp; 1850 1851 /* set the wb address whether it's enabled or not */ 1852 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1853 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1854 mqd->cp_hqd_pq_rptr_report_addr_hi = 1855 upper_32_bits(wb_gpu_addr) & 0xffff; 1856 1857 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1858 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1859 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1860 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1861 1862 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1863 ring->wptr = 0; 1864 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1865 1866 /* set the vmid for the queue */ 1867 mqd->cp_hqd_vmid = 0; 1868 1869 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1870 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1871 mqd->cp_hqd_persistent_state = tmp; 1872 1873 /* set MIN_IB_AVAIL_SIZE */ 1874 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1875 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1876 mqd->cp_hqd_ib_control = tmp; 1877 1878 /* set static priority for a queue/ring */ 1879 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1880 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1881 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1); 1882 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 1883 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 1884 mqd->cp_hqd_quantum = tmp; 1885 1886 /* map_queues packet doesn't need activate the queue, 1887 * so only kiq need set this field. 1888 */ 1889 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1890 mqd->cp_hqd_active = 1; 1891 1892 return 0; 1893 } 1894 1895 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1896 int xcc_id) 1897 { 1898 struct amdgpu_device *adev = ring->adev; 1899 struct v9_mqd *mqd = ring->mqd_ptr; 1900 int j; 1901 1902 /* disable wptr polling */ 1903 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1904 1905 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1906 mqd->cp_hqd_eop_base_addr_lo); 1907 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1908 mqd->cp_hqd_eop_base_addr_hi); 1909 1910 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1911 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1912 mqd->cp_hqd_eop_control); 1913 1914 /* enable doorbell? */ 1915 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1916 mqd->cp_hqd_pq_doorbell_control); 1917 1918 /* disable the queue if it's active */ 1919 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1920 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1921 for (j = 0; j < adev->usec_timeout; j++) { 1922 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1923 break; 1924 udelay(1); 1925 } 1926 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1927 mqd->cp_hqd_dequeue_request); 1928 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1929 mqd->cp_hqd_pq_rptr); 1930 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1931 mqd->cp_hqd_pq_wptr_lo); 1932 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1933 mqd->cp_hqd_pq_wptr_hi); 1934 } 1935 1936 /* set the pointer to the MQD */ 1937 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1938 mqd->cp_mqd_base_addr_lo); 1939 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1940 mqd->cp_mqd_base_addr_hi); 1941 1942 /* set MQD vmid to 0 */ 1943 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1944 mqd->cp_mqd_control); 1945 1946 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1947 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1948 mqd->cp_hqd_pq_base_lo); 1949 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1950 mqd->cp_hqd_pq_base_hi); 1951 1952 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1953 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1954 mqd->cp_hqd_pq_control); 1955 1956 /* set the wb address whether it's enabled or not */ 1957 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1958 mqd->cp_hqd_pq_rptr_report_addr_lo); 1959 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1960 mqd->cp_hqd_pq_rptr_report_addr_hi); 1961 1962 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1963 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1964 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1965 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1966 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1967 1968 /* enable the doorbell if requested */ 1969 if (ring->use_doorbell) { 1970 WREG32_SOC15( 1971 GC, GET_INST(GC, xcc_id), 1972 regCP_MEC_DOORBELL_RANGE_LOWER, 1973 ((adev->doorbell_index.kiq + 1974 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1975 2) << 2); 1976 WREG32_SOC15( 1977 GC, GET_INST(GC, xcc_id), 1978 regCP_MEC_DOORBELL_RANGE_UPPER, 1979 ((adev->doorbell_index.userqueue_end + 1980 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1981 2) << 2); 1982 } 1983 1984 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1985 mqd->cp_hqd_pq_doorbell_control); 1986 1987 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1988 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1989 mqd->cp_hqd_pq_wptr_lo); 1990 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1991 mqd->cp_hqd_pq_wptr_hi); 1992 1993 /* set the vmid for the queue */ 1994 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1995 1996 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1997 mqd->cp_hqd_persistent_state); 1998 1999 /* activate the queue */ 2000 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2001 mqd->cp_hqd_active); 2002 2003 if (ring->use_doorbell) 2004 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2005 2006 return 0; 2007 } 2008 2009 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2010 int xcc_id) 2011 { 2012 struct amdgpu_device *adev = ring->adev; 2013 int j; 2014 2015 /* disable the queue if it's active */ 2016 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2017 2018 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2019 2020 for (j = 0; j < adev->usec_timeout; j++) { 2021 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2022 break; 2023 udelay(1); 2024 } 2025 2026 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2027 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2028 2029 /* Manual disable if dequeue request times out */ 2030 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2031 } 2032 2033 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2034 0); 2035 } 2036 2037 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2038 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2039 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2040 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2041 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2042 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2043 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2044 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2045 2046 return 0; 2047 } 2048 2049 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2050 { 2051 struct amdgpu_device *adev = ring->adev; 2052 struct v9_mqd *mqd = ring->mqd_ptr; 2053 struct v9_mqd *tmp_mqd; 2054 2055 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2056 2057 /* GPU could be in bad state during probe, driver trigger the reset 2058 * after load the SMU, in this case , the mqd is not be initialized. 2059 * driver need to re-init the mqd. 2060 * check mqd->cp_hqd_pq_control since this value should not be 0 2061 */ 2062 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2063 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2064 /* for GPU_RESET case , reset MQD to a clean status */ 2065 if (adev->gfx.kiq[xcc_id].mqd_backup) 2066 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2067 2068 /* reset ring buffer */ 2069 ring->wptr = 0; 2070 amdgpu_ring_clear_ring(ring); 2071 mutex_lock(&adev->srbm_mutex); 2072 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2073 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2074 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2075 mutex_unlock(&adev->srbm_mutex); 2076 } else { 2077 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2078 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2079 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2080 mutex_lock(&adev->srbm_mutex); 2081 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2082 amdgpu_ring_clear_ring(ring); 2083 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2084 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2085 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2086 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2087 mutex_unlock(&adev->srbm_mutex); 2088 2089 if (adev->gfx.kiq[xcc_id].mqd_backup) 2090 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2091 } 2092 2093 return 0; 2094 } 2095 2096 static void gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, 2097 bool restore) 2098 { 2099 struct amdgpu_device *adev = ring->adev; 2100 struct v9_mqd *mqd = ring->mqd_ptr; 2101 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2102 struct v9_mqd *tmp_mqd; 2103 2104 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2105 * is not be initialized before 2106 */ 2107 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2108 2109 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2110 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2111 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2112 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2113 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2114 mutex_lock(&adev->srbm_mutex); 2115 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2116 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2117 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2118 mutex_unlock(&adev->srbm_mutex); 2119 2120 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2121 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2122 } else { 2123 /* restore MQD to a clean status */ 2124 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2125 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2126 /* reset ring buffer */ 2127 ring->wptr = 0; 2128 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2129 amdgpu_ring_clear_ring(ring); 2130 } 2131 } 2132 2133 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2134 { 2135 struct amdgpu_ring *ring; 2136 int j; 2137 2138 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2139 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2140 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2141 mutex_lock(&adev->srbm_mutex); 2142 soc15_grbm_select(adev, ring->me, 2143 ring->pipe, 2144 ring->queue, 0, GET_INST(GC, xcc_id)); 2145 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2146 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2147 mutex_unlock(&adev->srbm_mutex); 2148 } 2149 } 2150 2151 return 0; 2152 } 2153 2154 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2155 { 2156 gfx_v9_4_3_xcc_kiq_init_queue(&adev->gfx.kiq[xcc_id].ring, xcc_id); 2157 return 0; 2158 } 2159 2160 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2161 { 2162 struct amdgpu_ring *ring; 2163 int i; 2164 2165 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2166 2167 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2168 ring = &adev->gfx.compute_ring[i + xcc_id * 2169 adev->gfx.num_compute_rings]; 2170 2171 gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2172 } 2173 2174 return amdgpu_gfx_enable_kcq(adev, xcc_id); 2175 } 2176 2177 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2178 { 2179 struct amdgpu_ring *ring; 2180 int r, j; 2181 2182 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2183 2184 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2185 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2186 2187 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2188 if (r) 2189 return r; 2190 } else { 2191 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2192 } 2193 2194 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2195 if (r) 2196 return r; 2197 2198 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2199 if (r) 2200 return r; 2201 2202 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2203 ring = &adev->gfx.compute_ring 2204 [j + xcc_id * adev->gfx.num_compute_rings]; 2205 r = amdgpu_ring_test_helper(ring); 2206 if (r) 2207 return r; 2208 } 2209 2210 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2211 2212 return 0; 2213 } 2214 2215 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2216 { 2217 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2218 2219 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2220 if (amdgpu_sriov_vf(adev)) { 2221 enum amdgpu_gfx_partition mode; 2222 2223 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2224 AMDGPU_XCP_FL_NONE); 2225 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2226 return -EINVAL; 2227 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2228 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2229 num_xcp = num_xcc / num_xcc_per_xcp; 2230 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2231 2232 } else { 2233 if (adev->in_suspend) 2234 amdgpu_xcp_restore_partition_mode(adev->xcp_mgr); 2235 else if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2236 AMDGPU_XCP_FL_NONE) == 2237 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2238 r = amdgpu_xcp_switch_partition_mode( 2239 adev->xcp_mgr, amdgpu_user_partt_mode); 2240 } 2241 if (r) 2242 return r; 2243 2244 for (i = 0; i < num_xcc; i++) { 2245 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2246 if (r) 2247 return r; 2248 } 2249 2250 return 0; 2251 } 2252 2253 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2254 { 2255 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2256 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2257 2258 if (amdgpu_sriov_vf(adev)) { 2259 /* must disable polling for SRIOV when hw finished, otherwise 2260 * CPC engine may still keep fetching WB address which is already 2261 * invalid after sw finished and trigger DMAR reading error in 2262 * hypervisor side. 2263 */ 2264 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2265 return; 2266 } 2267 2268 /* Use deinitialize sequence from CAIL when unbinding device 2269 * from driver, otherwise KIQ is hanging when binding back 2270 */ 2271 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2272 mutex_lock(&adev->srbm_mutex); 2273 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2274 adev->gfx.kiq[xcc_id].ring.pipe, 2275 adev->gfx.kiq[xcc_id].ring.queue, 0, 2276 GET_INST(GC, xcc_id)); 2277 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2278 xcc_id); 2279 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2280 mutex_unlock(&adev->srbm_mutex); 2281 } 2282 2283 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2284 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2285 } 2286 2287 static int gfx_v9_4_3_set_userq_eop_interrupts(struct amdgpu_device *adev, 2288 bool enable) 2289 { 2290 int num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2291 unsigned int irq_type; 2292 int m, p, xcc_id, r; 2293 2294 if (adev->gfx.disable_kq) { 2295 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 2296 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 2297 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 2298 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2299 + (m * adev->gfx.mec.num_pipe_per_mec) 2300 + p; 2301 2302 if (enable) 2303 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, 2304 irq_type); 2305 else 2306 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, 2307 irq_type); 2308 if (r) { 2309 if (!enable) 2310 return r; 2311 goto err_compute; 2312 } 2313 } 2314 } 2315 } 2316 } 2317 2318 return 0; 2319 2320 err_compute: 2321 for (p--; p >= 0; p--) { 2322 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2323 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2324 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2325 } 2326 for (m--; m >= 0; m--) { 2327 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 2328 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2329 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2330 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2331 } 2332 } 2333 for (xcc_id--; xcc_id >= 0; xcc_id--) { 2334 for (m = adev->gfx.mec.num_mec - 1; m <= 0; m--) { 2335 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 2336 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2337 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2338 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2339 } 2340 } 2341 } 2342 2343 return r; 2344 } 2345 2346 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2347 { 2348 int r; 2349 struct amdgpu_device *adev = ip_block->adev; 2350 2351 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2352 adev->gfx.cleaner_shader_ptr); 2353 2354 if (!amdgpu_sriov_vf(adev)) 2355 gfx_v9_4_3_init_golden_registers(adev); 2356 2357 gfx_v9_4_3_constants_init(adev); 2358 2359 r = adev->gfx.rlc.funcs->resume(adev); 2360 if (r) 2361 return r; 2362 2363 r = gfx_v9_4_3_cp_resume(adev); 2364 if (r) 2365 return r; 2366 2367 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2368 if (r) 2369 return r; 2370 2371 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2372 if (r) 2373 goto err_priv_inst; 2374 2375 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2376 if (r) 2377 goto err_bad_op; 2378 r = gfx_v9_4_3_set_userq_eop_interrupts(adev, true); 2379 if (r) 2380 goto err_bad_eop; 2381 2382 return 0; 2383 2384 err_bad_eop: 2385 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2386 err_bad_op: 2387 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2388 err_priv_inst: 2389 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2390 return r; 2391 } 2392 2393 static int gfx_v9_4_3_perf_monitor_ptl_init(struct amdgpu_device *adev, bool enable) 2394 { 2395 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2396 uint32_t ptl_state = enable ? 1 : 0; 2397 uint32_t fmt1, fmt2; 2398 int r; 2399 2400 if (!adev->psp.funcs) 2401 return -EOPNOTSUPP; 2402 2403 if (!ptl->hw_supported) { 2404 fmt1 = GFX_FTYPE_VECTOR; 2405 fmt2 = GFX_FTYPE_F8; 2406 } else { 2407 fmt1 = ptl->fmt1; 2408 fmt2 = ptl->fmt2; 2409 } 2410 2411 /* initialize PTL with default formats: GFX_FTYPE_VECTOR & GFX_FTYPE_F8 */ 2412 r = amdgpu_ptl_perf_monitor_ctrl(adev, PSP_PTL_PERF_MON_SET, &ptl_state, 2413 &fmt1, &fmt2); 2414 if (r) 2415 return r; 2416 2417 ptl->hw_supported = true; 2418 2419 atomic_set(&ptl->disable_ref, 0); 2420 if (!enable && !amdgpu_in_reset(adev) && !adev->in_suspend) { 2421 dev_dbg(adev->dev, 2422 "PTL disabled (amdgpu.ptl=%d)\ 2423 To enable, set amdgpu.ptl=1 via module param or kernel cmdline\n", 2424 amdgpu_ptl); 2425 set_bit(AMDGPU_PTL_DISABLE_SYSFS, ptl->disable_bitmap); 2426 } 2427 2428 return 0; 2429 } 2430 2431 static int gfx_v9_4_3_ptl_hw_init(struct amdgpu_device *adev) 2432 { 2433 struct amdgpu_ptl *ptl = &adev->psp.ptl; 2434 bool enable; 2435 2436 switch (amdgpu_ptl) { 2437 case 1: 2438 enable = true; 2439 break; 2440 case 2: 2441 /* Permanently disabled - cannot be re-enabled */ 2442 enable = false; 2443 ptl->permanently_disabled = true; 2444 break; 2445 case -1: 2446 case 0: 2447 default: 2448 enable = false; 2449 break; 2450 } 2451 2452 gfx_v9_4_3_perf_monitor_ptl_init(adev, enable ? 1 : 0); 2453 2454 return 0; 2455 } 2456 2457 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2458 { 2459 struct amdgpu_device *adev = ip_block->adev; 2460 int i, num_xcc; 2461 2462 if (adev->psp.ptl.hw_supported && !amdgpu_in_reset(adev)) 2463 gfx_v9_4_3_perf_monitor_ptl_init(adev, false); 2464 2465 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2466 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2467 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2468 gfx_v9_4_3_set_userq_eop_interrupts(adev, false); 2469 2470 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2471 for (i = 0; i < num_xcc; i++) { 2472 gfx_v9_4_3_xcc_fini(adev, i); 2473 } 2474 2475 return 0; 2476 } 2477 2478 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2479 { 2480 return gfx_v9_4_3_hw_fini(ip_block); 2481 } 2482 2483 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2484 { 2485 return gfx_v9_4_3_hw_init(ip_block); 2486 } 2487 2488 static bool gfx_v9_4_3_is_idle(struct amdgpu_ip_block *ip_block) 2489 { 2490 struct amdgpu_device *adev = ip_block->adev; 2491 int i, num_xcc; 2492 u32 gc_ip_version; 2493 2494 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2495 gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0); 2496 2497 for (i = 0; i < num_xcc; i++) { 2498 if (gc_ip_version == IP_VERSION(9, 4, 4)) { 2499 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2500 GRBM_STATUS, SPI_BUSY)) 2501 return false; 2502 } else { 2503 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2504 GRBM_STATUS, GUI_ACTIVE)) 2505 return false; 2506 } 2507 } 2508 return true; 2509 } 2510 2511 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2512 { 2513 unsigned i; 2514 struct amdgpu_device *adev = ip_block->adev; 2515 2516 for (i = 0; i < adev->usec_timeout; i++) { 2517 if (gfx_v9_4_3_is_idle(ip_block)) 2518 return 0; 2519 udelay(1); 2520 } 2521 return -ETIMEDOUT; 2522 } 2523 2524 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2525 { 2526 u32 grbm_soft_reset = 0; 2527 u32 tmp; 2528 struct amdgpu_device *adev = ip_block->adev; 2529 2530 /* GRBM_STATUS */ 2531 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2532 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2533 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2534 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2535 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2536 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2537 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2538 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2539 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2540 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2541 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2542 } 2543 2544 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2545 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2546 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2547 } 2548 2549 /* GRBM_STATUS2 */ 2550 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2551 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2552 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2553 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2554 2555 2556 if (grbm_soft_reset) { 2557 /* stop the rlc */ 2558 adev->gfx.rlc.funcs->stop(adev); 2559 2560 /* Disable MEC parsing/prefetching */ 2561 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2562 2563 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2564 tmp |= grbm_soft_reset; 2565 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2566 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2567 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2568 2569 udelay(50); 2570 2571 tmp &= ~grbm_soft_reset; 2572 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2573 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2574 2575 /* Wait a little for things to settle down */ 2576 udelay(50); 2577 } 2578 return 0; 2579 } 2580 2581 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2582 uint32_t vmid, 2583 uint32_t gds_base, uint32_t gds_size, 2584 uint32_t gws_base, uint32_t gws_size, 2585 uint32_t oa_base, uint32_t oa_size) 2586 { 2587 struct amdgpu_device *adev = ring->adev; 2588 2589 /* GDS Base */ 2590 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2591 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2592 gds_base); 2593 2594 /* GDS Size */ 2595 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2596 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2597 gds_size); 2598 2599 /* GWS */ 2600 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2601 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2602 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2603 2604 /* OA */ 2605 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2606 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2607 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2608 } 2609 2610 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2611 { 2612 struct amdgpu_device *adev = ip_block->adev; 2613 2614 switch (amdgpu_user_queue) { 2615 case -1: 2616 case 0: 2617 default: 2618 adev->gfx.disable_kq = false; 2619 adev->gfx.disable_uq = true; 2620 break; 2621 case 2: 2622 adev->gfx.disable_kq = true; 2623 adev->gfx.disable_uq = true; 2624 break; 2625 } 2626 2627 if (adev->gfx.disable_kq) 2628 adev->gfx.num_compute_rings = 0; 2629 else 2630 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2631 AMDGPU_MAX_COMPUTE_RINGS); 2632 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2633 gfx_v9_4_3_set_ring_funcs(adev); 2634 gfx_v9_4_3_set_irq_funcs(adev); 2635 gfx_v9_4_3_set_gds_init(adev); 2636 gfx_v9_4_3_set_rlc_funcs(adev); 2637 2638 /* init rlcg reg access ctrl */ 2639 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2640 2641 amdgpu_init_rlc_reg_funcs(adev); 2642 2643 return gfx_v9_4_3_init_microcode(adev); 2644 } 2645 2646 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2647 { 2648 struct amdgpu_device *adev = ip_block->adev; 2649 2650 if (adev->gfx.ras && 2651 adev->gfx.ras->enable_watchdog_timer) 2652 adev->gfx.ras->enable_watchdog_timer(adev); 2653 2654 gfx_v9_4_3_ptl_hw_init(adev); 2655 2656 return 0; 2657 } 2658 2659 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2660 bool enable, int xcc_id) 2661 { 2662 uint32_t def, data; 2663 2664 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2665 return; 2666 2667 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2668 regRLC_CGTT_MGCG_OVERRIDE); 2669 2670 if (enable) 2671 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2672 else 2673 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2674 2675 if (def != data) 2676 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2677 regRLC_CGTT_MGCG_OVERRIDE, data); 2678 2679 } 2680 2681 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2682 bool enable, int xcc_id) 2683 { 2684 uint32_t def, data; 2685 2686 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2687 return; 2688 2689 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2690 regRLC_CGTT_MGCG_OVERRIDE); 2691 2692 if (enable) 2693 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2694 else 2695 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2696 2697 if (def != data) 2698 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2699 regRLC_CGTT_MGCG_OVERRIDE, data); 2700 } 2701 2702 static void 2703 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2704 bool enable, int xcc_id) 2705 { 2706 uint32_t data, def; 2707 2708 /* It is disabled by HW by default */ 2709 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2710 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2711 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2712 2713 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2714 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2715 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2716 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2717 2718 if (def != data) 2719 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2720 2721 /* MGLS is a global flag to control all MGLS in GFX */ 2722 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2723 /* 2 - RLC memory Light sleep */ 2724 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2725 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2726 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2727 if (def != data) 2728 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2729 } 2730 /* 3 - CP memory Light sleep */ 2731 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2732 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2733 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2734 if (def != data) 2735 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2736 } 2737 } 2738 } else { 2739 /* 1 - MGCG_OVERRIDE */ 2740 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2741 2742 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2743 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2744 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2745 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2746 2747 if (def != data) 2748 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2749 2750 /* 2 - disable MGLS in RLC */ 2751 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2752 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2753 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2754 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2755 } 2756 2757 /* 3 - disable MGLS in CP */ 2758 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2759 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2760 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2761 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2762 } 2763 } 2764 2765 } 2766 2767 static void 2768 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2769 bool enable, int xcc_id) 2770 { 2771 uint32_t def, data; 2772 2773 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2774 2775 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2776 /* unset CGCG override */ 2777 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2778 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2779 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2780 else 2781 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2782 /* update CGCG and CGLS override bits */ 2783 if (def != data) 2784 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2785 2786 /* CGCG Hysteresis: 400us */ 2787 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2788 2789 data = (0x2710 2790 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2791 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2792 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2793 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2794 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2795 if (def != data) 2796 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2797 2798 /* set IDLE_POLL_COUNT(0x33450100)*/ 2799 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2800 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2801 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2802 if (def != data) 2803 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2804 } else { 2805 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2806 /* reset CGCG/CGLS bits */ 2807 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2808 /* disable cgcg and cgls in FSM */ 2809 if (def != data) 2810 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2811 } 2812 2813 } 2814 2815 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2816 bool enable, int xcc_id) 2817 { 2818 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2819 2820 if (enable) { 2821 /* FGCG */ 2822 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2823 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2824 2825 /* CGCG/CGLS should be enabled after MGCG/MGLS 2826 * === MGCG + MGLS === 2827 */ 2828 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2829 xcc_id); 2830 /* === CGCG + CGLS === */ 2831 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2832 xcc_id); 2833 } else { 2834 /* CGCG/CGLS should be disabled before MGCG/MGLS 2835 * === CGCG + CGLS === 2836 */ 2837 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2838 xcc_id); 2839 /* === MGCG + MGLS === */ 2840 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2841 xcc_id); 2842 2843 /* FGCG */ 2844 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2845 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2846 } 2847 2848 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2849 2850 return 0; 2851 } 2852 2853 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2854 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2855 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2856 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2857 .init = gfx_v9_4_3_rlc_init, 2858 .resume = gfx_v9_4_3_rlc_resume, 2859 .stop = gfx_v9_4_3_rlc_stop, 2860 .reset = gfx_v9_4_3_rlc_reset, 2861 .start = gfx_v9_4_3_rlc_start, 2862 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2863 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2864 }; 2865 2866 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2867 enum amd_powergating_state state) 2868 { 2869 return 0; 2870 } 2871 2872 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2873 enum amd_clockgating_state state) 2874 { 2875 struct amdgpu_device *adev = ip_block->adev; 2876 int i, num_xcc; 2877 2878 if (amdgpu_sriov_vf(adev)) 2879 return 0; 2880 2881 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2882 for (i = 0; i < num_xcc; i++) 2883 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2884 adev, state == AMD_CG_STATE_GATE, i); 2885 2886 return 0; 2887 } 2888 2889 static void gfx_v9_4_3_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 2890 { 2891 struct amdgpu_device *adev = ip_block->adev; 2892 int data; 2893 2894 if (amdgpu_sriov_vf(adev)) 2895 *flags = 0; 2896 2897 /* AMD_CG_SUPPORT_GFX_MGCG */ 2898 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2899 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2900 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2901 2902 /* AMD_CG_SUPPORT_GFX_CGCG */ 2903 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2904 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2905 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2906 2907 /* AMD_CG_SUPPORT_GFX_CGLS */ 2908 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2909 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2910 2911 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2912 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2913 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2914 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2915 2916 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2917 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2918 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2919 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2920 } 2921 2922 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2923 { 2924 struct amdgpu_device *adev = ring->adev; 2925 u32 ref_and_mask, reg_mem_engine; 2926 2927 if (!adev->gfx.funcs->get_hdp_flush_mask) { 2928 dev_err(adev->dev, "%s: gfx hdp flush is not supported.\n", __func__); 2929 return; 2930 } 2931 2932 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); 2933 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2934 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2935 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2936 ref_and_mask, ref_and_mask, 0x20); 2937 } 2938 2939 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2940 struct amdgpu_job *job, 2941 struct amdgpu_ib *ib, 2942 uint32_t flags) 2943 { 2944 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2945 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2946 2947 /* Currently, there is a high possibility to get wave ID mismatch 2948 * between ME and GDS, leading to a hw deadlock, because ME generates 2949 * different wave IDs than the GDS expects. This situation happens 2950 * randomly when at least 5 compute pipes use GDS ordered append. 2951 * The wave IDs generated by ME are also wrong after suspend/resume. 2952 * Those are probably bugs somewhere else in the kernel driver. 2953 * 2954 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2955 * GDS to 0 for this ring (me/pipe). 2956 */ 2957 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2958 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2959 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2960 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2961 } 2962 2963 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2964 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 2965 amdgpu_ring_write(ring, 2966 #ifdef __BIG_ENDIAN 2967 (2 << 0) | 2968 #endif 2969 lower_32_bits(ib->gpu_addr)); 2970 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2971 amdgpu_ring_write(ring, control); 2972 } 2973 2974 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2975 u64 seq, unsigned flags) 2976 { 2977 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2978 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2979 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2980 2981 /* RELEASE_MEM - flush caches, send int */ 2982 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2983 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2984 EOP_TC_NC_ACTION_EN) : 2985 (EOP_TCL1_ACTION_EN | 2986 EOP_TC_ACTION_EN | 2987 EOP_TC_WB_ACTION_EN | 2988 EOP_TC_MD_ACTION_EN)) | 2989 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2990 EVENT_INDEX(5))); 2991 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2992 2993 /* 2994 * the address should be Qword aligned if 64bit write, Dword 2995 * aligned if only send 32bit data low (discard data high) 2996 */ 2997 if (write64bit) 2998 WARN_ON(addr & 0x7); 2999 else 3000 WARN_ON(addr & 0x3); 3001 amdgpu_ring_write(ring, lower_32_bits(addr)); 3002 amdgpu_ring_write(ring, upper_32_bits(addr)); 3003 amdgpu_ring_write(ring, lower_32_bits(seq)); 3004 amdgpu_ring_write(ring, upper_32_bits(seq)); 3005 amdgpu_ring_write(ring, 0); 3006 } 3007 3008 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3009 { 3010 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 3011 uint32_t seq = ring->fence_drv.sync_seq; 3012 uint64_t addr = ring->fence_drv.gpu_addr; 3013 3014 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 3015 lower_32_bits(addr), upper_32_bits(addr), 3016 seq, 0xffffffff, 4); 3017 } 3018 3019 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 3020 unsigned vmid, uint64_t pd_addr) 3021 { 3022 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3023 } 3024 3025 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 3026 { 3027 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 3028 } 3029 3030 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 3031 { 3032 u64 wptr; 3033 3034 /* XXX check if swapping is necessary on BE */ 3035 if (ring->use_doorbell) 3036 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 3037 else 3038 BUG(); 3039 return wptr; 3040 } 3041 3042 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 3043 { 3044 struct amdgpu_device *adev = ring->adev; 3045 3046 /* XXX check if swapping is necessary on BE */ 3047 if (ring->use_doorbell) { 3048 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3049 WDOORBELL64(ring->doorbell_index, ring->wptr); 3050 } else { 3051 BUG(); /* only DOORBELL method supported on gfx9 now */ 3052 } 3053 } 3054 3055 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 3056 u64 seq, unsigned int flags) 3057 { 3058 struct amdgpu_device *adev = ring->adev; 3059 3060 /* write fence seq to the "addr" */ 3061 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3062 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3063 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 3064 amdgpu_ring_write(ring, lower_32_bits(addr)); 3065 amdgpu_ring_write(ring, upper_32_bits(addr)); 3066 amdgpu_ring_write(ring, lower_32_bits(seq)); 3067 3068 if (flags & AMDGPU_FENCE_FLAG_INT) { 3069 /* set register to trigger INT */ 3070 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3071 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3072 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 3073 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 3074 amdgpu_ring_write(ring, 0); 3075 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 3076 } 3077 } 3078 3079 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3080 uint32_t reg_val_offs) 3081 { 3082 struct amdgpu_device *adev = ring->adev; 3083 3084 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3085 3086 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3087 amdgpu_ring_write(ring, 0 | /* src: register*/ 3088 (5 << 8) | /* dst: memory */ 3089 (1 << 20)); /* write confirm */ 3090 amdgpu_ring_write(ring, reg); 3091 amdgpu_ring_write(ring, 0); 3092 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3093 reg_val_offs * 4)); 3094 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3095 reg_val_offs * 4)); 3096 } 3097 3098 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3099 uint32_t val) 3100 { 3101 uint32_t cmd = 0; 3102 3103 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3104 3105 switch (ring->funcs->type) { 3106 case AMDGPU_RING_TYPE_GFX: 3107 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3108 break; 3109 case AMDGPU_RING_TYPE_KIQ: 3110 cmd = (1 << 16); /* no inc addr */ 3111 break; 3112 default: 3113 cmd = WR_CONFIRM; 3114 break; 3115 } 3116 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3117 amdgpu_ring_write(ring, cmd); 3118 amdgpu_ring_write(ring, reg); 3119 amdgpu_ring_write(ring, 0); 3120 amdgpu_ring_write(ring, val); 3121 } 3122 3123 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3124 uint32_t val, uint32_t mask) 3125 { 3126 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3127 } 3128 3129 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3130 uint32_t reg0, uint32_t reg1, 3131 uint32_t ref, uint32_t mask) 3132 { 3133 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3134 ref, mask); 3135 } 3136 3137 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3138 unsigned vmid) 3139 { 3140 struct amdgpu_device *adev = ring->adev; 3141 uint32_t value = 0; 3142 3143 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3144 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3145 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3146 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3147 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3148 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3149 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3150 } 3151 3152 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3153 struct amdgpu_device *adev, int me, int pipe, 3154 enum amdgpu_interrupt_state state, int xcc_id) 3155 { 3156 u32 mec_int_cntl, mec_int_cntl_reg; 3157 3158 /* 3159 * amdgpu controls only the first MEC. That's why this function only 3160 * handles the setting of interrupts for this specific MEC. All other 3161 * pipes' interrupts are set by amdkfd. 3162 */ 3163 3164 if (me == 1) { 3165 switch (pipe) { 3166 case 0: 3167 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3168 break; 3169 case 1: 3170 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3171 break; 3172 case 2: 3173 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3174 break; 3175 case 3: 3176 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3177 break; 3178 default: 3179 DRM_DEBUG("invalid pipe %d\n", pipe); 3180 return; 3181 } 3182 } else { 3183 DRM_DEBUG("invalid me %d\n", me); 3184 return; 3185 } 3186 3187 switch (state) { 3188 case AMDGPU_IRQ_STATE_DISABLE: 3189 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3190 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3191 TIME_STAMP_INT_ENABLE, 0); 3192 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3193 break; 3194 case AMDGPU_IRQ_STATE_ENABLE: 3195 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3196 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3197 TIME_STAMP_INT_ENABLE, 1); 3198 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3199 break; 3200 default: 3201 break; 3202 } 3203 } 3204 3205 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3206 int xcc_id, int me, int pipe) 3207 { 3208 /* 3209 * amdgpu controls only the first MEC. That's why this function only 3210 * handles the setting of interrupts for this specific MEC. All other 3211 * pipes' interrupts are set by amdkfd. 3212 */ 3213 if (me != 1) 3214 return 0; 3215 3216 switch (pipe) { 3217 case 0: 3218 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3219 case 1: 3220 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3221 case 2: 3222 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3223 case 3: 3224 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3225 default: 3226 return 0; 3227 } 3228 } 3229 3230 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3231 struct amdgpu_irq_src *source, 3232 unsigned type, 3233 enum amdgpu_interrupt_state state) 3234 { 3235 u32 mec_int_cntl_reg, mec_int_cntl; 3236 int i, j, k, num_xcc; 3237 3238 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3239 switch (state) { 3240 case AMDGPU_IRQ_STATE_DISABLE: 3241 case AMDGPU_IRQ_STATE_ENABLE: 3242 for (i = 0; i < num_xcc; i++) { 3243 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3244 PRIV_REG_INT_ENABLE, 3245 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3246 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3247 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3248 /* MECs start at 1 */ 3249 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3250 3251 if (mec_int_cntl_reg) { 3252 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3253 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3254 PRIV_REG_INT_ENABLE, 3255 state == AMDGPU_IRQ_STATE_ENABLE ? 3256 1 : 0); 3257 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3258 } 3259 } 3260 } 3261 } 3262 break; 3263 default: 3264 break; 3265 } 3266 3267 return 0; 3268 } 3269 3270 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3271 struct amdgpu_irq_src *source, 3272 unsigned type, 3273 enum amdgpu_interrupt_state state) 3274 { 3275 u32 mec_int_cntl_reg, mec_int_cntl; 3276 int i, j, k, num_xcc; 3277 3278 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3279 switch (state) { 3280 case AMDGPU_IRQ_STATE_DISABLE: 3281 case AMDGPU_IRQ_STATE_ENABLE: 3282 for (i = 0; i < num_xcc; i++) { 3283 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3284 OPCODE_ERROR_INT_ENABLE, 3285 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3286 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3287 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3288 /* MECs start at 1 */ 3289 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3290 3291 if (mec_int_cntl_reg) { 3292 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3293 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3294 OPCODE_ERROR_INT_ENABLE, 3295 state == AMDGPU_IRQ_STATE_ENABLE ? 3296 1 : 0); 3297 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3298 } 3299 } 3300 } 3301 } 3302 break; 3303 default: 3304 break; 3305 } 3306 3307 return 0; 3308 } 3309 3310 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3311 struct amdgpu_irq_src *source, 3312 unsigned type, 3313 enum amdgpu_interrupt_state state) 3314 { 3315 int i, num_xcc; 3316 3317 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3318 switch (state) { 3319 case AMDGPU_IRQ_STATE_DISABLE: 3320 case AMDGPU_IRQ_STATE_ENABLE: 3321 for (i = 0; i < num_xcc; i++) 3322 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3323 PRIV_INSTR_INT_ENABLE, 3324 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3325 break; 3326 default: 3327 break; 3328 } 3329 3330 return 0; 3331 } 3332 3333 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3334 struct amdgpu_irq_src *src, 3335 unsigned type, 3336 enum amdgpu_interrupt_state state) 3337 { 3338 int i, num_xcc; 3339 3340 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3341 for (i = 0; i < num_xcc; i++) { 3342 switch (type) { 3343 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3344 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3345 adev, 1, 0, state, i); 3346 break; 3347 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3348 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3349 adev, 1, 1, state, i); 3350 break; 3351 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3352 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3353 adev, 1, 2, state, i); 3354 break; 3355 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3356 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3357 adev, 1, 3, state, i); 3358 break; 3359 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3360 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3361 adev, 2, 0, state, i); 3362 break; 3363 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3364 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3365 adev, 2, 1, state, i); 3366 break; 3367 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3368 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3369 adev, 2, 2, state, i); 3370 break; 3371 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3372 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3373 adev, 2, 3, state, i); 3374 break; 3375 default: 3376 break; 3377 } 3378 } 3379 3380 return 0; 3381 } 3382 3383 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3384 struct amdgpu_irq_src *source, 3385 struct amdgpu_iv_entry *entry) 3386 { 3387 int i, xcc_id; 3388 u8 me_id, pipe_id, queue_id; 3389 struct amdgpu_ring *ring; 3390 3391 DRM_DEBUG("IH: CP EOP\n"); 3392 me_id = (entry->ring_id & 0x0c) >> 2; 3393 pipe_id = (entry->ring_id & 0x03) >> 0; 3394 queue_id = (entry->ring_id & 0x70) >> 4; 3395 3396 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3397 3398 if (xcc_id == -EINVAL) 3399 return -EINVAL; 3400 3401 switch (me_id) { 3402 case 0: 3403 case 1: 3404 case 2: 3405 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3406 ring = &adev->gfx.compute_ring 3407 [i + 3408 xcc_id * adev->gfx.num_compute_rings]; 3409 /* Per-queue interrupt is supported for MEC starting from VI. 3410 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3411 */ 3412 3413 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3414 amdgpu_fence_process(ring); 3415 } 3416 break; 3417 } 3418 return 0; 3419 } 3420 3421 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3422 struct amdgpu_iv_entry *entry) 3423 { 3424 u8 me_id, pipe_id, queue_id; 3425 struct amdgpu_ring *ring; 3426 int i, xcc_id; 3427 3428 me_id = (entry->ring_id & 0x0c) >> 2; 3429 pipe_id = (entry->ring_id & 0x03) >> 0; 3430 queue_id = (entry->ring_id & 0x70) >> 4; 3431 3432 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3433 3434 if (xcc_id == -EINVAL) 3435 return; 3436 3437 switch (me_id) { 3438 case 0: 3439 case 1: 3440 case 2: 3441 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3442 ring = &adev->gfx.compute_ring 3443 [i + 3444 xcc_id * adev->gfx.num_compute_rings]; 3445 if (ring->me == me_id && ring->pipe == pipe_id && 3446 ring->queue == queue_id) 3447 drm_sched_fault(&ring->sched); 3448 } 3449 break; 3450 } 3451 } 3452 3453 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3454 struct amdgpu_irq_src *source, 3455 struct amdgpu_iv_entry *entry) 3456 { 3457 DRM_ERROR("Illegal register access in command stream\n"); 3458 gfx_v9_4_3_fault(adev, entry); 3459 return 0; 3460 } 3461 3462 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3463 struct amdgpu_irq_src *source, 3464 struct amdgpu_iv_entry *entry) 3465 { 3466 DRM_ERROR("Illegal opcode in command stream\n"); 3467 gfx_v9_4_3_fault(adev, entry); 3468 return 0; 3469 } 3470 3471 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3472 struct amdgpu_irq_src *source, 3473 struct amdgpu_iv_entry *entry) 3474 { 3475 DRM_ERROR("Illegal instruction in command stream\n"); 3476 gfx_v9_4_3_fault(adev, entry); 3477 return 0; 3478 } 3479 3480 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3481 { 3482 const unsigned int cp_coher_cntl = 3483 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3484 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3485 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3486 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3487 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3488 3489 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3490 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3491 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3492 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3493 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3494 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3495 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3496 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3497 } 3498 3499 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3500 uint32_t pipe, bool enable) 3501 { 3502 struct amdgpu_device *adev = ring->adev; 3503 uint32_t val; 3504 uint32_t wcl_cs_reg; 3505 3506 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3507 val = enable ? 0x1 : 0x7f; 3508 3509 switch (pipe) { 3510 case 0: 3511 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3512 break; 3513 case 1: 3514 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3515 break; 3516 case 2: 3517 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3518 break; 3519 case 3: 3520 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3521 break; 3522 default: 3523 DRM_DEBUG("invalid pipe %d\n", pipe); 3524 return; 3525 } 3526 3527 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3528 3529 } 3530 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3531 { 3532 struct amdgpu_device *adev = ring->adev; 3533 uint32_t val; 3534 int i; 3535 3536 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3537 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3538 * around 25% of gpu resources. 3539 */ 3540 val = enable ? 0x1f : 0x07ffffff; 3541 amdgpu_ring_emit_wreg(ring, 3542 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3543 val); 3544 3545 /* Restrict waves for normal/low priority compute queues as well 3546 * to get best QoS for high priority compute jobs. 3547 * 3548 * amdgpu controls only 1st ME(0-3 CS pipes). 3549 */ 3550 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3551 if (i != ring->pipe) 3552 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3553 3554 } 3555 } 3556 3557 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3558 uint32_t pipe, uint32_t queue, 3559 uint32_t xcc_id) 3560 { 3561 int i, r; 3562 /* make sure dequeue is complete*/ 3563 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3564 mutex_lock(&adev->srbm_mutex); 3565 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3566 for (i = 0; i < adev->usec_timeout; i++) { 3567 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3568 break; 3569 udelay(1); 3570 } 3571 if (i >= adev->usec_timeout) 3572 r = -ETIMEDOUT; 3573 else 3574 r = 0; 3575 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3576 mutex_unlock(&adev->srbm_mutex); 3577 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3578 3579 return r; 3580 3581 } 3582 3583 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3584 { 3585 if (!!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3586 return true; 3587 else 3588 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3589 3590 return false; 3591 } 3592 3593 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3594 { 3595 struct amdgpu_device *adev = ring->adev; 3596 uint32_t reset_pipe, clean_pipe; 3597 int r; 3598 3599 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3600 return -EINVAL; 3601 3602 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3603 mutex_lock(&adev->srbm_mutex); 3604 3605 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3606 clean_pipe = reset_pipe; 3607 3608 if (ring->me == 1) { 3609 switch (ring->pipe) { 3610 case 0: 3611 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3612 MEC_ME1_PIPE0_RESET, 1); 3613 break; 3614 case 1: 3615 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3616 MEC_ME1_PIPE1_RESET, 1); 3617 break; 3618 case 2: 3619 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3620 MEC_ME1_PIPE2_RESET, 1); 3621 break; 3622 case 3: 3623 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3624 MEC_ME1_PIPE3_RESET, 1); 3625 break; 3626 default: 3627 break; 3628 } 3629 } else { 3630 if (ring->pipe) 3631 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3632 MEC_ME2_PIPE1_RESET, 1); 3633 else 3634 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3635 MEC_ME2_PIPE0_RESET, 1); 3636 } 3637 3638 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3639 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3640 mutex_unlock(&adev->srbm_mutex); 3641 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3642 3643 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3644 return r; 3645 } 3646 3647 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3648 unsigned int vmid, 3649 struct amdgpu_fence *timedout_fence) 3650 { 3651 struct amdgpu_device *adev = ring->adev; 3652 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3653 struct amdgpu_ring *kiq_ring = &kiq->ring; 3654 int reset_mode = AMDGPU_RESET_TYPE_PER_QUEUE; 3655 unsigned long flags; 3656 int r; 3657 3658 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3659 return -EINVAL; 3660 3661 amdgpu_ring_reset_helper_begin(ring, timedout_fence); 3662 3663 spin_lock_irqsave(&kiq->ring_lock, flags); 3664 3665 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3666 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3667 return -ENOMEM; 3668 } 3669 3670 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3671 0, 0); 3672 amdgpu_ring_commit(kiq_ring); 3673 3674 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3675 3676 r = amdgpu_ring_test_ring(kiq_ring); 3677 if (r) { 3678 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3679 ring->name); 3680 goto pipe_reset; 3681 } 3682 3683 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3684 if (r) 3685 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3686 3687 pipe_reset: 3688 if (r) { 3689 if (!(adev->gfx.compute_supported_reset & AMDGPU_RESET_TYPE_PER_PIPE)) 3690 return -EOPNOTSUPP; 3691 r = gfx_v9_4_3_reset_hw_pipe(ring); 3692 reset_mode = AMDGPU_RESET_TYPE_PER_PIPE; 3693 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3694 r ? "failed" : "successfully"); 3695 if (r) 3696 return r; 3697 } 3698 3699 gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3700 3701 spin_lock_irqsave(&kiq->ring_lock, flags); 3702 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3703 if (r) { 3704 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3705 return -ENOMEM; 3706 } 3707 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3708 amdgpu_ring_commit(kiq_ring); 3709 r = amdgpu_ring_test_ring(kiq_ring); 3710 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3711 if (r) { 3712 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) 3713 goto pipe_reset; 3714 3715 dev_err(adev->dev, "fail to remap queue\n"); 3716 return r; 3717 } 3718 3719 if (reset_mode == AMDGPU_RESET_TYPE_PER_QUEUE) { 3720 r = amdgpu_ring_test_ring(ring); 3721 if (r) 3722 goto pipe_reset; 3723 } 3724 3725 3726 return amdgpu_ring_reset_helper_end(ring, timedout_fence); 3727 } 3728 3729 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 3730 void *ras_error_status, int xcc_id) 3731 { 3732 uint32_t i; 3733 uint32_t data; 3734 3735 if (amdgpu_sriov_vf(adev)) 3736 return; 3737 3738 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 3739 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 3740 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 3741 3742 if (amdgpu_watchdog_timer.timeout_fatal_disable && 3743 (amdgpu_watchdog_timer.period < 1 || 3744 amdgpu_watchdog_timer.period > 0x23)) { 3745 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 3746 amdgpu_watchdog_timer.period = 0x23; 3747 } 3748 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 3749 amdgpu_watchdog_timer.period); 3750 3751 mutex_lock(&adev->grbm_idx_mutex); 3752 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3753 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 3754 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 3755 } 3756 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3757 xcc_id); 3758 mutex_unlock(&adev->grbm_idx_mutex); 3759 } 3760 3761 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 3762 { 3763 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 3764 } 3765 3766 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 3767 { 3768 /* Header itself is a NOP packet */ 3769 if (num_nop == 1) { 3770 amdgpu_ring_write(ring, ring->funcs->nop); 3771 return; 3772 } 3773 3774 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 3775 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 3776 3777 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 3778 amdgpu_ring_insert_nop(ring, num_nop - 1); 3779 } 3780 3781 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 3782 { 3783 struct amdgpu_device *adev = ip_block->adev; 3784 uint32_t i, j, k; 3785 uint32_t xcc_id, xcc_offset, inst_offset; 3786 uint32_t num_xcc, reg, num_inst; 3787 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 3788 3789 if (!adev->gfx.ip_dump_core) 3790 return; 3791 3792 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3793 drm_printf(p, "Number of Instances:%d\n", num_xcc); 3794 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 3795 xcc_offset = xcc_id * reg_count; 3796 drm_printf(p, "\nInstance id:%d\n", xcc_id); 3797 for (i = 0; i < reg_count; i++) 3798 drm_printf(p, "%-50s \t 0x%08x\n", 3799 gc_reg_list_9_4_3[i].reg_name, 3800 adev->gfx.ip_dump_core[xcc_offset + i]); 3801 } 3802 3803 /* print compute queue registers for all instances */ 3804 if (!adev->gfx.ip_dump_compute_queues) 3805 return; 3806 3807 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 3808 adev->gfx.mec.num_queue_per_pipe; 3809 3810 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 3811 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 3812 num_xcc, 3813 adev->gfx.mec.num_mec, 3814 adev->gfx.mec.num_pipe_per_mec, 3815 adev->gfx.mec.num_queue_per_pipe); 3816 3817 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 3818 xcc_offset = xcc_id * reg_count * num_inst; 3819 inst_offset = 0; 3820 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 3821 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 3822 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 3823 drm_printf(p, 3824 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 3825 xcc_id, i, j, k); 3826 for (reg = 0; reg < reg_count; reg++) { 3827 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 3828 regCP_MEC_ME1_HEADER_DUMP) 3829 drm_printf(p, 3830 "%-50s \t 0x%08x\n", 3831 "regCP_MEC_ME2_HEADER_DUMP", 3832 adev->gfx.ip_dump_compute_queues 3833 [xcc_offset + inst_offset + 3834 reg]); 3835 else 3836 drm_printf(p, 3837 "%-50s \t 0x%08x\n", 3838 gc_cp_reg_list_9_4_3[reg].reg_name, 3839 adev->gfx.ip_dump_compute_queues 3840 [xcc_offset + inst_offset + 3841 reg]); 3842 } 3843 inst_offset += reg_count; 3844 } 3845 } 3846 } 3847 } 3848 } 3849 3850 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 3851 { 3852 struct amdgpu_device *adev = ip_block->adev; 3853 uint32_t i, j, k; 3854 uint32_t num_xcc, reg, num_inst; 3855 uint32_t xcc_id, xcc_offset, inst_offset; 3856 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 3857 3858 if (!adev->gfx.ip_dump_core) 3859 return; 3860 3861 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3862 3863 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 3864 xcc_offset = xcc_id * reg_count; 3865 for (i = 0; i < reg_count; i++) 3866 adev->gfx.ip_dump_core[xcc_offset + i] = 3867 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 3868 GET_INST(GC, xcc_id))); 3869 } 3870 3871 /* dump compute queue registers for all instances */ 3872 if (!adev->gfx.ip_dump_compute_queues) 3873 return; 3874 3875 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 3876 adev->gfx.mec.num_queue_per_pipe; 3877 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 3878 mutex_lock(&adev->srbm_mutex); 3879 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 3880 xcc_offset = xcc_id * reg_count * num_inst; 3881 inst_offset = 0; 3882 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 3883 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 3884 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 3885 /* ME0 is for GFX so start from 1 for CP */ 3886 soc15_grbm_select(adev, 1 + i, j, k, 0, 3887 GET_INST(GC, xcc_id)); 3888 3889 for (reg = 0; reg < reg_count; reg++) { 3890 if (i && gc_cp_reg_list_9_4_3[reg].reg_offset == 3891 regCP_MEC_ME1_HEADER_DUMP) 3892 adev->gfx.ip_dump_compute_queues 3893 [xcc_offset + 3894 inst_offset + reg] = 3895 RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), 3896 regCP_MEC_ME2_HEADER_DUMP)); 3897 else 3898 adev->gfx.ip_dump_compute_queues 3899 [xcc_offset + 3900 inst_offset + reg] = 3901 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 3902 gc_cp_reg_list_9_4_3[reg], 3903 GET_INST(GC, xcc_id))); 3904 } 3905 inst_offset += reg_count; 3906 } 3907 } 3908 } 3909 } 3910 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 3911 mutex_unlock(&adev->srbm_mutex); 3912 } 3913 3914 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 3915 { 3916 /* Emit the cleaner shader */ 3917 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 3918 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 3919 } 3920 3921 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 3922 .name = "gfx_v9_4_3", 3923 .early_init = gfx_v9_4_3_early_init, 3924 .late_init = gfx_v9_4_3_late_init, 3925 .sw_init = gfx_v9_4_3_sw_init, 3926 .sw_fini = gfx_v9_4_3_sw_fini, 3927 .hw_init = gfx_v9_4_3_hw_init, 3928 .hw_fini = gfx_v9_4_3_hw_fini, 3929 .suspend = gfx_v9_4_3_suspend, 3930 .resume = gfx_v9_4_3_resume, 3931 .is_idle = gfx_v9_4_3_is_idle, 3932 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 3933 .soft_reset = gfx_v9_4_3_soft_reset, 3934 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 3935 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 3936 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 3937 .dump_ip_state = gfx_v9_4_3_ip_dump, 3938 .print_ip_state = gfx_v9_4_3_ip_print, 3939 }; 3940 3941 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 3942 .type = AMDGPU_RING_TYPE_COMPUTE, 3943 .align_mask = 0xff, 3944 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3945 .support_64bit_ptrs = true, 3946 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 3947 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 3948 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 3949 .emit_frame_size = 3950 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 3951 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 3952 5 + /* hdp invalidate */ 3953 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 3954 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3955 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 3956 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 3957 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 3958 7 + /* gfx_v9_4_3_emit_mem_sync */ 3959 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 3960 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 3961 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 3962 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 3963 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 3964 .emit_fence = gfx_v9_4_3_ring_emit_fence, 3965 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 3966 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 3967 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 3968 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 3969 .test_ring = gfx_v9_4_3_ring_test_ring, 3970 .test_ib = gfx_v9_4_3_ring_test_ib, 3971 .insert_nop = gfx_v9_4_3_ring_insert_nop, 3972 .pad_ib = amdgpu_ring_generic_pad_ib, 3973 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 3974 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 3975 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 3976 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 3977 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 3978 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 3979 .reset = gfx_v9_4_3_reset_kcq, 3980 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 3981 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 3982 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 3983 }; 3984 3985 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 3986 .type = AMDGPU_RING_TYPE_KIQ, 3987 .align_mask = 0xff, 3988 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3989 .support_64bit_ptrs = true, 3990 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 3991 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 3992 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 3993 .emit_frame_size = 3994 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 3995 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 3996 5 + /* hdp invalidate */ 3997 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 3998 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3999 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4000 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4001 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4002 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4003 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4004 .test_ring = gfx_v9_4_3_ring_test_ring, 4005 .insert_nop = amdgpu_ring_insert_nop, 4006 .pad_ib = amdgpu_ring_generic_pad_ib, 4007 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4008 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4009 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4010 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4011 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4012 }; 4013 4014 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4015 { 4016 int i, j, num_xcc; 4017 4018 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4019 for (i = 0; i < num_xcc; i++) { 4020 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4021 4022 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4023 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4024 = &gfx_v9_4_3_ring_funcs_compute; 4025 } 4026 } 4027 4028 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4029 .set = gfx_v9_4_3_set_eop_interrupt_state, 4030 .process = gfx_v9_4_3_eop_irq, 4031 }; 4032 4033 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4034 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4035 .process = gfx_v9_4_3_priv_reg_irq, 4036 }; 4037 4038 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4039 .set = gfx_v9_4_3_set_bad_op_fault_state, 4040 .process = gfx_v9_4_3_bad_op_irq, 4041 }; 4042 4043 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4044 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4045 .process = gfx_v9_4_3_priv_inst_irq, 4046 }; 4047 4048 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4049 { 4050 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4051 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4052 4053 adev->gfx.priv_reg_irq.num_types = 1; 4054 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4055 4056 adev->gfx.bad_op_irq.num_types = 1; 4057 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4058 4059 adev->gfx.priv_inst_irq.num_types = 1; 4060 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4061 } 4062 4063 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4064 { 4065 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4066 } 4067 4068 4069 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4070 { 4071 /* 9.4.3 variants removed all the GDS internal memory, 4072 * only support GWS opcode in kernel, like barrier 4073 * semaphore.etc */ 4074 4075 /* init asic gds info */ 4076 adev->gds.gds_size = 0; 4077 adev->gds.gds_compute_max_wave_id = 0; 4078 adev->gds.gws_size = 64; 4079 adev->gds.oa_size = 16; 4080 } 4081 4082 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4083 u32 bitmap, int xcc_id) 4084 { 4085 u32 data; 4086 4087 if (!bitmap) 4088 return; 4089 4090 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4091 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4092 4093 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4094 } 4095 4096 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4097 { 4098 u32 data, mask; 4099 4100 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4101 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4102 4103 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4104 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4105 4106 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4107 4108 return (~data) & mask; 4109 } 4110 4111 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4112 struct amdgpu_cu_info *cu_info) 4113 { 4114 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4115 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4116 unsigned disable_masks[4 * 4]; 4117 bool is_symmetric_cus; 4118 4119 if (!adev || !cu_info) 4120 return -EINVAL; 4121 4122 /* 4123 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4124 */ 4125 if (adev->gfx.config.max_shader_engines * 4126 adev->gfx.config.max_sh_per_se > 16) 4127 return -EINVAL; 4128 4129 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 4130 adev->gfx.config.max_shader_engines, 4131 adev->gfx.config.max_sh_per_se); 4132 4133 mutex_lock(&adev->grbm_idx_mutex); 4134 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4135 is_symmetric_cus = true; 4136 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4137 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4138 mask = 1; 4139 ao_bitmap = 0; 4140 counter = 0; 4141 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4142 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4143 adev, 4144 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4145 xcc_id); 4146 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4147 4148 cu_info->bitmap[xcc_id][i][j] = bitmap; 4149 4150 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4151 if (bitmap & mask) { 4152 if (counter < adev->gfx.config.max_cu_per_sh) 4153 ao_bitmap |= mask; 4154 counter++; 4155 } 4156 mask <<= 1; 4157 } 4158 active_cu_number += counter; 4159 if (i < 2 && j < 2) 4160 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4161 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4162 } 4163 if (i && is_symmetric_cus && prev_counter != counter) 4164 is_symmetric_cus = false; 4165 prev_counter = counter; 4166 } 4167 if (is_symmetric_cus) { 4168 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4169 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4170 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4171 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4172 } 4173 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4174 xcc_id); 4175 } 4176 mutex_unlock(&adev->grbm_idx_mutex); 4177 4178 cu_info->number = active_cu_number; 4179 cu_info->ao_cu_mask = ao_cu_mask; 4180 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4181 4182 return 0; 4183 } 4184 4185 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4186 .type = AMD_IP_BLOCK_TYPE_GFX, 4187 .major = 9, 4188 .minor = 4, 4189 .rev = 3, 4190 .funcs = &gfx_v9_4_3_ip_funcs, 4191 }; 4192 4193 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4194 { 4195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4196 uint32_t tmp_mask; 4197 int i, r; 4198 4199 /* TODO : Initialize golden regs */ 4200 /* gfx_v9_4_3_init_golden_registers(adev); */ 4201 4202 tmp_mask = inst_mask; 4203 for_each_inst(i, tmp_mask) 4204 gfx_v9_4_3_xcc_constants_init(adev, i); 4205 4206 if (!amdgpu_sriov_vf(adev)) { 4207 tmp_mask = inst_mask; 4208 for_each_inst(i, tmp_mask) { 4209 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4210 if (r) 4211 return r; 4212 } 4213 } 4214 4215 tmp_mask = inst_mask; 4216 for_each_inst(i, tmp_mask) { 4217 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4218 if (r) 4219 return r; 4220 } 4221 4222 return 0; 4223 } 4224 4225 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4226 { 4227 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4228 int i; 4229 4230 for_each_inst(i, inst_mask) 4231 gfx_v9_4_3_xcc_fini(adev, i); 4232 4233 return 0; 4234 } 4235 4236 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4237 .suspend = &gfx_v9_4_3_xcp_suspend, 4238 .resume = &gfx_v9_4_3_xcp_resume 4239 }; 4240 4241 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4242 .ras_block = { 4243 .hw_ops = NULL, 4244 }, 4245 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4246 }; 4247