1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "gfx_v9_4_3_cleaner_shader.h" 41 #include "amdgpu_xcp.h" 42 #include "amdgpu_aca.h" 43 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 45 MODULE_FIRMWARE("amdgpu/gc_9_4_4_mec.bin"); 46 MODULE_FIRMWARE("amdgpu/gc_9_5_0_mec.bin"); 47 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 48 MODULE_FIRMWARE("amdgpu/gc_9_4_4_rlc.bin"); 49 MODULE_FIRMWARE("amdgpu/gc_9_5_0_rlc.bin"); 50 MODULE_FIRMWARE("amdgpu/gc_9_4_3_sjt_mec.bin"); 51 MODULE_FIRMWARE("amdgpu/gc_9_4_4_sjt_mec.bin"); 52 53 #define GFX9_MEC_HPD_SIZE 4096 54 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 55 56 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 57 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 58 59 #define XCC_REG_RANGE_0_LOW 0x2000 /* XCC gfxdec0 lower Bound */ 60 #define XCC_REG_RANGE_0_HIGH 0x3400 /* XCC gfxdec0 upper Bound */ 61 #define XCC_REG_RANGE_1_LOW 0xA000 /* XCC gfxdec1 lower Bound */ 62 #define XCC_REG_RANGE_1_HIGH 0x10000 /* XCC gfxdec1 upper Bound */ 63 64 #define NORMALIZE_XCC_REG_OFFSET(offset) \ 65 (offset & 0xFFFF) 66 67 static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { 68 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 69 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 70 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 71 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 72 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 73 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 74 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 75 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 76 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 77 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 78 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 79 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 80 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 81 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 82 SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), 83 SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), 84 SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), 85 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 86 SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), 87 SOC15_REG_ENTRY_STR(GC, 0, regSQC_ICACHE_UTCL1_STATUS), 88 SOC15_REG_ENTRY_STR(GC, 0, regSQ_UTCL1_STATUS), 89 SOC15_REG_ENTRY_STR(GC, 0, regTCP_UTCL1_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 91 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL), 92 SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 98 SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), 99 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), 100 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_MESSAGE), 101 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_1), 102 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_ARGUMENT_2), 103 SOC15_REG_ENTRY_STR(GC, 0, regSMU_RLC_RESPONSE), 104 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SAFE_MODE), 105 SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_SAFE_MODE), 106 SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), 107 SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), 108 /* cp header registers */ 109 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 110 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP), 111 /* SE status registers */ 112 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 113 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 114 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2), 115 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) 116 }; 117 118 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { 119 /* compute queue registers */ 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 129 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 138 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 139 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 140 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 141 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 142 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 143 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 144 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), 157 }; 158 159 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 160 161 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 162 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 163 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 164 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 165 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 166 struct amdgpu_cu_info *cu_info); 167 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 168 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 169 170 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 171 uint64_t queue_mask) 172 { 173 struct amdgpu_device *adev = kiq_ring->adev; 174 u64 shader_mc_addr; 175 176 /* Cleaner shader MC address */ 177 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; 178 179 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 180 amdgpu_ring_write(kiq_ring, 181 PACKET3_SET_RESOURCES_VMID_MASK(0) | 182 /* vmid_mask:0* queue_type:0 (KIQ) */ 183 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 184 amdgpu_ring_write(kiq_ring, 185 lower_32_bits(queue_mask)); /* queue mask lo */ 186 amdgpu_ring_write(kiq_ring, 187 upper_32_bits(queue_mask)); /* queue mask hi */ 188 amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ 189 amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ 190 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 191 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 192 } 193 194 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 195 struct amdgpu_ring *ring) 196 { 197 struct amdgpu_device *adev = kiq_ring->adev; 198 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 199 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 200 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 201 202 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 203 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 204 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 205 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 206 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 207 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 208 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 209 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 210 /*queue_type: normal compute queue */ 211 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 212 /* alloc format: all_on_one_pipe */ 213 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 214 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 215 /* num_queues: must be 1 */ 216 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 217 amdgpu_ring_write(kiq_ring, 218 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 219 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 220 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 221 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 222 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 223 } 224 225 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 226 struct amdgpu_ring *ring, 227 enum amdgpu_unmap_queues_action action, 228 u64 gpu_addr, u64 seq) 229 { 230 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 231 232 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 233 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 234 PACKET3_UNMAP_QUEUES_ACTION(action) | 235 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 236 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 237 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 238 amdgpu_ring_write(kiq_ring, 239 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 240 241 if (action == PREEMPT_QUEUES_NO_UNMAP) { 242 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 243 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 244 amdgpu_ring_write(kiq_ring, seq); 245 } else { 246 amdgpu_ring_write(kiq_ring, 0); 247 amdgpu_ring_write(kiq_ring, 0); 248 amdgpu_ring_write(kiq_ring, 0); 249 } 250 } 251 252 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 253 struct amdgpu_ring *ring, 254 u64 addr, 255 u64 seq) 256 { 257 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 258 259 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 260 amdgpu_ring_write(kiq_ring, 261 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 262 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 263 PACKET3_QUERY_STATUS_COMMAND(2)); 264 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 265 amdgpu_ring_write(kiq_ring, 266 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 267 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 268 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 269 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 270 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 271 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 272 } 273 274 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 275 uint16_t pasid, uint32_t flush_type, 276 bool all_hub) 277 { 278 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 279 amdgpu_ring_write(kiq_ring, 280 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 281 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 282 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 283 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 284 } 285 286 static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, 287 uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, 288 uint32_t xcc_id, uint32_t vmid) 289 { 290 struct amdgpu_device *adev = kiq_ring->adev; 291 unsigned i; 292 293 /* enter save mode */ 294 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 295 mutex_lock(&adev->srbm_mutex); 296 soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); 297 298 if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { 299 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); 300 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); 301 /* wait till dequeue take effects */ 302 for (i = 0; i < adev->usec_timeout; i++) { 303 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 304 break; 305 udelay(1); 306 } 307 if (i >= adev->usec_timeout) 308 dev_err(adev->dev, "fail to wait on hqd deactive\n"); 309 } else { 310 dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); 311 } 312 313 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 314 mutex_unlock(&adev->srbm_mutex); 315 /* exit safe mode */ 316 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 317 } 318 319 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 320 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 321 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 322 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 323 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 324 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 325 .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, 326 .set_resources_size = 8, 327 .map_queues_size = 7, 328 .unmap_queues_size = 6, 329 .query_status_size = 7, 330 .invalidate_tlbs_size = 2, 331 }; 332 333 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 334 { 335 int i, num_xcc; 336 337 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 338 for (i = 0; i < num_xcc; i++) 339 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 340 } 341 342 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 343 { 344 int i, num_xcc, dev_inst; 345 346 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 347 for (i = 0; i < num_xcc; i++) { 348 dev_inst = GET_INST(GC, i); 349 350 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 351 GOLDEN_GB_ADDR_CONFIG); 352 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0)) { 353 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, SPARE, 0x1); 354 } else { 355 /* Golden settings applied by driver for ASIC with rev_id 0 */ 356 if (adev->rev_id == 0) { 357 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 358 REDUCE_FIFO_DEPTH_BY_2, 2); 359 } else { 360 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 361 SPARE, 0x1); 362 } 363 } 364 } 365 } 366 367 static uint32_t gfx_v9_4_3_normalize_xcc_reg_offset(uint32_t reg) 368 { 369 uint32_t normalized_reg = NORMALIZE_XCC_REG_OFFSET(reg); 370 371 /* If it is an XCC reg, normalize the reg to keep 372 lower 16 bits in local xcc */ 373 374 if (((normalized_reg >= XCC_REG_RANGE_0_LOW) && (normalized_reg < XCC_REG_RANGE_0_HIGH)) || 375 ((normalized_reg >= XCC_REG_RANGE_1_LOW) && (normalized_reg < XCC_REG_RANGE_1_HIGH))) 376 return normalized_reg; 377 else 378 return reg; 379 } 380 381 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 382 bool wc, uint32_t reg, uint32_t val) 383 { 384 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 385 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 386 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 387 WRITE_DATA_DST_SEL(0) | 388 (wc ? WR_CONFIRM : 0)); 389 amdgpu_ring_write(ring, reg); 390 amdgpu_ring_write(ring, 0); 391 amdgpu_ring_write(ring, val); 392 } 393 394 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 395 int mem_space, int opt, uint32_t addr0, 396 uint32_t addr1, uint32_t ref, uint32_t mask, 397 uint32_t inv) 398 { 399 /* Only do the normalization on regspace */ 400 if (mem_space == 0) { 401 addr0 = gfx_v9_4_3_normalize_xcc_reg_offset(addr0); 402 addr1 = gfx_v9_4_3_normalize_xcc_reg_offset(addr1); 403 } 404 405 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 406 amdgpu_ring_write(ring, 407 /* memory (1) or register (0) */ 408 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 409 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 410 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 411 WAIT_REG_MEM_ENGINE(eng_sel))); 412 413 if (mem_space) 414 BUG_ON(addr0 & 0x3); /* Dword align */ 415 amdgpu_ring_write(ring, addr0); 416 amdgpu_ring_write(ring, addr1); 417 amdgpu_ring_write(ring, ref); 418 amdgpu_ring_write(ring, mask); 419 amdgpu_ring_write(ring, inv); /* poll interval */ 420 } 421 422 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 423 { 424 uint32_t scratch_reg0_offset, xcc_offset; 425 struct amdgpu_device *adev = ring->adev; 426 uint32_t tmp = 0; 427 unsigned i; 428 int r; 429 430 /* Use register offset which is local to XCC in the packet */ 431 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 432 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 433 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 434 tmp = RREG32(scratch_reg0_offset); 435 436 r = amdgpu_ring_alloc(ring, 3); 437 if (r) 438 return r; 439 440 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 441 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 442 amdgpu_ring_write(ring, 0xDEADBEEF); 443 amdgpu_ring_commit(ring); 444 445 for (i = 0; i < adev->usec_timeout; i++) { 446 tmp = RREG32(scratch_reg0_offset); 447 if (tmp == 0xDEADBEEF) 448 break; 449 udelay(1); 450 } 451 452 if (i >= adev->usec_timeout) 453 r = -ETIMEDOUT; 454 return r; 455 } 456 457 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 458 { 459 struct amdgpu_device *adev = ring->adev; 460 struct amdgpu_ib ib; 461 struct dma_fence *f = NULL; 462 463 unsigned index; 464 uint64_t gpu_addr; 465 uint32_t tmp; 466 long r; 467 468 r = amdgpu_device_wb_get(adev, &index); 469 if (r) 470 return r; 471 472 gpu_addr = adev->wb.gpu_addr + (index * 4); 473 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 474 memset(&ib, 0, sizeof(ib)); 475 476 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 477 if (r) 478 goto err1; 479 480 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 481 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 482 ib.ptr[2] = lower_32_bits(gpu_addr); 483 ib.ptr[3] = upper_32_bits(gpu_addr); 484 ib.ptr[4] = 0xDEADBEEF; 485 ib.length_dw = 5; 486 487 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 488 if (r) 489 goto err2; 490 491 r = dma_fence_wait_timeout(f, false, timeout); 492 if (r == 0) { 493 r = -ETIMEDOUT; 494 goto err2; 495 } else if (r < 0) { 496 goto err2; 497 } 498 499 tmp = adev->wb.wb[index]; 500 if (tmp == 0xDEADBEEF) 501 r = 0; 502 else 503 r = -EINVAL; 504 505 err2: 506 amdgpu_ib_free(&ib, NULL); 507 dma_fence_put(f); 508 err1: 509 amdgpu_device_wb_free(adev, index); 510 return r; 511 } 512 513 514 /* This value might differs per partition */ 515 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 516 { 517 uint64_t clock; 518 519 mutex_lock(&adev->gfx.gpu_clock_mutex); 520 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 521 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 522 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 523 mutex_unlock(&adev->gfx.gpu_clock_mutex); 524 525 return clock; 526 } 527 528 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 529 { 530 amdgpu_ucode_release(&adev->gfx.pfp_fw); 531 amdgpu_ucode_release(&adev->gfx.me_fw); 532 amdgpu_ucode_release(&adev->gfx.ce_fw); 533 amdgpu_ucode_release(&adev->gfx.rlc_fw); 534 amdgpu_ucode_release(&adev->gfx.mec_fw); 535 amdgpu_ucode_release(&adev->gfx.mec2_fw); 536 537 kfree(adev->gfx.rlc.register_list_format); 538 } 539 540 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 541 const char *chip_name) 542 { 543 int err; 544 const struct rlc_firmware_header_v2_0 *rlc_hdr; 545 uint16_t version_major; 546 uint16_t version_minor; 547 548 549 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 550 AMDGPU_UCODE_REQUIRED, 551 "amdgpu/%s_rlc.bin", chip_name); 552 if (err) 553 goto out; 554 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 555 556 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 557 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 558 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 559 out: 560 if (err) 561 amdgpu_ucode_release(&adev->gfx.rlc_fw); 562 563 return err; 564 } 565 566 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 567 { 568 return true; 569 } 570 571 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 572 { 573 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 574 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 575 } 576 577 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 578 const char *chip_name) 579 { 580 int err; 581 582 if (amdgpu_sriov_vf(adev)) { 583 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 584 AMDGPU_UCODE_REQUIRED, 585 "amdgpu/%s_sjt_mec.bin", chip_name); 586 587 if (err) 588 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 589 AMDGPU_UCODE_REQUIRED, 590 "amdgpu/%s_mec.bin", chip_name); 591 } else 592 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 593 AMDGPU_UCODE_REQUIRED, 594 "amdgpu/%s_mec.bin", chip_name); 595 if (err) 596 goto out; 597 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 598 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 599 600 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 601 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 602 603 gfx_v9_4_3_check_if_need_gfxoff(adev); 604 605 out: 606 if (err) 607 amdgpu_ucode_release(&adev->gfx.mec_fw); 608 return err; 609 } 610 611 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 612 { 613 char ucode_prefix[15]; 614 int r; 615 616 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 617 618 r = gfx_v9_4_3_init_rlc_microcode(adev, ucode_prefix); 619 if (r) 620 return r; 621 622 r = gfx_v9_4_3_init_cp_compute_microcode(adev, ucode_prefix); 623 if (r) 624 return r; 625 626 return r; 627 } 628 629 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 630 { 631 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 632 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 633 } 634 635 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 636 { 637 int r, i, num_xcc; 638 u32 *hpd; 639 const __le32 *fw_data; 640 unsigned fw_size; 641 u32 *fw; 642 size_t mec_hpd_size; 643 644 const struct gfx_firmware_header_v1_0 *mec_hdr; 645 646 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 647 for (i = 0; i < num_xcc; i++) 648 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 649 AMDGPU_MAX_COMPUTE_QUEUES); 650 651 /* take ownership of the relevant compute queues */ 652 amdgpu_gfx_compute_queue_acquire(adev); 653 mec_hpd_size = 654 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 655 if (mec_hpd_size) { 656 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 657 AMDGPU_GEM_DOMAIN_VRAM | 658 AMDGPU_GEM_DOMAIN_GTT, 659 &adev->gfx.mec.hpd_eop_obj, 660 &adev->gfx.mec.hpd_eop_gpu_addr, 661 (void **)&hpd); 662 if (r) { 663 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 664 gfx_v9_4_3_mec_fini(adev); 665 return r; 666 } 667 668 if (amdgpu_emu_mode == 1) { 669 for (i = 0; i < mec_hpd_size / 4; i++) { 670 memset((void *)(hpd + i), 0, 4); 671 if (i % 50 == 0) 672 msleep(1); 673 } 674 } else { 675 memset(hpd, 0, mec_hpd_size); 676 } 677 678 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 679 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 680 } 681 682 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 683 684 fw_data = (const __le32 *) 685 (adev->gfx.mec_fw->data + 686 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 687 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 688 689 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 690 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 691 &adev->gfx.mec.mec_fw_obj, 692 &adev->gfx.mec.mec_fw_gpu_addr, 693 (void **)&fw); 694 if (r) { 695 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 696 gfx_v9_4_3_mec_fini(adev); 697 return r; 698 } 699 700 memcpy(fw, fw_data, fw_size); 701 702 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 703 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 704 705 return 0; 706 } 707 708 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 709 u32 sh_num, u32 instance, int xcc_id) 710 { 711 u32 data; 712 713 if (instance == 0xffffffff) 714 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 715 INSTANCE_BROADCAST_WRITES, 1); 716 else 717 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 718 INSTANCE_INDEX, instance); 719 720 if (se_num == 0xffffffff) 721 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 722 SE_BROADCAST_WRITES, 1); 723 else 724 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 725 726 if (sh_num == 0xffffffff) 727 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 728 SH_BROADCAST_WRITES, 1); 729 else 730 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 731 732 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 733 } 734 735 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 736 { 737 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 738 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 739 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 740 (address << SQ_IND_INDEX__INDEX__SHIFT) | 741 (SQ_IND_INDEX__FORCE_READ_MASK)); 742 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 743 } 744 745 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 746 uint32_t wave, uint32_t thread, 747 uint32_t regno, uint32_t num, uint32_t *out) 748 { 749 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 750 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 751 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 752 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 753 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 754 (SQ_IND_INDEX__FORCE_READ_MASK) | 755 (SQ_IND_INDEX__AUTO_INCR_MASK)); 756 while (num--) 757 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 758 } 759 760 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 761 uint32_t xcc_id, uint32_t simd, uint32_t wave, 762 uint32_t *dst, int *no_fields) 763 { 764 /* type 1 wave data */ 765 dst[(*no_fields)++] = 1; 766 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 767 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 768 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 769 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 770 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 771 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 772 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 773 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 774 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 775 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 776 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 777 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 778 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 779 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 780 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 781 } 782 783 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 784 uint32_t wave, uint32_t start, 785 uint32_t size, uint32_t *dst) 786 { 787 wave_read_regs(adev, xcc_id, simd, wave, 0, 788 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 789 } 790 791 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 792 uint32_t wave, uint32_t thread, 793 uint32_t start, uint32_t size, 794 uint32_t *dst) 795 { 796 wave_read_regs(adev, xcc_id, simd, wave, thread, 797 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 798 } 799 800 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 801 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 802 { 803 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 804 } 805 806 static int gfx_v9_4_3_get_xccs_per_xcp(struct amdgpu_device *adev) 807 { 808 u32 xcp_ctl; 809 810 /* Value is expected to be the same on all, fetch from first instance */ 811 xcp_ctl = RREG32_SOC15(GC, GET_INST(GC, 0), regCP_HYP_XCP_CTL); 812 813 return REG_GET_FIELD(xcp_ctl, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP); 814 } 815 816 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 817 int num_xccs_per_xcp) 818 { 819 int ret, i, num_xcc; 820 u32 tmp = 0; 821 822 if (adev->psp.funcs) { 823 ret = psp_spatial_partition(&adev->psp, 824 NUM_XCC(adev->gfx.xcc_mask) / 825 num_xccs_per_xcp); 826 if (ret) 827 return ret; 828 } else { 829 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 830 831 for (i = 0; i < num_xcc; i++) { 832 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 833 num_xccs_per_xcp); 834 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 835 i % num_xccs_per_xcp); 836 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 837 tmp); 838 } 839 ret = 0; 840 } 841 842 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 843 844 return ret; 845 } 846 847 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 848 { 849 int xcc; 850 851 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 852 if (!xcc) { 853 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 854 return -EINVAL; 855 } 856 857 return xcc - 1; 858 } 859 860 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 861 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 862 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 863 .read_wave_data = &gfx_v9_4_3_read_wave_data, 864 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 865 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 866 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 867 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 868 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 869 .get_xccs_per_xcp = &gfx_v9_4_3_get_xccs_per_xcp, 870 }; 871 872 static int gfx_v9_4_3_aca_bank_parser(struct aca_handle *handle, 873 struct aca_bank *bank, enum aca_smu_type type, 874 void *data) 875 { 876 struct aca_bank_info info; 877 u64 misc0; 878 u32 instlo; 879 int ret; 880 881 ret = aca_bank_info_decode(bank, &info); 882 if (ret) 883 return ret; 884 885 /* NOTE: overwrite info.die_id with xcd id for gfx */ 886 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 887 instlo &= GENMASK(31, 1); 888 info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 889 890 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 891 892 switch (type) { 893 case ACA_SMU_TYPE_UE: 894 ret = aca_error_cache_log_bank_error(handle, &info, 895 ACA_ERROR_TYPE_UE, 1ULL); 896 break; 897 case ACA_SMU_TYPE_CE: 898 ret = aca_error_cache_log_bank_error(handle, &info, 899 ACA_ERROR_TYPE_CE, ACA_REG__MISC0__ERRCNT(misc0)); 900 break; 901 default: 902 return -EINVAL; 903 } 904 905 return ret; 906 } 907 908 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 909 enum aca_smu_type type, void *data) 910 { 911 u32 instlo; 912 913 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 914 instlo &= GENMASK(31, 1); 915 switch (instlo) { 916 case mmSMNAID_XCD0_MCA_SMU: 917 case mmSMNAID_XCD1_MCA_SMU: 918 case mmSMNXCD_XCD0_MCA_SMU: 919 return true; 920 default: 921 break; 922 } 923 924 return false; 925 } 926 927 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 928 .aca_bank_parser = gfx_v9_4_3_aca_bank_parser, 929 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 930 }; 931 932 static const struct aca_info gfx_v9_4_3_aca_info = { 933 .hwip = ACA_HWIP_TYPE_SMU, 934 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 935 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 936 }; 937 938 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 939 { 940 u32 gb_addr_config; 941 942 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 943 adev->gfx.ras = &gfx_v9_4_3_ras; 944 945 adev->gfx.config.max_hw_contexts = 8; 946 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 947 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 948 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 949 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 950 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 951 952 adev->gfx.config.gb_addr_config = gb_addr_config; 953 954 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 955 REG_GET_FIELD( 956 adev->gfx.config.gb_addr_config, 957 GB_ADDR_CONFIG, 958 NUM_PIPES); 959 960 adev->gfx.config.max_tile_pipes = 961 adev->gfx.config.gb_addr_config_fields.num_pipes; 962 963 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 964 REG_GET_FIELD( 965 adev->gfx.config.gb_addr_config, 966 GB_ADDR_CONFIG, 967 NUM_BANKS); 968 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 969 REG_GET_FIELD( 970 adev->gfx.config.gb_addr_config, 971 GB_ADDR_CONFIG, 972 MAX_COMPRESSED_FRAGS); 973 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 974 REG_GET_FIELD( 975 adev->gfx.config.gb_addr_config, 976 GB_ADDR_CONFIG, 977 NUM_RB_PER_SE); 978 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 979 REG_GET_FIELD( 980 adev->gfx.config.gb_addr_config, 981 GB_ADDR_CONFIG, 982 NUM_SHADER_ENGINES); 983 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 984 REG_GET_FIELD( 985 adev->gfx.config.gb_addr_config, 986 GB_ADDR_CONFIG, 987 PIPE_INTERLEAVE_SIZE)); 988 989 return 0; 990 } 991 992 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 993 int xcc_id, int mec, int pipe, int queue) 994 { 995 unsigned irq_type; 996 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 997 unsigned int hw_prio; 998 uint32_t xcc_doorbell_start; 999 1000 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 1001 ring_id]; 1002 1003 /* mec0 is me1 */ 1004 ring->xcc_id = xcc_id; 1005 ring->me = mec + 1; 1006 ring->pipe = pipe; 1007 ring->queue = queue; 1008 1009 ring->ring_obj = NULL; 1010 ring->use_doorbell = true; 1011 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 1012 xcc_id * adev->doorbell_index.xcc_doorbell_range; 1013 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 1014 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 1015 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 1016 GFX9_MEC_HPD_SIZE; 1017 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 1018 sprintf(ring->name, "comp_%d.%d.%d.%d", 1019 ring->xcc_id, ring->me, ring->pipe, ring->queue); 1020 1021 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1022 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1023 + ring->pipe; 1024 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 1025 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 1026 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1027 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 1028 hw_prio, NULL); 1029 } 1030 1031 static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) 1032 { 1033 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 1034 uint32_t *ptr, num_xcc, inst; 1035 1036 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1037 1038 ptr = kcalloc(reg_count * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1039 if (!ptr) { 1040 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1041 adev->gfx.ip_dump_core = NULL; 1042 } else { 1043 adev->gfx.ip_dump_core = ptr; 1044 } 1045 1046 /* Allocate memory for compute queue registers for all the instances */ 1047 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 1048 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1049 adev->gfx.mec.num_queue_per_pipe; 1050 1051 ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); 1052 if (!ptr) { 1053 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1054 adev->gfx.ip_dump_compute_queues = NULL; 1055 } else { 1056 adev->gfx.ip_dump_compute_queues = ptr; 1057 } 1058 } 1059 1060 static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) 1061 { 1062 int i, j, k, r, ring_id, xcc_id, num_xcc; 1063 struct amdgpu_device *adev = ip_block->adev; 1064 1065 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1066 case IP_VERSION(9, 4, 3): 1067 case IP_VERSION(9, 4, 4): 1068 adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; 1069 adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); 1070 if (adev->gfx.mec_fw_version >= 153) { 1071 adev->gfx.enable_cleaner_shader = true; 1072 r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); 1073 if (r) { 1074 adev->gfx.enable_cleaner_shader = false; 1075 dev_err(adev->dev, "Failed to initialize cleaner shader\n"); 1076 } 1077 } 1078 break; 1079 default: 1080 adev->gfx.enable_cleaner_shader = false; 1081 break; 1082 } 1083 1084 adev->gfx.mec.num_mec = 2; 1085 adev->gfx.mec.num_pipe_per_mec = 4; 1086 adev->gfx.mec.num_queue_per_pipe = 8; 1087 1088 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1089 1090 /* EOP Event */ 1091 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1092 if (r) 1093 return r; 1094 1095 /* Bad opcode Event */ 1096 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1097 GFX_9_0__SRCID__CP_BAD_OPCODE_ERROR, 1098 &adev->gfx.bad_op_irq); 1099 if (r) 1100 return r; 1101 1102 /* Privileged reg */ 1103 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1104 &adev->gfx.priv_reg_irq); 1105 if (r) 1106 return r; 1107 1108 /* Privileged inst */ 1109 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1110 &adev->gfx.priv_inst_irq); 1111 if (r) 1112 return r; 1113 1114 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1115 1116 r = adev->gfx.rlc.funcs->init(adev); 1117 if (r) { 1118 DRM_ERROR("Failed to init rlc BOs!\n"); 1119 return r; 1120 } 1121 1122 r = gfx_v9_4_3_mec_init(adev); 1123 if (r) { 1124 DRM_ERROR("Failed to init MEC BOs!\n"); 1125 return r; 1126 } 1127 1128 /* set up the compute queues - allocate horizontally across pipes */ 1129 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1130 ring_id = 0; 1131 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1132 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1133 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 1134 k++) { 1135 if (!amdgpu_gfx_is_mec_queue_enabled( 1136 adev, xcc_id, i, k, j)) 1137 continue; 1138 1139 r = gfx_v9_4_3_compute_ring_init(adev, 1140 ring_id, 1141 xcc_id, 1142 i, k, j); 1143 if (r) 1144 return r; 1145 1146 ring_id++; 1147 } 1148 } 1149 } 1150 1151 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 1152 if (r) { 1153 DRM_ERROR("Failed to init KIQ BOs!\n"); 1154 return r; 1155 } 1156 1157 r = amdgpu_gfx_kiq_init_ring(adev, xcc_id); 1158 if (r) 1159 return r; 1160 1161 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1162 r = amdgpu_gfx_mqd_sw_init(adev, 1163 sizeof(struct v9_mqd_allocation), xcc_id); 1164 if (r) 1165 return r; 1166 } 1167 1168 adev->gfx.compute_supported_reset = 1169 amdgpu_get_soft_full_reset_mask(&adev->gfx.compute_ring[0]); 1170 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1171 case IP_VERSION(9, 4, 3): 1172 case IP_VERSION(9, 4, 4): 1173 if (adev->gfx.mec_fw_version >= 155) { 1174 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE; 1175 adev->gfx.compute_supported_reset |= AMDGPU_RESET_TYPE_PER_PIPE; 1176 } 1177 break; 1178 default: 1179 break; 1180 } 1181 r = gfx_v9_4_3_gpu_early_init(adev); 1182 if (r) 1183 return r; 1184 1185 r = amdgpu_gfx_ras_sw_init(adev); 1186 if (r) 1187 return r; 1188 1189 r = amdgpu_gfx_sysfs_init(adev); 1190 if (r) 1191 return r; 1192 1193 gfx_v9_4_3_alloc_ip_dump(adev); 1194 1195 return 0; 1196 } 1197 1198 static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) 1199 { 1200 int i, num_xcc; 1201 struct amdgpu_device *adev = ip_block->adev; 1202 1203 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1204 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1205 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1206 1207 for (i = 0; i < num_xcc; i++) { 1208 amdgpu_gfx_mqd_sw_fini(adev, i); 1209 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 1210 amdgpu_gfx_kiq_fini(adev, i); 1211 } 1212 1213 amdgpu_gfx_cleaner_shader_sw_fini(adev); 1214 1215 gfx_v9_4_3_mec_fini(adev); 1216 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 1217 gfx_v9_4_3_free_microcode(adev); 1218 amdgpu_gfx_sysfs_fini(adev); 1219 1220 kfree(adev->gfx.ip_dump_core); 1221 kfree(adev->gfx.ip_dump_compute_queues); 1222 1223 return 0; 1224 } 1225 1226 #define DEFAULT_SH_MEM_BASES (0x6000) 1227 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 1228 int xcc_id) 1229 { 1230 int i; 1231 uint32_t sh_mem_config; 1232 uint32_t sh_mem_bases; 1233 uint32_t data; 1234 1235 /* 1236 * Configure apertures: 1237 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1238 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1239 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1240 */ 1241 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1242 1243 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1244 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1245 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1246 1247 mutex_lock(&adev->srbm_mutex); 1248 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1249 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1250 /* CP and shaders */ 1251 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1252 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1253 1254 /* Enable trap for each kfd vmid. */ 1255 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1256 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1257 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1258 } 1259 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1260 mutex_unlock(&adev->srbm_mutex); 1261 1262 /* 1263 * Initialize all compute VMIDs to have no GDS, GWS, or OA 1264 * access. These should be enabled by FW for target VMIDs. 1265 */ 1266 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1267 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1268 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1269 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1270 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1271 } 1272 } 1273 1274 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1275 { 1276 int vmid; 1277 1278 /* 1279 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1280 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1281 * the driver can enable them for graphics. VMID0 should maintain 1282 * access so that HWS firmware can save/restore entries. 1283 */ 1284 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1285 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1286 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1287 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1288 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1289 } 1290 } 1291 1292 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1293 int xcc_id) 1294 { 1295 u32 tmp; 1296 int i; 1297 1298 /* XXX SH_MEM regs */ 1299 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1300 mutex_lock(&adev->srbm_mutex); 1301 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1302 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1303 /* CP and shaders */ 1304 if (i == 0) { 1305 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1306 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1307 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1308 !!adev->gmc.noretry); 1309 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1310 regSH_MEM_CONFIG, tmp); 1311 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1312 regSH_MEM_BASES, 0); 1313 } else { 1314 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1315 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1316 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1317 !!adev->gmc.noretry); 1318 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1319 regSH_MEM_CONFIG, tmp); 1320 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1321 (adev->gmc.private_aperture_start >> 1322 48)); 1323 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1324 (adev->gmc.shared_aperture_start >> 1325 48)); 1326 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1327 regSH_MEM_BASES, tmp); 1328 } 1329 } 1330 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1331 1332 mutex_unlock(&adev->srbm_mutex); 1333 1334 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1335 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1336 } 1337 1338 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1339 { 1340 int i, num_xcc; 1341 1342 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1343 1344 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1345 adev->gfx.config.db_debug2 = 1346 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1347 1348 for (i = 0; i < num_xcc; i++) 1349 gfx_v9_4_3_xcc_constants_init(adev, i); 1350 } 1351 1352 static void 1353 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1354 int xcc_id) 1355 { 1356 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1357 } 1358 1359 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1360 { 1361 /* 1362 * Rlc save restore list is workable since v2_1. 1363 * And it's needed by gfxoff feature. 1364 */ 1365 if (adev->gfx.rlc.is_rlc_v2_1) 1366 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1367 } 1368 1369 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1370 { 1371 uint32_t data; 1372 1373 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1374 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1375 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1376 } 1377 1378 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1379 { 1380 uint32_t rlc_setting; 1381 1382 /* if RLC is not enabled, do nothing */ 1383 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1384 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1385 return false; 1386 1387 return true; 1388 } 1389 1390 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1391 { 1392 uint32_t data; 1393 unsigned i; 1394 1395 data = RLC_SAFE_MODE__CMD_MASK; 1396 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1397 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1398 1399 /* wait for RLC_SAFE_MODE */ 1400 for (i = 0; i < adev->usec_timeout; i++) { 1401 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1402 break; 1403 udelay(1); 1404 } 1405 } 1406 1407 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1408 int xcc_id) 1409 { 1410 uint32_t data; 1411 1412 data = RLC_SAFE_MODE__CMD_MASK; 1413 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1414 } 1415 1416 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1417 { 1418 int xcc_id, num_xcc; 1419 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1420 1421 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1422 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1423 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1424 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1425 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1426 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1427 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1428 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1429 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1430 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1431 } 1432 adev->gfx.rlc.rlcg_reg_access_supported = true; 1433 } 1434 1435 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1436 { 1437 /* init spm vmid with 0xf */ 1438 if (adev->gfx.rlc.funcs->update_spm_vmid) 1439 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1440 1441 return 0; 1442 } 1443 1444 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1445 int xcc_id) 1446 { 1447 u32 i, j, k; 1448 u32 mask; 1449 1450 mutex_lock(&adev->grbm_idx_mutex); 1451 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1452 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1453 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1454 xcc_id); 1455 for (k = 0; k < adev->usec_timeout; k++) { 1456 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1457 break; 1458 udelay(1); 1459 } 1460 if (k == adev->usec_timeout) { 1461 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1462 0xffffffff, 1463 0xffffffff, xcc_id); 1464 mutex_unlock(&adev->grbm_idx_mutex); 1465 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1466 i, j); 1467 return; 1468 } 1469 } 1470 } 1471 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1472 xcc_id); 1473 mutex_unlock(&adev->grbm_idx_mutex); 1474 1475 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1476 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1477 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1478 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1479 for (k = 0; k < adev->usec_timeout; k++) { 1480 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1481 break; 1482 udelay(1); 1483 } 1484 } 1485 1486 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1487 bool enable, int xcc_id) 1488 { 1489 u32 tmp; 1490 1491 /* These interrupts should be enabled to drive DS clock */ 1492 1493 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1494 1495 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1496 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1497 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1498 1499 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1500 } 1501 1502 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1503 { 1504 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1505 RLC_ENABLE_F32, 0); 1506 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1507 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1508 } 1509 1510 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1511 { 1512 int i, num_xcc; 1513 1514 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1515 for (i = 0; i < num_xcc; i++) 1516 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1517 } 1518 1519 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1520 { 1521 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1522 SOFT_RESET_RLC, 1); 1523 udelay(50); 1524 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1525 SOFT_RESET_RLC, 0); 1526 udelay(50); 1527 } 1528 1529 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1530 { 1531 int i, num_xcc; 1532 1533 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1534 for (i = 0; i < num_xcc; i++) 1535 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1536 } 1537 1538 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1539 { 1540 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1541 RLC_ENABLE_F32, 1); 1542 udelay(50); 1543 1544 /* carrizo do enable cp interrupt after cp inited */ 1545 if (!(adev->flags & AMD_IS_APU)) { 1546 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1547 udelay(50); 1548 } 1549 } 1550 1551 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1552 { 1553 #ifdef AMDGPU_RLC_DEBUG_RETRY 1554 u32 rlc_ucode_ver; 1555 #endif 1556 int i, num_xcc; 1557 1558 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1559 for (i = 0; i < num_xcc; i++) { 1560 gfx_v9_4_3_xcc_rlc_start(adev, i); 1561 #ifdef AMDGPU_RLC_DEBUG_RETRY 1562 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1563 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1564 if (rlc_ucode_ver == 0x108) { 1565 dev_info(adev->dev, 1566 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1567 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1568 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1569 * default is 0x9C4 to create a 100us interval */ 1570 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1571 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1572 * to disable the page fault retry interrupts, default is 1573 * 0x100 (256) */ 1574 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1575 } 1576 #endif 1577 } 1578 } 1579 1580 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1581 int xcc_id) 1582 { 1583 const struct rlc_firmware_header_v2_0 *hdr; 1584 const __le32 *fw_data; 1585 unsigned i, fw_size; 1586 1587 if (!adev->gfx.rlc_fw) 1588 return -EINVAL; 1589 1590 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1591 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1592 1593 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1594 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1595 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1596 1597 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1598 RLCG_UCODE_LOADING_START_ADDRESS); 1599 for (i = 0; i < fw_size; i++) { 1600 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1601 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1602 msleep(1); 1603 } 1604 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1605 } 1606 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1607 1608 return 0; 1609 } 1610 1611 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1612 { 1613 int r; 1614 1615 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1616 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1617 /* legacy rlc firmware loading */ 1618 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1619 if (r) 1620 return r; 1621 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1622 } 1623 1624 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1625 /* disable CG */ 1626 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1627 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1628 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1629 1630 return 0; 1631 } 1632 1633 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1634 { 1635 int r, i, num_xcc; 1636 1637 if (amdgpu_sriov_vf(adev)) 1638 return 0; 1639 1640 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1641 for (i = 0; i < num_xcc; i++) { 1642 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1643 if (r) 1644 return r; 1645 } 1646 1647 return 0; 1648 } 1649 1650 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1651 unsigned vmid) 1652 { 1653 u32 reg, pre_data, data; 1654 1655 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1656 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) 1657 pre_data = RREG32_NO_KIQ(reg); 1658 else 1659 pre_data = RREG32(reg); 1660 1661 data = pre_data & (~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK); 1662 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1663 1664 if (pre_data != data) { 1665 if (amdgpu_sriov_is_pp_one_vf(adev) && !amdgpu_sriov_runtime(adev)) { 1666 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1667 } else 1668 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1669 } 1670 } 1671 1672 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1673 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1674 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1675 }; 1676 1677 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1678 uint32_t offset, 1679 struct soc15_reg_rlcg *entries, int arr_size) 1680 { 1681 int i, inst; 1682 uint32_t reg; 1683 1684 if (!entries) 1685 return false; 1686 1687 for (i = 0; i < arr_size; i++) { 1688 const struct soc15_reg_rlcg *entry; 1689 1690 entry = &entries[i]; 1691 inst = adev->ip_map.logical_to_dev_inst ? 1692 adev->ip_map.logical_to_dev_inst( 1693 adev, entry->hwip, entry->instance) : 1694 entry->instance; 1695 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1696 entry->reg; 1697 if (offset == reg) 1698 return true; 1699 } 1700 1701 return false; 1702 } 1703 1704 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1705 { 1706 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1707 (void *)rlcg_access_gc_9_4_3, 1708 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1709 } 1710 1711 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1712 bool enable, int xcc_id) 1713 { 1714 if (enable) { 1715 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1716 } else { 1717 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1718 (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | 1719 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | 1720 CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | 1721 CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | 1722 CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | 1723 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | 1724 CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | 1725 CP_MEC_CNTL__MEC_ME1_HALT_MASK | 1726 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1727 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1728 } 1729 udelay(50); 1730 } 1731 1732 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1733 int xcc_id) 1734 { 1735 const struct gfx_firmware_header_v1_0 *mec_hdr; 1736 const __le32 *fw_data; 1737 unsigned i; 1738 u32 tmp; 1739 u32 mec_ucode_addr_offset; 1740 u32 mec_ucode_data_offset; 1741 1742 if (!adev->gfx.mec_fw) 1743 return -EINVAL; 1744 1745 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1746 1747 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1748 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1749 1750 fw_data = (const __le32 *) 1751 (adev->gfx.mec_fw->data + 1752 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1753 tmp = 0; 1754 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1755 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1756 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1757 1758 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1759 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1760 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1761 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1762 1763 mec_ucode_addr_offset = 1764 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1765 mec_ucode_data_offset = 1766 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1767 1768 /* MEC1 */ 1769 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1770 for (i = 0; i < mec_hdr->jt_size; i++) 1771 WREG32(mec_ucode_data_offset, 1772 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1773 1774 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1775 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1776 1777 return 0; 1778 } 1779 1780 /* KIQ functions */ 1781 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1782 { 1783 uint32_t tmp; 1784 struct amdgpu_device *adev = ring->adev; 1785 1786 /* tell RLC which is KIQ queue */ 1787 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1788 tmp &= 0xffffff00; 1789 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1790 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp | 0x80); 1791 } 1792 1793 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1794 { 1795 struct amdgpu_device *adev = ring->adev; 1796 1797 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1798 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1799 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1800 mqd->cp_hqd_queue_priority = 1801 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1802 } 1803 } 1804 } 1805 1806 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1807 { 1808 struct amdgpu_device *adev = ring->adev; 1809 struct v9_mqd *mqd = ring->mqd_ptr; 1810 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1811 uint32_t tmp; 1812 1813 mqd->header = 0xC0310800; 1814 mqd->compute_pipelinestat_enable = 0x00000001; 1815 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1816 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1817 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1818 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1819 mqd->compute_misc_reserved = 0x00000003; 1820 1821 mqd->dynamic_cu_mask_addr_lo = 1822 lower_32_bits(ring->mqd_gpu_addr 1823 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1824 mqd->dynamic_cu_mask_addr_hi = 1825 upper_32_bits(ring->mqd_gpu_addr 1826 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1827 1828 eop_base_addr = ring->eop_gpu_addr >> 8; 1829 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1830 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1831 1832 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1833 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1834 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1835 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1836 1837 mqd->cp_hqd_eop_control = tmp; 1838 1839 /* enable doorbell? */ 1840 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1841 1842 if (ring->use_doorbell) { 1843 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1844 DOORBELL_OFFSET, ring->doorbell_index); 1845 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1846 DOORBELL_EN, 1); 1847 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1848 DOORBELL_SOURCE, 0); 1849 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1850 DOORBELL_HIT, 0); 1851 if (amdgpu_sriov_vf(adev)) 1852 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1853 DOORBELL_MODE, 1); 1854 } else { 1855 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1856 DOORBELL_EN, 0); 1857 } 1858 1859 mqd->cp_hqd_pq_doorbell_control = tmp; 1860 1861 /* disable the queue if it's active */ 1862 ring->wptr = 0; 1863 mqd->cp_hqd_dequeue_request = 0; 1864 mqd->cp_hqd_pq_rptr = 0; 1865 mqd->cp_hqd_pq_wptr_lo = 0; 1866 mqd->cp_hqd_pq_wptr_hi = 0; 1867 1868 /* set the pointer to the MQD */ 1869 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1870 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1871 1872 /* set MQD vmid to 0 */ 1873 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1874 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1875 mqd->cp_mqd_control = tmp; 1876 1877 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1878 hqd_gpu_addr = ring->gpu_addr >> 8; 1879 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1880 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1881 1882 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1883 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1884 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1885 (order_base_2(ring->ring_size / 4) - 1)); 1886 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1887 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1888 #ifdef __BIG_ENDIAN 1889 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1890 #endif 1891 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1892 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1893 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1894 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1895 mqd->cp_hqd_pq_control = tmp; 1896 1897 /* set the wb address whether it's enabled or not */ 1898 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1899 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1900 mqd->cp_hqd_pq_rptr_report_addr_hi = 1901 upper_32_bits(wb_gpu_addr) & 0xffff; 1902 1903 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1904 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1905 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1906 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1907 1908 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1909 ring->wptr = 0; 1910 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1911 1912 /* set the vmid for the queue */ 1913 mqd->cp_hqd_vmid = 0; 1914 1915 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1916 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1917 mqd->cp_hqd_persistent_state = tmp; 1918 1919 /* set MIN_IB_AVAIL_SIZE */ 1920 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1921 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1922 mqd->cp_hqd_ib_control = tmp; 1923 1924 /* set static priority for a queue/ring */ 1925 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1926 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1927 1928 /* map_queues packet doesn't need activate the queue, 1929 * so only kiq need set this field. 1930 */ 1931 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1932 mqd->cp_hqd_active = 1; 1933 1934 return 0; 1935 } 1936 1937 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1938 int xcc_id) 1939 { 1940 struct amdgpu_device *adev = ring->adev; 1941 struct v9_mqd *mqd = ring->mqd_ptr; 1942 int j; 1943 1944 /* disable wptr polling */ 1945 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1946 1947 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1948 mqd->cp_hqd_eop_base_addr_lo); 1949 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1950 mqd->cp_hqd_eop_base_addr_hi); 1951 1952 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1953 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1954 mqd->cp_hqd_eop_control); 1955 1956 /* enable doorbell? */ 1957 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1958 mqd->cp_hqd_pq_doorbell_control); 1959 1960 /* disable the queue if it's active */ 1961 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1962 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1963 for (j = 0; j < adev->usec_timeout; j++) { 1964 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1965 break; 1966 udelay(1); 1967 } 1968 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1969 mqd->cp_hqd_dequeue_request); 1970 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1971 mqd->cp_hqd_pq_rptr); 1972 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1973 mqd->cp_hqd_pq_wptr_lo); 1974 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1975 mqd->cp_hqd_pq_wptr_hi); 1976 } 1977 1978 /* set the pointer to the MQD */ 1979 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1980 mqd->cp_mqd_base_addr_lo); 1981 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1982 mqd->cp_mqd_base_addr_hi); 1983 1984 /* set MQD vmid to 0 */ 1985 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1986 mqd->cp_mqd_control); 1987 1988 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1989 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1990 mqd->cp_hqd_pq_base_lo); 1991 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1992 mqd->cp_hqd_pq_base_hi); 1993 1994 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1995 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1996 mqd->cp_hqd_pq_control); 1997 1998 /* set the wb address whether it's enabled or not */ 1999 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 2000 mqd->cp_hqd_pq_rptr_report_addr_lo); 2001 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2002 mqd->cp_hqd_pq_rptr_report_addr_hi); 2003 2004 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2005 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 2006 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2007 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2008 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2009 2010 /* enable the doorbell if requested */ 2011 if (ring->use_doorbell) { 2012 WREG32_SOC15( 2013 GC, GET_INST(GC, xcc_id), 2014 regCP_MEC_DOORBELL_RANGE_LOWER, 2015 ((adev->doorbell_index.kiq + 2016 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2017 2) << 2); 2018 WREG32_SOC15( 2019 GC, GET_INST(GC, xcc_id), 2020 regCP_MEC_DOORBELL_RANGE_UPPER, 2021 ((adev->doorbell_index.userqueue_end + 2022 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2023 2) << 2); 2024 } 2025 2026 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 2027 mqd->cp_hqd_pq_doorbell_control); 2028 2029 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2030 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 2031 mqd->cp_hqd_pq_wptr_lo); 2032 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 2033 mqd->cp_hqd_pq_wptr_hi); 2034 2035 /* set the vmid for the queue */ 2036 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 2037 2038 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 2039 mqd->cp_hqd_persistent_state); 2040 2041 /* activate the queue */ 2042 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 2043 mqd->cp_hqd_active); 2044 2045 if (ring->use_doorbell) 2046 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2047 2048 return 0; 2049 } 2050 2051 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 2052 int xcc_id) 2053 { 2054 struct amdgpu_device *adev = ring->adev; 2055 int j; 2056 2057 /* disable the queue if it's active */ 2058 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 2059 2060 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 2061 2062 for (j = 0; j < adev->usec_timeout; j++) { 2063 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 2064 break; 2065 udelay(1); 2066 } 2067 2068 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2069 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 2070 2071 /* Manual disable if dequeue request times out */ 2072 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 2073 } 2074 2075 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 2076 0); 2077 } 2078 2079 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 2080 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 2081 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 2082 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2083 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 2084 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 2085 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 2086 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 2087 2088 return 0; 2089 } 2090 2091 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 2092 { 2093 struct amdgpu_device *adev = ring->adev; 2094 struct v9_mqd *mqd = ring->mqd_ptr; 2095 struct v9_mqd *tmp_mqd; 2096 2097 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 2098 2099 /* GPU could be in bad state during probe, driver trigger the reset 2100 * after load the SMU, in this case , the mqd is not be initialized. 2101 * driver need to re-init the mqd. 2102 * check mqd->cp_hqd_pq_control since this value should not be 0 2103 */ 2104 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 2105 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 2106 /* for GPU_RESET case , reset MQD to a clean status */ 2107 if (adev->gfx.kiq[xcc_id].mqd_backup) 2108 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 2109 2110 /* reset ring buffer */ 2111 ring->wptr = 0; 2112 amdgpu_ring_clear_ring(ring); 2113 mutex_lock(&adev->srbm_mutex); 2114 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2115 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2116 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2117 mutex_unlock(&adev->srbm_mutex); 2118 } else { 2119 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2120 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2121 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2122 mutex_lock(&adev->srbm_mutex); 2123 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 2124 amdgpu_ring_clear_ring(ring); 2125 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2126 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2127 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 2128 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2129 mutex_unlock(&adev->srbm_mutex); 2130 2131 if (adev->gfx.kiq[xcc_id].mqd_backup) 2132 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 2133 } 2134 2135 return 0; 2136 } 2137 2138 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) 2139 { 2140 struct amdgpu_device *adev = ring->adev; 2141 struct v9_mqd *mqd = ring->mqd_ptr; 2142 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2143 struct v9_mqd *tmp_mqd; 2144 2145 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 2146 * is not be initialized before 2147 */ 2148 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 2149 2150 if (!restore && (!tmp_mqd->cp_hqd_pq_control || 2151 (!amdgpu_in_reset(adev) && !adev->in_suspend))) { 2152 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 2153 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 2154 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 2155 mutex_lock(&adev->srbm_mutex); 2156 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2157 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 2158 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2159 mutex_unlock(&adev->srbm_mutex); 2160 2161 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2162 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 2163 } else { 2164 /* restore MQD to a clean status */ 2165 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2166 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2167 /* reset ring buffer */ 2168 ring->wptr = 0; 2169 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 2170 amdgpu_ring_clear_ring(ring); 2171 } 2172 2173 return 0; 2174 } 2175 2176 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 2177 { 2178 struct amdgpu_ring *ring; 2179 int j; 2180 2181 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2182 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 2183 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2184 mutex_lock(&adev->srbm_mutex); 2185 soc15_grbm_select(adev, ring->me, 2186 ring->pipe, 2187 ring->queue, 0, GET_INST(GC, xcc_id)); 2188 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 2189 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2190 mutex_unlock(&adev->srbm_mutex); 2191 } 2192 } 2193 2194 return 0; 2195 } 2196 2197 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 2198 { 2199 struct amdgpu_ring *ring; 2200 int r; 2201 2202 ring = &adev->gfx.kiq[xcc_id].ring; 2203 2204 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2205 if (unlikely(r != 0)) 2206 return r; 2207 2208 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2209 if (unlikely(r != 0)) { 2210 amdgpu_bo_unreserve(ring->mqd_obj); 2211 return r; 2212 } 2213 2214 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 2215 amdgpu_bo_kunmap(ring->mqd_obj); 2216 ring->mqd_ptr = NULL; 2217 amdgpu_bo_unreserve(ring->mqd_obj); 2218 return 0; 2219 } 2220 2221 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 2222 { 2223 struct amdgpu_ring *ring = NULL; 2224 int r = 0, i; 2225 2226 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 2227 2228 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2229 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2230 2231 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2232 if (unlikely(r != 0)) 2233 goto done; 2234 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2235 if (!r) { 2236 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); 2237 amdgpu_bo_kunmap(ring->mqd_obj); 2238 ring->mqd_ptr = NULL; 2239 } 2240 amdgpu_bo_unreserve(ring->mqd_obj); 2241 if (r) 2242 goto done; 2243 } 2244 2245 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2246 done: 2247 return r; 2248 } 2249 2250 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 2251 { 2252 struct amdgpu_ring *ring; 2253 int r, j; 2254 2255 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2256 2257 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2258 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 2259 2260 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 2261 if (r) 2262 return r; 2263 } else { 2264 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2265 } 2266 2267 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 2268 if (r) 2269 return r; 2270 2271 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 2272 if (r) 2273 return r; 2274 2275 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2276 ring = &adev->gfx.compute_ring 2277 [j + xcc_id * adev->gfx.num_compute_rings]; 2278 r = amdgpu_ring_test_helper(ring); 2279 if (r) 2280 return r; 2281 } 2282 2283 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2284 2285 return 0; 2286 } 2287 2288 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2289 { 2290 int r = 0, i, num_xcc, num_xcp, num_xcc_per_xcp; 2291 2292 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2293 if (amdgpu_sriov_vf(adev)) { 2294 enum amdgpu_gfx_partition mode; 2295 2296 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2297 AMDGPU_XCP_FL_NONE); 2298 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2299 return -EINVAL; 2300 num_xcc_per_xcp = gfx_v9_4_3_get_xccs_per_xcp(adev); 2301 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2302 num_xcp = num_xcc / num_xcc_per_xcp; 2303 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2304 2305 } else { 2306 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2307 AMDGPU_XCP_FL_NONE) == 2308 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2309 r = amdgpu_xcp_switch_partition_mode( 2310 adev->xcp_mgr, amdgpu_user_partt_mode); 2311 } 2312 if (r) 2313 return r; 2314 2315 for (i = 0; i < num_xcc; i++) { 2316 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2317 if (r) 2318 return r; 2319 } 2320 2321 return 0; 2322 } 2323 2324 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2325 { 2326 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2327 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2328 2329 if (amdgpu_sriov_vf(adev)) { 2330 /* must disable polling for SRIOV when hw finished, otherwise 2331 * CPC engine may still keep fetching WB address which is already 2332 * invalid after sw finished and trigger DMAR reading error in 2333 * hypervisor side. 2334 */ 2335 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2336 return; 2337 } 2338 2339 /* Use deinitialize sequence from CAIL when unbinding device 2340 * from driver, otherwise KIQ is hanging when binding back 2341 */ 2342 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2343 mutex_lock(&adev->srbm_mutex); 2344 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2345 adev->gfx.kiq[xcc_id].ring.pipe, 2346 adev->gfx.kiq[xcc_id].ring.queue, 0, 2347 GET_INST(GC, xcc_id)); 2348 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2349 xcc_id); 2350 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2351 mutex_unlock(&adev->srbm_mutex); 2352 } 2353 2354 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2355 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 2356 } 2357 2358 static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) 2359 { 2360 int r; 2361 struct amdgpu_device *adev = ip_block->adev; 2362 2363 amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, 2364 adev->gfx.cleaner_shader_ptr); 2365 2366 if (!amdgpu_sriov_vf(adev)) 2367 gfx_v9_4_3_init_golden_registers(adev); 2368 2369 gfx_v9_4_3_constants_init(adev); 2370 2371 r = adev->gfx.rlc.funcs->resume(adev); 2372 if (r) 2373 return r; 2374 2375 r = gfx_v9_4_3_cp_resume(adev); 2376 if (r) 2377 return r; 2378 2379 return r; 2380 } 2381 2382 static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) 2383 { 2384 struct amdgpu_device *adev = ip_block->adev; 2385 int i, num_xcc; 2386 2387 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2388 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2389 amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); 2390 2391 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2392 for (i = 0; i < num_xcc; i++) { 2393 gfx_v9_4_3_xcc_fini(adev, i); 2394 } 2395 2396 return 0; 2397 } 2398 2399 static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) 2400 { 2401 return gfx_v9_4_3_hw_fini(ip_block); 2402 } 2403 2404 static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) 2405 { 2406 return gfx_v9_4_3_hw_init(ip_block); 2407 } 2408 2409 static bool gfx_v9_4_3_is_idle(void *handle) 2410 { 2411 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2412 int i, num_xcc; 2413 2414 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2415 for (i = 0; i < num_xcc; i++) { 2416 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2417 GRBM_STATUS, GUI_ACTIVE)) 2418 return false; 2419 } 2420 return true; 2421 } 2422 2423 static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) 2424 { 2425 unsigned i; 2426 struct amdgpu_device *adev = ip_block->adev; 2427 2428 for (i = 0; i < adev->usec_timeout; i++) { 2429 if (gfx_v9_4_3_is_idle(adev)) 2430 return 0; 2431 udelay(1); 2432 } 2433 return -ETIMEDOUT; 2434 } 2435 2436 static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) 2437 { 2438 u32 grbm_soft_reset = 0; 2439 u32 tmp; 2440 struct amdgpu_device *adev = ip_block->adev; 2441 2442 /* GRBM_STATUS */ 2443 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2444 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2445 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2446 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2447 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2448 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2449 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2450 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2451 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2452 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2453 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2454 } 2455 2456 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2457 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2458 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2459 } 2460 2461 /* GRBM_STATUS2 */ 2462 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2463 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2464 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2465 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2466 2467 2468 if (grbm_soft_reset) { 2469 /* stop the rlc */ 2470 adev->gfx.rlc.funcs->stop(adev); 2471 2472 /* Disable MEC parsing/prefetching */ 2473 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2474 2475 if (grbm_soft_reset) { 2476 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2477 tmp |= grbm_soft_reset; 2478 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2479 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2480 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2481 2482 udelay(50); 2483 2484 tmp &= ~grbm_soft_reset; 2485 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2486 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2487 } 2488 2489 /* Wait a little for things to settle down */ 2490 udelay(50); 2491 } 2492 return 0; 2493 } 2494 2495 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2496 uint32_t vmid, 2497 uint32_t gds_base, uint32_t gds_size, 2498 uint32_t gws_base, uint32_t gws_size, 2499 uint32_t oa_base, uint32_t oa_size) 2500 { 2501 struct amdgpu_device *adev = ring->adev; 2502 2503 /* GDS Base */ 2504 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2505 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2506 gds_base); 2507 2508 /* GDS Size */ 2509 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2510 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2511 gds_size); 2512 2513 /* GWS */ 2514 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2515 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2516 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2517 2518 /* OA */ 2519 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2520 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2521 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2522 } 2523 2524 static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) 2525 { 2526 struct amdgpu_device *adev = ip_block->adev; 2527 2528 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2529 AMDGPU_MAX_COMPUTE_RINGS); 2530 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2531 gfx_v9_4_3_set_ring_funcs(adev); 2532 gfx_v9_4_3_set_irq_funcs(adev); 2533 gfx_v9_4_3_set_gds_init(adev); 2534 gfx_v9_4_3_set_rlc_funcs(adev); 2535 2536 /* init rlcg reg access ctrl */ 2537 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2538 2539 return gfx_v9_4_3_init_microcode(adev); 2540 } 2541 2542 static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) 2543 { 2544 struct amdgpu_device *adev = ip_block->adev; 2545 int r; 2546 2547 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2548 if (r) 2549 return r; 2550 2551 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2552 if (r) 2553 return r; 2554 2555 r = amdgpu_irq_get(adev, &adev->gfx.bad_op_irq, 0); 2556 if (r) 2557 return r; 2558 2559 if (adev->gfx.ras && 2560 adev->gfx.ras->enable_watchdog_timer) 2561 adev->gfx.ras->enable_watchdog_timer(adev); 2562 2563 return 0; 2564 } 2565 2566 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2567 bool enable, int xcc_id) 2568 { 2569 uint32_t def, data; 2570 2571 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2572 return; 2573 2574 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2575 regRLC_CGTT_MGCG_OVERRIDE); 2576 2577 if (enable) 2578 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2579 else 2580 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2581 2582 if (def != data) 2583 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2584 regRLC_CGTT_MGCG_OVERRIDE, data); 2585 2586 } 2587 2588 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2589 bool enable, int xcc_id) 2590 { 2591 uint32_t def, data; 2592 2593 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2594 return; 2595 2596 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2597 regRLC_CGTT_MGCG_OVERRIDE); 2598 2599 if (enable) 2600 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2601 else 2602 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2603 2604 if (def != data) 2605 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2606 regRLC_CGTT_MGCG_OVERRIDE, data); 2607 } 2608 2609 static void 2610 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2611 bool enable, int xcc_id) 2612 { 2613 uint32_t data, def; 2614 2615 /* It is disabled by HW by default */ 2616 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2617 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2618 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2619 2620 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2621 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2622 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2623 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2624 2625 if (def != data) 2626 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2627 2628 /* MGLS is a global flag to control all MGLS in GFX */ 2629 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2630 /* 2 - RLC memory Light sleep */ 2631 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2632 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2633 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2634 if (def != data) 2635 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2636 } 2637 /* 3 - CP memory Light sleep */ 2638 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2639 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2640 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2641 if (def != data) 2642 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2643 } 2644 } 2645 } else { 2646 /* 1 - MGCG_OVERRIDE */ 2647 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2648 2649 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2650 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2651 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2652 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2653 2654 if (def != data) 2655 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2656 2657 /* 2 - disable MGLS in RLC */ 2658 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2659 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2660 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2661 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2662 } 2663 2664 /* 3 - disable MGLS in CP */ 2665 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2666 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2667 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2668 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2669 } 2670 } 2671 2672 } 2673 2674 static void 2675 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2676 bool enable, int xcc_id) 2677 { 2678 uint32_t def, data; 2679 2680 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2681 2682 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2683 /* unset CGCG override */ 2684 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2685 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2686 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2687 else 2688 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2689 /* update CGCG and CGLS override bits */ 2690 if (def != data) 2691 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2692 2693 /* CGCG Hysteresis: 400us */ 2694 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2695 2696 data = (0x2710 2697 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2698 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2699 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2700 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2701 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2702 if (def != data) 2703 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2704 2705 /* set IDLE_POLL_COUNT(0x33450100)*/ 2706 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2707 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2708 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2709 if (def != data) 2710 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2711 } else { 2712 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2713 /* reset CGCG/CGLS bits */ 2714 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2715 /* disable cgcg and cgls in FSM */ 2716 if (def != data) 2717 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2718 } 2719 2720 } 2721 2722 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2723 bool enable, int xcc_id) 2724 { 2725 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2726 2727 if (enable) { 2728 /* FGCG */ 2729 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2730 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2731 2732 /* CGCG/CGLS should be enabled after MGCG/MGLS 2733 * === MGCG + MGLS === 2734 */ 2735 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2736 xcc_id); 2737 /* === CGCG + CGLS === */ 2738 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2739 xcc_id); 2740 } else { 2741 /* CGCG/CGLS should be disabled before MGCG/MGLS 2742 * === CGCG + CGLS === 2743 */ 2744 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2745 xcc_id); 2746 /* === MGCG + MGLS === */ 2747 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2748 xcc_id); 2749 2750 /* FGCG */ 2751 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2752 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2753 } 2754 2755 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2756 2757 return 0; 2758 } 2759 2760 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2761 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2762 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2763 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2764 .init = gfx_v9_4_3_rlc_init, 2765 .resume = gfx_v9_4_3_rlc_resume, 2766 .stop = gfx_v9_4_3_rlc_stop, 2767 .reset = gfx_v9_4_3_rlc_reset, 2768 .start = gfx_v9_4_3_rlc_start, 2769 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2770 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2771 }; 2772 2773 static int gfx_v9_4_3_set_powergating_state(struct amdgpu_ip_block *ip_block, 2774 enum amd_powergating_state state) 2775 { 2776 return 0; 2777 } 2778 2779 static int gfx_v9_4_3_set_clockgating_state(struct amdgpu_ip_block *ip_block, 2780 enum amd_clockgating_state state) 2781 { 2782 struct amdgpu_device *adev = ip_block->adev; 2783 int i, num_xcc; 2784 2785 if (amdgpu_sriov_vf(adev)) 2786 return 0; 2787 2788 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2789 for (i = 0; i < num_xcc; i++) 2790 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2791 adev, state == AMD_CG_STATE_GATE, i); 2792 2793 return 0; 2794 } 2795 2796 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2797 { 2798 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2799 int data; 2800 2801 if (amdgpu_sriov_vf(adev)) 2802 *flags = 0; 2803 2804 /* AMD_CG_SUPPORT_GFX_MGCG */ 2805 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2806 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2807 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2808 2809 /* AMD_CG_SUPPORT_GFX_CGCG */ 2810 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2811 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2812 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2813 2814 /* AMD_CG_SUPPORT_GFX_CGLS */ 2815 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2816 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2817 2818 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2819 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2820 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2821 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2822 2823 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2824 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2825 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2826 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2827 } 2828 2829 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2830 { 2831 struct amdgpu_device *adev = ring->adev; 2832 u32 ref_and_mask, reg_mem_engine; 2833 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2834 2835 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2836 switch (ring->me) { 2837 case 1: 2838 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2839 break; 2840 case 2: 2841 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2842 break; 2843 default: 2844 return; 2845 } 2846 reg_mem_engine = 0; 2847 } else { 2848 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2849 reg_mem_engine = 1; /* pfp */ 2850 } 2851 2852 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2853 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2854 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2855 ref_and_mask, ref_and_mask, 0x20); 2856 } 2857 2858 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2859 struct amdgpu_job *job, 2860 struct amdgpu_ib *ib, 2861 uint32_t flags) 2862 { 2863 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2864 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2865 2866 /* Currently, there is a high possibility to get wave ID mismatch 2867 * between ME and GDS, leading to a hw deadlock, because ME generates 2868 * different wave IDs than the GDS expects. This situation happens 2869 * randomly when at least 5 compute pipes use GDS ordered append. 2870 * The wave IDs generated by ME are also wrong after suspend/resume. 2871 * Those are probably bugs somewhere else in the kernel driver. 2872 * 2873 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2874 * GDS to 0 for this ring (me/pipe). 2875 */ 2876 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2877 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2878 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2879 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2880 } 2881 2882 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2883 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2884 amdgpu_ring_write(ring, 2885 #ifdef __BIG_ENDIAN 2886 (2 << 0) | 2887 #endif 2888 lower_32_bits(ib->gpu_addr)); 2889 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2890 amdgpu_ring_write(ring, control); 2891 } 2892 2893 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2894 u64 seq, unsigned flags) 2895 { 2896 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2897 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2898 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2899 2900 /* RELEASE_MEM - flush caches, send int */ 2901 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2902 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2903 EOP_TC_NC_ACTION_EN) : 2904 (EOP_TCL1_ACTION_EN | 2905 EOP_TC_ACTION_EN | 2906 EOP_TC_WB_ACTION_EN | 2907 EOP_TC_MD_ACTION_EN)) | 2908 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2909 EVENT_INDEX(5))); 2910 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2911 2912 /* 2913 * the address should be Qword aligned if 64bit write, Dword 2914 * aligned if only send 32bit data low (discard data high) 2915 */ 2916 if (write64bit) 2917 BUG_ON(addr & 0x7); 2918 else 2919 BUG_ON(addr & 0x3); 2920 amdgpu_ring_write(ring, lower_32_bits(addr)); 2921 amdgpu_ring_write(ring, upper_32_bits(addr)); 2922 amdgpu_ring_write(ring, lower_32_bits(seq)); 2923 amdgpu_ring_write(ring, upper_32_bits(seq)); 2924 amdgpu_ring_write(ring, 0); 2925 } 2926 2927 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2928 { 2929 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2930 uint32_t seq = ring->fence_drv.sync_seq; 2931 uint64_t addr = ring->fence_drv.gpu_addr; 2932 2933 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2934 lower_32_bits(addr), upper_32_bits(addr), 2935 seq, 0xffffffff, 4); 2936 } 2937 2938 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2939 unsigned vmid, uint64_t pd_addr) 2940 { 2941 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2942 } 2943 2944 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2945 { 2946 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2947 } 2948 2949 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2950 { 2951 u64 wptr; 2952 2953 /* XXX check if swapping is necessary on BE */ 2954 if (ring->use_doorbell) 2955 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2956 else 2957 BUG(); 2958 return wptr; 2959 } 2960 2961 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2962 { 2963 struct amdgpu_device *adev = ring->adev; 2964 2965 /* XXX check if swapping is necessary on BE */ 2966 if (ring->use_doorbell) { 2967 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2968 WDOORBELL64(ring->doorbell_index, ring->wptr); 2969 } else { 2970 BUG(); /* only DOORBELL method supported on gfx9 now */ 2971 } 2972 } 2973 2974 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2975 u64 seq, unsigned int flags) 2976 { 2977 struct amdgpu_device *adev = ring->adev; 2978 2979 /* we only allocate 32bit for each seq wb address */ 2980 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2981 2982 /* write fence seq to the "addr" */ 2983 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2984 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2985 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2986 amdgpu_ring_write(ring, lower_32_bits(addr)); 2987 amdgpu_ring_write(ring, upper_32_bits(addr)); 2988 amdgpu_ring_write(ring, lower_32_bits(seq)); 2989 2990 if (flags & AMDGPU_FENCE_FLAG_INT) { 2991 /* set register to trigger INT */ 2992 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2993 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2994 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2995 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2996 amdgpu_ring_write(ring, 0); 2997 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2998 } 2999 } 3000 3001 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 3002 uint32_t reg_val_offs) 3003 { 3004 struct amdgpu_device *adev = ring->adev; 3005 3006 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3007 3008 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 3009 amdgpu_ring_write(ring, 0 | /* src: register*/ 3010 (5 << 8) | /* dst: memory */ 3011 (1 << 20)); /* write confirm */ 3012 amdgpu_ring_write(ring, reg); 3013 amdgpu_ring_write(ring, 0); 3014 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 3015 reg_val_offs * 4)); 3016 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 3017 reg_val_offs * 4)); 3018 } 3019 3020 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 3021 uint32_t val) 3022 { 3023 uint32_t cmd = 0; 3024 3025 reg = gfx_v9_4_3_normalize_xcc_reg_offset(reg); 3026 3027 switch (ring->funcs->type) { 3028 case AMDGPU_RING_TYPE_GFX: 3029 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 3030 break; 3031 case AMDGPU_RING_TYPE_KIQ: 3032 cmd = (1 << 16); /* no inc addr */ 3033 break; 3034 default: 3035 cmd = WR_CONFIRM; 3036 break; 3037 } 3038 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3039 amdgpu_ring_write(ring, cmd); 3040 amdgpu_ring_write(ring, reg); 3041 amdgpu_ring_write(ring, 0); 3042 amdgpu_ring_write(ring, val); 3043 } 3044 3045 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3046 uint32_t val, uint32_t mask) 3047 { 3048 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3049 } 3050 3051 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3052 uint32_t reg0, uint32_t reg1, 3053 uint32_t ref, uint32_t mask) 3054 { 3055 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 3056 ref, mask); 3057 } 3058 3059 static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, 3060 unsigned vmid) 3061 { 3062 struct amdgpu_device *adev = ring->adev; 3063 uint32_t value = 0; 3064 3065 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 3066 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 3067 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 3068 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 3069 amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); 3070 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); 3071 amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); 3072 } 3073 3074 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3075 struct amdgpu_device *adev, int me, int pipe, 3076 enum amdgpu_interrupt_state state, int xcc_id) 3077 { 3078 u32 mec_int_cntl, mec_int_cntl_reg; 3079 3080 /* 3081 * amdgpu controls only the first MEC. That's why this function only 3082 * handles the setting of interrupts for this specific MEC. All other 3083 * pipes' interrupts are set by amdkfd. 3084 */ 3085 3086 if (me == 1) { 3087 switch (pipe) { 3088 case 0: 3089 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3090 break; 3091 case 1: 3092 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3093 break; 3094 case 2: 3095 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3096 break; 3097 case 3: 3098 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3099 break; 3100 default: 3101 DRM_DEBUG("invalid pipe %d\n", pipe); 3102 return; 3103 } 3104 } else { 3105 DRM_DEBUG("invalid me %d\n", me); 3106 return; 3107 } 3108 3109 switch (state) { 3110 case AMDGPU_IRQ_STATE_DISABLE: 3111 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3112 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3113 TIME_STAMP_INT_ENABLE, 0); 3114 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3115 break; 3116 case AMDGPU_IRQ_STATE_ENABLE: 3117 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3118 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3119 TIME_STAMP_INT_ENABLE, 1); 3120 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3121 break; 3122 default: 3123 break; 3124 } 3125 } 3126 3127 static u32 gfx_v9_4_3_get_cpc_int_cntl(struct amdgpu_device *adev, 3128 int xcc_id, int me, int pipe) 3129 { 3130 /* 3131 * amdgpu controls only the first MEC. That's why this function only 3132 * handles the setting of interrupts for this specific MEC. All other 3133 * pipes' interrupts are set by amdkfd. 3134 */ 3135 if (me != 1) 3136 return 0; 3137 3138 switch (pipe) { 3139 case 0: 3140 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 3141 case 1: 3142 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 3143 case 2: 3144 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 3145 case 3: 3146 return SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 3147 default: 3148 return 0; 3149 } 3150 } 3151 3152 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 3153 struct amdgpu_irq_src *source, 3154 unsigned type, 3155 enum amdgpu_interrupt_state state) 3156 { 3157 u32 mec_int_cntl_reg, mec_int_cntl; 3158 int i, j, k, num_xcc; 3159 3160 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3161 switch (state) { 3162 case AMDGPU_IRQ_STATE_DISABLE: 3163 case AMDGPU_IRQ_STATE_ENABLE: 3164 for (i = 0; i < num_xcc; i++) { 3165 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3166 PRIV_REG_INT_ENABLE, 3167 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3168 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3169 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3170 /* MECs start at 1 */ 3171 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3172 3173 if (mec_int_cntl_reg) { 3174 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3175 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3176 PRIV_REG_INT_ENABLE, 3177 state == AMDGPU_IRQ_STATE_ENABLE ? 3178 1 : 0); 3179 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3180 } 3181 } 3182 } 3183 } 3184 break; 3185 default: 3186 break; 3187 } 3188 3189 return 0; 3190 } 3191 3192 static int gfx_v9_4_3_set_bad_op_fault_state(struct amdgpu_device *adev, 3193 struct amdgpu_irq_src *source, 3194 unsigned type, 3195 enum amdgpu_interrupt_state state) 3196 { 3197 u32 mec_int_cntl_reg, mec_int_cntl; 3198 int i, j, k, num_xcc; 3199 3200 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3201 switch (state) { 3202 case AMDGPU_IRQ_STATE_DISABLE: 3203 case AMDGPU_IRQ_STATE_ENABLE: 3204 for (i = 0; i < num_xcc; i++) { 3205 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3206 OPCODE_ERROR_INT_ENABLE, 3207 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3208 for (j = 0; j < adev->gfx.mec.num_mec; j++) { 3209 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 3210 /* MECs start at 1 */ 3211 mec_int_cntl_reg = gfx_v9_4_3_get_cpc_int_cntl(adev, i, j + 1, k); 3212 3213 if (mec_int_cntl_reg) { 3214 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, i); 3215 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3216 OPCODE_ERROR_INT_ENABLE, 3217 state == AMDGPU_IRQ_STATE_ENABLE ? 3218 1 : 0); 3219 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, i); 3220 } 3221 } 3222 } 3223 } 3224 break; 3225 default: 3226 break; 3227 } 3228 3229 return 0; 3230 } 3231 3232 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 3233 struct amdgpu_irq_src *source, 3234 unsigned type, 3235 enum amdgpu_interrupt_state state) 3236 { 3237 int i, num_xcc; 3238 3239 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3240 switch (state) { 3241 case AMDGPU_IRQ_STATE_DISABLE: 3242 case AMDGPU_IRQ_STATE_ENABLE: 3243 for (i = 0; i < num_xcc; i++) 3244 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3245 PRIV_INSTR_INT_ENABLE, 3246 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3247 break; 3248 default: 3249 break; 3250 } 3251 3252 return 0; 3253 } 3254 3255 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 3256 struct amdgpu_irq_src *src, 3257 unsigned type, 3258 enum amdgpu_interrupt_state state) 3259 { 3260 int i, num_xcc; 3261 3262 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3263 for (i = 0; i < num_xcc; i++) { 3264 switch (type) { 3265 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3266 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3267 adev, 1, 0, state, i); 3268 break; 3269 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3270 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3271 adev, 1, 1, state, i); 3272 break; 3273 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3274 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3275 adev, 1, 2, state, i); 3276 break; 3277 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3278 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3279 adev, 1, 3, state, i); 3280 break; 3281 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 3282 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3283 adev, 2, 0, state, i); 3284 break; 3285 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 3286 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3287 adev, 2, 1, state, i); 3288 break; 3289 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 3290 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3291 adev, 2, 2, state, i); 3292 break; 3293 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 3294 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 3295 adev, 2, 3, state, i); 3296 break; 3297 default: 3298 break; 3299 } 3300 } 3301 3302 return 0; 3303 } 3304 3305 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 3306 struct amdgpu_irq_src *source, 3307 struct amdgpu_iv_entry *entry) 3308 { 3309 int i, xcc_id; 3310 u8 me_id, pipe_id, queue_id; 3311 struct amdgpu_ring *ring; 3312 3313 DRM_DEBUG("IH: CP EOP\n"); 3314 me_id = (entry->ring_id & 0x0c) >> 2; 3315 pipe_id = (entry->ring_id & 0x03) >> 0; 3316 queue_id = (entry->ring_id & 0x70) >> 4; 3317 3318 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3319 3320 if (xcc_id == -EINVAL) 3321 return -EINVAL; 3322 3323 switch (me_id) { 3324 case 0: 3325 case 1: 3326 case 2: 3327 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3328 ring = &adev->gfx.compute_ring 3329 [i + 3330 xcc_id * adev->gfx.num_compute_rings]; 3331 /* Per-queue interrupt is supported for MEC starting from VI. 3332 * The interrupt can only be enabled/disabled per pipe instead of per queue. 3333 */ 3334 3335 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 3336 amdgpu_fence_process(ring); 3337 } 3338 break; 3339 } 3340 return 0; 3341 } 3342 3343 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 3344 struct amdgpu_iv_entry *entry) 3345 { 3346 u8 me_id, pipe_id, queue_id; 3347 struct amdgpu_ring *ring; 3348 int i, xcc_id; 3349 3350 me_id = (entry->ring_id & 0x0c) >> 2; 3351 pipe_id = (entry->ring_id & 0x03) >> 0; 3352 queue_id = (entry->ring_id & 0x70) >> 4; 3353 3354 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 3355 3356 if (xcc_id == -EINVAL) 3357 return; 3358 3359 switch (me_id) { 3360 case 0: 3361 case 1: 3362 case 2: 3363 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3364 ring = &adev->gfx.compute_ring 3365 [i + 3366 xcc_id * adev->gfx.num_compute_rings]; 3367 if (ring->me == me_id && ring->pipe == pipe_id && 3368 ring->queue == queue_id) 3369 drm_sched_fault(&ring->sched); 3370 } 3371 break; 3372 } 3373 } 3374 3375 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 3376 struct amdgpu_irq_src *source, 3377 struct amdgpu_iv_entry *entry) 3378 { 3379 DRM_ERROR("Illegal register access in command stream\n"); 3380 gfx_v9_4_3_fault(adev, entry); 3381 return 0; 3382 } 3383 3384 static int gfx_v9_4_3_bad_op_irq(struct amdgpu_device *adev, 3385 struct amdgpu_irq_src *source, 3386 struct amdgpu_iv_entry *entry) 3387 { 3388 DRM_ERROR("Illegal opcode in command stream\n"); 3389 gfx_v9_4_3_fault(adev, entry); 3390 return 0; 3391 } 3392 3393 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 3394 struct amdgpu_irq_src *source, 3395 struct amdgpu_iv_entry *entry) 3396 { 3397 DRM_ERROR("Illegal instruction in command stream\n"); 3398 gfx_v9_4_3_fault(adev, entry); 3399 return 0; 3400 } 3401 3402 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3403 { 3404 const unsigned int cp_coher_cntl = 3405 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3406 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3407 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3408 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3409 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3410 3411 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3412 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3413 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3414 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3415 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3416 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3417 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3418 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3419 } 3420 3421 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3422 uint32_t pipe, bool enable) 3423 { 3424 struct amdgpu_device *adev = ring->adev; 3425 uint32_t val; 3426 uint32_t wcl_cs_reg; 3427 3428 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3429 val = enable ? 0x1 : 0x7f; 3430 3431 switch (pipe) { 3432 case 0: 3433 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3434 break; 3435 case 1: 3436 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3437 break; 3438 case 2: 3439 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3440 break; 3441 case 3: 3442 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3443 break; 3444 default: 3445 DRM_DEBUG("invalid pipe %d\n", pipe); 3446 return; 3447 } 3448 3449 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3450 3451 } 3452 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3453 { 3454 struct amdgpu_device *adev = ring->adev; 3455 uint32_t val; 3456 int i; 3457 3458 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3459 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3460 * around 25% of gpu resources. 3461 */ 3462 val = enable ? 0x1f : 0x07ffffff; 3463 amdgpu_ring_emit_wreg(ring, 3464 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3465 val); 3466 3467 /* Restrict waves for normal/low priority compute queues as well 3468 * to get best QoS for high priority compute jobs. 3469 * 3470 * amdgpu controls only 1st ME(0-3 CS pipes). 3471 */ 3472 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3473 if (i != ring->pipe) 3474 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3475 3476 } 3477 } 3478 3479 static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, 3480 uint32_t pipe, uint32_t queue, 3481 uint32_t xcc_id) 3482 { 3483 int i, r; 3484 /* make sure dequeue is complete*/ 3485 gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); 3486 mutex_lock(&adev->srbm_mutex); 3487 soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); 3488 for (i = 0; i < adev->usec_timeout; i++) { 3489 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 3490 break; 3491 udelay(1); 3492 } 3493 if (i >= adev->usec_timeout) 3494 r = -ETIMEDOUT; 3495 else 3496 r = 0; 3497 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 3498 mutex_unlock(&adev->srbm_mutex); 3499 gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); 3500 3501 return r; 3502 3503 } 3504 3505 static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) 3506 { 3507 /*TODO: Need check gfx9.4.4 mec fw whether supports pipe reset as well.*/ 3508 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && 3509 adev->gfx.mec_fw_version >= 0x0000009b) 3510 return true; 3511 else 3512 dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); 3513 3514 return false; 3515 } 3516 3517 static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) 3518 { 3519 struct amdgpu_device *adev = ring->adev; 3520 uint32_t reset_pipe, clean_pipe; 3521 int r; 3522 3523 if (!gfx_v9_4_3_pipe_reset_support(adev)) 3524 return -EINVAL; 3525 3526 gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); 3527 mutex_lock(&adev->srbm_mutex); 3528 3529 reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); 3530 clean_pipe = reset_pipe; 3531 3532 if (ring->me == 1) { 3533 switch (ring->pipe) { 3534 case 0: 3535 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3536 MEC_ME1_PIPE0_RESET, 1); 3537 break; 3538 case 1: 3539 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3540 MEC_ME1_PIPE1_RESET, 1); 3541 break; 3542 case 2: 3543 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3544 MEC_ME1_PIPE2_RESET, 1); 3545 break; 3546 case 3: 3547 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3548 MEC_ME1_PIPE3_RESET, 1); 3549 break; 3550 default: 3551 break; 3552 } 3553 } else { 3554 if (ring->pipe) 3555 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3556 MEC_ME2_PIPE1_RESET, 1); 3557 else 3558 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, 3559 MEC_ME2_PIPE0_RESET, 1); 3560 } 3561 3562 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); 3563 WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); 3564 mutex_unlock(&adev->srbm_mutex); 3565 gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); 3566 3567 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3568 return r; 3569 } 3570 3571 static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, 3572 unsigned int vmid) 3573 { 3574 struct amdgpu_device *adev = ring->adev; 3575 struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; 3576 struct amdgpu_ring *kiq_ring = &kiq->ring; 3577 unsigned long flags; 3578 int r; 3579 3580 if (amdgpu_sriov_vf(adev)) 3581 return -EINVAL; 3582 3583 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3584 return -EINVAL; 3585 3586 spin_lock_irqsave(&kiq->ring_lock, flags); 3587 3588 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 3589 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3590 return -ENOMEM; 3591 } 3592 3593 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 3594 0, 0); 3595 amdgpu_ring_commit(kiq_ring); 3596 3597 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3598 3599 r = amdgpu_ring_test_ring(kiq_ring); 3600 if (r) { 3601 dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", 3602 ring->name); 3603 goto pipe_reset; 3604 } 3605 3606 r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); 3607 if (r) 3608 dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); 3609 3610 pipe_reset: 3611 if(r) { 3612 r = gfx_v9_4_3_reset_hw_pipe(ring); 3613 dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, 3614 r ? "failed" : "successfully"); 3615 if (r) 3616 return r; 3617 } 3618 3619 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3620 if (unlikely(r != 0)){ 3621 dev_err(adev->dev, "fail to resv mqd_obj\n"); 3622 return r; 3623 } 3624 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3625 if (!r) { 3626 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); 3627 amdgpu_bo_kunmap(ring->mqd_obj); 3628 ring->mqd_ptr = NULL; 3629 } 3630 amdgpu_bo_unreserve(ring->mqd_obj); 3631 if (r) { 3632 dev_err(adev->dev, "fail to unresv mqd_obj\n"); 3633 return r; 3634 } 3635 spin_lock_irqsave(&kiq->ring_lock, flags); 3636 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 3637 if (r) { 3638 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3639 return -ENOMEM; 3640 } 3641 kiq->pmf->kiq_map_queues(kiq_ring, ring); 3642 amdgpu_ring_commit(kiq_ring); 3643 spin_unlock_irqrestore(&kiq->ring_lock, flags); 3644 3645 r = amdgpu_ring_test_ring(kiq_ring); 3646 if (r) { 3647 dev_err(adev->dev, "fail to remap queue\n"); 3648 return r; 3649 } 3650 return amdgpu_ring_test_ring(ring); 3651 } 3652 3653 enum amdgpu_gfx_cp_ras_mem_id { 3654 AMDGPU_GFX_CP_MEM1 = 1, 3655 AMDGPU_GFX_CP_MEM2, 3656 AMDGPU_GFX_CP_MEM3, 3657 AMDGPU_GFX_CP_MEM4, 3658 AMDGPU_GFX_CP_MEM5, 3659 }; 3660 3661 enum amdgpu_gfx_gcea_ras_mem_id { 3662 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3663 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3664 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3665 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3666 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3667 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3668 AMDGPU_GFX_GCEA_MAM_DMEM0, 3669 AMDGPU_GFX_GCEA_MAM_DMEM1, 3670 AMDGPU_GFX_GCEA_MAM_DMEM2, 3671 AMDGPU_GFX_GCEA_MAM_DMEM3, 3672 AMDGPU_GFX_GCEA_MAM_AMEM0, 3673 AMDGPU_GFX_GCEA_MAM_AMEM1, 3674 AMDGPU_GFX_GCEA_MAM_AMEM2, 3675 AMDGPU_GFX_GCEA_MAM_AMEM3, 3676 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3677 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3678 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3679 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3680 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3681 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3682 }; 3683 3684 enum amdgpu_gfx_gc_cane_ras_mem_id { 3685 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3686 }; 3687 3688 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3689 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3690 }; 3691 3692 enum amdgpu_gfx_gds_ras_mem_id { 3693 AMDGPU_GFX_GDS_MEM0 = 0, 3694 }; 3695 3696 enum amdgpu_gfx_lds_ras_mem_id { 3697 AMDGPU_GFX_LDS_BANK0 = 0, 3698 AMDGPU_GFX_LDS_BANK1, 3699 AMDGPU_GFX_LDS_BANK2, 3700 AMDGPU_GFX_LDS_BANK3, 3701 AMDGPU_GFX_LDS_BANK4, 3702 AMDGPU_GFX_LDS_BANK5, 3703 AMDGPU_GFX_LDS_BANK6, 3704 AMDGPU_GFX_LDS_BANK7, 3705 AMDGPU_GFX_LDS_BANK8, 3706 AMDGPU_GFX_LDS_BANK9, 3707 AMDGPU_GFX_LDS_BANK10, 3708 AMDGPU_GFX_LDS_BANK11, 3709 AMDGPU_GFX_LDS_BANK12, 3710 AMDGPU_GFX_LDS_BANK13, 3711 AMDGPU_GFX_LDS_BANK14, 3712 AMDGPU_GFX_LDS_BANK15, 3713 AMDGPU_GFX_LDS_BANK16, 3714 AMDGPU_GFX_LDS_BANK17, 3715 AMDGPU_GFX_LDS_BANK18, 3716 AMDGPU_GFX_LDS_BANK19, 3717 AMDGPU_GFX_LDS_BANK20, 3718 AMDGPU_GFX_LDS_BANK21, 3719 AMDGPU_GFX_LDS_BANK22, 3720 AMDGPU_GFX_LDS_BANK23, 3721 AMDGPU_GFX_LDS_BANK24, 3722 AMDGPU_GFX_LDS_BANK25, 3723 AMDGPU_GFX_LDS_BANK26, 3724 AMDGPU_GFX_LDS_BANK27, 3725 AMDGPU_GFX_LDS_BANK28, 3726 AMDGPU_GFX_LDS_BANK29, 3727 AMDGPU_GFX_LDS_BANK30, 3728 AMDGPU_GFX_LDS_BANK31, 3729 AMDGPU_GFX_LDS_SP_BUFFER_A, 3730 AMDGPU_GFX_LDS_SP_BUFFER_B, 3731 }; 3732 3733 enum amdgpu_gfx_rlc_ras_mem_id { 3734 AMDGPU_GFX_RLC_GPMF32 = 1, 3735 AMDGPU_GFX_RLC_RLCVF32, 3736 AMDGPU_GFX_RLC_SCRATCH, 3737 AMDGPU_GFX_RLC_SRM_ARAM, 3738 AMDGPU_GFX_RLC_SRM_DRAM, 3739 AMDGPU_GFX_RLC_TCTAG, 3740 AMDGPU_GFX_RLC_SPM_SE, 3741 AMDGPU_GFX_RLC_SPM_GRBMT, 3742 }; 3743 3744 enum amdgpu_gfx_sp_ras_mem_id { 3745 AMDGPU_GFX_SP_SIMDID0 = 0, 3746 }; 3747 3748 enum amdgpu_gfx_spi_ras_mem_id { 3749 AMDGPU_GFX_SPI_MEM0 = 0, 3750 AMDGPU_GFX_SPI_MEM1, 3751 AMDGPU_GFX_SPI_MEM2, 3752 AMDGPU_GFX_SPI_MEM3, 3753 }; 3754 3755 enum amdgpu_gfx_sqc_ras_mem_id { 3756 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3757 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3758 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3759 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3760 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3761 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3762 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3763 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3764 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3765 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3766 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3767 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3768 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3769 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3770 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3771 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3772 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3773 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3774 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3775 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3776 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3777 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3778 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3779 }; 3780 3781 enum amdgpu_gfx_sq_ras_mem_id { 3782 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3783 AMDGPU_GFX_SQ_SGPR_MEM1, 3784 AMDGPU_GFX_SQ_SGPR_MEM2, 3785 AMDGPU_GFX_SQ_SGPR_MEM3, 3786 }; 3787 3788 enum amdgpu_gfx_ta_ras_mem_id { 3789 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3790 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3791 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3792 AMDGPU_GFX_TA_FSX_LFIFO, 3793 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3794 }; 3795 3796 enum amdgpu_gfx_tcc_ras_mem_id { 3797 AMDGPU_GFX_TCC_MEM1 = 1, 3798 }; 3799 3800 enum amdgpu_gfx_tca_ras_mem_id { 3801 AMDGPU_GFX_TCA_MEM1 = 1, 3802 }; 3803 3804 enum amdgpu_gfx_tci_ras_mem_id { 3805 AMDGPU_GFX_TCIW_MEM = 1, 3806 }; 3807 3808 enum amdgpu_gfx_tcp_ras_mem_id { 3809 AMDGPU_GFX_TCP_LFIFO0 = 1, 3810 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3811 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3812 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3813 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3814 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3815 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3816 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3817 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3818 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3819 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3820 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3821 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3822 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3823 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3824 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3825 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3826 AMDGPU_GFX_TCP_VM_FIFO, 3827 AMDGPU_GFX_TCP_DB_TAGRAM0, 3828 AMDGPU_GFX_TCP_DB_TAGRAM1, 3829 AMDGPU_GFX_TCP_DB_TAGRAM2, 3830 AMDGPU_GFX_TCP_DB_TAGRAM3, 3831 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3832 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3833 AMDGPU_GFX_TCP_CMD_FIFO, 3834 }; 3835 3836 enum amdgpu_gfx_td_ras_mem_id { 3837 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3838 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3839 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3840 }; 3841 3842 enum amdgpu_gfx_tcx_ras_mem_id { 3843 AMDGPU_GFX_TCX_FIFOD0 = 0, 3844 AMDGPU_GFX_TCX_FIFOD1, 3845 AMDGPU_GFX_TCX_FIFOD2, 3846 AMDGPU_GFX_TCX_FIFOD3, 3847 AMDGPU_GFX_TCX_FIFOD4, 3848 AMDGPU_GFX_TCX_FIFOD5, 3849 AMDGPU_GFX_TCX_FIFOD6, 3850 AMDGPU_GFX_TCX_FIFOD7, 3851 AMDGPU_GFX_TCX_FIFOB0, 3852 AMDGPU_GFX_TCX_FIFOB1, 3853 AMDGPU_GFX_TCX_FIFOB2, 3854 AMDGPU_GFX_TCX_FIFOB3, 3855 AMDGPU_GFX_TCX_FIFOB4, 3856 AMDGPU_GFX_TCX_FIFOB5, 3857 AMDGPU_GFX_TCX_FIFOB6, 3858 AMDGPU_GFX_TCX_FIFOB7, 3859 AMDGPU_GFX_TCX_FIFOA0, 3860 AMDGPU_GFX_TCX_FIFOA1, 3861 AMDGPU_GFX_TCX_FIFOA2, 3862 AMDGPU_GFX_TCX_FIFOA3, 3863 AMDGPU_GFX_TCX_FIFOA4, 3864 AMDGPU_GFX_TCX_FIFOA5, 3865 AMDGPU_GFX_TCX_FIFOA6, 3866 AMDGPU_GFX_TCX_FIFOA7, 3867 AMDGPU_GFX_TCX_CFIFO0, 3868 AMDGPU_GFX_TCX_CFIFO1, 3869 AMDGPU_GFX_TCX_CFIFO2, 3870 AMDGPU_GFX_TCX_CFIFO3, 3871 AMDGPU_GFX_TCX_CFIFO4, 3872 AMDGPU_GFX_TCX_CFIFO5, 3873 AMDGPU_GFX_TCX_CFIFO6, 3874 AMDGPU_GFX_TCX_CFIFO7, 3875 AMDGPU_GFX_TCX_FIFO_ACKB0, 3876 AMDGPU_GFX_TCX_FIFO_ACKB1, 3877 AMDGPU_GFX_TCX_FIFO_ACKB2, 3878 AMDGPU_GFX_TCX_FIFO_ACKB3, 3879 AMDGPU_GFX_TCX_FIFO_ACKB4, 3880 AMDGPU_GFX_TCX_FIFO_ACKB5, 3881 AMDGPU_GFX_TCX_FIFO_ACKB6, 3882 AMDGPU_GFX_TCX_FIFO_ACKB7, 3883 AMDGPU_GFX_TCX_FIFO_ACKD0, 3884 AMDGPU_GFX_TCX_FIFO_ACKD1, 3885 AMDGPU_GFX_TCX_FIFO_ACKD2, 3886 AMDGPU_GFX_TCX_FIFO_ACKD3, 3887 AMDGPU_GFX_TCX_FIFO_ACKD4, 3888 AMDGPU_GFX_TCX_FIFO_ACKD5, 3889 AMDGPU_GFX_TCX_FIFO_ACKD6, 3890 AMDGPU_GFX_TCX_FIFO_ACKD7, 3891 AMDGPU_GFX_TCX_DST_FIFOA0, 3892 AMDGPU_GFX_TCX_DST_FIFOA1, 3893 AMDGPU_GFX_TCX_DST_FIFOA2, 3894 AMDGPU_GFX_TCX_DST_FIFOA3, 3895 AMDGPU_GFX_TCX_DST_FIFOA4, 3896 AMDGPU_GFX_TCX_DST_FIFOA5, 3897 AMDGPU_GFX_TCX_DST_FIFOA6, 3898 AMDGPU_GFX_TCX_DST_FIFOA7, 3899 AMDGPU_GFX_TCX_DST_FIFOB0, 3900 AMDGPU_GFX_TCX_DST_FIFOB1, 3901 AMDGPU_GFX_TCX_DST_FIFOB2, 3902 AMDGPU_GFX_TCX_DST_FIFOB3, 3903 AMDGPU_GFX_TCX_DST_FIFOB4, 3904 AMDGPU_GFX_TCX_DST_FIFOB5, 3905 AMDGPU_GFX_TCX_DST_FIFOB6, 3906 AMDGPU_GFX_TCX_DST_FIFOB7, 3907 AMDGPU_GFX_TCX_DST_FIFOD0, 3908 AMDGPU_GFX_TCX_DST_FIFOD1, 3909 AMDGPU_GFX_TCX_DST_FIFOD2, 3910 AMDGPU_GFX_TCX_DST_FIFOD3, 3911 AMDGPU_GFX_TCX_DST_FIFOD4, 3912 AMDGPU_GFX_TCX_DST_FIFOD5, 3913 AMDGPU_GFX_TCX_DST_FIFOD6, 3914 AMDGPU_GFX_TCX_DST_FIFOD7, 3915 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3916 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3917 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3918 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3919 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3920 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3921 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3922 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3923 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3924 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3925 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3926 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3927 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3928 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3929 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3930 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3931 }; 3932 3933 enum amdgpu_gfx_atc_l2_ras_mem_id { 3934 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3935 }; 3936 3937 enum amdgpu_gfx_utcl2_ras_mem_id { 3938 AMDGPU_GFX_UTCL2_MEM0 = 0, 3939 }; 3940 3941 enum amdgpu_gfx_vml2_ras_mem_id { 3942 AMDGPU_GFX_VML2_MEM0 = 0, 3943 }; 3944 3945 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3946 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3947 }; 3948 3949 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3950 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3951 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3952 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3953 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3954 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3955 }; 3956 3957 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3958 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3959 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3960 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3961 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3962 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3963 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3964 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3965 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3966 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3967 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3968 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3969 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3970 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3971 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3972 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3973 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3974 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3975 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3976 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3977 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3978 }; 3979 3980 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3981 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3982 }; 3983 3984 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3985 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3986 }; 3987 3988 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3989 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3990 }; 3991 3992 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3993 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3994 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3995 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3996 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3997 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3998 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3999 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 4000 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 4001 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 4002 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 4003 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 4004 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 4005 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 4006 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 4007 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 4008 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 4009 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 4010 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 4011 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 4012 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 4013 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 4014 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 4015 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 4016 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 4017 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 4018 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 4019 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 4020 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 4021 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 4022 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 4023 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 4024 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 4025 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 4026 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 4027 }; 4028 4029 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 4030 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 4031 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 4032 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 4033 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 4034 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 4035 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 4036 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 4037 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 4038 }; 4039 4040 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 4041 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 4042 }; 4043 4044 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 4045 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 4046 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 4047 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 4048 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 4049 }; 4050 4051 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 4052 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 4053 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 4054 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 4055 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 4056 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 4057 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 4058 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 4059 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 4060 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 4061 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 4062 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 4063 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 4064 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 4065 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 4066 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 4067 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 4068 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 4069 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 4070 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 4071 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 4072 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 4073 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 4074 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 4075 }; 4076 4077 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 4078 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 4079 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 4080 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 4081 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 4082 }; 4083 4084 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 4085 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 4086 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 4087 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 4088 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 4089 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 4090 }; 4091 4092 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 4093 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 4094 }; 4095 4096 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 4097 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 4098 }; 4099 4100 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 4101 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 4102 }; 4103 4104 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 4105 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 4106 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 4107 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 4108 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 4109 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 4110 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 4111 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 4112 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 4113 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 4114 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 4115 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 4116 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 4117 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 4118 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 4119 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 4120 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 4121 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 4122 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 4123 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 4124 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 4125 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 4126 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 4127 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 4128 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 4129 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 4130 }; 4131 4132 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 4133 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 4134 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 4135 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 4136 }; 4137 4138 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 4139 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 4140 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 4141 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 4142 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 4143 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 4144 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 4145 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 4146 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 4147 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 4148 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 4149 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 4150 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 4151 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 4152 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 4153 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 4154 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 4155 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 4156 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 4157 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 4158 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 4159 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 4160 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 4161 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 4162 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 4163 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 4164 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 4165 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 4166 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 4167 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 4168 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 4169 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 4170 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 4171 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 4172 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 4173 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 4174 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 4175 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 4176 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 4177 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 4178 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 4179 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 4180 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 4181 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 4182 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 4183 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 4184 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 4185 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 4186 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 4187 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 4188 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 4189 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 4190 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 4191 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 4192 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 4193 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 4194 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 4195 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 4196 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 4197 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 4198 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 4199 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 4200 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 4201 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 4202 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 4203 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 4204 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 4205 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 4206 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 4207 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 4208 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 4209 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 4210 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 4211 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 4212 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 4213 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 4214 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 4215 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 4216 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 4217 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 4218 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 4219 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 4220 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 4221 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 4222 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 4223 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 4224 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 4225 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 4226 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 4227 }; 4228 4229 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 4230 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 4231 }; 4232 4233 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 4234 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 4235 }; 4236 4237 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 4238 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 4239 }; 4240 4241 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 4242 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 4243 }; 4244 4245 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 4246 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 4247 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 4248 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 4249 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 4250 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 4251 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 4252 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 4253 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 4254 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 4255 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 4256 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 4257 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 4258 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 4259 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 4260 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 4261 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 4262 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 4263 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 4264 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 4265 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 4266 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 4267 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 4268 }; 4269 4270 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 4271 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 4272 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4273 AMDGPU_GFX_RLC_MEM, 1}, 4274 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 4275 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4276 AMDGPU_GFX_CP_MEM, 1}, 4277 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 4278 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4279 AMDGPU_GFX_CP_MEM, 1}, 4280 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 4281 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4282 AMDGPU_GFX_CP_MEM, 1}, 4283 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 4284 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4285 AMDGPU_GFX_GDS_MEM, 1}, 4286 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 4287 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4288 AMDGPU_GFX_GC_CANE_MEM, 1}, 4289 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 4290 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4291 AMDGPU_GFX_SPI_MEM, 1}, 4292 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 4293 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4294 AMDGPU_GFX_SP_MEM, 4}, 4295 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 4296 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4297 AMDGPU_GFX_SP_MEM, 4}, 4298 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 4299 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4300 AMDGPU_GFX_SQ_MEM, 4}, 4301 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 4302 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4303 AMDGPU_GFX_SQC_MEM, 4}, 4304 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 4305 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4306 AMDGPU_GFX_TCX_MEM, 1}, 4307 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 4308 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4309 AMDGPU_GFX_TCC_MEM, 1}, 4310 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 4311 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4312 AMDGPU_GFX_TA_MEM, 4}, 4313 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 4314 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4315 AMDGPU_GFX_TCI_MEM, 1}, 4316 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 4317 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4318 AMDGPU_GFX_TCP_MEM, 4}, 4319 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 4320 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4321 AMDGPU_GFX_TD_MEM, 4}, 4322 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 4323 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4324 AMDGPU_GFX_GCEA_MEM, 1}, 4325 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 4326 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4327 AMDGPU_GFX_LDS_MEM, 4}, 4328 }; 4329 4330 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 4331 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 4332 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 4333 AMDGPU_GFX_RLC_MEM, 1}, 4334 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 4335 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 4336 AMDGPU_GFX_CP_MEM, 1}, 4337 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 4338 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 4339 AMDGPU_GFX_CP_MEM, 1}, 4340 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 4341 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 4342 AMDGPU_GFX_CP_MEM, 1}, 4343 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 4344 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 4345 AMDGPU_GFX_GDS_MEM, 1}, 4346 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 4347 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 4348 AMDGPU_GFX_GC_CANE_MEM, 1}, 4349 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 4350 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 4351 AMDGPU_GFX_SPI_MEM, 1}, 4352 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 4353 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 4354 AMDGPU_GFX_SP_MEM, 4}, 4355 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 4356 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 4357 AMDGPU_GFX_SP_MEM, 4}, 4358 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 4359 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 4360 AMDGPU_GFX_SQ_MEM, 4}, 4361 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 4362 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 4363 AMDGPU_GFX_SQC_MEM, 4}, 4364 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 4365 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 4366 AMDGPU_GFX_TCX_MEM, 1}, 4367 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 4368 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 4369 AMDGPU_GFX_TCC_MEM, 1}, 4370 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 4371 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 4372 AMDGPU_GFX_TA_MEM, 4}, 4373 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 4374 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 4375 AMDGPU_GFX_TCI_MEM, 1}, 4376 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 4377 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 4378 AMDGPU_GFX_TCP_MEM, 4}, 4379 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 4380 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 4381 AMDGPU_GFX_TD_MEM, 4}, 4382 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 4383 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 4384 AMDGPU_GFX_TCA_MEM, 1}, 4385 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 4386 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 4387 AMDGPU_GFX_GCEA_MEM, 1}, 4388 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 4389 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 4390 AMDGPU_GFX_LDS_MEM, 4}, 4391 }; 4392 4393 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 4394 void *ras_error_status, int xcc_id) 4395 { 4396 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 4397 unsigned long ce_count = 0, ue_count = 0; 4398 uint32_t i, j, k; 4399 4400 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 4401 struct amdgpu_smuio_mcm_config_info mcm_info = { 4402 .socket_id = adev->smuio.funcs->get_socket_id(adev), 4403 .die_id = xcc_id & 0x01 ? 1 : 0, 4404 }; 4405 4406 mutex_lock(&adev->grbm_idx_mutex); 4407 4408 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4409 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4410 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4411 /* no need to select if instance number is 1 */ 4412 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4413 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4414 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4415 4416 amdgpu_ras_inst_query_ras_error_count(adev, 4417 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4418 1, 4419 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 4420 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 4421 GET_INST(GC, xcc_id), 4422 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 4423 &ce_count); 4424 4425 amdgpu_ras_inst_query_ras_error_count(adev, 4426 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4427 1, 4428 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4429 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4430 GET_INST(GC, xcc_id), 4431 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4432 &ue_count); 4433 } 4434 } 4435 } 4436 4437 /* handle extra register entries of UE */ 4438 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4439 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4440 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4441 /* no need to select if instance number is 1 */ 4442 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4443 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4444 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4445 4446 amdgpu_ras_inst_query_ras_error_count(adev, 4447 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4448 1, 4449 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 4450 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 4451 GET_INST(GC, xcc_id), 4452 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 4453 &ue_count); 4454 } 4455 } 4456 } 4457 4458 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4459 xcc_id); 4460 mutex_unlock(&adev->grbm_idx_mutex); 4461 4462 /* the caller should make sure initialize value of 4463 * err_data->ue_count and err_data->ce_count 4464 */ 4465 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, ue_count); 4466 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, ce_count); 4467 } 4468 4469 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 4470 void *ras_error_status, int xcc_id) 4471 { 4472 uint32_t i, j, k; 4473 4474 mutex_lock(&adev->grbm_idx_mutex); 4475 4476 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 4477 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 4478 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 4479 /* no need to select if instance number is 1 */ 4480 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 4481 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 4482 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4483 4484 amdgpu_ras_inst_reset_ras_error_count(adev, 4485 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 4486 1, 4487 GET_INST(GC, xcc_id)); 4488 4489 amdgpu_ras_inst_reset_ras_error_count(adev, 4490 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4491 1, 4492 GET_INST(GC, xcc_id)); 4493 } 4494 } 4495 } 4496 4497 /* handle extra register entries of UE */ 4498 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 4499 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 4500 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 4501 /* no need to select if instance number is 1 */ 4502 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 4503 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 4504 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 4505 4506 amdgpu_ras_inst_reset_ras_error_count(adev, 4507 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 4508 1, 4509 GET_INST(GC, xcc_id)); 4510 } 4511 } 4512 } 4513 4514 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4515 xcc_id); 4516 mutex_unlock(&adev->grbm_idx_mutex); 4517 } 4518 4519 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 4520 void *ras_error_status, int xcc_id) 4521 { 4522 uint32_t i; 4523 uint32_t data; 4524 4525 if (amdgpu_sriov_vf(adev)) 4526 return; 4527 4528 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 4529 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 4530 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 4531 4532 if (amdgpu_watchdog_timer.timeout_fatal_disable && 4533 (amdgpu_watchdog_timer.period < 1 || 4534 amdgpu_watchdog_timer.period > 0x23)) { 4535 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 4536 amdgpu_watchdog_timer.period = 0x23; 4537 } 4538 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 4539 amdgpu_watchdog_timer.period); 4540 4541 mutex_lock(&adev->grbm_idx_mutex); 4542 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4543 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 4544 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 4545 } 4546 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4547 xcc_id); 4548 mutex_unlock(&adev->grbm_idx_mutex); 4549 } 4550 4551 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 4552 void *ras_error_status) 4553 { 4554 amdgpu_gfx_ras_error_func(adev, ras_error_status, 4555 gfx_v9_4_3_inst_query_ras_err_count); 4556 } 4557 4558 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 4559 { 4560 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 4561 } 4562 4563 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 4564 { 4565 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 4566 } 4567 4568 static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) 4569 { 4570 /* Header itself is a NOP packet */ 4571 if (num_nop == 1) { 4572 amdgpu_ring_write(ring, ring->funcs->nop); 4573 return; 4574 } 4575 4576 /* Max HW optimization till 0x3ffe, followed by remaining one NOP at a time*/ 4577 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, min(num_nop - 2, 0x3ffe))); 4578 4579 /* Header is at index 0, followed by num_nops - 1 NOP packet's */ 4580 amdgpu_ring_insert_nop(ring, num_nop - 1); 4581 } 4582 4583 static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) 4584 { 4585 struct amdgpu_device *adev = ip_block->adev; 4586 uint32_t i, j, k; 4587 uint32_t xcc_id, xcc_offset, inst_offset; 4588 uint32_t num_xcc, reg, num_inst; 4589 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4590 4591 if (!adev->gfx.ip_dump_core) 4592 return; 4593 4594 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4595 drm_printf(p, "Number of Instances:%d\n", num_xcc); 4596 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4597 xcc_offset = xcc_id * reg_count; 4598 drm_printf(p, "\nInstance id:%d\n", xcc_id); 4599 for (i = 0; i < reg_count; i++) 4600 drm_printf(p, "%-50s \t 0x%08x\n", 4601 gc_reg_list_9_4_3[i].reg_name, 4602 adev->gfx.ip_dump_core[xcc_offset + i]); 4603 } 4604 4605 /* print compute queue registers for all instances */ 4606 if (!adev->gfx.ip_dump_compute_queues) 4607 return; 4608 4609 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4610 adev->gfx.mec.num_queue_per_pipe; 4611 4612 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4613 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 4614 num_xcc, 4615 adev->gfx.mec.num_mec, 4616 adev->gfx.mec.num_pipe_per_mec, 4617 adev->gfx.mec.num_queue_per_pipe); 4618 4619 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4620 xcc_offset = xcc_id * reg_count * num_inst; 4621 inst_offset = 0; 4622 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4623 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4624 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4625 drm_printf(p, 4626 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 4627 xcc_id, i, j, k); 4628 for (reg = 0; reg < reg_count; reg++) { 4629 drm_printf(p, 4630 "%-50s \t 0x%08x\n", 4631 gc_cp_reg_list_9_4_3[reg].reg_name, 4632 adev->gfx.ip_dump_compute_queues 4633 [xcc_offset + inst_offset + 4634 reg]); 4635 } 4636 inst_offset += reg_count; 4637 } 4638 } 4639 } 4640 } 4641 } 4642 4643 static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) 4644 { 4645 struct amdgpu_device *adev = ip_block->adev; 4646 uint32_t i, j, k; 4647 uint32_t num_xcc, reg, num_inst; 4648 uint32_t xcc_id, xcc_offset, inst_offset; 4649 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); 4650 4651 if (!adev->gfx.ip_dump_core) 4652 return; 4653 4654 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4655 4656 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4657 xcc_offset = xcc_id * reg_count; 4658 for (i = 0; i < reg_count; i++) 4659 adev->gfx.ip_dump_core[xcc_offset + i] = 4660 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_9_4_3[i], 4661 GET_INST(GC, xcc_id))); 4662 } 4663 4664 /* dump compute queue registers for all instances */ 4665 if (!adev->gfx.ip_dump_compute_queues) 4666 return; 4667 4668 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 4669 adev->gfx.mec.num_queue_per_pipe; 4670 reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); 4671 mutex_lock(&adev->srbm_mutex); 4672 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 4673 xcc_offset = xcc_id * reg_count * num_inst; 4674 inst_offset = 0; 4675 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 4676 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 4677 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 4678 /* ME0 is for GFX so start from 1 for CP */ 4679 soc15_grbm_select(adev, 1 + i, j, k, 0, 4680 GET_INST(GC, xcc_id)); 4681 4682 for (reg = 0; reg < reg_count; reg++) { 4683 adev->gfx.ip_dump_compute_queues 4684 [xcc_offset + 4685 inst_offset + reg] = 4686 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 4687 gc_cp_reg_list_9_4_3[reg], 4688 GET_INST(GC, xcc_id))); 4689 } 4690 inst_offset += reg_count; 4691 } 4692 } 4693 } 4694 } 4695 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 4696 mutex_unlock(&adev->srbm_mutex); 4697 } 4698 4699 static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) 4700 { 4701 /* Emit the cleaner shader */ 4702 amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); 4703 amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ 4704 } 4705 4706 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 4707 .name = "gfx_v9_4_3", 4708 .early_init = gfx_v9_4_3_early_init, 4709 .late_init = gfx_v9_4_3_late_init, 4710 .sw_init = gfx_v9_4_3_sw_init, 4711 .sw_fini = gfx_v9_4_3_sw_fini, 4712 .hw_init = gfx_v9_4_3_hw_init, 4713 .hw_fini = gfx_v9_4_3_hw_fini, 4714 .suspend = gfx_v9_4_3_suspend, 4715 .resume = gfx_v9_4_3_resume, 4716 .is_idle = gfx_v9_4_3_is_idle, 4717 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4718 .soft_reset = gfx_v9_4_3_soft_reset, 4719 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4720 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4721 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4722 .dump_ip_state = gfx_v9_4_3_ip_dump, 4723 .print_ip_state = gfx_v9_4_3_ip_print, 4724 }; 4725 4726 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4727 .type = AMDGPU_RING_TYPE_COMPUTE, 4728 .align_mask = 0xff, 4729 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4730 .support_64bit_ptrs = true, 4731 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4732 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4733 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4734 .emit_frame_size = 4735 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4736 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4737 5 + /* hdp invalidate */ 4738 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4739 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4740 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4741 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4742 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4743 7 + /* gfx_v9_4_3_emit_mem_sync */ 4744 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4745 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4746 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ 4747 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4748 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4749 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4750 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4751 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4752 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4753 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4754 .test_ring = gfx_v9_4_3_ring_test_ring, 4755 .test_ib = gfx_v9_4_3_ring_test_ib, 4756 .insert_nop = gfx_v9_4_3_ring_insert_nop, 4757 .pad_ib = amdgpu_ring_generic_pad_ib, 4758 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4759 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4760 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4761 .soft_recovery = gfx_v9_4_3_ring_soft_recovery, 4762 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4763 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4764 .reset = gfx_v9_4_3_reset_kcq, 4765 .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, 4766 .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, 4767 .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, 4768 }; 4769 4770 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4771 .type = AMDGPU_RING_TYPE_KIQ, 4772 .align_mask = 0xff, 4773 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4774 .support_64bit_ptrs = true, 4775 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4776 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4777 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4778 .emit_frame_size = 4779 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4780 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4781 5 + /* hdp invalidate */ 4782 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4783 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4784 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4785 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4786 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4787 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4788 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4789 .test_ring = gfx_v9_4_3_ring_test_ring, 4790 .insert_nop = amdgpu_ring_insert_nop, 4791 .pad_ib = amdgpu_ring_generic_pad_ib, 4792 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4793 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4794 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4795 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4796 }; 4797 4798 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4799 { 4800 int i, j, num_xcc; 4801 4802 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4803 for (i = 0; i < num_xcc; i++) { 4804 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4805 4806 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4807 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4808 = &gfx_v9_4_3_ring_funcs_compute; 4809 } 4810 } 4811 4812 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4813 .set = gfx_v9_4_3_set_eop_interrupt_state, 4814 .process = gfx_v9_4_3_eop_irq, 4815 }; 4816 4817 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4818 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4819 .process = gfx_v9_4_3_priv_reg_irq, 4820 }; 4821 4822 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_bad_op_irq_funcs = { 4823 .set = gfx_v9_4_3_set_bad_op_fault_state, 4824 .process = gfx_v9_4_3_bad_op_irq, 4825 }; 4826 4827 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4828 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4829 .process = gfx_v9_4_3_priv_inst_irq, 4830 }; 4831 4832 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4833 { 4834 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4835 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4836 4837 adev->gfx.priv_reg_irq.num_types = 1; 4838 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4839 4840 adev->gfx.bad_op_irq.num_types = 1; 4841 adev->gfx.bad_op_irq.funcs = &gfx_v9_4_3_bad_op_irq_funcs; 4842 4843 adev->gfx.priv_inst_irq.num_types = 1; 4844 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4845 } 4846 4847 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4848 { 4849 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4850 } 4851 4852 4853 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4854 { 4855 /* 9.4.3 variants removed all the GDS internal memory, 4856 * only support GWS opcode in kernel, like barrier 4857 * semaphore.etc */ 4858 4859 /* init asic gds info */ 4860 adev->gds.gds_size = 0; 4861 adev->gds.gds_compute_max_wave_id = 0; 4862 adev->gds.gws_size = 64; 4863 adev->gds.oa_size = 16; 4864 } 4865 4866 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4867 u32 bitmap, int xcc_id) 4868 { 4869 u32 data; 4870 4871 if (!bitmap) 4872 return; 4873 4874 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4875 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4876 4877 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4878 } 4879 4880 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4881 { 4882 u32 data, mask; 4883 4884 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4885 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4886 4887 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4888 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4889 4890 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4891 4892 return (~data) & mask; 4893 } 4894 4895 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4896 struct amdgpu_cu_info *cu_info) 4897 { 4898 int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0; 4899 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp; 4900 unsigned disable_masks[4 * 4]; 4901 bool is_symmetric_cus; 4902 4903 if (!adev || !cu_info) 4904 return -EINVAL; 4905 4906 /* 4907 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4908 */ 4909 if (adev->gfx.config.max_shader_engines * 4910 adev->gfx.config.max_sh_per_se > 16) 4911 return -EINVAL; 4912 4913 amdgpu_gfx_parse_disable_cu(disable_masks, 4914 adev->gfx.config.max_shader_engines, 4915 adev->gfx.config.max_sh_per_se); 4916 4917 mutex_lock(&adev->grbm_idx_mutex); 4918 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4919 is_symmetric_cus = true; 4920 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4921 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4922 mask = 1; 4923 ao_bitmap = 0; 4924 counter = 0; 4925 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4926 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4927 adev, 4928 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4929 xcc_id); 4930 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4931 4932 cu_info->bitmap[xcc_id][i][j] = bitmap; 4933 4934 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4935 if (bitmap & mask) { 4936 if (counter < adev->gfx.config.max_cu_per_sh) 4937 ao_bitmap |= mask; 4938 counter++; 4939 } 4940 mask <<= 1; 4941 } 4942 active_cu_number += counter; 4943 if (i < 2 && j < 2) 4944 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4945 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4946 } 4947 if (i && is_symmetric_cus && prev_counter != counter) 4948 is_symmetric_cus = false; 4949 prev_counter = counter; 4950 } 4951 if (is_symmetric_cus) { 4952 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG); 4953 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1); 4954 tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1); 4955 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp); 4956 } 4957 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4958 xcc_id); 4959 } 4960 mutex_unlock(&adev->grbm_idx_mutex); 4961 4962 cu_info->number = active_cu_number; 4963 cu_info->ao_cu_mask = ao_cu_mask; 4964 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4965 4966 return 0; 4967 } 4968 4969 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4970 .type = AMD_IP_BLOCK_TYPE_GFX, 4971 .major = 9, 4972 .minor = 4, 4973 .rev = 3, 4974 .funcs = &gfx_v9_4_3_ip_funcs, 4975 }; 4976 4977 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4978 { 4979 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4980 uint32_t tmp_mask; 4981 int i, r; 4982 4983 /* TODO : Initialize golden regs */ 4984 /* gfx_v9_4_3_init_golden_registers(adev); */ 4985 4986 tmp_mask = inst_mask; 4987 for_each_inst(i, tmp_mask) 4988 gfx_v9_4_3_xcc_constants_init(adev, i); 4989 4990 if (!amdgpu_sriov_vf(adev)) { 4991 tmp_mask = inst_mask; 4992 for_each_inst(i, tmp_mask) { 4993 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4994 if (r) 4995 return r; 4996 } 4997 } 4998 4999 tmp_mask = inst_mask; 5000 for_each_inst(i, tmp_mask) { 5001 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 5002 if (r) 5003 return r; 5004 } 5005 5006 return 0; 5007 } 5008 5009 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 5010 { 5011 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5012 int i; 5013 5014 for_each_inst(i, inst_mask) 5015 gfx_v9_4_3_xcc_fini(adev, i); 5016 5017 return 0; 5018 } 5019 5020 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 5021 .suspend = &gfx_v9_4_3_xcp_suspend, 5022 .resume = &gfx_v9_4_3_xcp_resume 5023 }; 5024 5025 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 5026 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 5027 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 5028 }; 5029 5030 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 5031 { 5032 int r; 5033 5034 r = amdgpu_ras_block_late_init(adev, ras_block); 5035 if (r) 5036 return r; 5037 5038 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 5039 &gfx_v9_4_3_aca_info, 5040 NULL); 5041 if (r) 5042 goto late_fini; 5043 5044 return 0; 5045 5046 late_fini: 5047 amdgpu_ras_block_late_fini(adev, ras_block); 5048 5049 return r; 5050 } 5051 5052 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 5053 .ras_block = { 5054 .hw_ops = &gfx_v9_4_3_ras_ops, 5055 .ras_late_init = &gfx_v9_4_3_ras_late_init, 5056 }, 5057 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 5058 }; 5059