1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_gfx.h" 27 #include "soc15.h" 28 #include "soc15d.h" 29 #include "soc15_common.h" 30 #include "vega10_enum.h" 31 32 #include "v9_structs.h" 33 34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 35 36 #include "gc/gc_9_4_3_offset.h" 37 #include "gc/gc_9_4_3_sh_mask.h" 38 39 #include "gfx_v9_4_3.h" 40 #include "amdgpu_xcp.h" 41 #include "amdgpu_aca.h" 42 43 MODULE_FIRMWARE("amdgpu/gc_9_4_3_mec.bin"); 44 MODULE_FIRMWARE("amdgpu/gc_9_4_3_rlc.bin"); 45 46 #define GFX9_MEC_HPD_SIZE 4096 47 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 48 49 #define GOLDEN_GB_ADDR_CONFIG 0x2a114042 50 #define CP_HQD_PERSISTENT_STATE_DEFAULT 0xbe05301 51 52 #define mmSMNAID_XCD0_MCA_SMU 0x36430400 /* SMN AID XCD0 */ 53 #define mmSMNAID_XCD1_MCA_SMU 0x38430400 /* SMN AID XCD1 */ 54 #define mmSMNXCD_XCD0_MCA_SMU 0x40430400 /* SMN XCD XCD0 */ 55 56 struct amdgpu_gfx_ras gfx_v9_4_3_ras; 57 58 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); 59 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev); 60 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); 61 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); 62 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 63 struct amdgpu_cu_info *cu_info); 64 65 static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, 66 uint64_t queue_mask) 67 { 68 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 69 amdgpu_ring_write(kiq_ring, 70 PACKET3_SET_RESOURCES_VMID_MASK(0) | 71 /* vmid_mask:0* queue_type:0 (KIQ) */ 72 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 73 amdgpu_ring_write(kiq_ring, 74 lower_32_bits(queue_mask)); /* queue mask lo */ 75 amdgpu_ring_write(kiq_ring, 76 upper_32_bits(queue_mask)); /* queue mask hi */ 77 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 78 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 79 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 80 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 81 } 82 83 static void gfx_v9_4_3_kiq_map_queues(struct amdgpu_ring *kiq_ring, 84 struct amdgpu_ring *ring) 85 { 86 struct amdgpu_device *adev = kiq_ring->adev; 87 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 88 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 89 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 90 91 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 92 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 93 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 94 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 95 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 96 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 97 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 98 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 99 /*queue_type: normal compute queue */ 100 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 101 /* alloc format: all_on_one_pipe */ 102 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 103 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 104 /* num_queues: must be 1 */ 105 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 106 amdgpu_ring_write(kiq_ring, 107 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 108 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 109 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 110 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 111 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 112 } 113 114 static void gfx_v9_4_3_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 115 struct amdgpu_ring *ring, 116 enum amdgpu_unmap_queues_action action, 117 u64 gpu_addr, u64 seq) 118 { 119 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 120 121 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 122 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 123 PACKET3_UNMAP_QUEUES_ACTION(action) | 124 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 125 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 126 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 127 amdgpu_ring_write(kiq_ring, 128 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 129 130 if (action == PREEMPT_QUEUES_NO_UNMAP) { 131 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 132 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 133 amdgpu_ring_write(kiq_ring, seq); 134 } else { 135 amdgpu_ring_write(kiq_ring, 0); 136 amdgpu_ring_write(kiq_ring, 0); 137 amdgpu_ring_write(kiq_ring, 0); 138 } 139 } 140 141 static void gfx_v9_4_3_kiq_query_status(struct amdgpu_ring *kiq_ring, 142 struct amdgpu_ring *ring, 143 u64 addr, 144 u64 seq) 145 { 146 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 147 148 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 149 amdgpu_ring_write(kiq_ring, 150 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 151 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 152 PACKET3_QUERY_STATUS_COMMAND(2)); 153 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 154 amdgpu_ring_write(kiq_ring, 155 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 156 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 157 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 158 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 159 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 160 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 161 } 162 163 static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 164 uint16_t pasid, uint32_t flush_type, 165 bool all_hub) 166 { 167 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 168 amdgpu_ring_write(kiq_ring, 169 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 170 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 171 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 172 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 173 } 174 175 static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { 176 .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, 177 .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, 178 .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, 179 .kiq_query_status = gfx_v9_4_3_kiq_query_status, 180 .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, 181 .set_resources_size = 8, 182 .map_queues_size = 7, 183 .unmap_queues_size = 6, 184 .query_status_size = 7, 185 .invalidate_tlbs_size = 2, 186 }; 187 188 static void gfx_v9_4_3_set_kiq_pm4_funcs(struct amdgpu_device *adev) 189 { 190 int i, num_xcc; 191 192 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 193 for (i = 0; i < num_xcc; i++) 194 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs; 195 } 196 197 static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) 198 { 199 int i, num_xcc, dev_inst; 200 201 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 202 for (i = 0; i < num_xcc; i++) { 203 dev_inst = GET_INST(GC, i); 204 205 WREG32_SOC15(GC, dev_inst, regGB_ADDR_CONFIG, 206 GOLDEN_GB_ADDR_CONFIG); 207 /* Golden settings applied by driver for ASIC with rev_id 0 */ 208 if (adev->rev_id == 0) { 209 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, 210 REDUCE_FIFO_DEPTH_BY_2, 2); 211 } else { 212 WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, 213 SPARE, 0x1); 214 } 215 } 216 } 217 218 static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 219 bool wc, uint32_t reg, uint32_t val) 220 { 221 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 222 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 223 WRITE_DATA_DST_SEL(0) | 224 (wc ? WR_CONFIRM : 0)); 225 amdgpu_ring_write(ring, reg); 226 amdgpu_ring_write(ring, 0); 227 amdgpu_ring_write(ring, val); 228 } 229 230 static void gfx_v9_4_3_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 231 int mem_space, int opt, uint32_t addr0, 232 uint32_t addr1, uint32_t ref, uint32_t mask, 233 uint32_t inv) 234 { 235 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 236 amdgpu_ring_write(ring, 237 /* memory (1) or register (0) */ 238 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 239 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 240 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 241 WAIT_REG_MEM_ENGINE(eng_sel))); 242 243 if (mem_space) 244 BUG_ON(addr0 & 0x3); /* Dword align */ 245 amdgpu_ring_write(ring, addr0); 246 amdgpu_ring_write(ring, addr1); 247 amdgpu_ring_write(ring, ref); 248 amdgpu_ring_write(ring, mask); 249 amdgpu_ring_write(ring, inv); /* poll interval */ 250 } 251 252 static int gfx_v9_4_3_ring_test_ring(struct amdgpu_ring *ring) 253 { 254 uint32_t scratch_reg0_offset, xcc_offset; 255 struct amdgpu_device *adev = ring->adev; 256 uint32_t tmp = 0; 257 unsigned i; 258 int r; 259 260 /* Use register offset which is local to XCC in the packet */ 261 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 262 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 263 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 264 tmp = RREG32(scratch_reg0_offset); 265 266 r = amdgpu_ring_alloc(ring, 3); 267 if (r) 268 return r; 269 270 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 271 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 272 amdgpu_ring_write(ring, 0xDEADBEEF); 273 amdgpu_ring_commit(ring); 274 275 for (i = 0; i < adev->usec_timeout; i++) { 276 tmp = RREG32(scratch_reg0_offset); 277 if (tmp == 0xDEADBEEF) 278 break; 279 udelay(1); 280 } 281 282 if (i >= adev->usec_timeout) 283 r = -ETIMEDOUT; 284 return r; 285 } 286 287 static int gfx_v9_4_3_ring_test_ib(struct amdgpu_ring *ring, long timeout) 288 { 289 struct amdgpu_device *adev = ring->adev; 290 struct amdgpu_ib ib; 291 struct dma_fence *f = NULL; 292 293 unsigned index; 294 uint64_t gpu_addr; 295 uint32_t tmp; 296 long r; 297 298 r = amdgpu_device_wb_get(adev, &index); 299 if (r) 300 return r; 301 302 gpu_addr = adev->wb.gpu_addr + (index * 4); 303 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 304 memset(&ib, 0, sizeof(ib)); 305 306 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 307 if (r) 308 goto err1; 309 310 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 311 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 312 ib.ptr[2] = lower_32_bits(gpu_addr); 313 ib.ptr[3] = upper_32_bits(gpu_addr); 314 ib.ptr[4] = 0xDEADBEEF; 315 ib.length_dw = 5; 316 317 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 318 if (r) 319 goto err2; 320 321 r = dma_fence_wait_timeout(f, false, timeout); 322 if (r == 0) { 323 r = -ETIMEDOUT; 324 goto err2; 325 } else if (r < 0) { 326 goto err2; 327 } 328 329 tmp = adev->wb.wb[index]; 330 if (tmp == 0xDEADBEEF) 331 r = 0; 332 else 333 r = -EINVAL; 334 335 err2: 336 amdgpu_ib_free(adev, &ib, NULL); 337 dma_fence_put(f); 338 err1: 339 amdgpu_device_wb_free(adev, index); 340 return r; 341 } 342 343 344 /* This value might differs per partition */ 345 static uint64_t gfx_v9_4_3_get_gpu_clock_counter(struct amdgpu_device *adev) 346 { 347 uint64_t clock; 348 349 mutex_lock(&adev->gfx.gpu_clock_mutex); 350 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 351 clock = (uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_LSB) | 352 ((uint64_t)RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 353 mutex_unlock(&adev->gfx.gpu_clock_mutex); 354 355 return clock; 356 } 357 358 static void gfx_v9_4_3_free_microcode(struct amdgpu_device *adev) 359 { 360 amdgpu_ucode_release(&adev->gfx.pfp_fw); 361 amdgpu_ucode_release(&adev->gfx.me_fw); 362 amdgpu_ucode_release(&adev->gfx.ce_fw); 363 amdgpu_ucode_release(&adev->gfx.rlc_fw); 364 amdgpu_ucode_release(&adev->gfx.mec_fw); 365 amdgpu_ucode_release(&adev->gfx.mec2_fw); 366 367 kfree(adev->gfx.rlc.register_list_format); 368 } 369 370 static int gfx_v9_4_3_init_rlc_microcode(struct amdgpu_device *adev, 371 const char *chip_name) 372 { 373 char fw_name[30]; 374 int err; 375 const struct rlc_firmware_header_v2_0 *rlc_hdr; 376 uint16_t version_major; 377 uint16_t version_minor; 378 379 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 380 381 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name); 382 if (err) 383 goto out; 384 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 385 386 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 387 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 388 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 389 out: 390 if (err) 391 amdgpu_ucode_release(&adev->gfx.rlc_fw); 392 393 return err; 394 } 395 396 static bool gfx_v9_4_3_should_disable_gfxoff(struct pci_dev *pdev) 397 { 398 return true; 399 } 400 401 static void gfx_v9_4_3_check_if_need_gfxoff(struct amdgpu_device *adev) 402 { 403 if (gfx_v9_4_3_should_disable_gfxoff(adev->pdev)) 404 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 405 } 406 407 static int gfx_v9_4_3_init_cp_compute_microcode(struct amdgpu_device *adev, 408 const char *chip_name) 409 { 410 char fw_name[30]; 411 int err; 412 413 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 414 415 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name); 416 if (err) 417 goto out; 418 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 419 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 420 421 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version; 422 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version; 423 424 gfx_v9_4_3_check_if_need_gfxoff(adev); 425 426 out: 427 if (err) 428 amdgpu_ucode_release(&adev->gfx.mec_fw); 429 return err; 430 } 431 432 static int gfx_v9_4_3_init_microcode(struct amdgpu_device *adev) 433 { 434 const char *chip_name; 435 int r; 436 437 chip_name = "gc_9_4_3"; 438 439 r = gfx_v9_4_3_init_rlc_microcode(adev, chip_name); 440 if (r) 441 return r; 442 443 r = gfx_v9_4_3_init_cp_compute_microcode(adev, chip_name); 444 if (r) 445 return r; 446 447 return r; 448 } 449 450 static void gfx_v9_4_3_mec_fini(struct amdgpu_device *adev) 451 { 452 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 453 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 454 } 455 456 static int gfx_v9_4_3_mec_init(struct amdgpu_device *adev) 457 { 458 int r, i, num_xcc; 459 u32 *hpd; 460 const __le32 *fw_data; 461 unsigned fw_size; 462 u32 *fw; 463 size_t mec_hpd_size; 464 465 const struct gfx_firmware_header_v1_0 *mec_hdr; 466 467 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 468 for (i = 0; i < num_xcc; i++) 469 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 470 AMDGPU_MAX_COMPUTE_QUEUES); 471 472 /* take ownership of the relevant compute queues */ 473 amdgpu_gfx_compute_queue_acquire(adev); 474 mec_hpd_size = 475 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; 476 if (mec_hpd_size) { 477 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 478 AMDGPU_GEM_DOMAIN_VRAM | 479 AMDGPU_GEM_DOMAIN_GTT, 480 &adev->gfx.mec.hpd_eop_obj, 481 &adev->gfx.mec.hpd_eop_gpu_addr, 482 (void **)&hpd); 483 if (r) { 484 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 485 gfx_v9_4_3_mec_fini(adev); 486 return r; 487 } 488 489 if (amdgpu_emu_mode == 1) { 490 for (i = 0; i < mec_hpd_size / 4; i++) { 491 memset((void *)(hpd + i), 0, 4); 492 if (i % 50 == 0) 493 msleep(1); 494 } 495 } else { 496 memset(hpd, 0, mec_hpd_size); 497 } 498 499 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 500 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 501 } 502 503 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 504 505 fw_data = (const __le32 *) 506 (adev->gfx.mec_fw->data + 507 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 508 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 509 510 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 511 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 512 &adev->gfx.mec.mec_fw_obj, 513 &adev->gfx.mec.mec_fw_gpu_addr, 514 (void **)&fw); 515 if (r) { 516 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 517 gfx_v9_4_3_mec_fini(adev); 518 return r; 519 } 520 521 memcpy(fw, fw_data, fw_size); 522 523 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 524 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 525 526 return 0; 527 } 528 529 static void gfx_v9_4_3_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 530 u32 sh_num, u32 instance, int xcc_id) 531 { 532 u32 data; 533 534 if (instance == 0xffffffff) 535 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 536 INSTANCE_BROADCAST_WRITES, 1); 537 else 538 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 539 INSTANCE_INDEX, instance); 540 541 if (se_num == 0xffffffff) 542 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 543 SE_BROADCAST_WRITES, 1); 544 else 545 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 546 547 if (sh_num == 0xffffffff) 548 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 549 SH_BROADCAST_WRITES, 1); 550 else 551 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 552 553 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 554 } 555 556 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t address) 557 { 558 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 559 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 560 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 561 (address << SQ_IND_INDEX__INDEX__SHIFT) | 562 (SQ_IND_INDEX__FORCE_READ_MASK)); 563 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 564 } 565 566 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 567 uint32_t wave, uint32_t thread, 568 uint32_t regno, uint32_t num, uint32_t *out) 569 { 570 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 571 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 572 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 573 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 574 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 575 (SQ_IND_INDEX__FORCE_READ_MASK) | 576 (SQ_IND_INDEX__AUTO_INCR_MASK)); 577 while (num--) 578 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 579 } 580 581 static void gfx_v9_4_3_read_wave_data(struct amdgpu_device *adev, 582 uint32_t xcc_id, uint32_t simd, uint32_t wave, 583 uint32_t *dst, int *no_fields) 584 { 585 /* type 1 wave data */ 586 dst[(*no_fields)++] = 1; 587 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); 588 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); 589 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); 590 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); 591 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); 592 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_HW_ID); 593 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW0); 594 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_INST_DW1); 595 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_GPR_ALLOC); 596 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_LDS_ALLOC); 597 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_TRAPSTS); 598 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_STS); 599 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_IB_DBG0); 600 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_M0); 601 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_MODE); 602 } 603 604 static void gfx_v9_4_3_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 605 uint32_t wave, uint32_t start, 606 uint32_t size, uint32_t *dst) 607 { 608 wave_read_regs(adev, xcc_id, simd, wave, 0, 609 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 610 } 611 612 static void gfx_v9_4_3_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, 613 uint32_t wave, uint32_t thread, 614 uint32_t start, uint32_t size, 615 uint32_t *dst) 616 { 617 wave_read_regs(adev, xcc_id, simd, wave, thread, 618 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 619 } 620 621 static void gfx_v9_4_3_select_me_pipe_q(struct amdgpu_device *adev, 622 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 623 { 624 soc15_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 625 } 626 627 628 static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev, 629 int num_xccs_per_xcp) 630 { 631 int ret, i, num_xcc; 632 u32 tmp = 0; 633 634 if (adev->psp.funcs) { 635 ret = psp_spatial_partition(&adev->psp, 636 NUM_XCC(adev->gfx.xcc_mask) / 637 num_xccs_per_xcp); 638 if (ret) 639 return ret; 640 } else { 641 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 642 643 for (i = 0; i < num_xcc; i++) { 644 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP, 645 num_xccs_per_xcp); 646 tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID, 647 i % num_xccs_per_xcp); 648 WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL, 649 tmp); 650 } 651 ret = 0; 652 } 653 654 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp; 655 656 return ret; 657 } 658 659 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 660 { 661 int xcc; 662 663 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0)); 664 if (!xcc) { 665 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 666 return -EINVAL; 667 } 668 669 return xcc - 1; 670 } 671 672 static const struct amdgpu_gfx_funcs gfx_v9_4_3_gfx_funcs = { 673 .get_gpu_clock_counter = &gfx_v9_4_3_get_gpu_clock_counter, 674 .select_se_sh = &gfx_v9_4_3_xcc_select_se_sh, 675 .read_wave_data = &gfx_v9_4_3_read_wave_data, 676 .read_wave_sgprs = &gfx_v9_4_3_read_wave_sgprs, 677 .read_wave_vgprs = &gfx_v9_4_3_read_wave_vgprs, 678 .select_me_pipe_q = &gfx_v9_4_3_select_me_pipe_q, 679 .switch_partition_mode = &gfx_v9_4_3_switch_compute_partition, 680 .ih_node_to_logical_xcc = &gfx_v9_4_3_ih_to_xcc_inst, 681 }; 682 683 static int gfx_v9_4_3_aca_bank_generate_report(struct aca_handle *handle, 684 struct aca_bank *bank, enum aca_error_type type, 685 struct aca_bank_report *report, void *data) 686 { 687 u64 status, misc0; 688 u32 instlo; 689 int ret; 690 691 status = bank->regs[ACA_REG_IDX_STATUS]; 692 if ((type == ACA_ERROR_TYPE_UE && 693 ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_FAULT) || 694 (type == ACA_ERROR_TYPE_CE && 695 ACA_REG__STATUS__ERRORCODEEXT(status) == ACA_EXTERROR_CODE_CE)) { 696 697 ret = aca_bank_info_decode(bank, &report->info); 698 if (ret) 699 return ret; 700 701 /* NOTE: overwrite info.die_id with xcd id for gfx */ 702 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 703 instlo &= GENMASK(31, 1); 704 report->info.die_id = instlo == mmSMNAID_XCD0_MCA_SMU ? 0 : 1; 705 706 misc0 = bank->regs[ACA_REG_IDX_MISC0]; 707 report->count[type] = ACA_REG__MISC0__ERRCNT(misc0); 708 } 709 710 return 0; 711 } 712 713 static bool gfx_v9_4_3_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank, 714 enum aca_error_type type, void *data) 715 { 716 u32 instlo; 717 718 instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]); 719 instlo &= GENMASK(31, 1); 720 switch (instlo) { 721 case mmSMNAID_XCD0_MCA_SMU: 722 case mmSMNAID_XCD1_MCA_SMU: 723 case mmSMNXCD_XCD0_MCA_SMU: 724 return true; 725 default: 726 break; 727 } 728 729 return false; 730 } 731 732 static const struct aca_bank_ops gfx_v9_4_3_aca_bank_ops = { 733 .aca_bank_generate_report = gfx_v9_4_3_aca_bank_generate_report, 734 .aca_bank_is_valid = gfx_v9_4_3_aca_bank_is_valid, 735 }; 736 737 static const struct aca_info gfx_v9_4_3_aca_info = { 738 .hwip = ACA_HWIP_TYPE_SMU, 739 .mask = ACA_ERROR_UE_MASK | ACA_ERROR_CE_MASK, 740 .bank_ops = &gfx_v9_4_3_aca_bank_ops, 741 }; 742 743 static int gfx_v9_4_3_gpu_early_init(struct amdgpu_device *adev) 744 { 745 u32 gb_addr_config; 746 747 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs; 748 adev->gfx.ras = &gfx_v9_4_3_ras; 749 750 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 751 case IP_VERSION(9, 4, 3): 752 adev->gfx.config.max_hw_contexts = 8; 753 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 754 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 755 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 756 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 757 gb_addr_config = RREG32_SOC15(GC, GET_INST(GC, 0), regGB_ADDR_CONFIG); 758 break; 759 default: 760 BUG(); 761 break; 762 } 763 764 adev->gfx.config.gb_addr_config = gb_addr_config; 765 766 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 767 REG_GET_FIELD( 768 adev->gfx.config.gb_addr_config, 769 GB_ADDR_CONFIG, 770 NUM_PIPES); 771 772 adev->gfx.config.max_tile_pipes = 773 adev->gfx.config.gb_addr_config_fields.num_pipes; 774 775 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 776 REG_GET_FIELD( 777 adev->gfx.config.gb_addr_config, 778 GB_ADDR_CONFIG, 779 NUM_BANKS); 780 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 781 REG_GET_FIELD( 782 adev->gfx.config.gb_addr_config, 783 GB_ADDR_CONFIG, 784 MAX_COMPRESSED_FRAGS); 785 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 786 REG_GET_FIELD( 787 adev->gfx.config.gb_addr_config, 788 GB_ADDR_CONFIG, 789 NUM_RB_PER_SE); 790 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 791 REG_GET_FIELD( 792 adev->gfx.config.gb_addr_config, 793 GB_ADDR_CONFIG, 794 NUM_SHADER_ENGINES); 795 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 796 REG_GET_FIELD( 797 adev->gfx.config.gb_addr_config, 798 GB_ADDR_CONFIG, 799 PIPE_INTERLEAVE_SIZE)); 800 801 return 0; 802 } 803 804 static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, 805 int xcc_id, int mec, int pipe, int queue) 806 { 807 unsigned irq_type; 808 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 809 unsigned int hw_prio; 810 uint32_t xcc_doorbell_start; 811 812 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 813 ring_id]; 814 815 /* mec0 is me1 */ 816 ring->xcc_id = xcc_id; 817 ring->me = mec + 1; 818 ring->pipe = pipe; 819 ring->queue = queue; 820 821 ring->ring_obj = NULL; 822 ring->use_doorbell = true; 823 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 824 xcc_id * adev->doorbell_index.xcc_doorbell_range; 825 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 826 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 827 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 828 GFX9_MEC_HPD_SIZE; 829 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 830 sprintf(ring->name, "comp_%d.%d.%d.%d", 831 ring->xcc_id, ring->me, ring->pipe, ring->queue); 832 833 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 834 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 835 + ring->pipe; 836 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 837 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 838 /* type-2 packets are deprecated on MEC, use type-3 instead */ 839 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 840 hw_prio, NULL); 841 } 842 843 static int gfx_v9_4_3_sw_init(void *handle) 844 { 845 int i, j, k, r, ring_id, xcc_id, num_xcc; 846 struct amdgpu_kiq *kiq; 847 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 848 849 adev->gfx.mec.num_mec = 2; 850 adev->gfx.mec.num_pipe_per_mec = 4; 851 adev->gfx.mec.num_queue_per_pipe = 8; 852 853 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 854 855 /* EOP Event */ 856 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 857 if (r) 858 return r; 859 860 /* Privileged reg */ 861 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 862 &adev->gfx.priv_reg_irq); 863 if (r) 864 return r; 865 866 /* Privileged inst */ 867 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 868 &adev->gfx.priv_inst_irq); 869 if (r) 870 return r; 871 872 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 873 874 r = adev->gfx.rlc.funcs->init(adev); 875 if (r) { 876 DRM_ERROR("Failed to init rlc BOs!\n"); 877 return r; 878 } 879 880 r = gfx_v9_4_3_mec_init(adev); 881 if (r) { 882 DRM_ERROR("Failed to init MEC BOs!\n"); 883 return r; 884 } 885 886 /* set up the compute queues - allocate horizontally across pipes */ 887 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 888 ring_id = 0; 889 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 890 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 891 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; 892 k++) { 893 if (!amdgpu_gfx_is_mec_queue_enabled( 894 adev, xcc_id, i, k, j)) 895 continue; 896 897 r = gfx_v9_4_3_compute_ring_init(adev, 898 ring_id, 899 xcc_id, 900 i, k, j); 901 if (r) 902 return r; 903 904 ring_id++; 905 } 906 } 907 } 908 909 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE, xcc_id); 910 if (r) { 911 DRM_ERROR("Failed to init KIQ BOs!\n"); 912 return r; 913 } 914 915 kiq = &adev->gfx.kiq[xcc_id]; 916 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, xcc_id); 917 if (r) 918 return r; 919 920 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 921 r = amdgpu_gfx_mqd_sw_init(adev, 922 sizeof(struct v9_mqd_allocation), xcc_id); 923 if (r) 924 return r; 925 } 926 927 r = gfx_v9_4_3_gpu_early_init(adev); 928 if (r) 929 return r; 930 931 r = amdgpu_gfx_ras_sw_init(adev); 932 if (r) 933 return r; 934 935 936 if (!amdgpu_sriov_vf(adev)) 937 r = amdgpu_gfx_sysfs_init(adev); 938 939 return r; 940 } 941 942 static int gfx_v9_4_3_sw_fini(void *handle) 943 { 944 int i, num_xcc; 945 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 946 947 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 948 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 949 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 950 951 for (i = 0; i < num_xcc; i++) { 952 amdgpu_gfx_mqd_sw_fini(adev, i); 953 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring); 954 amdgpu_gfx_kiq_fini(adev, i); 955 } 956 957 gfx_v9_4_3_mec_fini(adev); 958 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 959 gfx_v9_4_3_free_microcode(adev); 960 if (!amdgpu_sriov_vf(adev)) 961 amdgpu_gfx_sysfs_fini(adev); 962 963 return 0; 964 } 965 966 #define DEFAULT_SH_MEM_BASES (0x6000) 967 static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, 968 int xcc_id) 969 { 970 int i; 971 uint32_t sh_mem_config; 972 uint32_t sh_mem_bases; 973 uint32_t data; 974 975 /* 976 * Configure apertures: 977 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 978 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 979 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 980 */ 981 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 982 983 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 984 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 985 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 986 987 mutex_lock(&adev->srbm_mutex); 988 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 989 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 990 /* CP and shaders */ 991 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 992 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 993 994 /* Enable trap for each kfd vmid. */ 995 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 996 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 997 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 998 } 999 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1000 mutex_unlock(&adev->srbm_mutex); 1001 1002 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1003 acccess. These should be enabled by FW for target VMIDs. */ 1004 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1005 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); 1006 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); 1007 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, i, 0); 1008 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, i, 0); 1009 } 1010 } 1011 1012 static void gfx_v9_4_3_xcc_init_gds_vmid(struct amdgpu_device *adev, int xcc_id) 1013 { 1014 int vmid; 1015 1016 /* 1017 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1018 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1019 * the driver can enable them for graphics. VMID0 should maintain 1020 * access so that HWS firmware can save/restore entries. 1021 */ 1022 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 1023 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * vmid, 0); 1024 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * vmid, 0); 1025 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_GWS_VMID0, vmid, 0); 1026 WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_OA_VMID0, vmid, 0); 1027 } 1028 } 1029 1030 static void gfx_v9_4_3_xcc_constants_init(struct amdgpu_device *adev, 1031 int xcc_id) 1032 { 1033 u32 tmp; 1034 int i; 1035 1036 /* XXX SH_MEM regs */ 1037 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1038 mutex_lock(&adev->srbm_mutex); 1039 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) { 1040 soc15_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1041 /* CP and shaders */ 1042 if (i == 0) { 1043 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1044 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1045 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1046 !!adev->gmc.noretry); 1047 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1048 regSH_MEM_CONFIG, tmp); 1049 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1050 regSH_MEM_BASES, 0); 1051 } else { 1052 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1053 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1054 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 1055 !!adev->gmc.noretry); 1056 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1057 regSH_MEM_CONFIG, tmp); 1058 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1059 (adev->gmc.private_aperture_start >> 1060 48)); 1061 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1062 (adev->gmc.shared_aperture_start >> 1063 48)); 1064 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), 1065 regSH_MEM_BASES, tmp); 1066 } 1067 } 1068 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, 0)); 1069 1070 mutex_unlock(&adev->srbm_mutex); 1071 1072 gfx_v9_4_3_xcc_init_compute_vmid(adev, xcc_id); 1073 gfx_v9_4_3_xcc_init_gds_vmid(adev, xcc_id); 1074 } 1075 1076 static void gfx_v9_4_3_constants_init(struct amdgpu_device *adev) 1077 { 1078 int i, num_xcc; 1079 1080 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1081 1082 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info); 1083 adev->gfx.config.db_debug2 = 1084 RREG32_SOC15(GC, GET_INST(GC, 0), regDB_DEBUG2); 1085 1086 for (i = 0; i < num_xcc; i++) 1087 gfx_v9_4_3_xcc_constants_init(adev, i); 1088 } 1089 1090 static void 1091 gfx_v9_4_3_xcc_enable_save_restore_machine(struct amdgpu_device *adev, 1092 int xcc_id) 1093 { 1094 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_SRM_CNTL, SRM_ENABLE, 1); 1095 } 1096 1097 static void gfx_v9_4_3_xcc_init_pg(struct amdgpu_device *adev, int xcc_id) 1098 { 1099 /* 1100 * Rlc save restore list is workable since v2_1. 1101 * And it's needed by gfxoff feature. 1102 */ 1103 if (adev->gfx.rlc.is_rlc_v2_1) 1104 gfx_v9_4_3_xcc_enable_save_restore_machine(adev, xcc_id); 1105 } 1106 1107 static void gfx_v9_4_3_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id) 1108 { 1109 uint32_t data; 1110 1111 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 1112 data |= CPC_PSP_DEBUG__UTCL2IUGPAOVERRIDE_MASK; 1113 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 1114 } 1115 1116 static bool gfx_v9_4_3_is_rlc_enabled(struct amdgpu_device *adev) 1117 { 1118 uint32_t rlc_setting; 1119 1120 /* if RLC is not enabled, do nothing */ 1121 rlc_setting = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 1122 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 1123 return false; 1124 1125 return true; 1126 } 1127 1128 static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id) 1129 { 1130 uint32_t data; 1131 unsigned i; 1132 1133 data = RLC_SAFE_MODE__CMD_MASK; 1134 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 1135 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1136 1137 /* wait for RLC_SAFE_MODE */ 1138 for (i = 0; i < adev->usec_timeout; i++) { 1139 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 1140 break; 1141 udelay(1); 1142 } 1143 } 1144 1145 static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, 1146 int xcc_id) 1147 { 1148 uint32_t data; 1149 1150 data = RLC_SAFE_MODE__CMD_MASK; 1151 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 1152 } 1153 1154 static void gfx_v9_4_3_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 1155 { 1156 int xcc_id, num_xcc; 1157 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 1158 1159 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1160 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1161 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 1162 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); 1163 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); 1164 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); 1165 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); 1166 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 1167 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 1168 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); 1169 } 1170 adev->gfx.rlc.rlcg_reg_access_supported = true; 1171 } 1172 1173 static int gfx_v9_4_3_rlc_init(struct amdgpu_device *adev) 1174 { 1175 /* init spm vmid with 0xf */ 1176 if (adev->gfx.rlc.funcs->update_spm_vmid) 1177 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); 1178 1179 return 0; 1180 } 1181 1182 static void gfx_v9_4_3_xcc_wait_for_rlc_serdes(struct amdgpu_device *adev, 1183 int xcc_id) 1184 { 1185 u32 i, j, k; 1186 u32 mask; 1187 1188 mutex_lock(&adev->grbm_idx_mutex); 1189 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1190 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1191 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 1192 xcc_id); 1193 for (k = 0; k < adev->usec_timeout; k++) { 1194 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_CU_MASTER_BUSY) == 0) 1195 break; 1196 udelay(1); 1197 } 1198 if (k == adev->usec_timeout) { 1199 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 1200 0xffffffff, 1201 0xffffffff, xcc_id); 1202 mutex_unlock(&adev->grbm_idx_mutex); 1203 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1204 i, j); 1205 return; 1206 } 1207 } 1208 } 1209 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 1210 xcc_id); 1211 mutex_unlock(&adev->grbm_idx_mutex); 1212 1213 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1214 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1215 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1216 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1217 for (k = 0; k < adev->usec_timeout; k++) { 1218 if ((RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1219 break; 1220 udelay(1); 1221 } 1222 } 1223 1224 static void gfx_v9_4_3_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1225 bool enable, int xcc_id) 1226 { 1227 u32 tmp; 1228 1229 /* These interrupts should be enabled to drive DS clock */ 1230 1231 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1232 1233 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1234 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1235 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1236 1237 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1238 } 1239 1240 static void gfx_v9_4_3_xcc_rlc_stop(struct amdgpu_device *adev, int xcc_id) 1241 { 1242 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1243 RLC_ENABLE_F32, 0); 1244 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1245 gfx_v9_4_3_xcc_wait_for_rlc_serdes(adev, xcc_id); 1246 } 1247 1248 static void gfx_v9_4_3_rlc_stop(struct amdgpu_device *adev) 1249 { 1250 int i, num_xcc; 1251 1252 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1253 for (i = 0; i < num_xcc; i++) 1254 gfx_v9_4_3_xcc_rlc_stop(adev, i); 1255 } 1256 1257 static void gfx_v9_4_3_xcc_rlc_reset(struct amdgpu_device *adev, int xcc_id) 1258 { 1259 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1260 SOFT_RESET_RLC, 1); 1261 udelay(50); 1262 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), GRBM_SOFT_RESET, 1263 SOFT_RESET_RLC, 0); 1264 udelay(50); 1265 } 1266 1267 static void gfx_v9_4_3_rlc_reset(struct amdgpu_device *adev) 1268 { 1269 int i, num_xcc; 1270 1271 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1272 for (i = 0; i < num_xcc; i++) 1273 gfx_v9_4_3_xcc_rlc_reset(adev, i); 1274 } 1275 1276 static void gfx_v9_4_3_xcc_rlc_start(struct amdgpu_device *adev, int xcc_id) 1277 { 1278 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, 1279 RLC_ENABLE_F32, 1); 1280 udelay(50); 1281 1282 /* carrizo do enable cp interrupt after cp inited */ 1283 if (!(adev->flags & AMD_IS_APU)) { 1284 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 1285 udelay(50); 1286 } 1287 } 1288 1289 static void gfx_v9_4_3_rlc_start(struct amdgpu_device *adev) 1290 { 1291 #ifdef AMDGPU_RLC_DEBUG_RETRY 1292 u32 rlc_ucode_ver; 1293 #endif 1294 int i, num_xcc; 1295 1296 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1297 for (i = 0; i < num_xcc; i++) { 1298 gfx_v9_4_3_xcc_rlc_start(adev, i); 1299 #ifdef AMDGPU_RLC_DEBUG_RETRY 1300 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 1301 rlc_ucode_ver = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_6); 1302 if (rlc_ucode_ver == 0x108) { 1303 dev_info(adev->dev, 1304 "Using rlc debug ucode. regRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 1305 rlc_ucode_ver, adev->gfx.rlc_fw_version); 1306 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 1307 * default is 0x9C4 to create a 100us interval */ 1308 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_TIMER_INT_3, 0x9C4); 1309 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 1310 * to disable the page fault retry interrupts, default is 1311 * 0x100 (256) */ 1312 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_GENERAL_12, 0x100); 1313 } 1314 #endif 1315 } 1316 } 1317 1318 static int gfx_v9_4_3_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1319 int xcc_id) 1320 { 1321 const struct rlc_firmware_header_v2_0 *hdr; 1322 const __le32 *fw_data; 1323 unsigned i, fw_size; 1324 1325 if (!adev->gfx.rlc_fw) 1326 return -EINVAL; 1327 1328 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1329 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1330 1331 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1332 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1333 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1334 1335 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1336 RLCG_UCODE_LOADING_START_ADDRESS); 1337 for (i = 0; i < fw_size; i++) { 1338 if (amdgpu_emu_mode == 1 && i % 100 == 0) { 1339 dev_info(adev->dev, "Write RLC ucode data %u DWs\n", i); 1340 msleep(1); 1341 } 1342 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 1343 } 1344 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1345 1346 return 0; 1347 } 1348 1349 static int gfx_v9_4_3_xcc_rlc_resume(struct amdgpu_device *adev, int xcc_id) 1350 { 1351 int r; 1352 1353 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1354 gfx_v9_4_3_xcc_rlc_stop(adev, xcc_id); 1355 /* legacy rlc firmware loading */ 1356 r = gfx_v9_4_3_xcc_rlc_load_microcode(adev, xcc_id); 1357 if (r) 1358 return r; 1359 gfx_v9_4_3_xcc_rlc_start(adev, xcc_id); 1360 } 1361 1362 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 1363 /* disable CG */ 1364 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1365 gfx_v9_4_3_xcc_init_pg(adev, xcc_id); 1366 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 1367 1368 return 0; 1369 } 1370 1371 static int gfx_v9_4_3_rlc_resume(struct amdgpu_device *adev) 1372 { 1373 int r, i, num_xcc; 1374 1375 if (amdgpu_sriov_vf(adev)) 1376 return 0; 1377 1378 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1379 for (i = 0; i < num_xcc; i++) { 1380 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 1381 if (r) 1382 return r; 1383 } 1384 1385 return 0; 1386 } 1387 1388 static void gfx_v9_4_3_update_spm_vmid(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1389 unsigned vmid) 1390 { 1391 u32 reg, data; 1392 1393 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); 1394 if (amdgpu_sriov_is_pp_one_vf(adev)) 1395 data = RREG32_NO_KIQ(reg); 1396 else 1397 data = RREG32(reg); 1398 1399 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 1400 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 1401 1402 if (amdgpu_sriov_is_pp_one_vf(adev)) 1403 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1404 else 1405 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); 1406 } 1407 1408 static const struct soc15_reg_rlcg rlcg_access_gc_9_4_3[] = { 1409 {SOC15_REG_ENTRY(GC, 0, regGRBM_GFX_INDEX)}, 1410 {SOC15_REG_ENTRY(GC, 0, regSQ_IND_INDEX)}, 1411 }; 1412 1413 static bool gfx_v9_4_3_check_rlcg_range(struct amdgpu_device *adev, 1414 uint32_t offset, 1415 struct soc15_reg_rlcg *entries, int arr_size) 1416 { 1417 int i, inst; 1418 uint32_t reg; 1419 1420 if (!entries) 1421 return false; 1422 1423 for (i = 0; i < arr_size; i++) { 1424 const struct soc15_reg_rlcg *entry; 1425 1426 entry = &entries[i]; 1427 inst = adev->ip_map.logical_to_dev_inst ? 1428 adev->ip_map.logical_to_dev_inst( 1429 adev, entry->hwip, entry->instance) : 1430 entry->instance; 1431 reg = adev->reg_offset[entry->hwip][inst][entry->segment] + 1432 entry->reg; 1433 if (offset == reg) 1434 return true; 1435 } 1436 1437 return false; 1438 } 1439 1440 static bool gfx_v9_4_3_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 1441 { 1442 return gfx_v9_4_3_check_rlcg_range(adev, offset, 1443 (void *)rlcg_access_gc_9_4_3, 1444 ARRAY_SIZE(rlcg_access_gc_9_4_3)); 1445 } 1446 1447 static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, 1448 bool enable, int xcc_id) 1449 { 1450 if (enable) { 1451 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); 1452 } else { 1453 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 1454 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 1455 adev->gfx.kiq[xcc_id].ring.sched.ready = false; 1456 } 1457 udelay(50); 1458 } 1459 1460 static int gfx_v9_4_3_xcc_cp_compute_load_microcode(struct amdgpu_device *adev, 1461 int xcc_id) 1462 { 1463 const struct gfx_firmware_header_v1_0 *mec_hdr; 1464 const __le32 *fw_data; 1465 unsigned i; 1466 u32 tmp; 1467 u32 mec_ucode_addr_offset; 1468 u32 mec_ucode_data_offset; 1469 1470 if (!adev->gfx.mec_fw) 1471 return -EINVAL; 1472 1473 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); 1474 1475 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1476 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 1477 1478 fw_data = (const __le32 *) 1479 (adev->gfx.mec_fw->data + 1480 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1481 tmp = 0; 1482 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 1483 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 1484 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 1485 1486 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 1487 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 1488 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 1489 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 1490 1491 mec_ucode_addr_offset = 1492 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_ADDR); 1493 mec_ucode_data_offset = 1494 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_MEC_ME1_UCODE_DATA); 1495 1496 /* MEC1 */ 1497 WREG32(mec_ucode_addr_offset, mec_hdr->jt_offset); 1498 for (i = 0; i < mec_hdr->jt_size; i++) 1499 WREG32(mec_ucode_data_offset, 1500 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 1501 1502 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version); 1503 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 1504 1505 return 0; 1506 } 1507 1508 /* KIQ functions */ 1509 static void gfx_v9_4_3_xcc_kiq_setting(struct amdgpu_ring *ring, int xcc_id) 1510 { 1511 uint32_t tmp; 1512 struct amdgpu_device *adev = ring->adev; 1513 1514 /* tell RLC which is KIQ queue */ 1515 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 1516 tmp &= 0xffffff00; 1517 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1518 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1519 tmp |= 0x80; 1520 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 1521 } 1522 1523 static void gfx_v9_4_3_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 1524 { 1525 struct amdgpu_device *adev = ring->adev; 1526 1527 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 1528 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) { 1529 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 1530 mqd->cp_hqd_queue_priority = 1531 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 1532 } 1533 } 1534 } 1535 1536 static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id) 1537 { 1538 struct amdgpu_device *adev = ring->adev; 1539 struct v9_mqd *mqd = ring->mqd_ptr; 1540 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 1541 uint32_t tmp; 1542 1543 mqd->header = 0xC0310800; 1544 mqd->compute_pipelinestat_enable = 0x00000001; 1545 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 1546 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 1547 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 1548 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 1549 mqd->compute_misc_reserved = 0x00000003; 1550 1551 mqd->dynamic_cu_mask_addr_lo = 1552 lower_32_bits(ring->mqd_gpu_addr 1553 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1554 mqd->dynamic_cu_mask_addr_hi = 1555 upper_32_bits(ring->mqd_gpu_addr 1556 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 1557 1558 eop_base_addr = ring->eop_gpu_addr >> 8; 1559 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 1560 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 1561 1562 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1563 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL); 1564 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 1565 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 1566 1567 mqd->cp_hqd_eop_control = tmp; 1568 1569 /* enable doorbell? */ 1570 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); 1571 1572 if (ring->use_doorbell) { 1573 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1574 DOORBELL_OFFSET, ring->doorbell_index); 1575 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1576 DOORBELL_EN, 1); 1577 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1578 DOORBELL_SOURCE, 0); 1579 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1580 DOORBELL_HIT, 0); 1581 } else { 1582 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 1583 DOORBELL_EN, 0); 1584 } 1585 1586 mqd->cp_hqd_pq_doorbell_control = tmp; 1587 1588 /* disable the queue if it's active */ 1589 ring->wptr = 0; 1590 mqd->cp_hqd_dequeue_request = 0; 1591 mqd->cp_hqd_pq_rptr = 0; 1592 mqd->cp_hqd_pq_wptr_lo = 0; 1593 mqd->cp_hqd_pq_wptr_hi = 0; 1594 1595 /* set the pointer to the MQD */ 1596 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 1597 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 1598 1599 /* set MQD vmid to 0 */ 1600 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL); 1601 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 1602 mqd->cp_mqd_control = tmp; 1603 1604 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1605 hqd_gpu_addr = ring->gpu_addr >> 8; 1606 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 1607 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 1608 1609 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1610 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL); 1611 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 1612 (order_base_2(ring->ring_size / 4) - 1)); 1613 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 1614 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 1615 #ifdef __BIG_ENDIAN 1616 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 1617 #endif 1618 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 1619 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 1620 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 1621 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 1622 mqd->cp_hqd_pq_control = tmp; 1623 1624 /* set the wb address whether it's enabled or not */ 1625 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 1626 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 1627 mqd->cp_hqd_pq_rptr_report_addr_hi = 1628 upper_32_bits(wb_gpu_addr) & 0xffff; 1629 1630 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1631 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 1632 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 1633 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 1634 1635 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1636 ring->wptr = 0; 1637 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR); 1638 1639 /* set the vmid for the queue */ 1640 mqd->cp_hqd_vmid = 0; 1641 1642 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE); 1643 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 1644 mqd->cp_hqd_persistent_state = tmp; 1645 1646 /* set MIN_IB_AVAIL_SIZE */ 1647 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL); 1648 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 1649 mqd->cp_hqd_ib_control = tmp; 1650 1651 /* set static priority for a queue/ring */ 1652 gfx_v9_4_3_mqd_set_priority(ring, mqd); 1653 mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM); 1654 1655 /* map_queues packet doesn't need activate the queue, 1656 * so only kiq need set this field. 1657 */ 1658 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 1659 mqd->cp_hqd_active = 1; 1660 1661 return 0; 1662 } 1663 1664 static int gfx_v9_4_3_xcc_kiq_init_register(struct amdgpu_ring *ring, 1665 int xcc_id) 1666 { 1667 struct amdgpu_device *adev = ring->adev; 1668 struct v9_mqd *mqd = ring->mqd_ptr; 1669 int j; 1670 1671 /* disable wptr polling */ 1672 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 1673 1674 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR, 1675 mqd->cp_hqd_eop_base_addr_lo); 1676 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_BASE_ADDR_HI, 1677 mqd->cp_hqd_eop_base_addr_hi); 1678 1679 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 1680 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_EOP_CONTROL, 1681 mqd->cp_hqd_eop_control); 1682 1683 /* enable doorbell? */ 1684 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1685 mqd->cp_hqd_pq_doorbell_control); 1686 1687 /* disable the queue if it's active */ 1688 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1689 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1690 for (j = 0; j < adev->usec_timeout; j++) { 1691 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1692 break; 1693 udelay(1); 1694 } 1695 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1696 mqd->cp_hqd_dequeue_request); 1697 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 1698 mqd->cp_hqd_pq_rptr); 1699 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1700 mqd->cp_hqd_pq_wptr_lo); 1701 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1702 mqd->cp_hqd_pq_wptr_hi); 1703 } 1704 1705 /* set the pointer to the MQD */ 1706 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR, 1707 mqd->cp_mqd_base_addr_lo); 1708 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_BASE_ADDR_HI, 1709 mqd->cp_mqd_base_addr_hi); 1710 1711 /* set MQD vmid to 0 */ 1712 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MQD_CONTROL, 1713 mqd->cp_mqd_control); 1714 1715 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 1716 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE, 1717 mqd->cp_hqd_pq_base_lo); 1718 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_BASE_HI, 1719 mqd->cp_hqd_pq_base_hi); 1720 1721 /* set up the HQD, this is similar to CP_RB0_CNTL */ 1722 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_CONTROL, 1723 mqd->cp_hqd_pq_control); 1724 1725 /* set the wb address whether it's enabled or not */ 1726 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR, 1727 mqd->cp_hqd_pq_rptr_report_addr_lo); 1728 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 1729 mqd->cp_hqd_pq_rptr_report_addr_hi); 1730 1731 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 1732 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR, 1733 mqd->cp_hqd_pq_wptr_poll_addr_lo); 1734 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 1735 mqd->cp_hqd_pq_wptr_poll_addr_hi); 1736 1737 /* enable the doorbell if requested */ 1738 if (ring->use_doorbell) { 1739 WREG32_SOC15( 1740 GC, GET_INST(GC, xcc_id), 1741 regCP_MEC_DOORBELL_RANGE_LOWER, 1742 ((adev->doorbell_index.kiq + 1743 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1744 2) << 2); 1745 WREG32_SOC15( 1746 GC, GET_INST(GC, xcc_id), 1747 regCP_MEC_DOORBELL_RANGE_UPPER, 1748 ((adev->doorbell_index.userqueue_end + 1749 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 1750 2) << 2); 1751 } 1752 1753 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 1754 mqd->cp_hqd_pq_doorbell_control); 1755 1756 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 1757 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 1758 mqd->cp_hqd_pq_wptr_lo); 1759 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 1760 mqd->cp_hqd_pq_wptr_hi); 1761 1762 /* set the vmid for the queue */ 1763 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_VMID, mqd->cp_hqd_vmid); 1764 1765 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, 1766 mqd->cp_hqd_persistent_state); 1767 1768 /* activate the queue */ 1769 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 1770 mqd->cp_hqd_active); 1771 1772 if (ring->use_doorbell) 1773 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_STATUS, DOORBELL_ENABLE, 1); 1774 1775 return 0; 1776 } 1777 1778 static int gfx_v9_4_3_xcc_q_fini_register(struct amdgpu_ring *ring, 1779 int xcc_id) 1780 { 1781 struct amdgpu_device *adev = ring->adev; 1782 int j; 1783 1784 /* disable the queue if it's active */ 1785 if (RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1) { 1786 1787 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1); 1788 1789 for (j = 0; j < adev->usec_timeout; j++) { 1790 if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) 1791 break; 1792 udelay(1); 1793 } 1794 1795 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 1796 DRM_DEBUG("%s dequeue request failed.\n", ring->name); 1797 1798 /* Manual disable if dequeue request times out */ 1799 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE, 0); 1800 } 1801 1802 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 1803 0); 1804 } 1805 1806 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IQ_TIMER, 0); 1807 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_IB_CONTROL, 0); 1808 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PERSISTENT_STATE, CP_HQD_PERSISTENT_STATE_DEFAULT); 1809 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 1810 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1811 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_RPTR, 0); 1812 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_HI, 0); 1813 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_WPTR_LO, 0); 1814 1815 return 0; 1816 } 1817 1818 static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1819 { 1820 struct amdgpu_device *adev = ring->adev; 1821 struct v9_mqd *mqd = ring->mqd_ptr; 1822 struct v9_mqd *tmp_mqd; 1823 1824 gfx_v9_4_3_xcc_kiq_setting(ring, xcc_id); 1825 1826 /* GPU could be in bad state during probe, driver trigger the reset 1827 * after load the SMU, in this case , the mqd is not be initialized. 1828 * driver need to re-init the mqd. 1829 * check mqd->cp_hqd_pq_control since this value should not be 0 1830 */ 1831 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup; 1832 if (amdgpu_in_reset(adev) && tmp_mqd->cp_hqd_pq_control) { 1833 /* for GPU_RESET case , reset MQD to a clean status */ 1834 if (adev->gfx.kiq[xcc_id].mqd_backup) 1835 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation)); 1836 1837 /* reset ring buffer */ 1838 ring->wptr = 0; 1839 amdgpu_ring_clear_ring(ring); 1840 mutex_lock(&adev->srbm_mutex); 1841 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1842 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1843 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1844 mutex_unlock(&adev->srbm_mutex); 1845 } else { 1846 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1847 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1848 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1849 mutex_lock(&adev->srbm_mutex); 1850 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 1851 amdgpu_ring_clear_ring(ring); 1852 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1853 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1854 gfx_v9_4_3_xcc_kiq_init_register(ring, xcc_id); 1855 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1856 mutex_unlock(&adev->srbm_mutex); 1857 1858 if (adev->gfx.kiq[xcc_id].mqd_backup) 1859 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation)); 1860 } 1861 1862 return 0; 1863 } 1864 1865 static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) 1866 { 1867 struct amdgpu_device *adev = ring->adev; 1868 struct v9_mqd *mqd = ring->mqd_ptr; 1869 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 1870 struct v9_mqd *tmp_mqd; 1871 1872 /* Same as above kiq init, driver need to re-init the mqd if mqd->cp_hqd_pq_control 1873 * is not be initialized before 1874 */ 1875 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; 1876 1877 if (!tmp_mqd->cp_hqd_pq_control || 1878 (!amdgpu_in_reset(adev) && !adev->in_suspend)) { 1879 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 1880 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 1881 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 1882 mutex_lock(&adev->srbm_mutex); 1883 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 1884 gfx_v9_4_3_xcc_mqd_init(ring, xcc_id); 1885 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1886 mutex_unlock(&adev->srbm_mutex); 1887 1888 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1889 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 1890 } else { 1891 /* restore MQD to a clean status */ 1892 if (adev->gfx.mec.mqd_backup[mqd_idx]) 1893 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 1894 /* reset ring buffer */ 1895 ring->wptr = 0; 1896 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 1897 amdgpu_ring_clear_ring(ring); 1898 } 1899 1900 return 0; 1901 } 1902 1903 static int gfx_v9_4_3_xcc_kcq_fini_register(struct amdgpu_device *adev, int xcc_id) 1904 { 1905 struct amdgpu_ring *ring; 1906 int j; 1907 1908 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 1909 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; 1910 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 1911 mutex_lock(&adev->srbm_mutex); 1912 soc15_grbm_select(adev, ring->me, 1913 ring->pipe, 1914 ring->queue, 0, GET_INST(GC, xcc_id)); 1915 gfx_v9_4_3_xcc_q_fini_register(ring, xcc_id); 1916 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1917 mutex_unlock(&adev->srbm_mutex); 1918 } 1919 } 1920 1921 return 0; 1922 } 1923 1924 static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id) 1925 { 1926 struct amdgpu_ring *ring; 1927 int r; 1928 1929 ring = &adev->gfx.kiq[xcc_id].ring; 1930 1931 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1932 if (unlikely(r != 0)) 1933 return r; 1934 1935 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1936 if (unlikely(r != 0)) { 1937 amdgpu_bo_unreserve(ring->mqd_obj); 1938 return r; 1939 } 1940 1941 gfx_v9_4_3_xcc_kiq_init_queue(ring, xcc_id); 1942 amdgpu_bo_kunmap(ring->mqd_obj); 1943 ring->mqd_ptr = NULL; 1944 amdgpu_bo_unreserve(ring->mqd_obj); 1945 return 0; 1946 } 1947 1948 static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) 1949 { 1950 struct amdgpu_ring *ring = NULL; 1951 int r = 0, i; 1952 1953 gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id); 1954 1955 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 1956 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 1957 1958 r = amdgpu_bo_reserve(ring->mqd_obj, false); 1959 if (unlikely(r != 0)) 1960 goto done; 1961 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 1962 if (!r) { 1963 r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); 1964 amdgpu_bo_kunmap(ring->mqd_obj); 1965 ring->mqd_ptr = NULL; 1966 } 1967 amdgpu_bo_unreserve(ring->mqd_obj); 1968 if (r) 1969 goto done; 1970 } 1971 1972 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 1973 done: 1974 return r; 1975 } 1976 1977 static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) 1978 { 1979 struct amdgpu_ring *ring; 1980 int r, j; 1981 1982 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 1983 1984 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 1985 gfx_v9_4_3_xcc_disable_gpa_mode(adev, xcc_id); 1986 1987 r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); 1988 if (r) 1989 return r; 1990 } 1991 1992 r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); 1993 if (r) 1994 return r; 1995 1996 r = gfx_v9_4_3_xcc_kcq_resume(adev, xcc_id); 1997 if (r) 1998 return r; 1999 2000 for (j = 0; j < adev->gfx.num_compute_rings; j++) { 2001 ring = &adev->gfx.compute_ring 2002 [j + xcc_id * adev->gfx.num_compute_rings]; 2003 r = amdgpu_ring_test_helper(ring); 2004 if (r) 2005 return r; 2006 } 2007 2008 gfx_v9_4_3_xcc_enable_gui_idle_interrupt(adev, true, xcc_id); 2009 2010 return 0; 2011 } 2012 2013 static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) 2014 { 2015 int r = 0, i, num_xcc; 2016 2017 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2018 AMDGPU_XCP_FL_NONE) == 2019 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2020 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 2021 amdgpu_user_partt_mode); 2022 2023 if (r) 2024 return r; 2025 2026 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2027 for (i = 0; i < num_xcc; i++) { 2028 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 2029 if (r) 2030 return r; 2031 } 2032 2033 return 0; 2034 } 2035 2036 static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, 2037 int xcc_id) 2038 { 2039 gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); 2040 } 2041 2042 static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) 2043 { 2044 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2045 DRM_ERROR("XCD %d KCQ disable failed\n", xcc_id); 2046 2047 if (amdgpu_sriov_vf(adev)) { 2048 /* must disable polling for SRIOV when hw finished, otherwise 2049 * CPC engine may still keep fetching WB address which is already 2050 * invalid after sw finished and trigger DMAR reading error in 2051 * hypervisor side. 2052 */ 2053 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), CP_PQ_WPTR_POLL_CNTL, EN, 0); 2054 return; 2055 } 2056 2057 /* Use deinitialize sequence from CAIL when unbinding device 2058 * from driver, otherwise KIQ is hanging when binding back 2059 */ 2060 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2061 mutex_lock(&adev->srbm_mutex); 2062 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me, 2063 adev->gfx.kiq[xcc_id].ring.pipe, 2064 adev->gfx.kiq[xcc_id].ring.queue, 0, 2065 GET_INST(GC, xcc_id)); 2066 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring, 2067 xcc_id); 2068 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2069 mutex_unlock(&adev->srbm_mutex); 2070 } 2071 2072 gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); 2073 gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); 2074 } 2075 2076 static int gfx_v9_4_3_hw_init(void *handle) 2077 { 2078 int r; 2079 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2080 2081 if (!amdgpu_sriov_vf(adev)) 2082 gfx_v9_4_3_init_golden_registers(adev); 2083 2084 gfx_v9_4_3_constants_init(adev); 2085 2086 r = adev->gfx.rlc.funcs->resume(adev); 2087 if (r) 2088 return r; 2089 2090 r = gfx_v9_4_3_cp_resume(adev); 2091 if (r) 2092 return r; 2093 2094 return r; 2095 } 2096 2097 static int gfx_v9_4_3_hw_fini(void *handle) 2098 { 2099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2100 int i, num_xcc; 2101 2102 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2103 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2104 2105 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2106 for (i = 0; i < num_xcc; i++) { 2107 gfx_v9_4_3_xcc_fini(adev, i); 2108 } 2109 2110 return 0; 2111 } 2112 2113 static int gfx_v9_4_3_suspend(void *handle) 2114 { 2115 return gfx_v9_4_3_hw_fini(handle); 2116 } 2117 2118 static int gfx_v9_4_3_resume(void *handle) 2119 { 2120 return gfx_v9_4_3_hw_init(handle); 2121 } 2122 2123 static bool gfx_v9_4_3_is_idle(void *handle) 2124 { 2125 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2126 int i, num_xcc; 2127 2128 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2129 for (i = 0; i < num_xcc; i++) { 2130 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), regGRBM_STATUS), 2131 GRBM_STATUS, GUI_ACTIVE)) 2132 return false; 2133 } 2134 return true; 2135 } 2136 2137 static int gfx_v9_4_3_wait_for_idle(void *handle) 2138 { 2139 unsigned i; 2140 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2141 2142 for (i = 0; i < adev->usec_timeout; i++) { 2143 if (gfx_v9_4_3_is_idle(handle)) 2144 return 0; 2145 udelay(1); 2146 } 2147 return -ETIMEDOUT; 2148 } 2149 2150 static int gfx_v9_4_3_soft_reset(void *handle) 2151 { 2152 u32 grbm_soft_reset = 0; 2153 u32 tmp; 2154 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2155 2156 /* GRBM_STATUS */ 2157 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); 2158 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 2159 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 2160 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 2161 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 2162 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 2163 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 2164 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2165 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2166 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2167 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 2168 } 2169 2170 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 2171 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2172 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 2173 } 2174 2175 /* GRBM_STATUS2 */ 2176 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS2); 2177 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 2178 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 2179 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2180 2181 2182 if (grbm_soft_reset) { 2183 /* stop the rlc */ 2184 adev->gfx.rlc.funcs->stop(adev); 2185 2186 /* Disable MEC parsing/prefetching */ 2187 gfx_v9_4_3_xcc_cp_compute_enable(adev, false, 0); 2188 2189 if (grbm_soft_reset) { 2190 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2191 tmp |= grbm_soft_reset; 2192 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 2193 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2194 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2195 2196 udelay(50); 2197 2198 tmp &= ~grbm_soft_reset; 2199 WREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET, tmp); 2200 tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_SOFT_RESET); 2201 } 2202 2203 /* Wait a little for things to settle down */ 2204 udelay(50); 2205 } 2206 return 0; 2207 } 2208 2209 static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, 2210 uint32_t vmid, 2211 uint32_t gds_base, uint32_t gds_size, 2212 uint32_t gws_base, uint32_t gws_size, 2213 uint32_t oa_base, uint32_t oa_size) 2214 { 2215 struct amdgpu_device *adev = ring->adev; 2216 2217 /* GDS Base */ 2218 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2219 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_BASE) + 2 * vmid, 2220 gds_base); 2221 2222 /* GDS Size */ 2223 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2224 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_VMID0_SIZE) + 2 * vmid, 2225 gds_size); 2226 2227 /* GWS */ 2228 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2229 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_GWS_VMID0) + vmid, 2230 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 2231 2232 /* OA */ 2233 gfx_v9_4_3_write_data_to_reg(ring, 0, false, 2234 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regGDS_OA_VMID0) + vmid, 2235 (1 << (oa_size + oa_base)) - (1 << oa_base)); 2236 } 2237 2238 static int gfx_v9_4_3_early_init(void *handle) 2239 { 2240 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2241 2242 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2243 AMDGPU_MAX_COMPUTE_RINGS); 2244 gfx_v9_4_3_set_kiq_pm4_funcs(adev); 2245 gfx_v9_4_3_set_ring_funcs(adev); 2246 gfx_v9_4_3_set_irq_funcs(adev); 2247 gfx_v9_4_3_set_gds_init(adev); 2248 gfx_v9_4_3_set_rlc_funcs(adev); 2249 2250 /* init rlcg reg access ctrl */ 2251 gfx_v9_4_3_init_rlcg_reg_access_ctrl(adev); 2252 2253 return gfx_v9_4_3_init_microcode(adev); 2254 } 2255 2256 static int gfx_v9_4_3_late_init(void *handle) 2257 { 2258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2259 int r; 2260 2261 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2262 if (r) 2263 return r; 2264 2265 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2266 if (r) 2267 return r; 2268 2269 if (adev->gfx.ras && 2270 adev->gfx.ras->enable_watchdog_timer) 2271 adev->gfx.ras->enable_watchdog_timer(adev); 2272 2273 return 0; 2274 } 2275 2276 static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, 2277 bool enable, int xcc_id) 2278 { 2279 uint32_t def, data; 2280 2281 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 2282 return; 2283 2284 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2285 regRLC_CGTT_MGCG_OVERRIDE); 2286 2287 if (enable) 2288 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2289 else 2290 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 2291 2292 if (def != data) 2293 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2294 regRLC_CGTT_MGCG_OVERRIDE, data); 2295 2296 } 2297 2298 static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 2299 bool enable, int xcc_id) 2300 { 2301 uint32_t def, data; 2302 2303 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 2304 return; 2305 2306 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2307 regRLC_CGTT_MGCG_OVERRIDE); 2308 2309 if (enable) 2310 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2311 else 2312 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REP_FGCG_OVERRIDE_MASK; 2313 2314 if (def != data) 2315 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2316 regRLC_CGTT_MGCG_OVERRIDE, data); 2317 } 2318 2319 static void 2320 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(struct amdgpu_device *adev, 2321 bool enable, int xcc_id) 2322 { 2323 uint32_t data, def; 2324 2325 /* It is disabled by HW by default */ 2326 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 2327 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 2328 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2329 2330 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2331 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2332 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2333 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2334 2335 if (def != data) 2336 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2337 2338 /* MGLS is a global flag to control all MGLS in GFX */ 2339 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 2340 /* 2 - RLC memory Light sleep */ 2341 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 2342 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2343 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2344 if (def != data) 2345 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2346 } 2347 /* 3 - CP memory Light sleep */ 2348 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 2349 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2350 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2351 if (def != data) 2352 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2353 } 2354 } 2355 } else { 2356 /* 1 - MGCG_OVERRIDE */ 2357 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2358 2359 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 2360 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 2361 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 2362 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 2363 2364 if (def != data) 2365 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2366 2367 /* 2 - disable MGLS in RLC */ 2368 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL); 2369 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 2370 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 2371 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_MEM_SLP_CNTL, data); 2372 } 2373 2374 /* 3 - disable MGLS in CP */ 2375 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL); 2376 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 2377 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 2378 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEM_SLP_CNTL, data); 2379 } 2380 } 2381 2382 } 2383 2384 static void 2385 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2386 bool enable, int xcc_id) 2387 { 2388 uint32_t def, data; 2389 2390 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 2391 2392 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 2393 /* unset CGCG override */ 2394 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 2395 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2396 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2397 else 2398 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 2399 /* update CGCG and CGLS override bits */ 2400 if (def != data) 2401 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 2402 2403 /* enable cgcg FSM(0x0000363F) */ 2404 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2405 2406 data = (0x36 2407 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 2408 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 2409 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 2410 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 2411 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 2412 if (def != data) 2413 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2414 2415 /* set IDLE_POLL_COUNT(0x00900100) */ 2416 def = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 2417 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 2418 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2419 if (def != data) 2420 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 2421 } else { 2422 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 2423 /* reset CGCG/CGLS bits */ 2424 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 2425 /* disable cgcg and cgls in FSM */ 2426 if (def != data) 2427 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 2428 } 2429 2430 } 2431 2432 static int gfx_v9_4_3_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 2433 bool enable, int xcc_id) 2434 { 2435 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 2436 2437 if (enable) { 2438 /* FGCG */ 2439 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2440 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2441 2442 /* CGCG/CGLS should be enabled after MGCG/MGLS 2443 * === MGCG + MGLS === 2444 */ 2445 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2446 xcc_id); 2447 /* === CGCG + CGLS === */ 2448 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2449 xcc_id); 2450 } else { 2451 /* CGCG/CGLS should be disabled before MGCG/MGLS 2452 * === CGCG + CGLS === 2453 */ 2454 gfx_v9_4_3_xcc_update_coarse_grain_clock_gating(adev, enable, 2455 xcc_id); 2456 /* === MGCG + MGLS === */ 2457 gfx_v9_4_3_xcc_update_medium_grain_clock_gating(adev, enable, 2458 xcc_id); 2459 2460 /* FGCG */ 2461 gfx_v9_4_3_xcc_update_sram_fgcg(adev, enable, xcc_id); 2462 gfx_v9_4_3_xcc_update_repeater_fgcg(adev, enable, xcc_id); 2463 } 2464 2465 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 2466 2467 return 0; 2468 } 2469 2470 static const struct amdgpu_rlc_funcs gfx_v9_4_3_rlc_funcs = { 2471 .is_rlc_enabled = gfx_v9_4_3_is_rlc_enabled, 2472 .set_safe_mode = gfx_v9_4_3_xcc_set_safe_mode, 2473 .unset_safe_mode = gfx_v9_4_3_xcc_unset_safe_mode, 2474 .init = gfx_v9_4_3_rlc_init, 2475 .resume = gfx_v9_4_3_rlc_resume, 2476 .stop = gfx_v9_4_3_rlc_stop, 2477 .reset = gfx_v9_4_3_rlc_reset, 2478 .start = gfx_v9_4_3_rlc_start, 2479 .update_spm_vmid = gfx_v9_4_3_update_spm_vmid, 2480 .is_rlcg_access_range = gfx_v9_4_3_is_rlcg_access_range, 2481 }; 2482 2483 static int gfx_v9_4_3_set_powergating_state(void *handle, 2484 enum amd_powergating_state state) 2485 { 2486 return 0; 2487 } 2488 2489 static int gfx_v9_4_3_set_clockgating_state(void *handle, 2490 enum amd_clockgating_state state) 2491 { 2492 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2493 int i, num_xcc; 2494 2495 if (amdgpu_sriov_vf(adev)) 2496 return 0; 2497 2498 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2499 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2500 case IP_VERSION(9, 4, 3): 2501 for (i = 0; i < num_xcc; i++) 2502 gfx_v9_4_3_xcc_update_gfx_clock_gating( 2503 adev, state == AMD_CG_STATE_GATE, i); 2504 break; 2505 default: 2506 break; 2507 } 2508 return 0; 2509 } 2510 2511 static void gfx_v9_4_3_get_clockgating_state(void *handle, u64 *flags) 2512 { 2513 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2514 int data; 2515 2516 if (amdgpu_sriov_vf(adev)) 2517 *flags = 0; 2518 2519 /* AMD_CG_SUPPORT_GFX_MGCG */ 2520 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE)); 2521 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 2522 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 2523 2524 /* AMD_CG_SUPPORT_GFX_CGCG */ 2525 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL)); 2526 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 2527 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 2528 2529 /* AMD_CG_SUPPORT_GFX_CGLS */ 2530 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 2531 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 2532 2533 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 2534 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_MEM_SLP_CNTL)); 2535 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 2536 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 2537 2538 /* AMD_CG_SUPPORT_GFX_CP_LS */ 2539 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCP_MEM_SLP_CNTL)); 2540 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 2541 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 2542 } 2543 2544 static void gfx_v9_4_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) 2545 { 2546 struct amdgpu_device *adev = ring->adev; 2547 u32 ref_and_mask, reg_mem_engine; 2548 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 2549 2550 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 2551 switch (ring->me) { 2552 case 1: 2553 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 2554 break; 2555 case 2: 2556 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 2557 break; 2558 default: 2559 return; 2560 } 2561 reg_mem_engine = 0; 2562 } else { 2563 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 2564 reg_mem_engine = 1; /* pfp */ 2565 } 2566 2567 gfx_v9_4_3_wait_reg_mem(ring, reg_mem_engine, 0, 1, 2568 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 2569 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 2570 ref_and_mask, ref_and_mask, 0x20); 2571 } 2572 2573 static void gfx_v9_4_3_ring_emit_ib_compute(struct amdgpu_ring *ring, 2574 struct amdgpu_job *job, 2575 struct amdgpu_ib *ib, 2576 uint32_t flags) 2577 { 2578 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 2579 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 2580 2581 /* Currently, there is a high possibility to get wave ID mismatch 2582 * between ME and GDS, leading to a hw deadlock, because ME generates 2583 * different wave IDs than the GDS expects. This situation happens 2584 * randomly when at least 5 compute pipes use GDS ordered append. 2585 * The wave IDs generated by ME are also wrong after suspend/resume. 2586 * Those are probably bugs somewhere else in the kernel driver. 2587 * 2588 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 2589 * GDS to 0 for this ring (me/pipe). 2590 */ 2591 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 2592 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2593 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 2594 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 2595 } 2596 2597 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2598 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 2599 amdgpu_ring_write(ring, 2600 #ifdef __BIG_ENDIAN 2601 (2 << 0) | 2602 #endif 2603 lower_32_bits(ib->gpu_addr)); 2604 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 2605 amdgpu_ring_write(ring, control); 2606 } 2607 2608 static void gfx_v9_4_3_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 2609 u64 seq, unsigned flags) 2610 { 2611 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 2612 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 2613 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 2614 2615 /* RELEASE_MEM - flush caches, send int */ 2616 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 2617 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 2618 EOP_TC_NC_ACTION_EN) : 2619 (EOP_TCL1_ACTION_EN | 2620 EOP_TC_ACTION_EN | 2621 EOP_TC_WB_ACTION_EN | 2622 EOP_TC_MD_ACTION_EN)) | 2623 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 2624 EVENT_INDEX(5))); 2625 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 2626 2627 /* 2628 * the address should be Qword aligned if 64bit write, Dword 2629 * aligned if only send 32bit data low (discard data high) 2630 */ 2631 if (write64bit) 2632 BUG_ON(addr & 0x7); 2633 else 2634 BUG_ON(addr & 0x3); 2635 amdgpu_ring_write(ring, lower_32_bits(addr)); 2636 amdgpu_ring_write(ring, upper_32_bits(addr)); 2637 amdgpu_ring_write(ring, lower_32_bits(seq)); 2638 amdgpu_ring_write(ring, upper_32_bits(seq)); 2639 amdgpu_ring_write(ring, 0); 2640 } 2641 2642 static void gfx_v9_4_3_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 2643 { 2644 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 2645 uint32_t seq = ring->fence_drv.sync_seq; 2646 uint64_t addr = ring->fence_drv.gpu_addr; 2647 2648 gfx_v9_4_3_wait_reg_mem(ring, usepfp, 1, 0, 2649 lower_32_bits(addr), upper_32_bits(addr), 2650 seq, 0xffffffff, 4); 2651 } 2652 2653 static void gfx_v9_4_3_ring_emit_vm_flush(struct amdgpu_ring *ring, 2654 unsigned vmid, uint64_t pd_addr) 2655 { 2656 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 2657 } 2658 2659 static u64 gfx_v9_4_3_ring_get_rptr_compute(struct amdgpu_ring *ring) 2660 { 2661 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 2662 } 2663 2664 static u64 gfx_v9_4_3_ring_get_wptr_compute(struct amdgpu_ring *ring) 2665 { 2666 u64 wptr; 2667 2668 /* XXX check if swapping is necessary on BE */ 2669 if (ring->use_doorbell) 2670 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 2671 else 2672 BUG(); 2673 return wptr; 2674 } 2675 2676 static void gfx_v9_4_3_ring_set_wptr_compute(struct amdgpu_ring *ring) 2677 { 2678 struct amdgpu_device *adev = ring->adev; 2679 2680 /* XXX check if swapping is necessary on BE */ 2681 if (ring->use_doorbell) { 2682 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 2683 WDOORBELL64(ring->doorbell_index, ring->wptr); 2684 } else { 2685 BUG(); /* only DOORBELL method supported on gfx9 now */ 2686 } 2687 } 2688 2689 static void gfx_v9_4_3_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 2690 u64 seq, unsigned int flags) 2691 { 2692 struct amdgpu_device *adev = ring->adev; 2693 2694 /* we only allocate 32bit for each seq wb address */ 2695 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 2696 2697 /* write fence seq to the "addr" */ 2698 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2699 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2700 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 2701 amdgpu_ring_write(ring, lower_32_bits(addr)); 2702 amdgpu_ring_write(ring, upper_32_bits(addr)); 2703 amdgpu_ring_write(ring, lower_32_bits(seq)); 2704 2705 if (flags & AMDGPU_FENCE_FLAG_INT) { 2706 /* set register to trigger INT */ 2707 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2708 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2709 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 2710 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS)); 2711 amdgpu_ring_write(ring, 0); 2712 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 2713 } 2714 } 2715 2716 static void gfx_v9_4_3_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 2717 uint32_t reg_val_offs) 2718 { 2719 struct amdgpu_device *adev = ring->adev; 2720 2721 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 2722 amdgpu_ring_write(ring, 0 | /* src: register*/ 2723 (5 << 8) | /* dst: memory */ 2724 (1 << 20)); /* write confirm */ 2725 amdgpu_ring_write(ring, reg); 2726 amdgpu_ring_write(ring, 0); 2727 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 2728 reg_val_offs * 4)); 2729 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 2730 reg_val_offs * 4)); 2731 } 2732 2733 static void gfx_v9_4_3_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 2734 uint32_t val) 2735 { 2736 uint32_t cmd = 0; 2737 2738 switch (ring->funcs->type) { 2739 case AMDGPU_RING_TYPE_GFX: 2740 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 2741 break; 2742 case AMDGPU_RING_TYPE_KIQ: 2743 cmd = (1 << 16); /* no inc addr */ 2744 break; 2745 default: 2746 cmd = WR_CONFIRM; 2747 break; 2748 } 2749 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 2750 amdgpu_ring_write(ring, cmd); 2751 amdgpu_ring_write(ring, reg); 2752 amdgpu_ring_write(ring, 0); 2753 amdgpu_ring_write(ring, val); 2754 } 2755 2756 static void gfx_v9_4_3_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 2757 uint32_t val, uint32_t mask) 2758 { 2759 gfx_v9_4_3_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 2760 } 2761 2762 static void gfx_v9_4_3_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 2763 uint32_t reg0, uint32_t reg1, 2764 uint32_t ref, uint32_t mask) 2765 { 2766 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 2767 ref, mask); 2768 } 2769 2770 static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2771 struct amdgpu_device *adev, int me, int pipe, 2772 enum amdgpu_interrupt_state state, int xcc_id) 2773 { 2774 u32 mec_int_cntl, mec_int_cntl_reg; 2775 2776 /* 2777 * amdgpu controls only the first MEC. That's why this function only 2778 * handles the setting of interrupts for this specific MEC. All other 2779 * pipes' interrupts are set by amdkfd. 2780 */ 2781 2782 if (me == 1) { 2783 switch (pipe) { 2784 case 0: 2785 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE0_INT_CNTL); 2786 break; 2787 case 1: 2788 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE1_INT_CNTL); 2789 break; 2790 case 2: 2791 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE2_INT_CNTL); 2792 break; 2793 case 3: 2794 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regCP_ME1_PIPE3_INT_CNTL); 2795 break; 2796 default: 2797 DRM_DEBUG("invalid pipe %d\n", pipe); 2798 return; 2799 } 2800 } else { 2801 DRM_DEBUG("invalid me %d\n", me); 2802 return; 2803 } 2804 2805 switch (state) { 2806 case AMDGPU_IRQ_STATE_DISABLE: 2807 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2808 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2809 TIME_STAMP_INT_ENABLE, 0); 2810 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2811 break; 2812 case AMDGPU_IRQ_STATE_ENABLE: 2813 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 2814 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 2815 TIME_STAMP_INT_ENABLE, 1); 2816 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 2817 break; 2818 default: 2819 break; 2820 } 2821 } 2822 2823 static int gfx_v9_4_3_set_priv_reg_fault_state(struct amdgpu_device *adev, 2824 struct amdgpu_irq_src *source, 2825 unsigned type, 2826 enum amdgpu_interrupt_state state) 2827 { 2828 int i, num_xcc; 2829 2830 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2831 switch (state) { 2832 case AMDGPU_IRQ_STATE_DISABLE: 2833 case AMDGPU_IRQ_STATE_ENABLE: 2834 for (i = 0; i < num_xcc; i++) 2835 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2836 PRIV_REG_INT_ENABLE, 2837 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2838 break; 2839 default: 2840 break; 2841 } 2842 2843 return 0; 2844 } 2845 2846 static int gfx_v9_4_3_set_priv_inst_fault_state(struct amdgpu_device *adev, 2847 struct amdgpu_irq_src *source, 2848 unsigned type, 2849 enum amdgpu_interrupt_state state) 2850 { 2851 int i, num_xcc; 2852 2853 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2854 switch (state) { 2855 case AMDGPU_IRQ_STATE_DISABLE: 2856 case AMDGPU_IRQ_STATE_ENABLE: 2857 for (i = 0; i < num_xcc; i++) 2858 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 2859 PRIV_INSTR_INT_ENABLE, 2860 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 2861 break; 2862 default: 2863 break; 2864 } 2865 2866 return 0; 2867 } 2868 2869 static int gfx_v9_4_3_set_eop_interrupt_state(struct amdgpu_device *adev, 2870 struct amdgpu_irq_src *src, 2871 unsigned type, 2872 enum amdgpu_interrupt_state state) 2873 { 2874 int i, num_xcc; 2875 2876 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2877 for (i = 0; i < num_xcc; i++) { 2878 switch (type) { 2879 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 2880 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2881 adev, 1, 0, state, i); 2882 break; 2883 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 2884 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2885 adev, 1, 1, state, i); 2886 break; 2887 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 2888 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2889 adev, 1, 2, state, i); 2890 break; 2891 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 2892 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2893 adev, 1, 3, state, i); 2894 break; 2895 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 2896 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2897 adev, 2, 0, state, i); 2898 break; 2899 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 2900 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2901 adev, 2, 1, state, i); 2902 break; 2903 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 2904 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2905 adev, 2, 2, state, i); 2906 break; 2907 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 2908 gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( 2909 adev, 2, 3, state, i); 2910 break; 2911 default: 2912 break; 2913 } 2914 } 2915 2916 return 0; 2917 } 2918 2919 static int gfx_v9_4_3_eop_irq(struct amdgpu_device *adev, 2920 struct amdgpu_irq_src *source, 2921 struct amdgpu_iv_entry *entry) 2922 { 2923 int i, xcc_id; 2924 u8 me_id, pipe_id, queue_id; 2925 struct amdgpu_ring *ring; 2926 2927 DRM_DEBUG("IH: CP EOP\n"); 2928 me_id = (entry->ring_id & 0x0c) >> 2; 2929 pipe_id = (entry->ring_id & 0x03) >> 0; 2930 queue_id = (entry->ring_id & 0x70) >> 4; 2931 2932 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2933 2934 if (xcc_id == -EINVAL) 2935 return -EINVAL; 2936 2937 switch (me_id) { 2938 case 0: 2939 case 1: 2940 case 2: 2941 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2942 ring = &adev->gfx.compute_ring 2943 [i + 2944 xcc_id * adev->gfx.num_compute_rings]; 2945 /* Per-queue interrupt is supported for MEC starting from VI. 2946 * The interrupt can only be enabled/disabled per pipe instead of per queue. 2947 */ 2948 2949 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 2950 amdgpu_fence_process(ring); 2951 } 2952 break; 2953 } 2954 return 0; 2955 } 2956 2957 static void gfx_v9_4_3_fault(struct amdgpu_device *adev, 2958 struct amdgpu_iv_entry *entry) 2959 { 2960 u8 me_id, pipe_id, queue_id; 2961 struct amdgpu_ring *ring; 2962 int i, xcc_id; 2963 2964 me_id = (entry->ring_id & 0x0c) >> 2; 2965 pipe_id = (entry->ring_id & 0x03) >> 0; 2966 queue_id = (entry->ring_id & 0x70) >> 4; 2967 2968 xcc_id = gfx_v9_4_3_ih_to_xcc_inst(adev, entry->node_id); 2969 2970 if (xcc_id == -EINVAL) 2971 return; 2972 2973 switch (me_id) { 2974 case 0: 2975 case 1: 2976 case 2: 2977 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2978 ring = &adev->gfx.compute_ring 2979 [i + 2980 xcc_id * adev->gfx.num_compute_rings]; 2981 if (ring->me == me_id && ring->pipe == pipe_id && 2982 ring->queue == queue_id) 2983 drm_sched_fault(&ring->sched); 2984 } 2985 break; 2986 } 2987 } 2988 2989 static int gfx_v9_4_3_priv_reg_irq(struct amdgpu_device *adev, 2990 struct amdgpu_irq_src *source, 2991 struct amdgpu_iv_entry *entry) 2992 { 2993 DRM_ERROR("Illegal register access in command stream\n"); 2994 gfx_v9_4_3_fault(adev, entry); 2995 return 0; 2996 } 2997 2998 static int gfx_v9_4_3_priv_inst_irq(struct amdgpu_device *adev, 2999 struct amdgpu_irq_src *source, 3000 struct amdgpu_iv_entry *entry) 3001 { 3002 DRM_ERROR("Illegal instruction in command stream\n"); 3003 gfx_v9_4_3_fault(adev, entry); 3004 return 0; 3005 } 3006 3007 static void gfx_v9_4_3_emit_mem_sync(struct amdgpu_ring *ring) 3008 { 3009 const unsigned int cp_coher_cntl = 3010 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_ICACHE_ACTION_ENA(1) | 3011 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_SH_KCACHE_ACTION_ENA(1) | 3012 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_ACTION_ENA(1) | 3013 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TCL1_ACTION_ENA(1) | 3014 PACKET3_ACQUIRE_MEM_CP_COHER_CNTL_TC_WB_ACTION_ENA(1); 3015 3016 /* ACQUIRE_MEM -make one or more surfaces valid for use by the subsequent operations */ 3017 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 5)); 3018 amdgpu_ring_write(ring, cp_coher_cntl); /* CP_COHER_CNTL */ 3019 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3020 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3021 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3022 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3023 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3024 } 3025 3026 static void gfx_v9_4_3_emit_wave_limit_cs(struct amdgpu_ring *ring, 3027 uint32_t pipe, bool enable) 3028 { 3029 struct amdgpu_device *adev = ring->adev; 3030 uint32_t val; 3031 uint32_t wcl_cs_reg; 3032 3033 /* regSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ 3034 val = enable ? 0x1 : 0x7f; 3035 3036 switch (pipe) { 3037 case 0: 3038 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS0); 3039 break; 3040 case 1: 3041 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS1); 3042 break; 3043 case 2: 3044 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS2); 3045 break; 3046 case 3: 3047 wcl_cs_reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_CS3); 3048 break; 3049 default: 3050 DRM_DEBUG("invalid pipe %d\n", pipe); 3051 return; 3052 } 3053 3054 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); 3055 3056 } 3057 static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) 3058 { 3059 struct amdgpu_device *adev = ring->adev; 3060 uint32_t val; 3061 int i; 3062 3063 /* regSPI_WCL_PIPE_PERCENT_GFX is 7 bit multiplier register to limit 3064 * number of gfx waves. Setting 5 bit will make sure gfx only gets 3065 * around 25% of gpu resources. 3066 */ 3067 val = enable ? 0x1f : 0x07ffffff; 3068 amdgpu_ring_emit_wreg(ring, 3069 SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regSPI_WCL_PIPE_PERCENT_GFX), 3070 val); 3071 3072 /* Restrict waves for normal/low priority compute queues as well 3073 * to get best QoS for high priority compute jobs. 3074 * 3075 * amdgpu controls only 1st ME(0-3 CS pipes). 3076 */ 3077 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 3078 if (i != ring->pipe) 3079 gfx_v9_4_3_emit_wave_limit_cs(ring, i, enable); 3080 3081 } 3082 } 3083 3084 enum amdgpu_gfx_cp_ras_mem_id { 3085 AMDGPU_GFX_CP_MEM1 = 1, 3086 AMDGPU_GFX_CP_MEM2, 3087 AMDGPU_GFX_CP_MEM3, 3088 AMDGPU_GFX_CP_MEM4, 3089 AMDGPU_GFX_CP_MEM5, 3090 }; 3091 3092 enum amdgpu_gfx_gcea_ras_mem_id { 3093 AMDGPU_GFX_GCEA_IOWR_CMDMEM = 4, 3094 AMDGPU_GFX_GCEA_IORD_CMDMEM, 3095 AMDGPU_GFX_GCEA_GMIWR_CMDMEM, 3096 AMDGPU_GFX_GCEA_GMIRD_CMDMEM, 3097 AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, 3098 AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, 3099 AMDGPU_GFX_GCEA_MAM_DMEM0, 3100 AMDGPU_GFX_GCEA_MAM_DMEM1, 3101 AMDGPU_GFX_GCEA_MAM_DMEM2, 3102 AMDGPU_GFX_GCEA_MAM_DMEM3, 3103 AMDGPU_GFX_GCEA_MAM_AMEM0, 3104 AMDGPU_GFX_GCEA_MAM_AMEM1, 3105 AMDGPU_GFX_GCEA_MAM_AMEM2, 3106 AMDGPU_GFX_GCEA_MAM_AMEM3, 3107 AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, 3108 AMDGPU_GFX_GCEA_WRET_TAGMEM, 3109 AMDGPU_GFX_GCEA_RRET_TAGMEM, 3110 AMDGPU_GFX_GCEA_IOWR_DATAMEM, 3111 AMDGPU_GFX_GCEA_GMIWR_DATAMEM, 3112 AMDGPU_GFX_GCEA_DRAM_DATAMEM, 3113 }; 3114 3115 enum amdgpu_gfx_gc_cane_ras_mem_id { 3116 AMDGPU_GFX_GC_CANE_MEM0 = 0, 3117 }; 3118 3119 enum amdgpu_gfx_gcutcl2_ras_mem_id { 3120 AMDGPU_GFX_GCUTCL2_MEM2P512X95 = 160, 3121 }; 3122 3123 enum amdgpu_gfx_gds_ras_mem_id { 3124 AMDGPU_GFX_GDS_MEM0 = 0, 3125 }; 3126 3127 enum amdgpu_gfx_lds_ras_mem_id { 3128 AMDGPU_GFX_LDS_BANK0 = 0, 3129 AMDGPU_GFX_LDS_BANK1, 3130 AMDGPU_GFX_LDS_BANK2, 3131 AMDGPU_GFX_LDS_BANK3, 3132 AMDGPU_GFX_LDS_BANK4, 3133 AMDGPU_GFX_LDS_BANK5, 3134 AMDGPU_GFX_LDS_BANK6, 3135 AMDGPU_GFX_LDS_BANK7, 3136 AMDGPU_GFX_LDS_BANK8, 3137 AMDGPU_GFX_LDS_BANK9, 3138 AMDGPU_GFX_LDS_BANK10, 3139 AMDGPU_GFX_LDS_BANK11, 3140 AMDGPU_GFX_LDS_BANK12, 3141 AMDGPU_GFX_LDS_BANK13, 3142 AMDGPU_GFX_LDS_BANK14, 3143 AMDGPU_GFX_LDS_BANK15, 3144 AMDGPU_GFX_LDS_BANK16, 3145 AMDGPU_GFX_LDS_BANK17, 3146 AMDGPU_GFX_LDS_BANK18, 3147 AMDGPU_GFX_LDS_BANK19, 3148 AMDGPU_GFX_LDS_BANK20, 3149 AMDGPU_GFX_LDS_BANK21, 3150 AMDGPU_GFX_LDS_BANK22, 3151 AMDGPU_GFX_LDS_BANK23, 3152 AMDGPU_GFX_LDS_BANK24, 3153 AMDGPU_GFX_LDS_BANK25, 3154 AMDGPU_GFX_LDS_BANK26, 3155 AMDGPU_GFX_LDS_BANK27, 3156 AMDGPU_GFX_LDS_BANK28, 3157 AMDGPU_GFX_LDS_BANK29, 3158 AMDGPU_GFX_LDS_BANK30, 3159 AMDGPU_GFX_LDS_BANK31, 3160 AMDGPU_GFX_LDS_SP_BUFFER_A, 3161 AMDGPU_GFX_LDS_SP_BUFFER_B, 3162 }; 3163 3164 enum amdgpu_gfx_rlc_ras_mem_id { 3165 AMDGPU_GFX_RLC_GPMF32 = 1, 3166 AMDGPU_GFX_RLC_RLCVF32, 3167 AMDGPU_GFX_RLC_SCRATCH, 3168 AMDGPU_GFX_RLC_SRM_ARAM, 3169 AMDGPU_GFX_RLC_SRM_DRAM, 3170 AMDGPU_GFX_RLC_TCTAG, 3171 AMDGPU_GFX_RLC_SPM_SE, 3172 AMDGPU_GFX_RLC_SPM_GRBMT, 3173 }; 3174 3175 enum amdgpu_gfx_sp_ras_mem_id { 3176 AMDGPU_GFX_SP_SIMDID0 = 0, 3177 }; 3178 3179 enum amdgpu_gfx_spi_ras_mem_id { 3180 AMDGPU_GFX_SPI_MEM0 = 0, 3181 AMDGPU_GFX_SPI_MEM1, 3182 AMDGPU_GFX_SPI_MEM2, 3183 AMDGPU_GFX_SPI_MEM3, 3184 }; 3185 3186 enum amdgpu_gfx_sqc_ras_mem_id { 3187 AMDGPU_GFX_SQC_INST_CACHE_A = 100, 3188 AMDGPU_GFX_SQC_INST_CACHE_B = 101, 3189 AMDGPU_GFX_SQC_INST_CACHE_TAG_A = 102, 3190 AMDGPU_GFX_SQC_INST_CACHE_TAG_B = 103, 3191 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A = 104, 3192 AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B = 105, 3193 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A = 106, 3194 AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B = 107, 3195 AMDGPU_GFX_SQC_DATA_CACHE_A = 200, 3196 AMDGPU_GFX_SQC_DATA_CACHE_B = 201, 3197 AMDGPU_GFX_SQC_DATA_CACHE_TAG_A = 202, 3198 AMDGPU_GFX_SQC_DATA_CACHE_TAG_B = 203, 3199 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A = 204, 3200 AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B = 205, 3201 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A = 206, 3202 AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B = 207, 3203 AMDGPU_GFX_SQC_DIRTY_BIT_A = 208, 3204 AMDGPU_GFX_SQC_DIRTY_BIT_B = 209, 3205 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0 = 210, 3206 AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1 = 211, 3207 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A = 212, 3208 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B = 213, 3209 AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE = 108, 3210 }; 3211 3212 enum amdgpu_gfx_sq_ras_mem_id { 3213 AMDGPU_GFX_SQ_SGPR_MEM0 = 0, 3214 AMDGPU_GFX_SQ_SGPR_MEM1, 3215 AMDGPU_GFX_SQ_SGPR_MEM2, 3216 AMDGPU_GFX_SQ_SGPR_MEM3, 3217 }; 3218 3219 enum amdgpu_gfx_ta_ras_mem_id { 3220 AMDGPU_GFX_TA_FS_AFIFO_RAM_LO = 1, 3221 AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, 3222 AMDGPU_GFX_TA_FS_CFIFO_RAM, 3223 AMDGPU_GFX_TA_FSX_LFIFO, 3224 AMDGPU_GFX_TA_FS_DFIFO_RAM, 3225 }; 3226 3227 enum amdgpu_gfx_tcc_ras_mem_id { 3228 AMDGPU_GFX_TCC_MEM1 = 1, 3229 }; 3230 3231 enum amdgpu_gfx_tca_ras_mem_id { 3232 AMDGPU_GFX_TCA_MEM1 = 1, 3233 }; 3234 3235 enum amdgpu_gfx_tci_ras_mem_id { 3236 AMDGPU_GFX_TCIW_MEM = 1, 3237 }; 3238 3239 enum amdgpu_gfx_tcp_ras_mem_id { 3240 AMDGPU_GFX_TCP_LFIFO0 = 1, 3241 AMDGPU_GFX_TCP_SET0BANK0_RAM, 3242 AMDGPU_GFX_TCP_SET0BANK1_RAM, 3243 AMDGPU_GFX_TCP_SET0BANK2_RAM, 3244 AMDGPU_GFX_TCP_SET0BANK3_RAM, 3245 AMDGPU_GFX_TCP_SET1BANK0_RAM, 3246 AMDGPU_GFX_TCP_SET1BANK1_RAM, 3247 AMDGPU_GFX_TCP_SET1BANK2_RAM, 3248 AMDGPU_GFX_TCP_SET1BANK3_RAM, 3249 AMDGPU_GFX_TCP_SET2BANK0_RAM, 3250 AMDGPU_GFX_TCP_SET2BANK1_RAM, 3251 AMDGPU_GFX_TCP_SET2BANK2_RAM, 3252 AMDGPU_GFX_TCP_SET2BANK3_RAM, 3253 AMDGPU_GFX_TCP_SET3BANK0_RAM, 3254 AMDGPU_GFX_TCP_SET3BANK1_RAM, 3255 AMDGPU_GFX_TCP_SET3BANK2_RAM, 3256 AMDGPU_GFX_TCP_SET3BANK3_RAM, 3257 AMDGPU_GFX_TCP_VM_FIFO, 3258 AMDGPU_GFX_TCP_DB_TAGRAM0, 3259 AMDGPU_GFX_TCP_DB_TAGRAM1, 3260 AMDGPU_GFX_TCP_DB_TAGRAM2, 3261 AMDGPU_GFX_TCP_DB_TAGRAM3, 3262 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, 3263 AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, 3264 AMDGPU_GFX_TCP_CMD_FIFO, 3265 }; 3266 3267 enum amdgpu_gfx_td_ras_mem_id { 3268 AMDGPU_GFX_TD_UTD_CS_FIFO_MEM = 1, 3269 AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, 3270 AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, 3271 }; 3272 3273 enum amdgpu_gfx_tcx_ras_mem_id { 3274 AMDGPU_GFX_TCX_FIFOD0 = 0, 3275 AMDGPU_GFX_TCX_FIFOD1, 3276 AMDGPU_GFX_TCX_FIFOD2, 3277 AMDGPU_GFX_TCX_FIFOD3, 3278 AMDGPU_GFX_TCX_FIFOD4, 3279 AMDGPU_GFX_TCX_FIFOD5, 3280 AMDGPU_GFX_TCX_FIFOD6, 3281 AMDGPU_GFX_TCX_FIFOD7, 3282 AMDGPU_GFX_TCX_FIFOB0, 3283 AMDGPU_GFX_TCX_FIFOB1, 3284 AMDGPU_GFX_TCX_FIFOB2, 3285 AMDGPU_GFX_TCX_FIFOB3, 3286 AMDGPU_GFX_TCX_FIFOB4, 3287 AMDGPU_GFX_TCX_FIFOB5, 3288 AMDGPU_GFX_TCX_FIFOB6, 3289 AMDGPU_GFX_TCX_FIFOB7, 3290 AMDGPU_GFX_TCX_FIFOA0, 3291 AMDGPU_GFX_TCX_FIFOA1, 3292 AMDGPU_GFX_TCX_FIFOA2, 3293 AMDGPU_GFX_TCX_FIFOA3, 3294 AMDGPU_GFX_TCX_FIFOA4, 3295 AMDGPU_GFX_TCX_FIFOA5, 3296 AMDGPU_GFX_TCX_FIFOA6, 3297 AMDGPU_GFX_TCX_FIFOA7, 3298 AMDGPU_GFX_TCX_CFIFO0, 3299 AMDGPU_GFX_TCX_CFIFO1, 3300 AMDGPU_GFX_TCX_CFIFO2, 3301 AMDGPU_GFX_TCX_CFIFO3, 3302 AMDGPU_GFX_TCX_CFIFO4, 3303 AMDGPU_GFX_TCX_CFIFO5, 3304 AMDGPU_GFX_TCX_CFIFO6, 3305 AMDGPU_GFX_TCX_CFIFO7, 3306 AMDGPU_GFX_TCX_FIFO_ACKB0, 3307 AMDGPU_GFX_TCX_FIFO_ACKB1, 3308 AMDGPU_GFX_TCX_FIFO_ACKB2, 3309 AMDGPU_GFX_TCX_FIFO_ACKB3, 3310 AMDGPU_GFX_TCX_FIFO_ACKB4, 3311 AMDGPU_GFX_TCX_FIFO_ACKB5, 3312 AMDGPU_GFX_TCX_FIFO_ACKB6, 3313 AMDGPU_GFX_TCX_FIFO_ACKB7, 3314 AMDGPU_GFX_TCX_FIFO_ACKD0, 3315 AMDGPU_GFX_TCX_FIFO_ACKD1, 3316 AMDGPU_GFX_TCX_FIFO_ACKD2, 3317 AMDGPU_GFX_TCX_FIFO_ACKD3, 3318 AMDGPU_GFX_TCX_FIFO_ACKD4, 3319 AMDGPU_GFX_TCX_FIFO_ACKD5, 3320 AMDGPU_GFX_TCX_FIFO_ACKD6, 3321 AMDGPU_GFX_TCX_FIFO_ACKD7, 3322 AMDGPU_GFX_TCX_DST_FIFOA0, 3323 AMDGPU_GFX_TCX_DST_FIFOA1, 3324 AMDGPU_GFX_TCX_DST_FIFOA2, 3325 AMDGPU_GFX_TCX_DST_FIFOA3, 3326 AMDGPU_GFX_TCX_DST_FIFOA4, 3327 AMDGPU_GFX_TCX_DST_FIFOA5, 3328 AMDGPU_GFX_TCX_DST_FIFOA6, 3329 AMDGPU_GFX_TCX_DST_FIFOA7, 3330 AMDGPU_GFX_TCX_DST_FIFOB0, 3331 AMDGPU_GFX_TCX_DST_FIFOB1, 3332 AMDGPU_GFX_TCX_DST_FIFOB2, 3333 AMDGPU_GFX_TCX_DST_FIFOB3, 3334 AMDGPU_GFX_TCX_DST_FIFOB4, 3335 AMDGPU_GFX_TCX_DST_FIFOB5, 3336 AMDGPU_GFX_TCX_DST_FIFOB6, 3337 AMDGPU_GFX_TCX_DST_FIFOB7, 3338 AMDGPU_GFX_TCX_DST_FIFOD0, 3339 AMDGPU_GFX_TCX_DST_FIFOD1, 3340 AMDGPU_GFX_TCX_DST_FIFOD2, 3341 AMDGPU_GFX_TCX_DST_FIFOD3, 3342 AMDGPU_GFX_TCX_DST_FIFOD4, 3343 AMDGPU_GFX_TCX_DST_FIFOD5, 3344 AMDGPU_GFX_TCX_DST_FIFOD6, 3345 AMDGPU_GFX_TCX_DST_FIFOD7, 3346 AMDGPU_GFX_TCX_DST_FIFO_ACKB0, 3347 AMDGPU_GFX_TCX_DST_FIFO_ACKB1, 3348 AMDGPU_GFX_TCX_DST_FIFO_ACKB2, 3349 AMDGPU_GFX_TCX_DST_FIFO_ACKB3, 3350 AMDGPU_GFX_TCX_DST_FIFO_ACKB4, 3351 AMDGPU_GFX_TCX_DST_FIFO_ACKB5, 3352 AMDGPU_GFX_TCX_DST_FIFO_ACKB6, 3353 AMDGPU_GFX_TCX_DST_FIFO_ACKB7, 3354 AMDGPU_GFX_TCX_DST_FIFO_ACKD0, 3355 AMDGPU_GFX_TCX_DST_FIFO_ACKD1, 3356 AMDGPU_GFX_TCX_DST_FIFO_ACKD2, 3357 AMDGPU_GFX_TCX_DST_FIFO_ACKD3, 3358 AMDGPU_GFX_TCX_DST_FIFO_ACKD4, 3359 AMDGPU_GFX_TCX_DST_FIFO_ACKD5, 3360 AMDGPU_GFX_TCX_DST_FIFO_ACKD6, 3361 AMDGPU_GFX_TCX_DST_FIFO_ACKD7, 3362 }; 3363 3364 enum amdgpu_gfx_atc_l2_ras_mem_id { 3365 AMDGPU_GFX_ATC_L2_MEM0 = 0, 3366 }; 3367 3368 enum amdgpu_gfx_utcl2_ras_mem_id { 3369 AMDGPU_GFX_UTCL2_MEM0 = 0, 3370 }; 3371 3372 enum amdgpu_gfx_vml2_ras_mem_id { 3373 AMDGPU_GFX_VML2_MEM0 = 0, 3374 }; 3375 3376 enum amdgpu_gfx_vml2_walker_ras_mem_id { 3377 AMDGPU_GFX_VML2_WALKER_MEM0 = 0, 3378 }; 3379 3380 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_cp_mem_list[] = { 3381 {AMDGPU_GFX_CP_MEM1, "CP_MEM1"}, 3382 {AMDGPU_GFX_CP_MEM2, "CP_MEM2"}, 3383 {AMDGPU_GFX_CP_MEM3, "CP_MEM3"}, 3384 {AMDGPU_GFX_CP_MEM4, "CP_MEM4"}, 3385 {AMDGPU_GFX_CP_MEM5, "CP_MEM5"}, 3386 }; 3387 3388 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcea_mem_list[] = { 3389 {AMDGPU_GFX_GCEA_IOWR_CMDMEM, "GCEA_IOWR_CMDMEM"}, 3390 {AMDGPU_GFX_GCEA_IORD_CMDMEM, "GCEA_IORD_CMDMEM"}, 3391 {AMDGPU_GFX_GCEA_GMIWR_CMDMEM, "GCEA_GMIWR_CMDMEM"}, 3392 {AMDGPU_GFX_GCEA_GMIRD_CMDMEM, "GCEA_GMIRD_CMDMEM"}, 3393 {AMDGPU_GFX_GCEA_DRAMWR_CMDMEM, "GCEA_DRAMWR_CMDMEM"}, 3394 {AMDGPU_GFX_GCEA_DRAMRD_CMDMEM, "GCEA_DRAMRD_CMDMEM"}, 3395 {AMDGPU_GFX_GCEA_MAM_DMEM0, "GCEA_MAM_DMEM0"}, 3396 {AMDGPU_GFX_GCEA_MAM_DMEM1, "GCEA_MAM_DMEM1"}, 3397 {AMDGPU_GFX_GCEA_MAM_DMEM2, "GCEA_MAM_DMEM2"}, 3398 {AMDGPU_GFX_GCEA_MAM_DMEM3, "GCEA_MAM_DMEM3"}, 3399 {AMDGPU_GFX_GCEA_MAM_AMEM0, "GCEA_MAM_AMEM0"}, 3400 {AMDGPU_GFX_GCEA_MAM_AMEM1, "GCEA_MAM_AMEM1"}, 3401 {AMDGPU_GFX_GCEA_MAM_AMEM2, "GCEA_MAM_AMEM2"}, 3402 {AMDGPU_GFX_GCEA_MAM_AMEM3, "GCEA_MAM_AMEM3"}, 3403 {AMDGPU_GFX_GCEA_MAM_AFLUSH_BUFFER, "GCEA_MAM_AFLUSH_BUFFER"}, 3404 {AMDGPU_GFX_GCEA_WRET_TAGMEM, "GCEA_WRET_TAGMEM"}, 3405 {AMDGPU_GFX_GCEA_RRET_TAGMEM, "GCEA_RRET_TAGMEM"}, 3406 {AMDGPU_GFX_GCEA_IOWR_DATAMEM, "GCEA_IOWR_DATAMEM"}, 3407 {AMDGPU_GFX_GCEA_GMIWR_DATAMEM, "GCEA_GMIWR_DATAMEM"}, 3408 {AMDGPU_GFX_GCEA_DRAM_DATAMEM, "GCEA_DRAM_DATAMEM"}, 3409 }; 3410 3411 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gc_cane_mem_list[] = { 3412 {AMDGPU_GFX_GC_CANE_MEM0, "GC_CANE_MEM0"}, 3413 }; 3414 3415 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gcutcl2_mem_list[] = { 3416 {AMDGPU_GFX_GCUTCL2_MEM2P512X95, "GCUTCL2_MEM2P512X95"}, 3417 }; 3418 3419 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_gds_mem_list[] = { 3420 {AMDGPU_GFX_GDS_MEM0, "GDS_MEM"}, 3421 }; 3422 3423 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_lds_mem_list[] = { 3424 {AMDGPU_GFX_LDS_BANK0, "LDS_BANK0"}, 3425 {AMDGPU_GFX_LDS_BANK1, "LDS_BANK1"}, 3426 {AMDGPU_GFX_LDS_BANK2, "LDS_BANK2"}, 3427 {AMDGPU_GFX_LDS_BANK3, "LDS_BANK3"}, 3428 {AMDGPU_GFX_LDS_BANK4, "LDS_BANK4"}, 3429 {AMDGPU_GFX_LDS_BANK5, "LDS_BANK5"}, 3430 {AMDGPU_GFX_LDS_BANK6, "LDS_BANK6"}, 3431 {AMDGPU_GFX_LDS_BANK7, "LDS_BANK7"}, 3432 {AMDGPU_GFX_LDS_BANK8, "LDS_BANK8"}, 3433 {AMDGPU_GFX_LDS_BANK9, "LDS_BANK9"}, 3434 {AMDGPU_GFX_LDS_BANK10, "LDS_BANK10"}, 3435 {AMDGPU_GFX_LDS_BANK11, "LDS_BANK11"}, 3436 {AMDGPU_GFX_LDS_BANK12, "LDS_BANK12"}, 3437 {AMDGPU_GFX_LDS_BANK13, "LDS_BANK13"}, 3438 {AMDGPU_GFX_LDS_BANK14, "LDS_BANK14"}, 3439 {AMDGPU_GFX_LDS_BANK15, "LDS_BANK15"}, 3440 {AMDGPU_GFX_LDS_BANK16, "LDS_BANK16"}, 3441 {AMDGPU_GFX_LDS_BANK17, "LDS_BANK17"}, 3442 {AMDGPU_GFX_LDS_BANK18, "LDS_BANK18"}, 3443 {AMDGPU_GFX_LDS_BANK19, "LDS_BANK19"}, 3444 {AMDGPU_GFX_LDS_BANK20, "LDS_BANK20"}, 3445 {AMDGPU_GFX_LDS_BANK21, "LDS_BANK21"}, 3446 {AMDGPU_GFX_LDS_BANK22, "LDS_BANK22"}, 3447 {AMDGPU_GFX_LDS_BANK23, "LDS_BANK23"}, 3448 {AMDGPU_GFX_LDS_BANK24, "LDS_BANK24"}, 3449 {AMDGPU_GFX_LDS_BANK25, "LDS_BANK25"}, 3450 {AMDGPU_GFX_LDS_BANK26, "LDS_BANK26"}, 3451 {AMDGPU_GFX_LDS_BANK27, "LDS_BANK27"}, 3452 {AMDGPU_GFX_LDS_BANK28, "LDS_BANK28"}, 3453 {AMDGPU_GFX_LDS_BANK29, "LDS_BANK29"}, 3454 {AMDGPU_GFX_LDS_BANK30, "LDS_BANK30"}, 3455 {AMDGPU_GFX_LDS_BANK31, "LDS_BANK31"}, 3456 {AMDGPU_GFX_LDS_SP_BUFFER_A, "LDS_SP_BUFFER_A"}, 3457 {AMDGPU_GFX_LDS_SP_BUFFER_B, "LDS_SP_BUFFER_B"}, 3458 }; 3459 3460 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_rlc_mem_list[] = { 3461 {AMDGPU_GFX_RLC_GPMF32, "RLC_GPMF32"}, 3462 {AMDGPU_GFX_RLC_RLCVF32, "RLC_RLCVF32"}, 3463 {AMDGPU_GFX_RLC_SCRATCH, "RLC_SCRATCH"}, 3464 {AMDGPU_GFX_RLC_SRM_ARAM, "RLC_SRM_ARAM"}, 3465 {AMDGPU_GFX_RLC_SRM_DRAM, "RLC_SRM_DRAM"}, 3466 {AMDGPU_GFX_RLC_TCTAG, "RLC_TCTAG"}, 3467 {AMDGPU_GFX_RLC_SPM_SE, "RLC_SPM_SE"}, 3468 {AMDGPU_GFX_RLC_SPM_GRBMT, "RLC_SPM_GRBMT"}, 3469 }; 3470 3471 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sp_mem_list[] = { 3472 {AMDGPU_GFX_SP_SIMDID0, "SP_SIMDID0"}, 3473 }; 3474 3475 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_spi_mem_list[] = { 3476 {AMDGPU_GFX_SPI_MEM0, "SPI_MEM0"}, 3477 {AMDGPU_GFX_SPI_MEM1, "SPI_MEM1"}, 3478 {AMDGPU_GFX_SPI_MEM2, "SPI_MEM2"}, 3479 {AMDGPU_GFX_SPI_MEM3, "SPI_MEM3"}, 3480 }; 3481 3482 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sqc_mem_list[] = { 3483 {AMDGPU_GFX_SQC_INST_CACHE_A, "SQC_INST_CACHE_A"}, 3484 {AMDGPU_GFX_SQC_INST_CACHE_B, "SQC_INST_CACHE_B"}, 3485 {AMDGPU_GFX_SQC_INST_CACHE_TAG_A, "SQC_INST_CACHE_TAG_A"}, 3486 {AMDGPU_GFX_SQC_INST_CACHE_TAG_B, "SQC_INST_CACHE_TAG_B"}, 3487 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_A, "SQC_INST_CACHE_MISS_FIFO_A"}, 3488 {AMDGPU_GFX_SQC_INST_CACHE_MISS_FIFO_B, "SQC_INST_CACHE_MISS_FIFO_B"}, 3489 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_A, "SQC_INST_CACHE_GATCL1_MISS_FIFO_A"}, 3490 {AMDGPU_GFX_SQC_INST_CACHE_GATCL1_MISS_FIFO_B, "SQC_INST_CACHE_GATCL1_MISS_FIFO_B"}, 3491 {AMDGPU_GFX_SQC_DATA_CACHE_A, "SQC_DATA_CACHE_A"}, 3492 {AMDGPU_GFX_SQC_DATA_CACHE_B, "SQC_DATA_CACHE_B"}, 3493 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_A, "SQC_DATA_CACHE_TAG_A"}, 3494 {AMDGPU_GFX_SQC_DATA_CACHE_TAG_B, "SQC_DATA_CACHE_TAG_B"}, 3495 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_A, "SQC_DATA_CACHE_MISS_FIFO_A"}, 3496 {AMDGPU_GFX_SQC_DATA_CACHE_MISS_FIFO_B, "SQC_DATA_CACHE_MISS_FIFO_B"}, 3497 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_A, "SQC_DATA_CACHE_HIT_FIFO_A"}, 3498 {AMDGPU_GFX_SQC_DATA_CACHE_HIT_FIFO_B, "SQC_DATA_CACHE_HIT_FIFO_B"}, 3499 {AMDGPU_GFX_SQC_DIRTY_BIT_A, "SQC_DIRTY_BIT_A"}, 3500 {AMDGPU_GFX_SQC_DIRTY_BIT_B, "SQC_DIRTY_BIT_B"}, 3501 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU0, "SQC_WRITE_DATA_BUFFER_CU0"}, 3502 {AMDGPU_GFX_SQC_WRITE_DATA_BUFFER_CU1, "SQC_WRITE_DATA_BUFFER_CU1"}, 3503 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_A"}, 3504 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B, "SQC_UTCL1_MISS_LFIFO_DATA_CACHE_B"}, 3505 {AMDGPU_GFX_SQC_UTCL1_MISS_LFIFO_INST_CACHE, "SQC_UTCL1_MISS_LFIFO_INST_CACHE"}, 3506 }; 3507 3508 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_sq_mem_list[] = { 3509 {AMDGPU_GFX_SQ_SGPR_MEM0, "SQ_SGPR_MEM0"}, 3510 {AMDGPU_GFX_SQ_SGPR_MEM1, "SQ_SGPR_MEM1"}, 3511 {AMDGPU_GFX_SQ_SGPR_MEM2, "SQ_SGPR_MEM2"}, 3512 {AMDGPU_GFX_SQ_SGPR_MEM3, "SQ_SGPR_MEM3"}, 3513 }; 3514 3515 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_ta_mem_list[] = { 3516 {AMDGPU_GFX_TA_FS_AFIFO_RAM_LO, "TA_FS_AFIFO_RAM_LO"}, 3517 {AMDGPU_GFX_TA_FS_AFIFO_RAM_HI, "TA_FS_AFIFO_RAM_HI"}, 3518 {AMDGPU_GFX_TA_FS_CFIFO_RAM, "TA_FS_CFIFO_RAM"}, 3519 {AMDGPU_GFX_TA_FSX_LFIFO, "TA_FSX_LFIFO"}, 3520 {AMDGPU_GFX_TA_FS_DFIFO_RAM, "TA_FS_DFIFO_RAM"}, 3521 }; 3522 3523 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcc_mem_list[] = { 3524 {AMDGPU_GFX_TCC_MEM1, "TCC_MEM1"}, 3525 }; 3526 3527 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tca_mem_list[] = { 3528 {AMDGPU_GFX_TCA_MEM1, "TCA_MEM1"}, 3529 }; 3530 3531 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tci_mem_list[] = { 3532 {AMDGPU_GFX_TCIW_MEM, "TCIW_MEM"}, 3533 }; 3534 3535 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcp_mem_list[] = { 3536 {AMDGPU_GFX_TCP_LFIFO0, "TCP_LFIFO0"}, 3537 {AMDGPU_GFX_TCP_SET0BANK0_RAM, "TCP_SET0BANK0_RAM"}, 3538 {AMDGPU_GFX_TCP_SET0BANK1_RAM, "TCP_SET0BANK1_RAM"}, 3539 {AMDGPU_GFX_TCP_SET0BANK2_RAM, "TCP_SET0BANK2_RAM"}, 3540 {AMDGPU_GFX_TCP_SET0BANK3_RAM, "TCP_SET0BANK3_RAM"}, 3541 {AMDGPU_GFX_TCP_SET1BANK0_RAM, "TCP_SET1BANK0_RAM"}, 3542 {AMDGPU_GFX_TCP_SET1BANK1_RAM, "TCP_SET1BANK1_RAM"}, 3543 {AMDGPU_GFX_TCP_SET1BANK2_RAM, "TCP_SET1BANK2_RAM"}, 3544 {AMDGPU_GFX_TCP_SET1BANK3_RAM, "TCP_SET1BANK3_RAM"}, 3545 {AMDGPU_GFX_TCP_SET2BANK0_RAM, "TCP_SET2BANK0_RAM"}, 3546 {AMDGPU_GFX_TCP_SET2BANK1_RAM, "TCP_SET2BANK1_RAM"}, 3547 {AMDGPU_GFX_TCP_SET2BANK2_RAM, "TCP_SET2BANK2_RAM"}, 3548 {AMDGPU_GFX_TCP_SET2BANK3_RAM, "TCP_SET2BANK3_RAM"}, 3549 {AMDGPU_GFX_TCP_SET3BANK0_RAM, "TCP_SET3BANK0_RAM"}, 3550 {AMDGPU_GFX_TCP_SET3BANK1_RAM, "TCP_SET3BANK1_RAM"}, 3551 {AMDGPU_GFX_TCP_SET3BANK2_RAM, "TCP_SET3BANK2_RAM"}, 3552 {AMDGPU_GFX_TCP_SET3BANK3_RAM, "TCP_SET3BANK3_RAM"}, 3553 {AMDGPU_GFX_TCP_VM_FIFO, "TCP_VM_FIFO"}, 3554 {AMDGPU_GFX_TCP_DB_TAGRAM0, "TCP_DB_TAGRAM0"}, 3555 {AMDGPU_GFX_TCP_DB_TAGRAM1, "TCP_DB_TAGRAM1"}, 3556 {AMDGPU_GFX_TCP_DB_TAGRAM2, "TCP_DB_TAGRAM2"}, 3557 {AMDGPU_GFX_TCP_DB_TAGRAM3, "TCP_DB_TAGRAM3"}, 3558 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE0, "TCP_UTCL1_LFIFO_PROBE0"}, 3559 {AMDGPU_GFX_TCP_UTCL1_LFIFO_PROBE1, "TCP_UTCL1_LFIFO_PROBE1"}, 3560 {AMDGPU_GFX_TCP_CMD_FIFO, "TCP_CMD_FIFO"}, 3561 }; 3562 3563 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_td_mem_list[] = { 3564 {AMDGPU_GFX_TD_UTD_CS_FIFO_MEM, "TD_UTD_CS_FIFO_MEM"}, 3565 {AMDGPU_GFX_TD_UTD_SS_FIFO_LO_MEM, "TD_UTD_SS_FIFO_LO_MEM"}, 3566 {AMDGPU_GFX_TD_UTD_SS_FIFO_HI_MEM, "TD_UTD_SS_FIFO_HI_MEM"}, 3567 }; 3568 3569 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_tcx_mem_list[] = { 3570 {AMDGPU_GFX_TCX_FIFOD0, "TCX_FIFOD0"}, 3571 {AMDGPU_GFX_TCX_FIFOD1, "TCX_FIFOD1"}, 3572 {AMDGPU_GFX_TCX_FIFOD2, "TCX_FIFOD2"}, 3573 {AMDGPU_GFX_TCX_FIFOD3, "TCX_FIFOD3"}, 3574 {AMDGPU_GFX_TCX_FIFOD4, "TCX_FIFOD4"}, 3575 {AMDGPU_GFX_TCX_FIFOD5, "TCX_FIFOD5"}, 3576 {AMDGPU_GFX_TCX_FIFOD6, "TCX_FIFOD6"}, 3577 {AMDGPU_GFX_TCX_FIFOD7, "TCX_FIFOD7"}, 3578 {AMDGPU_GFX_TCX_FIFOB0, "TCX_FIFOB0"}, 3579 {AMDGPU_GFX_TCX_FIFOB1, "TCX_FIFOB1"}, 3580 {AMDGPU_GFX_TCX_FIFOB2, "TCX_FIFOB2"}, 3581 {AMDGPU_GFX_TCX_FIFOB3, "TCX_FIFOB3"}, 3582 {AMDGPU_GFX_TCX_FIFOB4, "TCX_FIFOB4"}, 3583 {AMDGPU_GFX_TCX_FIFOB5, "TCX_FIFOB5"}, 3584 {AMDGPU_GFX_TCX_FIFOB6, "TCX_FIFOB6"}, 3585 {AMDGPU_GFX_TCX_FIFOB7, "TCX_FIFOB7"}, 3586 {AMDGPU_GFX_TCX_FIFOA0, "TCX_FIFOA0"}, 3587 {AMDGPU_GFX_TCX_FIFOA1, "TCX_FIFOA1"}, 3588 {AMDGPU_GFX_TCX_FIFOA2, "TCX_FIFOA2"}, 3589 {AMDGPU_GFX_TCX_FIFOA3, "TCX_FIFOA3"}, 3590 {AMDGPU_GFX_TCX_FIFOA4, "TCX_FIFOA4"}, 3591 {AMDGPU_GFX_TCX_FIFOA5, "TCX_FIFOA5"}, 3592 {AMDGPU_GFX_TCX_FIFOA6, "TCX_FIFOA6"}, 3593 {AMDGPU_GFX_TCX_FIFOA7, "TCX_FIFOA7"}, 3594 {AMDGPU_GFX_TCX_CFIFO0, "TCX_CFIFO0"}, 3595 {AMDGPU_GFX_TCX_CFIFO1, "TCX_CFIFO1"}, 3596 {AMDGPU_GFX_TCX_CFIFO2, "TCX_CFIFO2"}, 3597 {AMDGPU_GFX_TCX_CFIFO3, "TCX_CFIFO3"}, 3598 {AMDGPU_GFX_TCX_CFIFO4, "TCX_CFIFO4"}, 3599 {AMDGPU_GFX_TCX_CFIFO5, "TCX_CFIFO5"}, 3600 {AMDGPU_GFX_TCX_CFIFO6, "TCX_CFIFO6"}, 3601 {AMDGPU_GFX_TCX_CFIFO7, "TCX_CFIFO7"}, 3602 {AMDGPU_GFX_TCX_FIFO_ACKB0, "TCX_FIFO_ACKB0"}, 3603 {AMDGPU_GFX_TCX_FIFO_ACKB1, "TCX_FIFO_ACKB1"}, 3604 {AMDGPU_GFX_TCX_FIFO_ACKB2, "TCX_FIFO_ACKB2"}, 3605 {AMDGPU_GFX_TCX_FIFO_ACKB3, "TCX_FIFO_ACKB3"}, 3606 {AMDGPU_GFX_TCX_FIFO_ACKB4, "TCX_FIFO_ACKB4"}, 3607 {AMDGPU_GFX_TCX_FIFO_ACKB5, "TCX_FIFO_ACKB5"}, 3608 {AMDGPU_GFX_TCX_FIFO_ACKB6, "TCX_FIFO_ACKB6"}, 3609 {AMDGPU_GFX_TCX_FIFO_ACKB7, "TCX_FIFO_ACKB7"}, 3610 {AMDGPU_GFX_TCX_FIFO_ACKD0, "TCX_FIFO_ACKD0"}, 3611 {AMDGPU_GFX_TCX_FIFO_ACKD1, "TCX_FIFO_ACKD1"}, 3612 {AMDGPU_GFX_TCX_FIFO_ACKD2, "TCX_FIFO_ACKD2"}, 3613 {AMDGPU_GFX_TCX_FIFO_ACKD3, "TCX_FIFO_ACKD3"}, 3614 {AMDGPU_GFX_TCX_FIFO_ACKD4, "TCX_FIFO_ACKD4"}, 3615 {AMDGPU_GFX_TCX_FIFO_ACKD5, "TCX_FIFO_ACKD5"}, 3616 {AMDGPU_GFX_TCX_FIFO_ACKD6, "TCX_FIFO_ACKD6"}, 3617 {AMDGPU_GFX_TCX_FIFO_ACKD7, "TCX_FIFO_ACKD7"}, 3618 {AMDGPU_GFX_TCX_DST_FIFOA0, "TCX_DST_FIFOA0"}, 3619 {AMDGPU_GFX_TCX_DST_FIFOA1, "TCX_DST_FIFOA1"}, 3620 {AMDGPU_GFX_TCX_DST_FIFOA2, "TCX_DST_FIFOA2"}, 3621 {AMDGPU_GFX_TCX_DST_FIFOA3, "TCX_DST_FIFOA3"}, 3622 {AMDGPU_GFX_TCX_DST_FIFOA4, "TCX_DST_FIFOA4"}, 3623 {AMDGPU_GFX_TCX_DST_FIFOA5, "TCX_DST_FIFOA5"}, 3624 {AMDGPU_GFX_TCX_DST_FIFOA6, "TCX_DST_FIFOA6"}, 3625 {AMDGPU_GFX_TCX_DST_FIFOA7, "TCX_DST_FIFOA7"}, 3626 {AMDGPU_GFX_TCX_DST_FIFOB0, "TCX_DST_FIFOB0"}, 3627 {AMDGPU_GFX_TCX_DST_FIFOB1, "TCX_DST_FIFOB1"}, 3628 {AMDGPU_GFX_TCX_DST_FIFOB2, "TCX_DST_FIFOB2"}, 3629 {AMDGPU_GFX_TCX_DST_FIFOB3, "TCX_DST_FIFOB3"}, 3630 {AMDGPU_GFX_TCX_DST_FIFOB4, "TCX_DST_FIFOB4"}, 3631 {AMDGPU_GFX_TCX_DST_FIFOB5, "TCX_DST_FIFOB5"}, 3632 {AMDGPU_GFX_TCX_DST_FIFOB6, "TCX_DST_FIFOB6"}, 3633 {AMDGPU_GFX_TCX_DST_FIFOB7, "TCX_DST_FIFOB7"}, 3634 {AMDGPU_GFX_TCX_DST_FIFOD0, "TCX_DST_FIFOD0"}, 3635 {AMDGPU_GFX_TCX_DST_FIFOD1, "TCX_DST_FIFOD1"}, 3636 {AMDGPU_GFX_TCX_DST_FIFOD2, "TCX_DST_FIFOD2"}, 3637 {AMDGPU_GFX_TCX_DST_FIFOD3, "TCX_DST_FIFOD3"}, 3638 {AMDGPU_GFX_TCX_DST_FIFOD4, "TCX_DST_FIFOD4"}, 3639 {AMDGPU_GFX_TCX_DST_FIFOD5, "TCX_DST_FIFOD5"}, 3640 {AMDGPU_GFX_TCX_DST_FIFOD6, "TCX_DST_FIFOD6"}, 3641 {AMDGPU_GFX_TCX_DST_FIFOD7, "TCX_DST_FIFOD7"}, 3642 {AMDGPU_GFX_TCX_DST_FIFO_ACKB0, "TCX_DST_FIFO_ACKB0"}, 3643 {AMDGPU_GFX_TCX_DST_FIFO_ACKB1, "TCX_DST_FIFO_ACKB1"}, 3644 {AMDGPU_GFX_TCX_DST_FIFO_ACKB2, "TCX_DST_FIFO_ACKB2"}, 3645 {AMDGPU_GFX_TCX_DST_FIFO_ACKB3, "TCX_DST_FIFO_ACKB3"}, 3646 {AMDGPU_GFX_TCX_DST_FIFO_ACKB4, "TCX_DST_FIFO_ACKB4"}, 3647 {AMDGPU_GFX_TCX_DST_FIFO_ACKB5, "TCX_DST_FIFO_ACKB5"}, 3648 {AMDGPU_GFX_TCX_DST_FIFO_ACKB6, "TCX_DST_FIFO_ACKB6"}, 3649 {AMDGPU_GFX_TCX_DST_FIFO_ACKB7, "TCX_DST_FIFO_ACKB7"}, 3650 {AMDGPU_GFX_TCX_DST_FIFO_ACKD0, "TCX_DST_FIFO_ACKD0"}, 3651 {AMDGPU_GFX_TCX_DST_FIFO_ACKD1, "TCX_DST_FIFO_ACKD1"}, 3652 {AMDGPU_GFX_TCX_DST_FIFO_ACKD2, "TCX_DST_FIFO_ACKD2"}, 3653 {AMDGPU_GFX_TCX_DST_FIFO_ACKD3, "TCX_DST_FIFO_ACKD3"}, 3654 {AMDGPU_GFX_TCX_DST_FIFO_ACKD4, "TCX_DST_FIFO_ACKD4"}, 3655 {AMDGPU_GFX_TCX_DST_FIFO_ACKD5, "TCX_DST_FIFO_ACKD5"}, 3656 {AMDGPU_GFX_TCX_DST_FIFO_ACKD6, "TCX_DST_FIFO_ACKD6"}, 3657 {AMDGPU_GFX_TCX_DST_FIFO_ACKD7, "TCX_DST_FIFO_ACKD7"}, 3658 }; 3659 3660 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_atc_l2_mem_list[] = { 3661 {AMDGPU_GFX_ATC_L2_MEM, "ATC_L2_MEM"}, 3662 }; 3663 3664 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_utcl2_mem_list[] = { 3665 {AMDGPU_GFX_UTCL2_MEM, "UTCL2_MEM"}, 3666 }; 3667 3668 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_mem_list[] = { 3669 {AMDGPU_GFX_VML2_MEM, "VML2_MEM"}, 3670 }; 3671 3672 static const struct amdgpu_ras_memory_id_entry gfx_v9_4_3_ras_vml2_walker_mem_list[] = { 3673 {AMDGPU_GFX_VML2_WALKER_MEM, "VML2_WALKER_MEM"}, 3674 }; 3675 3676 static const struct amdgpu_gfx_ras_mem_id_entry gfx_v9_4_3_ras_mem_list_array[AMDGPU_GFX_MEM_TYPE_NUM] = { 3677 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_cp_mem_list) 3678 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcea_mem_list) 3679 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gc_cane_mem_list) 3680 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gcutcl2_mem_list) 3681 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_gds_mem_list) 3682 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_lds_mem_list) 3683 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_rlc_mem_list) 3684 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sp_mem_list) 3685 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_spi_mem_list) 3686 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sqc_mem_list) 3687 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_sq_mem_list) 3688 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_ta_mem_list) 3689 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcc_mem_list) 3690 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tca_mem_list) 3691 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tci_mem_list) 3692 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcp_mem_list) 3693 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_td_mem_list) 3694 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_tcx_mem_list) 3695 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_atc_l2_mem_list) 3696 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_utcl2_mem_list) 3697 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_mem_list) 3698 AMDGPU_GFX_MEMID_ENT(gfx_v9_4_3_ras_vml2_walker_mem_list) 3699 }; 3700 3701 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ce_reg_list[] = { 3702 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_CE_ERR_STATUS_LOW, regRLC_CE_ERR_STATUS_HIGH), 3703 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3704 AMDGPU_GFX_RLC_MEM, 1}, 3705 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_CE_ERR_STATUS_LO, regCPC_CE_ERR_STATUS_HI), 3706 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3707 AMDGPU_GFX_CP_MEM, 1}, 3708 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_CE_ERR_STATUS_LO, regCPF_CE_ERR_STATUS_HI), 3709 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3710 AMDGPU_GFX_CP_MEM, 1}, 3711 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_CE_ERR_STATUS_LO, regCPG_CE_ERR_STATUS_HI), 3712 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3713 AMDGPU_GFX_CP_MEM, 1}, 3714 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_CE_ERR_STATUS_LO, regGDS_CE_ERR_STATUS_HI), 3715 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3716 AMDGPU_GFX_GDS_MEM, 1}, 3717 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_CE_ERR_STATUS_LO, regGC_CANE_CE_ERR_STATUS_HI), 3718 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3719 AMDGPU_GFX_GC_CANE_MEM, 1}, 3720 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_CE_ERR_STATUS_LO, regSPI_CE_ERR_STATUS_HI), 3721 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3722 AMDGPU_GFX_SPI_MEM, 1}, 3723 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_CE_ERR_STATUS_LO, regSP0_CE_ERR_STATUS_HI), 3724 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3725 AMDGPU_GFX_SP_MEM, 4}, 3726 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_CE_ERR_STATUS_LO, regSP1_CE_ERR_STATUS_HI), 3727 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3728 AMDGPU_GFX_SP_MEM, 4}, 3729 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_CE_ERR_STATUS_LO, regSQ_CE_ERR_STATUS_HI), 3730 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3731 AMDGPU_GFX_SQ_MEM, 4}, 3732 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_CE_EDC_LO, regSQC_CE_EDC_HI), 3733 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3734 AMDGPU_GFX_SQC_MEM, 4}, 3735 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_CE_ERR_STATUS_LO, regTCX_CE_ERR_STATUS_HI), 3736 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3737 AMDGPU_GFX_TCX_MEM, 1}, 3738 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_CE_ERR_STATUS_LO, regTCC_CE_ERR_STATUS_HI), 3739 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3740 AMDGPU_GFX_TCC_MEM, 1}, 3741 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_CE_EDC_LO, regTA_CE_EDC_HI), 3742 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3743 AMDGPU_GFX_TA_MEM, 4}, 3744 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_CE_EDC_LO_REG, regTCI_CE_EDC_HI_REG), 3745 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3746 AMDGPU_GFX_TCI_MEM, 1}, 3747 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_CE_EDC_LO_REG, regTCP_CE_EDC_HI_REG), 3748 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3749 AMDGPU_GFX_TCP_MEM, 4}, 3750 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_CE_EDC_LO, regTD_CE_EDC_HI), 3751 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3752 AMDGPU_GFX_TD_MEM, 4}, 3753 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_CE_ERR_STATUS_LO, regGCEA_CE_ERR_STATUS_HI), 3754 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3755 AMDGPU_GFX_GCEA_MEM, 1}, 3756 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_CE_ERR_STATUS_LO, regLDS_CE_ERR_STATUS_HI), 3757 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3758 AMDGPU_GFX_LDS_MEM, 4}, 3759 }; 3760 3761 static const struct amdgpu_gfx_ras_reg_entry gfx_v9_4_3_ue_reg_list[] = { 3762 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regRLC_UE_ERR_STATUS_LOW, regRLC_UE_ERR_STATUS_HIGH), 3763 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "RLC"}, 3764 AMDGPU_GFX_RLC_MEM, 1}, 3765 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPC_UE_ERR_STATUS_LO, regCPC_UE_ERR_STATUS_HI), 3766 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPC"}, 3767 AMDGPU_GFX_CP_MEM, 1}, 3768 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPF_UE_ERR_STATUS_LO, regCPF_UE_ERR_STATUS_HI), 3769 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPF"}, 3770 AMDGPU_GFX_CP_MEM, 1}, 3771 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regCPG_UE_ERR_STATUS_LO, regCPG_UE_ERR_STATUS_HI), 3772 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CPG"}, 3773 AMDGPU_GFX_CP_MEM, 1}, 3774 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGDS_UE_ERR_STATUS_LO, regGDS_UE_ERR_STATUS_HI), 3775 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GDS"}, 3776 AMDGPU_GFX_GDS_MEM, 1}, 3777 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGC_CANE_UE_ERR_STATUS_LO, regGC_CANE_UE_ERR_STATUS_HI), 3778 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "CANE"}, 3779 AMDGPU_GFX_GC_CANE_MEM, 1}, 3780 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSPI_UE_ERR_STATUS_LO, regSPI_UE_ERR_STATUS_HI), 3781 1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SPI"}, 3782 AMDGPU_GFX_SPI_MEM, 1}, 3783 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP0_UE_ERR_STATUS_LO, regSP0_UE_ERR_STATUS_HI), 3784 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP0"}, 3785 AMDGPU_GFX_SP_MEM, 4}, 3786 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSP1_UE_ERR_STATUS_LO, regSP1_UE_ERR_STATUS_HI), 3787 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SP1"}, 3788 AMDGPU_GFX_SP_MEM, 4}, 3789 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQ_UE_ERR_STATUS_LO, regSQ_UE_ERR_STATUS_HI), 3790 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQ"}, 3791 AMDGPU_GFX_SQ_MEM, 4}, 3792 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regSQC_UE_EDC_LO, regSQC_UE_EDC_HI), 3793 5, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SQC"}, 3794 AMDGPU_GFX_SQC_MEM, 4}, 3795 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCX_UE_ERR_STATUS_LO, regTCX_UE_ERR_STATUS_HI), 3796 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCX"}, 3797 AMDGPU_GFX_TCX_MEM, 1}, 3798 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCC_UE_ERR_STATUS_LO, regTCC_UE_ERR_STATUS_HI), 3799 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCC"}, 3800 AMDGPU_GFX_TCC_MEM, 1}, 3801 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTA_UE_EDC_LO, regTA_UE_EDC_HI), 3802 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TA"}, 3803 AMDGPU_GFX_TA_MEM, 4}, 3804 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCI_UE_EDC_LO_REG, regTCI_UE_EDC_HI_REG), 3805 27, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCI"}, 3806 AMDGPU_GFX_TCI_MEM, 1}, 3807 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCP_UE_EDC_LO_REG, regTCP_UE_EDC_HI_REG), 3808 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCP"}, 3809 AMDGPU_GFX_TCP_MEM, 4}, 3810 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTD_UE_EDC_LO, regTD_UE_EDC_HI), 3811 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TD"}, 3812 AMDGPU_GFX_TD_MEM, 4}, 3813 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regTCA_UE_ERR_STATUS_LO, regTCA_UE_ERR_STATUS_HI), 3814 2, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "TCA"}, 3815 AMDGPU_GFX_TCA_MEM, 1}, 3816 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regGCEA_UE_ERR_STATUS_LO, regGCEA_UE_ERR_STATUS_HI), 3817 16, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "GCEA"}, 3818 AMDGPU_GFX_GCEA_MEM, 1}, 3819 {{AMDGPU_RAS_REG_ENTRY(GC, 0, regLDS_UE_ERR_STATUS_LO, regLDS_UE_ERR_STATUS_HI), 3820 10, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "LDS"}, 3821 AMDGPU_GFX_LDS_MEM, 4}, 3822 }; 3823 3824 static void gfx_v9_4_3_inst_query_ras_err_count(struct amdgpu_device *adev, 3825 void *ras_error_status, int xcc_id) 3826 { 3827 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 3828 unsigned long ce_count = 0, ue_count = 0; 3829 uint32_t i, j, k; 3830 3831 /* NOTE: convert xcc_id to physical XCD ID (XCD0 or XCD1) */ 3832 struct amdgpu_smuio_mcm_config_info mcm_info = { 3833 .socket_id = adev->smuio.funcs->get_socket_id(adev), 3834 .die_id = xcc_id & 0x01 ? 1 : 0, 3835 }; 3836 3837 mutex_lock(&adev->grbm_idx_mutex); 3838 3839 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3840 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3841 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3842 /* no need to select if instance number is 1 */ 3843 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3844 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3845 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3846 3847 amdgpu_ras_inst_query_ras_error_count(adev, 3848 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3849 1, 3850 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].mem_id_ent, 3851 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ce_reg_list[i].mem_id_type].size, 3852 GET_INST(GC, xcc_id), 3853 AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 3854 &ce_count); 3855 3856 amdgpu_ras_inst_query_ras_error_count(adev, 3857 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3858 1, 3859 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3860 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3861 GET_INST(GC, xcc_id), 3862 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3863 &ue_count); 3864 } 3865 } 3866 } 3867 3868 /* handle extra register entries of UE */ 3869 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3870 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3871 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3872 /* no need to select if instance number is 1 */ 3873 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3874 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3875 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3876 3877 amdgpu_ras_inst_query_ras_error_count(adev, 3878 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3879 1, 3880 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].mem_id_ent, 3881 gfx_v9_4_3_ras_mem_list_array[gfx_v9_4_3_ue_reg_list[i].mem_id_type].size, 3882 GET_INST(GC, xcc_id), 3883 AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, 3884 &ue_count); 3885 } 3886 } 3887 } 3888 3889 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3890 xcc_id); 3891 mutex_unlock(&adev->grbm_idx_mutex); 3892 3893 /* the caller should make sure initialize value of 3894 * err_data->ue_count and err_data->ce_count 3895 */ 3896 amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count); 3897 amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, NULL, ce_count); 3898 } 3899 3900 static void gfx_v9_4_3_inst_reset_ras_err_count(struct amdgpu_device *adev, 3901 void *ras_error_status, int xcc_id) 3902 { 3903 uint32_t i, j, k; 3904 3905 mutex_lock(&adev->grbm_idx_mutex); 3906 3907 for (i = 0; i < ARRAY_SIZE(gfx_v9_4_3_ce_reg_list); i++) { 3908 for (j = 0; j < gfx_v9_4_3_ce_reg_list[i].se_num; j++) { 3909 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { 3910 /* no need to select if instance number is 1 */ 3911 if (gfx_v9_4_3_ce_reg_list[i].se_num > 1 || 3912 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) 3913 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3914 3915 amdgpu_ras_inst_reset_ras_error_count(adev, 3916 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), 3917 1, 3918 GET_INST(GC, xcc_id)); 3919 3920 amdgpu_ras_inst_reset_ras_error_count(adev, 3921 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3922 1, 3923 GET_INST(GC, xcc_id)); 3924 } 3925 } 3926 } 3927 3928 /* handle extra register entries of UE */ 3929 for (; i < ARRAY_SIZE(gfx_v9_4_3_ue_reg_list); i++) { 3930 for (j = 0; j < gfx_v9_4_3_ue_reg_list[i].se_num; j++) { 3931 for (k = 0; k < gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst; k++) { 3932 /* no need to select if instance number is 1 */ 3933 if (gfx_v9_4_3_ue_reg_list[i].se_num > 1 || 3934 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) 3935 gfx_v9_4_3_xcc_select_se_sh(adev, j, 0, k, xcc_id); 3936 3937 amdgpu_ras_inst_reset_ras_error_count(adev, 3938 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), 3939 1, 3940 GET_INST(GC, xcc_id)); 3941 } 3942 } 3943 } 3944 3945 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3946 xcc_id); 3947 mutex_unlock(&adev->grbm_idx_mutex); 3948 } 3949 3950 static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, 3951 void *ras_error_status, int xcc_id) 3952 { 3953 uint32_t i; 3954 uint32_t data; 3955 3956 data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); 3957 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, 3958 amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); 3959 3960 if (amdgpu_watchdog_timer.timeout_fatal_disable && 3961 (amdgpu_watchdog_timer.period < 1 || 3962 amdgpu_watchdog_timer.period > 0x23)) { 3963 dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n"); 3964 amdgpu_watchdog_timer.period = 0x23; 3965 } 3966 data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL, 3967 amdgpu_watchdog_timer.period); 3968 3969 mutex_lock(&adev->grbm_idx_mutex); 3970 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3971 gfx_v9_4_3_xcc_select_se_sh(adev, i, 0xffffffff, 0xffffffff, xcc_id); 3972 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_TIMEOUT_CONFIG, data); 3973 } 3974 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 3975 xcc_id); 3976 mutex_unlock(&adev->grbm_idx_mutex); 3977 } 3978 3979 static void gfx_v9_4_3_query_ras_error_count(struct amdgpu_device *adev, 3980 void *ras_error_status) 3981 { 3982 amdgpu_gfx_ras_error_func(adev, ras_error_status, 3983 gfx_v9_4_3_inst_query_ras_err_count); 3984 } 3985 3986 static void gfx_v9_4_3_reset_ras_error_count(struct amdgpu_device *adev) 3987 { 3988 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_reset_ras_err_count); 3989 } 3990 3991 static void gfx_v9_4_3_enable_watchdog_timer(struct amdgpu_device *adev) 3992 { 3993 amdgpu_gfx_ras_error_func(adev, NULL, gfx_v9_4_3_inst_enable_watchdog_timer); 3994 } 3995 3996 static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { 3997 .name = "gfx_v9_4_3", 3998 .early_init = gfx_v9_4_3_early_init, 3999 .late_init = gfx_v9_4_3_late_init, 4000 .sw_init = gfx_v9_4_3_sw_init, 4001 .sw_fini = gfx_v9_4_3_sw_fini, 4002 .hw_init = gfx_v9_4_3_hw_init, 4003 .hw_fini = gfx_v9_4_3_hw_fini, 4004 .suspend = gfx_v9_4_3_suspend, 4005 .resume = gfx_v9_4_3_resume, 4006 .is_idle = gfx_v9_4_3_is_idle, 4007 .wait_for_idle = gfx_v9_4_3_wait_for_idle, 4008 .soft_reset = gfx_v9_4_3_soft_reset, 4009 .set_clockgating_state = gfx_v9_4_3_set_clockgating_state, 4010 .set_powergating_state = gfx_v9_4_3_set_powergating_state, 4011 .get_clockgating_state = gfx_v9_4_3_get_clockgating_state, 4012 }; 4013 4014 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 4015 .type = AMDGPU_RING_TYPE_COMPUTE, 4016 .align_mask = 0xff, 4017 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4018 .support_64bit_ptrs = true, 4019 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4020 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4021 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4022 .emit_frame_size = 4023 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4024 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4025 5 + /* hdp invalidate */ 4026 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4027 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4028 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4029 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4030 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 4031 7 + /* gfx_v9_4_3_emit_mem_sync */ 4032 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ 4033 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ 4034 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4035 .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, 4036 .emit_fence = gfx_v9_4_3_ring_emit_fence, 4037 .emit_pipeline_sync = gfx_v9_4_3_ring_emit_pipeline_sync, 4038 .emit_vm_flush = gfx_v9_4_3_ring_emit_vm_flush, 4039 .emit_gds_switch = gfx_v9_4_3_ring_emit_gds_switch, 4040 .emit_hdp_flush = gfx_v9_4_3_ring_emit_hdp_flush, 4041 .test_ring = gfx_v9_4_3_ring_test_ring, 4042 .test_ib = gfx_v9_4_3_ring_test_ib, 4043 .insert_nop = amdgpu_ring_insert_nop, 4044 .pad_ib = amdgpu_ring_generic_pad_ib, 4045 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4046 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4047 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4048 .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, 4049 .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, 4050 }; 4051 4052 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { 4053 .type = AMDGPU_RING_TYPE_KIQ, 4054 .align_mask = 0xff, 4055 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4056 .support_64bit_ptrs = true, 4057 .get_rptr = gfx_v9_4_3_ring_get_rptr_compute, 4058 .get_wptr = gfx_v9_4_3_ring_get_wptr_compute, 4059 .set_wptr = gfx_v9_4_3_ring_set_wptr_compute, 4060 .emit_frame_size = 4061 20 + /* gfx_v9_4_3_ring_emit_gds_switch */ 4062 7 + /* gfx_v9_4_3_ring_emit_hdp_flush */ 4063 5 + /* hdp invalidate */ 4064 7 + /* gfx_v9_4_3_ring_emit_pipeline_sync */ 4065 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4066 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4067 2 + /* gfx_v9_4_3_ring_emit_vm_flush */ 4068 8 + 8 + 8, /* gfx_v9_4_3_ring_emit_fence_kiq x3 for user fence, vm fence */ 4069 .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ 4070 .emit_fence = gfx_v9_4_3_ring_emit_fence_kiq, 4071 .test_ring = gfx_v9_4_3_ring_test_ring, 4072 .insert_nop = amdgpu_ring_insert_nop, 4073 .pad_ib = amdgpu_ring_generic_pad_ib, 4074 .emit_rreg = gfx_v9_4_3_ring_emit_rreg, 4075 .emit_wreg = gfx_v9_4_3_ring_emit_wreg, 4076 .emit_reg_wait = gfx_v9_4_3_ring_emit_reg_wait, 4077 .emit_reg_write_reg_wait = gfx_v9_4_3_ring_emit_reg_write_reg_wait, 4078 }; 4079 4080 static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev) 4081 { 4082 int i, j, num_xcc; 4083 4084 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 4085 for (i = 0; i < num_xcc; i++) { 4086 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq; 4087 4088 for (j = 0; j < adev->gfx.num_compute_rings; j++) 4089 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs 4090 = &gfx_v9_4_3_ring_funcs_compute; 4091 } 4092 } 4093 4094 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_eop_irq_funcs = { 4095 .set = gfx_v9_4_3_set_eop_interrupt_state, 4096 .process = gfx_v9_4_3_eop_irq, 4097 }; 4098 4099 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_reg_irq_funcs = { 4100 .set = gfx_v9_4_3_set_priv_reg_fault_state, 4101 .process = gfx_v9_4_3_priv_reg_irq, 4102 }; 4103 4104 static const struct amdgpu_irq_src_funcs gfx_v9_4_3_priv_inst_irq_funcs = { 4105 .set = gfx_v9_4_3_set_priv_inst_fault_state, 4106 .process = gfx_v9_4_3_priv_inst_irq, 4107 }; 4108 4109 static void gfx_v9_4_3_set_irq_funcs(struct amdgpu_device *adev) 4110 { 4111 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4112 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs; 4113 4114 adev->gfx.priv_reg_irq.num_types = 1; 4115 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs; 4116 4117 adev->gfx.priv_inst_irq.num_types = 1; 4118 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs; 4119 } 4120 4121 static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev) 4122 { 4123 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs; 4124 } 4125 4126 4127 static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) 4128 { 4129 /* init asci gds info */ 4130 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4131 case IP_VERSION(9, 4, 3): 4132 /* 9.4.3 removed all the GDS internal memory, 4133 * only support GWS opcode in kernel, like barrier 4134 * semaphore.etc */ 4135 adev->gds.gds_size = 0; 4136 break; 4137 default: 4138 adev->gds.gds_size = 0x10000; 4139 break; 4140 } 4141 4142 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 4143 case IP_VERSION(9, 4, 3): 4144 /* deprecated for 9.4.3, no usage at all */ 4145 adev->gds.gds_compute_max_wave_id = 0; 4146 break; 4147 default: 4148 /* this really depends on the chip */ 4149 adev->gds.gds_compute_max_wave_id = 0x7ff; 4150 break; 4151 } 4152 4153 adev->gds.gws_size = 64; 4154 adev->gds.oa_size = 16; 4155 } 4156 4157 static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4158 u32 bitmap, int xcc_id) 4159 { 4160 u32 data; 4161 4162 if (!bitmap) 4163 return; 4164 4165 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4166 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4167 4168 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 4169 } 4170 4171 static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) 4172 { 4173 u32 data, mask; 4174 4175 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 4176 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 4177 4178 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4179 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4180 4181 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4182 4183 return (~data) & mask; 4184 } 4185 4186 static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 4187 struct amdgpu_cu_info *cu_info) 4188 { 4189 int i, j, k, counter, xcc_id, active_cu_number = 0; 4190 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4191 unsigned disable_masks[4 * 4]; 4192 4193 if (!adev || !cu_info) 4194 return -EINVAL; 4195 4196 /* 4197 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 4198 */ 4199 if (adev->gfx.config.max_shader_engines * 4200 adev->gfx.config.max_sh_per_se > 16) 4201 return -EINVAL; 4202 4203 amdgpu_gfx_parse_disable_cu(disable_masks, 4204 adev->gfx.config.max_shader_engines, 4205 adev->gfx.config.max_sh_per_se); 4206 4207 mutex_lock(&adev->grbm_idx_mutex); 4208 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 4209 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4210 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4211 mask = 1; 4212 ao_bitmap = 0; 4213 counter = 0; 4214 gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 4215 gfx_v9_4_3_set_user_cu_inactive_bitmap( 4216 adev, 4217 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 4218 xcc_id); 4219 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); 4220 4221 cu_info->bitmap[xcc_id][i][j] = bitmap; 4222 4223 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 4224 if (bitmap & mask) { 4225 if (counter < adev->gfx.config.max_cu_per_sh) 4226 ao_bitmap |= mask; 4227 counter++; 4228 } 4229 mask <<= 1; 4230 } 4231 active_cu_number += counter; 4232 if (i < 2 && j < 2) 4233 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4234 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4235 } 4236 } 4237 gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 4238 xcc_id); 4239 } 4240 mutex_unlock(&adev->grbm_idx_mutex); 4241 4242 cu_info->number = active_cu_number; 4243 cu_info->ao_cu_mask = ao_cu_mask; 4244 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4245 4246 return 0; 4247 } 4248 4249 const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block = { 4250 .type = AMD_IP_BLOCK_TYPE_GFX, 4251 .major = 9, 4252 .minor = 4, 4253 .rev = 3, 4254 .funcs = &gfx_v9_4_3_ip_funcs, 4255 }; 4256 4257 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) 4258 { 4259 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4260 uint32_t tmp_mask; 4261 int i, r; 4262 4263 /* TODO : Initialize golden regs */ 4264 /* gfx_v9_4_3_init_golden_registers(adev); */ 4265 4266 tmp_mask = inst_mask; 4267 for_each_inst(i, tmp_mask) 4268 gfx_v9_4_3_xcc_constants_init(adev, i); 4269 4270 if (!amdgpu_sriov_vf(adev)) { 4271 tmp_mask = inst_mask; 4272 for_each_inst(i, tmp_mask) { 4273 r = gfx_v9_4_3_xcc_rlc_resume(adev, i); 4274 if (r) 4275 return r; 4276 } 4277 } 4278 4279 tmp_mask = inst_mask; 4280 for_each_inst(i, tmp_mask) { 4281 r = gfx_v9_4_3_xcc_cp_resume(adev, i); 4282 if (r) 4283 return r; 4284 } 4285 4286 return 0; 4287 } 4288 4289 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) 4290 { 4291 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4292 int i; 4293 4294 for_each_inst(i, inst_mask) 4295 gfx_v9_4_3_xcc_fini(adev, i); 4296 4297 return 0; 4298 } 4299 4300 struct amdgpu_xcp_ip_funcs gfx_v9_4_3_xcp_funcs = { 4301 .suspend = &gfx_v9_4_3_xcp_suspend, 4302 .resume = &gfx_v9_4_3_xcp_resume 4303 }; 4304 4305 struct amdgpu_ras_block_hw_ops gfx_v9_4_3_ras_ops = { 4306 .query_ras_error_count = &gfx_v9_4_3_query_ras_error_count, 4307 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count, 4308 }; 4309 4310 static int gfx_v9_4_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 4311 { 4312 int r; 4313 4314 r = amdgpu_ras_block_late_init(adev, ras_block); 4315 if (r) 4316 return r; 4317 4318 r = amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__GFX, 4319 &gfx_v9_4_3_aca_info, 4320 NULL); 4321 if (r) 4322 goto late_fini; 4323 4324 return 0; 4325 4326 late_fini: 4327 amdgpu_ras_block_late_fini(adev, ras_block); 4328 4329 return r; 4330 } 4331 4332 struct amdgpu_gfx_ras gfx_v9_4_3_ras = { 4333 .ras_block = { 4334 .hw_ops = &gfx_v9_4_3_ras_ops, 4335 .ras_late_init = &gfx_v9_4_3_ras_late_init, 4336 }, 4337 .enable_watchdog_timer = &gfx_v9_4_3_enable_watchdog_timer, 4338 }; 4339